Semiconductor component comprising structured contact and method for producing component

Abstract

The assembly may be a semiconductor wafer or die that includes a plurality of structured contacts adapted to form an electrical connection with a respective contact of another semiconductor assembly, where each of the structured contacts includes a planar contact surface and a plurality of upstanding tubular structures extending outwardly from the planar contact surface. The tubular structures are preferably arranged in a regular array on respective contact surfaces. According to the invention, such structures are produced by a series of steps including patterning of a dielectric layer formed on the front surface of the component, said patterning producing an opening in said dielectric layer, and deposition of a conformal layer on said patterned dielectric layer, thereby lining the bottom and sidewalls of the opening. The conformal layer is then removed from the upper surface of the dielectric layer, and the material of the layer is selectively removed relative to the conformal layer, resulting in the tubular structure.

Description

Technical Field

[0001] The present invention relates to electrical bonding of semiconductor components such as chips or wafers. The present invention is applicable to 3D stacking methods involving fine pitch solder joints. Background Art

[0002] The term "3D stacking" refers to a technique for producing a stack of two or more electrically interconnected semiconductor dies. Conventional thermocompression bonding (TCB) for 3D interconnects typically combines electroplated high-melting-point metal microbumps and / or contact pads (such as bumps or pads formed of Cu or Ni) with lower-melting-point solder metals (such as Sn). When the bonding temperature is at or above the melting point of the solder, the liquid solder reacts rapidly with the base metal to form an intermetallic joint. For Sn-based solders, bonding temperatures above 250°C are required. However, temperature-sensitive devices (such as advanced memories and image sensors) require low temperatures for 3D stacking to increase the capacity of the memory and the resolution and quality of the image.

[0003] Especially for die-to-wafer stacking, as full-cycle TCB is applied to each die, the throughput that can be achieved with thermocompression bonding becomes too low to meet current industry needs. High-temperature cycling is also a barrier to continued pitch scaling, i.e., the evolution of bump arrays toward smaller bump sizes and pitches. As the pitch of the bump array becomes smaller, the risk of adjacent bumps shorting increases as the solder material melts. Finally, high-temperature bonding can be detrimental to alignment accuracy.

[0004] Low temperature solutions have been explored, including the use of alternative solder materials such as indium-based solders, but these alternatives cannot match tin-based solders in terms of bonding reliability. Another approach is to create sharp structures on the contact on the bonding side to achieve a mechanical interlock between the sharp structures and the solder inserted therein, such as described in patent publication EP3754706. According to this method, the sharp structures are plate-like grains of intermetallic compounds formed before bonding. However, the size and distribution of the sharp structures are uncontrollable, and thus this approach is incompatible with advanced pitch scaling techniques. Summary of the invention

[0005] The present invention relates to semiconductor components and methods for producing the same as disclosed in the appended claims, as well as assemblies of these components. The component may be a semiconductor wafer or die, comprising a plurality of structured contacts adapted to form electrical connections with corresponding contacts of another semiconductor component, wherein each of the structured contacts comprises a planar contact surface and a plurality of upright tubular structures attached to and extending outwardly from the planar contact surface. The tubular structures are preferably arranged in a regular array on the contact surface. According to the present invention, such structures are produced by a series of steps, including patterning a dielectric layer formed on the front surface of the component, the patterning producing an opening in the dielectric layer, and depositing a conformal layer on the patterned dielectric layer, thereby lining the bottom and sidewalls of the opening. The conformal layer is subsequently removed from the upper surface of the dielectric layer, and the material of the layer is selectively removed relative to the conformal layer, thereby producing the tubular structure.

[0006] The method and assembly according to the invention enable structuring of a planar contact surface by forming said tubular structures on said planar contact surface with sufficient sharpness and formed of a material with sufficient hardness to enable these structures to be inserted into solder bumps or metal contacts of a component configured to be bonded to a component comprising said structures. Thereby, said insertion establishes a mechanical interlock which improves the alignment of the bonded components, enables higher throughput in the case of die-to-wafer bonding, and enables bonding of components at temperatures below the melting temperature of the solder bumps when the contacts according to the invention are used in solder-based bonding processes.

[0007] Advantageously, the number and size of the tubular structures can be controlled by the method of the invention, allowing these parameters to be optimized depending on the size of the contacts or other parameters of the components to be bonded.

[0008] The invention relates in particular to a semiconductor component having a front side and a back side and comprising on the front side a plurality of structured contacts suitable for forming an electrical connection with corresponding contacts of another semiconductor component, characterised in that each of the structured contacts comprises a planar contact surface and a plurality of upright tubular structures extending outwardly from the planar contact surface.

[0009] According to an embodiment, the tubular structures are of equal size and are arranged in a regular pattern.

[0010] According to an embodiment, the planar contact surface of the contact is located in a corresponding cavity formed in a layer of dielectric material at the front side of the assembly and the top of the tubular structure is below the upper surface of the layer of dielectric material.

[0011] According to an embodiment, the tubular structure is formed from a chemically inert material.

[0012] The invention also relates to a method for producing a semiconductor component according to the invention, comprising the following steps:

[0013] providing a semiconductor component comprising a plurality of contacts having a planar upper surface,

[0014] producing a dielectric layer on the front surface of the component, said dielectric layer covering the contacts and having an upper surface parallel to the upper surface of the contacts,

[0015] patterning the dielectric layer to form openings therein, the openings being positioned such that a plurality of openings are distributed over a planar upper surface of each contact, and wherein a portion of the upper surface of the contact is exposed at a bottom of the opening,

[0016] depositing a conformal layer on the patterned dielectric layer so that the material of the conformal layer lines the bottom and sidewalls of the opening and the upper surface of the dielectric layer,

[0017] removing material of the conformal layer from an upper surface of the dielectric layer,

[0018] Material of the dielectric layer is removed selectively relative to material of the conformal layer such that a plurality of upstanding tubular structures are formed on the upper surface of the contact, thereby obtaining the structured contact.

[0019] According to an embodiment of the method of the invention, the contact is a contact pad embedded in a layer of dielectric material coplanar with the planar upper surface of the contact pad, and the coplanar surface of the layer of dielectric material and the contact pad forms the front surface of the component.

[0020] According to an embodiment of the method according to the invention, the contact is a contact bump having a base embedded in the layer of dielectric material and a top extending outwardly from the layer of dielectric material.

[0021] According to an embodiment of the method according to the invention, the step of removing material of the conformal layer from the upper surface of the dielectric layer is performed by planarizing the upper surface of the dielectric layer.

[0022] According to an embodiment of the method according to the invention, material of the dielectric layer is removed by etching said material selectively with respect to the material of the conformal layer.

[0023] According to an embodiment of the method according to the invention, an etch stop layer is produced on the component before producing the dielectric layer.

[0024] According to an embodiment of the method of the present invention, the dielectric layer is a first dielectric layer, and the method further comprises the following steps performed after the step of removing the material of the conformal layer from the upper surface of the first dielectric layer:

[0025] producing a second dielectric layer on the first dielectric layer,

[0026] patterning the second dielectric layer to create cavities therein, the cavities being positioned on respective planar surfaces of the contacts so that openings lined with the conformal layer are exposed at the bottom of the cavities,

[0027] The material of the first dielectric layer is removed only in the cavity.

[0028] According to one embodiment of the method of the present invention, after the step of depositing the conformal layer, the method further includes the step of filling the opening with a dummy material, the dummy material and the material of the conformal layer are removed from the upper surface of the dielectric layer by planarization, followed by the removal of the material of the dielectric layer and the selective removal of the dummy material relative to the conformal layer.

[0029] The invention likewise relates to a method for bonding a first semiconductor component according to the invention to a second semiconductor component comprising a plurality of second contacts, the first semiconductor component comprising a plurality of first contacts provided with the tubular structure,

[0030] The method comprises the sequential application of the following steps:

[0031] producing solder bumps on corresponding contacts of the second component,

[0032] aligning the second component with the first component such that the solder bumps on the second contacts are aligned with the first contacts of the first component,

[0033] bonding the first and second components together at a temperature below the melting temperature of the solder bumps so that the tubular structure of the first contact is inserted into the solder bumps on the second contact, thereby obtaining an assembly of the first and second components,

[0034] The assembly is annealed to thereby achieve an electrically conductive connection between the corresponding contacts of the first and second components.

[0035] According to an embodiment of the method according to the preceding paragraph, the annealing step is performed at a temperature below the melting temperature of the solder bump.

[0036] According to an embodiment of the method according to any of the two preceding paragraphs, the method further comprises the steps of applying an underfill material on the second component before bonding, and planarizing the underfill material and the solder bumps on the second component to a common planarized surface.

[0037] The invention likewise relates to a method for bonding a first semiconductor component according to the invention to a second semiconductor component comprising a plurality of second contacts, the first semiconductor component comprising a plurality of first contacts provided with the tubular structure,

[0038] The method comprises the sequential application of the following steps:

[0039] aligning the second component with the first component so that the second contact is aligned with the first contact,

[0040] combining the first and second components together such that the tubular structure of the first contact is inserted into the second contact, thereby obtaining an assembly of the first and second components,

[0041] The assembly is annealed to thereby achieve an electrically conductive connection between corresponding contacts of the first and second components by solid state interdiffusion.

[0042] The invention also relates to an assembly of stacked and electrically connected semiconductor components, comprising at least two components connected by connections formed between respective contacts of said two components, wherein a plurality of tubular structures are embedded in each of a plurality of said connections. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A small portion of an integrated circuit (IC) processed on a silicon wafer is shown, the portion illustrating the constituent layers of the IC and a plurality of contact pads.

[0044] Figures 2 to 10 The key steps of a method according to an embodiment of the present invention are shown. Figure 1 Sharp structures are produced on the contact pads of the IC shown.

[0045] Figure 11 to Figure 12 Another method for producing the sharp structures on the contact pads is shown.

[0046] Figures 13 to 15 Another alternative method for producing the sharp structures is shown.

[0047] Figures 16 to 19 A structured contact bump according to an embodiment of the present invention is shown.

[0048] Figures 20a to 20d Various bonding processes are shown in which solder bumps are bonded to contact pads constructed according to an embodiment of the present invention.

[0049] Figures 21a to 21c A bonding process is shown in which a direct metal-to-metal bond is realized between a structured metal contact pad according to the invention and a contact bump.

[0050] Figures 22a to 22c A direct hybrid bonding process using a structured contact pad according to the invention is shown.

[0051] Fig.23 A bonding process for bonding multiple stacked dies using bond pads constructed in accordance with the present invention is shown. DETAILED DESCRIPTION

[0052] The present invention will be described based on exemplary embodiments, however, this does not limit the scope of the present invention. All references to shapes, dimensions or materials are cited as examples only, and alternatives to these parameters will be described in various examples throughout the specification.

[0053] Figure 1 1 is a schematic diagram of a silicon process wafer 1 on which a plurality of integrated circuit chips have been processed on its front surface. The figure shows a cross section of a small portion of a chip, including a bulk silicon portion 2, a front end of line (FEOL) portion 3 including active devices such as transistors or diodes, and a back end of line (BEOL) portion 4, which is a multilayer structure of interconnecting electrical conductors and vias designed to provide signal routing to the active devices and embedded in an electrically insulating dielectric material. The chip also includes a regular array of copper contact pads 5 connected to the top layer of the BEOL portion 4. In the plane of the wafer 1, the pads 5 have a circular cross-section with a diameter of about 2m. The thickness of the pads 5 is less than 1m. The pitch of the array of contact pads 5 is about twice the diameter of the pads 5. As mentioned above, these shapes and sizes do not limit the scope of the present invention, but are only used as examples. The present invention is applicable to contact pads of any shape or size that are actually applicable to semiconductor components, for example, in terms of their main characterizing in-plane dimensions (diameter of a circular contact pad, such as the diagonal of a square or rectangular contact pad), ranging from about 1m to 10m. In addition to copper, other metals may also be used as the material of the contact pad, such as aluminum or nickel. Suitable metals for such contact pads are known in the art.

[0054] The pads 5 are laterally embedded in a layer 6 of dielectric material which electrically isolates the pads from each other, i.e. the layer 6 surrounds the pads 5, leaving the upper surface 5' of the contact pads free and coplanar with the isolation layer 6. The electrical isolation layer 6 may be a single layer or a stack of individual layers of different dielectric materials. The pads 5 may be processed by known damascene type processing techniques for producing BEOL type interconnect structures. Typically, there is a diffusion barrier ( Figure 1 not shown).

[0055] In this context, the "contact" of a semiconductor component is defined as a contact pad or contact bump. The contact pad 5 is as described above, i.e., it is completely embedded in the dielectric layer 6 and has an upper surface 5' coplanar with the upper surface of the dielectric layer 6. The contact bump has a base that is completely embedded in the dielectric layer and a top that protrudes outward from the dielectric layer. The present invention is also applicable to such contact bumps, which have a planar upper surface (i.e., the planar upper surface of the top). A structured contact is defined in this context as a contact having a planar upper surface with a structure extending outward from the surface. In other words, a plurality of (i.e., more than one) structures extend outward from the planar upper surface of the contact. The method for producing this structured contact according to the present invention will first be described in detail for the contact pad situation.

[0056] Figure 2 1 shows a cross-sectional view and a plan view of a single contact pad 5 as a starting point for a plurality of method steps to be performed on a wafer 1 according to an embodiment of the present invention. Figure 3 , two layers 7 and 8 are produced on the coplanar upper surface of the contact pad 5 and the isolation layer 6. These layers 7 and 8 are formed over the entire surface of the wafer 1. The first layer 7 is a thin etch stop layer, such as a SiN or SiCN layer. This layer is called an etch stop layer with respect to one or more etching processes applied at a later stage of the method, as will be further described. The etch stop layer 7 is thin, for example, less than about 10 nm.

[0057] The second layer 8 is a dielectric layer, for example a silicon oxide layer with a thickness of about 300 nm. Any known technique for producing these layers 7 and 8 is suitable. The person skilled in the art is familiar with these techniques, so the details thereof are not included in the present description.

[0058] Reference Figure 4 , the stack of etch stop layer 7 and dielectric layer 8 is patterned in the area above the contact pad 5. The same patterning is preferably applied on all contact pads 5 of the chip. The pattern comprises a plurality of circular openings 10 having a small diameter relative to the diameter of the contact pad 5. The openings are distributed over the entire surface area of ​​the contact pad 5 and are preferably arranged in a regular pattern, such as Figure 4 As shown in the top view.

[0059] The diameter of the opening may be, for example, about 200 nm. The opening 10 may be produced by photolithography and etching techniques known in the art. A suitable method for producing openings of these dimensions is to produce a hard mask stack on the dielectric layer 8, the hard mask stack being formed by a stack of a dielectric anti-reflective coating (DARC), a bottom anti-reflective coating (BARC) and a photoresist layer; patterning the resist layer and etching to form openings in the DARC / BARC layer stack and transferring these openings to the underlying dielectric layer 8 by an anisotropic etching process, and then stripping the hard mask.

[0060] If the anisotropic etching process is not selective with respect to the Cu of the contact pad 5, the etch stop layer 7 is used to stop the process. The etch stop layer 7 is also used to stop the wet etching step described further herein. The etch stop layer 7 is then removed in the opening 10 by a selective etching recipe to thereby expose the upper surface of the contact pad 5 at the bottom of the opening 10, as shown in FIG. Figure 4 shown.

[0061] Reference Figure 5 , a thin layer 11 is conformally produced on the dielectric layer 8, i.e., the layer 11 follows the topography defined by the layer 8 and the opening 10 formed therein. In the illustrated embodiment, the layer 11 is a tantalum layer, but other materials are possible as will be further explained. The thickness of the layer 11 may be about 10 nm. As shown, the Ta layer 11 lines the bottom and sidewalls of the opening 10.

[0062] After this, refer to Figure 6 , the Ta-lined opening 10 is filled with a sacrificial material 12 (i.e. a material that will be removed again later). This can be Cu or any other suitable dummy material. Cu can be deposited in the opening 10 by electroplating, which will also form a layer of Cu on top of the dielectric layer 8. A planarization step is then performed, for example comprising grinding and CMP (chemical mechanical polishing), to remove the electroplated Cu and Ta from the upper surface of the dielectric layer 8. The result of the planarization is Figure 6 Shown in.

[0063] A second dielectric layer 13 is then produced on the planarized surface, see Figure 7 In the embodiment shown, the layer 13 is thinner than the layer 8, but this is not a requirement of the invention. Figure 8 , a resist layer 14 is produced on the second dielectric layer 13, and by standard photolithography and etching, the resist layer 14 and the second dielectric layer 13 are patterned to form a cavity 15 therein. Preferably, the same type of cavity is formed on the other contact pads 5 of the chip. As shown in the figure, the cavity 15 can have a circular cross-section with the same diameter as the contact pad 5 and is aligned with the contact pad 5. However, small diameter differences and / or small misalignments due to overlap errors in the photolithography step are allowed. When forming the cavity 15, the Ta-lined and Cu-filled opening 10 is exposed at the bottom of the cavity 15, as shown in FIG. Figure 8 shown.

[0064] exist Fig. 9In the next step shown, with the resist 14 still in place, the dielectric material of the dielectric layer 8 and the sacrificial material 12 are removed starting from the bottom of the cavity 15. The removal of these materials can be accomplished by one or more suitable wet etching recipes that are capable of achieving said removal selectively relative to the Ta liner 11 of the opening 10 and relative to the etch stop layer 7, i.e., the etch stop layer 7 stops the etching process applied to remove the material of the dielectric layer 8 and the sacrificial material 12. The etch stop layer 7 can then also be removed selectively relative to the liner 11 and relative to the material of the contact pad 5, which can be accomplished by a dry etching process. Thereafter, the resist 14 is stripped to produce a structure such as Fig.10 Cross-sectional and top views are shown.

[0065] The Ta liner is now indicated by a new reference numeral 20, which indicates the bottom of the cavity 16 formed in the stack of dielectric layers 8 and 13, an upright tubular structure extending outward from the planar surface 5' of the contact pad 5. In the illustrated embodiment, the etching selectivity of the above etching recipe is considered to be 100%. As a result, the original Ta liner on the bottom and sidewalls of the opening 10 is completely retained. In practice, the etching selectivity is less than 100%, and the liner may be affected to some extent by the etching process. For example, the Ta formed at the bottom of the opening may be partially or completely removed, and the liner on the sidewall may be slightly shortened. However, the etching selectivity can be sufficient to produce a tubular structure with a significant height extending upward from the contact pad 5. In the illustrated embodiment, the height is about 300nm. However, according to other embodiments, the height can be much higher, which may include a tubular structure with a height of 1m or more. Such a structure can be produced on a contact pad having a diameter larger than the diameter shown, for example, on a circular contact pad with a diameter of 10m. According to an embodiment of the invention, the planar contact pad 5 comprising tubular structures 20 may be referred to as a structured contact pad 21. In the wording of the appended claims, the wafer 1 is provided with a contact 21 comprising a planar contact surface 5' provided with a plurality of upstanding tubular structures 20 extending outwardly therefrom.

[0066] An alternative method of producing the contact pads of the tubular structure 20 is described in Fig.11 and 12 According to this method, no dummy material is used, and after forming the conformal layer 11, that is, Figure 5 Directly after the step shown, a CMP step is applied. This CMP step removes layer 11 from the upper surface of dielectric layer 8 while keeping it at the bottom and sidewalls of opening 10. Thereafter, the material of dielectric layer 8 is removed by etching relative to layer 11 and stopping on etch stop layer 7. The latter etch stop layer 7 is then removed by a suitable etching recipe to produce Fig.12The structure 20 now extends outwards from the coplanar surface of the contact pad 5 and the dielectric isolation layer 6. The structured contact pad 21 obtained in this way is suitable for bonding the wafer 1 to another component in a direct hybrid bonding process, as will be described further.

[0067] It is also possible to avoid the use of dummy material, but still obtain a tubular structure 20 located in the cavity 16, such as Figures 13 to 15 After the CMP step (in which layer 11 is removed from the upper surface of dielectric layer 8 (as shown in FIG. Fig.11 As shown), a second dielectric layer 13 is deposited to fill the opening 10, and a layer 13 is formed on top of the first dielectric layer 9 (as shown). Fig.13 The layer 13 may be planarized by CMP to form a planar upper surface as shown. Then, a photoresist 14 is produced and patterned to form a cavity 17 therein (see Fig.14 ), and the cavity 17 is transferred into the stack of layers 8 and 13 by etching (see Fig.15 ) to form a cavity 16 after stripping the resist 4.

[0068] Fig.16 An example of a contact in the form of a metal bump 9 is shown, which comprises a base 9a embedded in a layer 6 of dielectric material and a top 9b protruding outwards from the dielectric layer 6, the top 9b having a flat upper surface 9'. The invention is also applicable to such contacts. The method according to the invention for producing a structured contact bump comprises substantially the same steps as described for the case of a contact pad. Fig.17 As shown, an etch stop layer 7 and a dielectric layer 8 are deposited, the layer 8 is planarized so that its upper surface is parallel to the planar upper surface of the contact bump 9, and an opening 10 is created. After this, the method of the present invention can be applied according to the various embodiments described above. This may result in Fig.18 The result shown is that the structured contact bump 22 including the tubular structure 20 is located in the cavity 16 formed in the stack of dielectric layers 8 and 13, or results in Fig.19 The result shown is that the structured contact bumps 22 protrude outward from the dielectric layer 6 .

[0069] From the description of the method according to the invention for producing a structured contact element it follows that the tubular structures 20 extend outwardly from the planar contact surface and that no filling material is applied between the tubular structures, ie each tubular structure extends entirely outwardly from the planar contact surface.

[0070] An advantage of applying the tubular structure 20 to the contact bump 9 is that, in case of solder based bonding, melted or softened solder material can form around the side walls of the bump.

[0071] The function of the tubular structure 20 is to interlock with a contact material that is part of or attached to another component in a bonding process, wherein the other component is bonded to a component including a structured contact pad or bump according to the present invention. The contact material can be a solder bump attached to other components, or a metal contact pad or bump of other components. To this end, the material of the structure 20 must have a higher hardness than the contact material. It is also preferred that the material of the structure 20 is chemically inert so that it does not interfere with the formation of intermetallic compounds during the bonding process. For example, the following materials: Ta, TaN, Pt or Au are inert materials with sufficient hardness, which are suitable for interlocking with solder materials in solder-based bonding processes, or interlocking with contact bumps or pads in direct metal-to-metal bonding processes. The wall thickness of the structure 20 makes the structure sharp enough so that it can be inserted into the contact material of another component in a bonding process.

[0072] Figures 20a to 20c An example of a solder based bonding process is shown. Fig.20a A structured contact pad 21 is shown on a wafer 1, i.e. comprising a planar contact pad 5 provided with a tubular structure 20. The tubular structure 20 is oriented upwards, as is the case when the silicon wafer 1 is placed on a horizontal holding table in a solder bonding tool known in the art. The wafer 1 is the first component in the bonding process, wherein the second component is to be bonded and electrically connected to the first component. Fig.20a As seen in FIG. 1 , the second component 24 includes a Cu contact bump 25. The contact bump 25 has a base 25a embedded in a dielectric isolation layer 26 and a protruding top 25b. The second component 24 can be another process wafer including a plurality of integrated circuit dies to be bonded to the wafer 1 in a wafer-to-wafer bonding process, or it can be a single die to be bonded to the wafer 1 in a die-to-wafer bonding process. The contact bump 25 of the second component has received a solder bump 27 thereon, which can be applied by known techniques (e.g., electroplating). The protruding top 25b of the bump 25 has a circular cross-section, whose diameter is smaller than the diameter of the contact pad 5 on the wafer 1, and the diameter of the solder bump 27 is approximately the same as the diameter of the protrusion 25b. The solder material can be any solder known in the art, such as Sn. The thickness of the solder bump 27 is about 1 to 1.5 μm.

[0073] The bonding sequence may be based on known solder-based bonding sequences, including bonding sequences in which the temperature is not raised above the melting temperature of the solder material. An example of such a sequence will be briefly described below for a die-to-wafer bonding process. Fig.20bAs shown, the second component 24 (i.e., a single die) is lowered until the tubular structure 20 is inserted into the solder material of the bump 27. This can be done at room temperature, but the temperature is preferably above room temperature but still below the melting point of the solder, so that the solder softens to a certain extent. By inserting the tubular structure 20 into the solder, a mechanical interlock is achieved between the contact pad 5 and the solder bump 27. This stage of the process is completed in a pick and place tool, where multiple dies are placed sequentially on the wafer 1.

[0074] This is followed by an annealing step in a batch annealing tool, in which the assembly of the wafer 1 with the plurality of dies 24 attached thereto is heated for a given period of time and at a given temperature, and possibly simultaneously with the application of downward pressure to the dies 24. The annealing temperature may be a temperature below the melting point of the solder, at which temperature intermetallic compounds are formed by solid state interdiffusion between the material of the contacts 5 and 25 on the one hand and the solder material on the other hand. Such low temperature annealing may result in Fig.20c A solder based connection 28 is shown. It can be seen that the solder has softened at the elevated temperature so that it partially fills the cavity 16. The connection 28 is formed by solder material and an intermetallic compound resulting from the interdiffusion of elements from the solder bump 27 and from the contacts 5 and 25.

[0075] The annealing step can also be performed at a temperature above the melting point of the solder, which results in Fig.20d Solder connection 29 is shown. The original solder bump has been completely melted and reflowed, resulting in connection 29 filling the entire cavity 16.

[0076] Fig.20c and 20d represents the preferred situation in which the tubular structures 20 are chemically inert so that these structures 20 remain in the final welded connection 28 or 29 .

[0077] The bonding sequence for a wafer-to-wafer bonding process (where the second component 24 is a wafer) is similar to that described above. The tubular structure 20 is then simultaneously inserted with solder bumps 27 for all the dies on the second component.

[0078] The mechanical interlocking of the structure 20 to the solder bump 27 enables high throughput in the case of die-to-wafer bonding, because the alignment between the interlocking contacts is maintained between the pick-and-place tool and the annealing tool. In addition, solid-state interdiffusion is promoted due to the plastic deformation of the sharp structure 20 after insertion into the solder bump 27. Although bonding above the melting point of the solder is still possible, this function enables the bonding process to be performed at a temperature that will not damage the device on the bonded assembly. These functions are similar to the functions of the sharp plate-like particles of the interlocking layer disclosed in EP3754706. The difference is that the position and size of the tubular structure 20 can be controlled so that the interlocking function can be optimized according to the pad size and the material applied. This makes it possible to produce a tubular structure 20 of suitable size on contacts of small size and spacing, so that the solder bump can be avoided from melting for these small sizes, thereby avoiding short circuits between adjacent solder connections. In other words, the present invention achieves advanced spacing scaling.

[0079] Another advantage of the present invention is that the sharp structures are able to penetrate oxides formed on the surface of the solder material. In standard solder bonding, flux is applied before bonding to remove these oxides. However, the flux material leaves residues on the bumps, which may cause reliability problems. Due to the mechanical breaking of the oxide layer, according to the present invention, no flux is required when applying the structured contact (i.e. including the tubular structure 20).

[0080] It is clear from the above description that the tubular structure 20 produced on the contact 5 or 9 must be harder than the solder material at the temperature applied during the insertion of the structure into the solder so that the structure 20 is not deformed by the insertion process. This represents a requirement for the material and thickness of the structure in question. As mentioned above, Ta or Ti or Pt or TaN or TiN or Au are suitable materials when used in combination with most known solder materials.

[0081] However, the invention is not limited to solder-based bonding but can also be applied to direct bonding processes, where the primaries are bonded together by solid-state interdiffusion without the intervention of solder material. Figures 21a to 21cThe bonding sequence shown is shown. The contact on the second component 24 is now a Cu contact bump 30, which includes a base 30a and a protruding top 30b. When lowered toward the contact pad 5 on the first component provided with the tubular structure 20, these structures are inserted into the Cu contact bump 30, provided that the hardness of these structures significantly exceeds the hardness of the Cu bump. This can be done at room temperature or in any case at a temperature far below the melting temperature of Cu. The structure is inserted into Cu by local plastic deformation of the upper Cu pad 30, thereby establishing a mechanical interlock as in the case of a solder bump. In order to achieve or facilitate the insertion and plastic deformation, it may be advantageous to manufacture an upper bump with a higher porosity than usual with copper.

[0082] Annealing is then preferably applied while the second component 24 is pressed down on the first component, thereby achieving solid state interdiffusion of the Cu contacts. In the case of die-to-wafer bonding, this can be done in a batch annealing tool after sequential pick and place of multiple dies. Fig.21c An interdiffusion zone 31 is formed in which Cu-Cu interdiffusion occurs, forming a strong conductive bond. When two planar copper surfaces are pressed together, the interdiffusion usually occurs at a temperature in the range of 250-350°C. However, when the tubular structure 20 is applied on one side, this temperature may be lower. This is because the local plastic deformation caused by the insertion of the structure 20 into the Cu bump 30 creates an area that can promote interdiffusion so that it starts at a lower temperature than the planar case.

[0083] exist Figures 20a-20d In the bonding sequence shown in Figures 21a-21c, no underfill material is shown. However, in most cases, it is preferred to fill the space between components with such an underfill material, which seals the connection to the outside of the bonded assembly.

[0084] In the case of a bonding process including contacts constructed according to the present invention, the bottom filler material can be applied in any manner known in the art today. The bottom filler can be any material known for this purpose. Therefore, the most famous material is a thermoplastic polymer, which enters the space between the bonded contacts in a fluid state at an elevated temperature and then hardens into a resinous matrix. The bottom filler can be applied after bonding or before bonding. In the latter case, the bottom filler material is preferably applied to the component without a tubular structure on the contact. As known in the art, it is advantageous to apply the bottom filler material pre-bonding because it helps to reduce the bump height non-uniformity of the solder bumps on the wafer. This is done by applying the bottom filler in a liquid state after applying the solder bumps and then cooling the wafer to harden the bottom filler material. The wafer is then CMPed to flatten the bottom filler material and the bumps to a common coplanar surface, thereby eliminating any bump height non-uniformity. In view of the fact that the contacts constructed according to the present invention are preferably applied in a low temperature bonding sequence, it is preferred to apply the above-mentioned pre-bonding bottom filler and flattening steps. Otherwise, bump height non-uniformity may be such that the only way to bond the wafers is to heat above the melting temperature of the solder bumps.

[0085] Figures 22a-22c A direct hybrid bonding process using a structured contact pad 21 according to the invention is shown on a bonded component. Fig.11 and Fig.12 The contact pad 21 obtained by the method shown is suitable for this purpose. Fig.22a As shown, a flat top wafer or die 24 including a Cu pad 35 coplanar with a dielectric layer 36 is bonded to a flat bottom wafer 1 having a structured Cu pad 21 coplanar with a dielectric layer 6. The dielectric material on the two wafer surfaces is suitable for a direct dielectric to dielectric bonding process. The material can be SiCN or SiO2, for example. The Cu pad will be bonded by direct Cu-Cu bonding, such as the bonding between the pad 5 and the Cu bump 30 in the previous embodiment. The term hybrid bonding refers to the fact that metal-metal bonding and dielectric-dielectric bonding are achieved simultaneously. In this case, no bottom fill material is required.

[0086] like Figure 22b As seen in FIG. 1 , the top component 24 is pressed onto the bottom component 1 until the structure 20 is inserted into the contact pads 35 of the top component. Fig.22c, the bonding annealing at a given pressure then achieves conductive bonding by Cu-Cu interdiffusion in the region 37 between the pads 5 and 35, and dielectric-dielectric bonding between the layers 6 and 36. If both layers 6 and 36 are formed uniformly from the same material (e.g. SiO2), the uniform dielectric layer 38 is the result of dielectric-dielectric bonding. As in the previous case, the Cu-Cu interdiffusion can occur at a lower temperature than the bonding between planar contacts.

[0087] Fig.23 The use of structured bonding pads according to the invention in a bonding sequence to produce a plurality of stacked dies 40, 41 on a wafer 1 is shown. The constituent parts of the wafer and the dies 40, 41 have been numbered with the same reference numerals as used in the above description, such as substrate part 2, FEOL and BEOL parts 3, 4, contact pads 5 and contact bumps 25 etc. Both dies 40, 41 comprise on their front side a structured contact pad 21 according to the invention, i.e. a planar contact pad 5 provided with an upstanding tubular structure 20 on its upper surface, and a TSV (through substrate via) connection 45 from its FEOL part 3 to the back side of the die, which is provided with a back side contact bump 25 as described above, on which a solder bump 27 is plated. The die stack assembly according to the invention is characterised in that there are tubular structures 20 embedded in the connections interconnecting the dies. These connections may be Fig.20c and 20d Solder / metal bumps 28, 29 or Fig.21c and 22c The intermetallic diffusion regions 31, 37 in the embodiment of the present invention are shown in FIG. 2 (in the latter case, the structure 20 may be only partially embedded in these regions 31, 37).

[0088] The presence of dielectric layers 8 and 13 represents an advantage for the bonding process. As a result of the method according to the invention for producing structured contacts 21, 22, the top of the tubular structure 20 is below the upper surface of the stack of layers 8+13. These layers thus enable the die 40, 41 to be attached to the holding chuck without directly contacting the tubular structure 20, thus avoiding damage to said structure during handling of the die.

[0089] Although the invention has been shown and described in detail in the drawings and the foregoing description, such illustration and description should be regarded as illustrative or exemplary and not restrictive. Other variations to the disclosed embodiments can be understood and implemented by those skilled in the art in practicing the claimed invention by studying the drawings, the present disclosure and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The fact that certain measures are cited in mutually different dependent claims does not mean that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be interpreted as limiting the scope.

Claims

1. A semiconductor component having a front side and a back side and comprising on the front side a plurality of structured contacts suitable for forming an electrical connection with corresponding contacts of another semiconductor component, characterized in that Each of the structured contacts includes a planar contact surface and a plurality of upstanding tubular structures extending outwardly from the planar contact surface.

2. The semiconductor component of claim 1, wherein the tubular structures have equal sizes and are arranged in a regular pattern.

3. A semiconductor component as claimed in claim 1, wherein the planar contact surface of the contact is located in a corresponding cavity formed in a layer of dielectric material on the front side of the component, and wherein the top of the tubular structure is below the upper surface of the layer of dielectric material.

4. The semiconductor component of claim 1, wherein the tubular structure is formed of a chemically inert material.

5. A method for producing a semiconductor component as claimed in any one of claims 1 to 4, the method comprising the following steps: providing a semiconductor component comprising a plurality of contacts having a planar upper surface, producing a dielectric layer on the front surface of the component, the dielectric layer covering the contacts and having an upper surface parallel to the upper surface of the contacts, patterning the dielectric layer to form openings therein, the openings being positioned such that a plurality of openings are distributed over the planar upper surface of each contact, and wherein a portion of the upper surface of the contact is exposed at a bottom of the opening, - depositing a conformal layer on the patterned dielectric layer so that the material of the conformal layer lines the bottom and sidewalls of the opening, and the upper surface of the dielectric layer, - removing material of the conformal layer from the upper surface of the dielectric layer, - removing material of the dielectric layer selectively relative to material of the conformal layer such that a plurality of upstanding tubular structures are formed on the upper surface of the contact, thereby obtaining the structured contact.

6. The method of claim 5, wherein the contact is a contact pad embedded in a layer of dielectric material coplanar with a planar upper surface of the contact pad, and wherein the coplanar surface of the layer of dielectric material and the contact pad forms the front surface of the component. 7 . The method of claim 5 , wherein the contact is a contact bump having a base embedded in a layer of dielectric material and a top extending outwardly from the layer of dielectric material.

8. The method of claim 5, wherein an etch stop layer is produced on the component before producing the dielectric layer.

9. The method of claim 5, wherein the dielectric layer is a first dielectric layer, and the method further comprises the following steps performed after the step of removing material of the conformal layer from the upper surface of the first dielectric layer: producing a second dielectric layer on said first dielectric layer, patterning the second dielectric layer to create a cavity therein, the cavity being positioned on a corresponding planar surface of the contact so that the opening lined with the conformal layer is exposed at a bottom of the cavity, And wherein the material of the first dielectric layer is removed only in the cavity.

10. The method of claim 5, wherein the method further comprises the step of filling the opening with a dummy material after the step of depositing the conformal layer, and wherein the dummy material and the material of the conformal layer are removed from the upper surface of the dielectric layer by planarization, followed by removal of the material of the dielectric layer and selective removal of the dummy material relative to the conformal layer.

11. A method for bonding a first semiconductor component as claimed in any one of claims 1 to 4 to a second semiconductor component comprising a plurality of second contacts, the first semiconductor component comprising a plurality of first contacts, the first contacts being provided with the tubular structure, The method comprises the consecutive application of the following steps: creating solder bumps on corresponding contacts of the second component, aligning the second component with the first component such that the solder bump on the second contact is aligned with the first contact of the first component, combining the first component and the second component together at a temperature below the melting temperature of the solder bump so that the tubular structure of the first contact is inserted into the solder bump on the second contact, thereby obtaining an assembly of the first component and the second component, The assembly is annealed to thereby achieve an electrically conductive connection between corresponding contacts of the first component and the second component.

12. The method of claim 11, wherein the annealing step is performed at a temperature below a melting temperature of the solder bump.

13. The method of claim 11, further comprising the steps of: An underfill material is applied on the second component prior to bonding and the underfill material and the solder bumps on the second component are planarized to a common planarized surface.

14. A method for bonding a first semiconductor component as claimed in any one of claims 1 to 4 to a second semiconductor component comprising a plurality of second contacts, the first semiconductor component comprising a plurality of first contacts, the first contacts being provided with the tubular structure, The method comprises the consecutive application of the following steps: aligning the second component with the first component so that the second contact is aligned with the first contact, combining the first component and the second component together so that the tubular structure of the first contact is inserted into the second contact, thereby obtaining an assembly of the first component and the second component, The assembly is annealed to thereby achieve conductive connections between corresponding contacts of the first and second components by solid state interdiffusion.

15. An assembly of stacked and electrically connected semiconductor components, comprising at least two components connected by connections formed between respective contacts of the two components, wherein a plurality of tubular structures are embedded in each of a plurality of the connections.

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