Interconnection Structure and Method between a Wafer-Level Chiplet Integration System and a System Mainboard

Abstract

The present invention discloses an interconnection structure and method between a wafer-level chiplet integration system and a system main board. The interconnection structure includes a SoW system, a wafer pressing plate, a PCB-let array, Pogo-pin spring pins, an alignment hole plate, and a system main board. The present invention realizes the first-level interconnection and transition and obtains a composite body by connecting a PCB-let array to one side of the SoW system and leading out pads for connecting the power supply and signals of the chiplets on the back of the PCB-let array. In order to alleviate the warping problem, the Pogo-pin spring pins are welded to the system main board, and after applying appropriate pressure through the wafer pressing plate, the needle tips achieve effective contact interconnection with the pads of the PCB-let array, thus completing the second-level interconnection and transition. The present invention is compatible with and applicable to wafer-level integrated interconnection systems of various (homogeneous and heterogeneous) chiplets, and has the characteristics of being insensitive to warping, separable between the wafer composite body and the system main board, and easy system debugging.

Description

Technical Field

[0001] The invention belongs to the field of electronic packaging, and relates to an interconnection structure and method of a wafer-level core particle integration system and a system mainboard. Background Art

[0002] With the slowdown of the progress of integrated circuit manufacturing technology and the gradual failure of Moore's Law, wafer-level packaging technology has shown great potential in the post-Moore era. Since the bonding of wafer-level chip integrated system (SoW, System On Wafer) and printed circuit board (PCB, Printed Circuit Board) can achieve high-density interconnection and low-cost assembly, this technology has gradually become a research hotspot in the packaging field. However, in practical applications, due to differences in material properties, the bonding process faces many challenges.

[0003] Currently, there are some technical solutions suitable for bonding SoW systems to PCBs. Some reports use metal bonding to achieve electrical connection of devices by making metal interconnect layers on the surface of SoW systems and PCBs. Metal bonding improves electrical conductivity and heat dissipation, but due to the large difference in thermal expansion coefficients between SoW systems and PCBs, warping and delamination are easily caused when bonding large-sized devices. Bonding technology based on conductive adhesive has certain advantages over existing solutions. The existing conductive adhesive bonding process mainly includes: (1) making pads on the surface of PCB; (2) coating conductive adhesive; (3) aligning SoW systems and PCBs; (4) thermal curing molding. Due to the limited thermal and electrical conductivity of conductive adhesives and the narrow process window, current technical solutions still cannot meet the needs of high-performance devices. On the other hand, due to the high process complexity and low production efficiency, the cost remains high.

[0004] Since the SoW system is mainly composed of silicon materials, while PCBs mostly use organic materials such as FR4, the physical and chemical properties of the two are significantly different, which directly affects the bonding quality. Therefore, the use of a stress buffer layer can improve the bonding reliability, but there is no relevant report yet. Summary of the invention

[0005] In order to solve the problems in the background technology, the present invention provides an interconnection structure between a wafer-level chip integration system and a system mainboard.

[0006] The technical solution adopted by the present invention is as follows:

[0007] An interconnection structure between a wafer-level core grain integrated system and a system mainboard, comprising a wafer-level core grain integrated system and a system mainboard, characterized in that it also comprises a wafer pressing plate, a printed substrate array, a spring pin and an alignment hole plate;

[0008] The described wafer-level die integration system includes a whole silicon wafer with dies mounted on its first surface and contacts provided on its second surface; the printed circuit board array consists of multiple printed circuit boards on the same plane, the first surface of each printed circuit board is bonded to the contacts of the wafer-level die integration system, and the second surface is provided with a power supply and signal pad array; one side of the system main board is provided with pads corresponding to the power supply and signal pad array;

[0009] The pogo pin includes an elastically interconnected barrel and a needle tip. The barrel is provided with a needle base for soldering. The number of pogo pins is the same as the number of pads in the power supply and signal pad array; the alignment hole board is provided with multiple through holes. The needle bases of the pogo pins are soldered to the pad array on the first surface of the system main board, and the needle tips pass through the through holes and contact the power supply and signal pad array to form an electrical connection;

[0010] The wafer pressing plate is fixedly attached to the first surface of the wafer-level die integration system to uniformly apply pressure to ensure the bonding of the pogo pins to the power supply and signal pad array.

[0011] The interconnect structure further includes a main frame for mounting and fixing the wafer-level die integration system, the alignment hole board, and the system main board; a plastic cushion plate is further provided on one side surface of the main frame facing the system main board to buffer the pressure between the main frame and the system main board; a groove for embedding the printed circuit board array is further provided on the surface of the alignment hole board.

[0012] A heat sink is further mounted on the surface of the die of the wafer-level die integration system, and a through hole for the heat sink to pass through is provided in the middle of the wafer pressing plate.

[0013] The present invention also provides a preparation method for the interconnect structure between the above-mentioned wafer-level die integration system and the system main board, which includes the following steps:

[0014] 1) Perform oven soldering on the second surface of the wafer-level die integration system and the first surface of the printed circuit board array to complete the first-level interconnection and transition from the die to the printed circuit board array;

[0015] 2) Perform reflow soldering on the pogo pins, the alignment hole board, the system main board, and the components on the board together;

[0016] 3) Fix the main frame, the plastic cushion plate, and the system main board through connectors;

[0017] 4) Mount a heat sink on the first surface of the wafer-level die integration system, and embed the printed circuit board array on the second surface of the wafer-level die integration system into the groove structure on the first surface of the alignment hole board;

[0018] 5) Press the wafer pressing plate tightly against the first surface of the wafer-level die integration system and fix it with connectors to achieve the second-level interconnection and transition from the die array to the system main board.

[0019] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0020] 1) The present invention uses pogo pins to achieve the bonding between the wafer-level chiplet integration system and the system main board. The expansion and contraction of the pogo pins can effectively solve the warping problem of the SoW system that is difficult to overcome by traditional soldering bonding methods, and effectively increase the reliability of the bonding between the SoW and the system main board;

[0021] 2) The present invention uses a small printed circuit board as an intermediate layer for bonding with the pogo pins on the wafer-level chiplet integration system and the system main board. The solder pads on the second surface of the printed circuit board array and the Pogo-pin are detachably connected, without soldering, and can be repeatedly pressed and separated, which is convenient for system upgrade and maintenance.

[0022] 3) The present invention uses a wafer pressing plate to strengthen the bonding between the pogo pins and the printed circuit board array. The wafer pressing plate uniformly applies pressure to the first surface of the wafer-level chiplet integration system, and to a certain extent, it can also improve the deformation of the wafer-level chiplet integration system, making the bonding between its second surface and the pogo pin array more reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a process flow chart of a method for realizing the interconnection structure between a wafer-level chiplet integration system and a system main board according to an embodiment of the present invention;

[0024] Figure 2 is an exploded view of the overall structure of the interconnection between a wafer-level chiplet integration system and a system main board according to an embodiment of the present invention;

[0025] Figure 3 is a cross-sectional view of the interior of the interconnection structure between a wafer-level chiplet integration system and a system main board according to an embodiment of the present invention;

[0026] Figure 4 is a structural diagram of a heat sink block according to an embodiment of the present invention;

[0027] Figure 5 is a structural diagram of a wafer pressing plate according to an embodiment of the present invention;

[0028] Figure 6 is a 3D structural diagram of the first surface of a wafer-level chiplet integration system according to an embodiment of the present invention;

[0029] Figure 7 is a 2D structural diagram of the second surface of a wafer-level chiplet integration system according to an embodiment of the present invention;

[0030] Figure 8 is a structural diagram of the second surface of a printed circuit board array according to an embodiment of the present invention;

[0031] Figure 9 is a structural diagram of the first surface of a printed circuit board array according to an embodiment of the present invention;

[0032] Figure 10 It is a side structure diagram of a wafer-level type II composite body in an embodiment of the present invention;

[0033] Figure 11 It is a second surface structure diagram of a wafer-level type II composite body in an embodiment of the present invention;

[0034] Figure 12 It is a structure diagram of a main body frame in an embodiment of the present invention;

[0035] Figure 13 It is a structure diagram of a registration hole plate in an embodiment of the present invention;

[0036] Figure 14 It is a structure diagram of a wafer carrier plate under the main board in an embodiment of the present invention.

[0037] In the figure: 1. Heat sink; 2. Wafer pressing plate; 3. SoW system; 4. PCB-let array; 5. Main body frame; 6. Plastic backing plate; 7. Pogo-pin spring pin; 8. Registration hole plate; 9. System main board; 10. Components on the board; 11. Carrier plate; 12. Wafer carrier plate backing plate; 13. Positioning screw; 14. Heat sink reserved hole; 15. Mounting screw hole; 16. Chiplet; 17. Silicon wafer; 18. C4 bump contacts on the surface of the SoW system; 19. Edge PCB-let; 20. Second surface pad of the edge PCB-let; 21. Intermediate PCB-let; 22. Pad of the intermediate PCB-let; 23. First surface pad of the PCB-let; 24. Reserved space for main board components; 25. First step; 26. Second step; 27. Reserved space for the registration hole plate; 28. Mounting screw hole for the wafer pressing plate; 29. Pogo-pin through hole; 30. Registration hole plate positioning post hole; 31. Reflow heat dissipation hole; 32. Mounting screw hole for the wafer carrier plate; 33. Reserved hole for decoupling capacitor. Detailed implementation manners

[0038] The present invention utilizes the elastic telescopic mechanism of the Pogo-pin spring pin to compensate for the overall warping of the wafer-level composite body, solves the problem that the wafer-level chiplet integrated chip and the large-size system main board cannot be effectively bonded, and at the same time, the present invention is compatible with and applicable to various (homogeneous and heterogeneous) wafer-level integrated interconnection systems of chiplets, and has the characteristics of being insensitive to warping, the wafer composite body and the system main board being separable, and being easy for system debugging.

[0039] The present invention will be further described below in conjunction with the accompanying drawings and specific examples. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. It should be understood that the present application is not limited by the example embodiments described herein. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application. Additionally, it should be noted that for the convenience of description, only the parts related to the present application rather than all are shown in the drawings.

[0040] Embodiment 1

[0041] The wafer-level chiplet integration system (SoW) is based on a whole silicon wafer, and multiple chiplets are tightly integrated, thereby expanding the chip area to the wafer level size and greatly enhancing the computing power of the system. The system main board is a double-sided PCB, and one side needs to achieve a reliable electrical connection with the SoW system. To realize the interconnection between the SoW system and the system main board, as Figure 2 , 3 shown, this embodiment provides an interconnection structure between a wafer-level chiplet integration system (SoW) and a system main board, including a wafer-level integrated packaging system 3 composed of multiple chiplets and a silicon wafer, a wafer pressing plate 2, multiple small printed circuit boards (PCB-lets), multiple Pogo-pin needles 7, an alignment hole plate 8, and a system main board 9;

[0042] The SoW system 3 is as Figure 6 , 7 shown, which is a double-sided wafer-level type I composite body, including a silicon wafer 17 and multiple chiplets 16. The chiplets 16 are only mounted on one side surface of the silicon wafer 17. The side with the mounted chiplets 16 is the first surface of the SoW system 3, and the other side is the second surface, which is provided with multiple bump contacts (C4 bump contacts are used in this embodiment) for mounting the PCB-let array 4. Multiple heat dissipation blocks 1 are arranged on the first surface of the SoW system 3, as Figure 4 shown. The heat dissipation blocks 1 are used to dissipate heat from the chiplets 16 to prevent the chiplets 16 from overheating. The material of the heat dissipation blocks 1 can be a semiconductor with good thermal conductivity.

[0043] Multiple small printed circuit boards form a printed circuit board array (PCB-let array) on the same plane. The PCB-let array 4 is composed of multiple PCB-lets. The PCB-let is a small-sized square PCB with pads on both sides and a redistribution layer (RDL) inside. As Figure 9 shown, the pads on one side surface of the PCB-let array 4 are smaller and have the same pad density as the pads on the second surface of the SoW system 3, which is the first surface of the PCB-let array 4. As Figure 8As shown, the pads on the second surface of the PCB-let array 4 are larger and sparser; the PCB-let array 4 is used to simplify the dense C4 bump contacts on the second surface of the SoW system 3, so that the density of the lead-out pads reaches the density achievable by the pogo pins. Specifically, the signals output by the C4 bump contacts with the same name on the second surface of the SoW system 3 are merged in the RDL layer inside the PCB-let, and then led out from the pads on the second surface of the PCB-let array 4. The signals that cannot be merged are directly led out from the pads on the second surface after passing through the RDL layer inside the PCB-let. The C4 bump contacts on the second surface of the SoW system 3 are bonded to the pads on the first surface of the PCB-let array 4 to form an electrical connection, so that the SoW system 3 and the PCB-let array 4 form a wafer-level type II composite body as shown in Figure 10 , multiple PCB-lets are closely mounted on the second surface of the SoW system 3 to form a PCB-let array 4 with a raised shape in a specific shape. At the same time, the power supply and signal pads on the second surface of the PCB-let array 4 form a power supply and signal pad array.

[0044] The Pogo-pin 7 is a retractable pogo pin, which includes a barrel and a needle tip, which form both ends of the pogo pin respectively. The barrel and the needle tip are connected by a spring. The needle tip can be compressed into the barrel under force. One end of the barrel is a needle seat that can be welded. The number of Pogo-pin 7 is the same as the number of pads in the power supply and signal pad array. Multiple Pogo-pin 7 are arranged in the arrangement of the pads in the power supply and signal pad array to form a Pogo-pin array, corresponding to the power supply and signal pad array. The alignment hole plate 8 has a double-sided structure, with through holes corresponding to the Pogo-pin array inside, called Pogo-pin through holes 29. One side has a groove-like structure corresponding to the raised shape of the PCB-let array 4, which is the first surface of the alignment hole plate 8, and the other side is the second surface of the alignment hole plate 8.

[0045] The system main board 9 is a double-sided PCB. The first surface of the system main board 9 has a pad array identical to the power supply and signal pad array, and the other side is the second surface of the system main board 9.

[0046] The socket of the Pogo-pin 7 is soldered to the pad array of the system main board 9 and inserted into the through holes of the alignment hole board 8. The needle tip exposes from the first surface of the alignment hole board 8. The raised PCB-let array 4 is embedded in the grooves corresponding to the shape on the first surface of the alignment hole board 8, realizing the electrical connection between the pad array on the second surface of the PCB-let and the Pogo-pin array, thereby realizing the electrical connection between the system main board 9 and the SoW system 3 as a whole. To ensure the reliability of the connection between the Pogo-pin and the power supply and signal pad arrays, the length of the Pogo-pin 7 should be greater than the warpage amount of the wafer-level type II composite, and the warpage amount refers to the maximum height difference of an object in the vertical direction.

[0047] The wafer pressing plate 2 is fixedly attached to the first surface of the SoW system 3 through structural members, realizing uniform pressure application to the first surface of the SoW system 3 to ensure sufficient bonding between the Pogo-pin array and the power supply and signal pad arrays on the PCB-let.

[0048] As a preferred solution of this embodiment, there is a redistribution layer inside the silicon wafer 17 in the SoW system 3 for electrical interconnection of both surfaces. The wafer pressing plate 2 is a rigid metal plate with a thickness of 3 - 10 mm, and there is also a reserved hole 14 for a heat sink in the middle of the wafer pressing plate 2. The Pogo-pin 7 is composed of a rigid metal with low resistivity, such as copper, etc. The alignment hole board 8 is made of an insulating and heat-resistant material.

[0049] The present invention utilizes the elastic telescopic mechanism of the Pogo-pin 7 itself to compensate for the overall warpage of the wafer-level composite, solving the problem that the wafer-level chiplet integrated chip and the large-size system main board 9 cannot be effectively bonded. The present invention utilizes the wafer pressing plate 2 and several fixing members to apply appropriate pressure on the chiplet side to ensure sufficient bonding between the Pogo-pin 7 and the pads on the PCB-let. The present invention improves the bonding reliability between the Pogo-pin 7 and the pads on the PCB-let through the alignment hole board 8 of the Pogo-pin 7, and realizes the alignment of the Pogo-pin array and the pad array by using the groove on one side of the needle tip of the alignment hole board 8. The present invention is compatible with and applicable to various (homogeneous and heterogeneous) wafer-level integrated interconnection systems of chiplets, and has the characteristics of being insensitive to warpage, the wafer composite and the system main board 9 being separable, and being easy for system debugging.

[0050] Embodiment 2

[0051] As Figure 1 shown, this embodiment provides a preparation method for the interconnection structure between the wafer-level chiplet integrated system and the system main board described in Embodiment 1, including the following steps:

[0052] Step 1): The second surface of the SoW system 3 is soldered to the first surface of the PCB-let array 4 through reflow soldering to complete the first-level interconnection and transition of the die 16 to the PCB-let array 4, forming a wafer-level Type II composite body;

[0053] Step 2): The Pogo-pin spring pins, the alignment hole plate, the system main board, and the components on the board are soldered together through reflow soldering;

[0054] Step 3): The main body frame 5 and the plastic backing plate 6 are fixed to the system main board with screws;

[0055] Step 4): The support plate 12 and the wafer support plate backing 11 are installed at the thimble on the second surface of the system main board;

[0056] Step 5): The heat sink 1 is mounted on the first surface of the SoW system 3, and the protrusions formed by the PCB-let array on its second surface are embedded in the groove structure on the first surface of the alignment hole plate;

[0057] Step 6): The wafer pressing plate is tightly pressed against the first surface of the SoW system through the structural connection member and fixed with screws to achieve the second-level interconnection and transition of the die to the system main board.

[0058] First, step S1 is executed, where the second surface of the SoW system 3 has Figure 7 the dense C4 bump contacts shown. The middle 8*8 part mainly leads out the power bump contacts, and the 8*1 parts on the upper, lower, left, and right edges mainly lead out the signal bump contacts. According to the C4 bump contact distribution on the second surface of the SoW system 3 and the working requirements, the PCB-lets are designed and manufactured. The size of a single PCB-let is about 20mm*20mm, and the thickness is about 1.6mm. Finally, the first surfaces of all the PCB-let arrays 4 are as Figure 9 shown, and the pad size is equivalent to the size of the C4 bump contacts 18 on the second surface of the SoW system 3. The second surface of the PCB-let is as Figure 8 shown. The large pads 22 on the middle 8*8 PCB-let array mainly lead out the merged bump contacts of the power part, with a diameter of about 3mm. The small pads 20 on the 8*1 PCB-let arrays on the upper, lower, left, and right edges mainly lead out the signal bump contacts, with a diameter of about 1.2mm. The Figure 7 shown C4 bump contact array is bonded to the Figure 9 shown pad array. To reduce the warping caused by the different thermal expansion coefficients of the silicon wafer and the PCB-let, the soldering process needs to be specially designed and process verification is carried out before actual mounting. Finally, the warping of the composite body is preferably within 2mm to meet the process requirements for manufacturing the Pogo-pin spring pins 7.

[0059] Then, step S2 is executed. The Pogo-pin 7 is customized to ensure that the warpage requirements of the wafer-level type II composite are met. Copper is selected as the material. The final telescopic length of the Pogo-pin 7 is about 1.8 mm. The barrel and the needle tip diameters of the Pogo-pin 7 in the middle power part are about 1.5 mm and 0.9 mm respectively. The barrel and the needle tip diameters of the Pogo-pin 7 in the edge signal part are about 1.2 mm and 0.6 mm respectively. The system main board 9 is designed and manufactured according to the chip working requirements and the distribution of the power and signal pad arrays. Among them, the on-board devices 10 of the system main board 9 are mainly distributed on the second surface, including the FPGA module, the power module, the interface module, etc. At the same time, decoupling capacitors need to be placed at the pin attachment positions on the second surface to ensure signal integrity and power integrity. Thinner surface-mounted devices can be placed in some areas on the first surface. The alignment hole board 8 is designed and manufactured according to the diameter and length of the Pogo-pin 7 and the distribution of the Pogo-pin array. The final obtained alignment hole board 8 is as Figure 13 shown. According to Figure 3 shown, there is a certain height of space between the alignment hole board 8 and the system main board 9 for heat dissipation during welding. According to Figure 13 shown, there are Pogo-pin through holes 29 on the alignment hole board 8, through holes for installing and positioning the alignment hole board, that is, alignment hole board positioning post holes 30, and through holes for heat dissipation during welding, that is, furnace passing heat dissipation holes 31. In order to reduce the probability of the welding pins being skewed, the Pogo-pin through holes 29 of the alignment hole board 8 are made as close as possible to the diameter of the Pogo-pin 7. If the Pogo-pin 7 is welded first and then the alignment hole board 8 is sleeved, it may occur that the needle tip array and the alignment hole array cannot be strictly aligned and the alignment hole board 8 cannot be sleeved. Therefore, it is selected to fix the alignment hole board 8 and the Pogo-pin 7 at the specified positions on the system main board 9 first and then weld them together through the furnace, which can avoid this problem. Among them, the alignment hole board 8 needs to be made of a heat-resistant and insulating rigid material. First, all the devices on the second surface are welded through the furnace, and then the Pogo-pin 7 and the remaining devices on the first surface are welded through the furnace.

[0060] Then, step S3 is executed. The main body frame 5 is as Figure 12As shown, it is made of aluminum alloy. Its core structure includes multi-level steps in the middle and a hollow part in the middle that has the same shape as the alignment orifice plate 8. The reserved space 27 of the alignment orifice plate is hollow, used to allow the alignment orifice plate 8 fixed on the first surface of the system main board 9 to be just snapped in. The second step 26 is an overall circular step, used to embed the wafer of the SoW system 3 to increase the structural stability. The first step 25 is an overall circular step, used to embed the wafer pressing plate 2 to increase the structural stability. There is also a reserved space 24 for main board devices on the main body frame 5, which is also hollow and is the space reserved for the devices on the first surface of the system main board 9. There needs to be a plastic cushion plate 6 between the main body frame 5 and the system main board 9 that has exactly the same shape as the lower surface of the system main board 9, used to buffer the pressure between the rigid main body frame 5 and the system main board 9. The cushion plate material can be PC material. After completing step S5, the Pogo-pin array on the first surface of the alignment orifice plate 8 is exposed from the 27 of the structural frame 5.

[0061] Then perform step S4. The position of the pallet 12 in the overall structure is as shown in Figure 2 and Figure 3 shown, and it is installed on the second surface of the system main board 9. The structure of the pallet 12 is as shown in Figure 14 shown. The overall material is aluminum alloy, and it is provided with a wafer pallet mounting screw hole 32 and a decoupling capacitor reserved hole 33. The decoupling capacitor reserved hole 33 is a through hole reserved for the installation position of the decoupling capacitor, and the wafer pallet mounting screw hole 32 is a screw hole for installation. Similar to step S5, a cushion plate is also needed between the pallet 12 and the system main board 9 to buffer the pressure, which is called the wafer pallet cushion plate 11, and the cushion plate material can be PC material.

[0062] Then perform step S5. The heat sink 1 and the first surface of the SoW system 3 can be bonded with silicone grease. Before bonding, the mounting positions of each heat sink 1 need to be drawn in advance to ensure that the heat sink 1 can pass through the heat sink reserved hole 14 of the wafer pressing plate 2. After fixing the heat sink 1, the wafer-level type II & heat sink composite body is integrally embedded into Figure 12 the multi-level steps and the hollow structure of the main body frame 5 in, as shown in Figure 13 shown. There are grooves on the first surface of the alignment orifice plate 8 that exactly correspond to the shape of the PCB-let array 4 as shown in Figure 11 shown. The PCB-let of the composite body is embedded therein, and at the same time the wafer is embedded into the second step 26.

[0063] Finally, perform step S6. The structure of the wafer pressing plate 2 is as shown in Figure 5 shown. After embedding the wafer pressing plate 2 into the first step 25 of the main body frame 5, use screws to fix the wafer pressing plate 2 to the structural member. After fixing, the wafer pressing plate 2 can uniformly apply pressure to the first surface of the SoW system 3, and to a certain extent improve the deformation of the wafer-level type II composite body, making the bonding between its second surface and the Pogo-pin array more reliable.

[0064] The present invention uses Pogo-pin spring pins to achieve the bonding of the SoW and the system motherboard. The telescoping of the spring pins can effectively solve the problem of SoW warping that is difficult to overcome by traditional welding bonding methods, and effectively increase the reliability of the bonding between the SoW and the system motherboard. At the same time, the present invention uses PCB-let as the intermediate layer for the bonding of the Pogo-pin spring pins on the SoW system and the system motherboard. The second-plane pads of the PCB-let and the Pogo-pin spring pins are separable connections, without the need for welding, and can be repeatedly pressed and separated, which is convenient for system upgrade and maintenance, and has high commercial utilization value.

[0065] The above-described embodiments merely represent several implementation manners of the present invention, and the description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent of the present invention. For those of ordinary skill in the art, without departing from the concept of the present invention, several deformations and improvements can still be made, and these all belong to the protection scope of the present invention.

Claims

1. An interconnection structure between a wafer-level chiplet integration system and a system motherboard, comprising a wafer-level chiplet integration system and a system motherboard, characterized in that, It also includes a wafer pressing plate, a printed circuit board array, spring pins, and an alignment hole plate; The wafer-level chiplet integration system includes a whole silicon wafer with chiplets mounted on its first surface and contacts provided on its second surface; the printed circuit board array consists of multiple printed circuit boards in the same plane, the first surface of each printed circuit board is bonded to the contacts of the wafer-level chiplet integration system, and the second surface is provided with a power supply and signal pad array; one side of the system main board is provided with pads corresponding to the power supply and signal pad array; The spring pin includes a barrel and a needle tip that are elastically interconnected. The barrel is provided with a needle base for welding. The number of spring pins is the same as the number of pads in the power supply and signal pad array; the alignment hole plate is provided with multiple through holes. The needle bases of the spring pins are welded to the pad array on the first surface of the system main board, and the needle tips pass through the through holes and contact the power supply and signal pad array to form an electrical connection; The wafer pressing plate is fixedly attached to the first surface of the wafer-level chiplet integration system to uniformly apply pressure to ensure the bonding of the spring pins to the power supply and signal pad array; The printed circuit board array is used for power supply and signal transmission of the chiplets. Both sides of the surface have pads. The pads on the first surface are small and dense, and the pads on the second surface are large and sparse. The signals output from the contacts on the second surface of the silicon wafer enter the interior of the printed circuit board array through the pads on the first surface of the printed circuit board array and are led out from the second surface through the internal redistribution layer, and some of the signals are merged in the redistribution layer; The length of the spring pin is greater than the warpage amount of the composite body composed of the wafer-level chiplet integration system and the printed circuit board array.

2. The interconnection structure between the wafer-level chiplet integration system and the system main board according to claim 1, characterized in that, The interconnection structure also includes a main body frame for mounting and fixing the wafer-level chiplet integration system, the alignment hole plate, and the system main board; one side surface of the main body frame facing the system main board is also provided with a layer of plastic cushion plate to buffer the pressure between the main body frame and the system main board; the surface of the alignment hole plate is also provided with a groove for embedding the printed circuit board array.

3. The interconnection structure between the wafer-level chiplet integration system and the system mainboard according to claim 2, wherein A heat sink is also mounted on the surface of the chiplets of the wafer-level chiplet integration system, and a through hole for the heat sink to pass through is provided in the middle of the wafer pressing plate.

4. The interconnection structure between the wafer-level chiplet integration system and the system motherboard according to claim 1, wherein The wafer-level chiplet integration system is a silicon wafer with multiple chiplets mounted on one side, and there is a redistribution layer inside the silicon wafer.

5. The interconnection structure between the wafer-level die integration system and the system motherboard according to claim 1, wherein The contacts are C4 bump contacts.

6. The interconnection structure between the wafer-level die integration system and the system motherboard according to claim 1, characterized in that The wafer pressing plate is a metal rigid flat plate with a thickness of 3 - 10 mm.

7. The interconnection structure between the wafer-level die integration system and the system main board according to claim 1, wherein, A space for welding and heat dissipation is left between the alignment hole plate and the system main board; the alignment hole plate is also provided with an oven through hole for welding and heat dissipation.

8. A method for preparing an interconnection structure between a wafer-level chiplet integration system and a system main board according to claim 3, characterized in that, It includes the following steps: 1) Perform oven welding on the second surface of the wafer-level chiplet integration system and the first surface of the printed circuit board array to complete the first-level interconnection and transition from the chiplets to the printed circuit board array; 2) Perform reflow welding on the spring pins, the alignment hole plate, the system main board, and the components on the board together; 3) Fix the main body frame, the plastic cushion plate, and the system main board through connectors; 4) Mount a heat sink on the first surface of the wafer-level chiplet integration system, and embed the printed circuit board array on the second surface of the wafer-level chiplet integration system into the groove structure on the first surface of the alignment hole plate; 5) Press the wafer pressing plate tightly against the first surface of the wafer-level chiplet integration system and fix it with connectors to achieve the second-level interconnection and transition from the chiplet array to the system main board.

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