A phase interpolator circuit with wideband high linearity and its CDR

Abstract

The present invention belongs to the technical field of phase interpolators, and particularly relates to a phase interpolator circuit with wide frequency and high linearity and its CDR. It includes: a quadrant selection module for coarsely adjusting the output clock phase of the phase interpolator and realizing the phase offset of four quadrant intervals; the input signal of the quadrant selection module is a four-phase clock signal with a wide range of frequencies provided by the PLL, and the output signal is an orthogonal differential clock signal; an amplitude adjustment module for adjusting the output clock amplitude VS1 to adjust the voltage conversion rate of the differential clock signal; a core interpolation circuit module for performing interpolation operations on the input differential clock signal and adjusting the tail current through an M+N-bit control bit adjustment signal to output a differential clock signal; a tail current control bit module for providing phase weight selection for the core interpolation circuit module. The overall phase interpolator of the present invention has the characteristics of wide output clock frequency and high linearity.

Description

Technical Field

[0001] The present invention belongs to the technical field of phase interpolators, and particularly relates to a phase interpolator circuit with wide frequency and high linearity and its CDR. Background Art

[0002] With the continuous improvement of the transmission rate of digital systems, higher requirements are put forward for the bit error rate. At the receiving end of a serial interface, the jitter of the sampling clock recovered by the CDR determines the bit error rate of the recovered sampling data. Among various structures of CDRs, the CDR based on a phase interpolator can achieve better loop stability and can share the PLL with multiple-phase clocks, and is widely used.

[0003] In a traditional phase interpolator, the tail current source consists of multiple equal-value current source arrays, and the weight control signal controls the current flow path of each current source, thereby adjusting the tail current magnitude of the differential pair of two input signals, so that the phase of the output signal interpolates between the phases of the two input signals. The relationship between the phase of the output signal obtained by this interpolation method and the weight control signal is non-linear, and the linearity of the interpolator is related to the phase difference between the two input signals. The larger the phase difference, the lower the linearity of the interpolator. Summary of the Invention

[0004] The purpose of the present invention is to provide a phase interpolator circuit with wide frequency and high linearity and its CDR. Based on the traditional phase interpolator, the overall phase interpolator of the present invention has the characteristics of wide output clock frequency and high linearity.

[0005] To solve the above technical problems, the present invention provides a phase interpolator circuit with wide frequency and high linearity, including:

[0006] A quadrant selection module for coarsely adjusting the phase of the output clock of the phase interpolator and realizing the phase offset of four quadrant intervals at 0° - 90°, 90° - 180°, 180° - 270°, and 270° - 360°; the input signals of the quadrant selection module are four-phase clock signals CLK0, CLK90, CLK180, and CLK270 with a wide range of frequencies provided by the PLL, and the output signals are orthogonal differential clock signals CLKQ, CLKQN, CLKI, and CLKIN;

[0007] An amplitude adjustment module for adjusting the amplitude VS1 of its output clock to adjust the voltage conversion rate of the differential clock signals CLKQ, CLKQN, CLKI, and CLKIN, so as to improve the linearity of the output clock of the phase interpolator;

[0008] The core interpolation circuit module uses a CML circuit to perform interpolation operations on the input differential clock signals CLKQ, CLKQN, CLKI, and CLKIN, and adjusts the tail current through the M+N-bit control bit adjustment signal to output the differential clock signals CLK_OUT and CLK_OUTN;

[0009] The tail current control bit module provides phase weight selection for the core interpolation circuit module, solves the non-linearity of the output clock caused by the setup time of the tail current switching during fine-tuning in the core interpolation circuit module through the M-bit control signal, and realizes the fine-tuning of the output phase of the phase interpolator through the N-bit control signal, and the phase accuracy of the fine-tuning is 90° / N.

[0010] Preferably, the quadrant selection module is composed of a first quadrant selection unit and a second quadrant selection unit, wherein both the first quadrant selection unit and the second quadrant selection unit include: capacitors C1~C4, switches S1~S8, inverters INV1~INV6, and resistors R1~R4;

[0011] Among them, one end of capacitor C1 is used as the clock signal input terminal, the other end of capacitor C1 is connected to one ends of switch S1, switch S4, and resistor R1, the other end of switch S1 is connected to the input terminal of inverter INV1, the output terminal of inverter INV1 is connected to the output terminal of inverter INV2 and is connected to one ends of capacitor C3, switch S7, and switch S8, the other end of capacitor C3 is connected to one end of resistor R3 and the input terminal of inverter INV5, and the output terminal of inverter INV5 is connected to the other end of resistor R3 and outputs a differential clock signal;

[0012] One end of capacitor C2 is used as the clock signal input terminal, the other end of capacitor C2 is connected to one ends of switch S2, switch S3, and resistor R2, the other end of switch S2 is connected to the input terminal of inverter INV2, the other end of switch S3 is connected to the input terminal of inverter INV3, the output terminal of inverter INV3 is connected to the output terminal of inverter INV4 and is connected to one ends of capacitor C4, switch S5, and switch S6, the other end of switch S4 is connected to the input terminal of inverter INV4, the other end of capacitor C4 is connected to one end of resistor R4 and the input terminal of inverter INV6, and the output terminal of inverter INV6 is connected to the other end of resistor R4 and outputs a differential clock signal;

[0013] The other end of resistor R1 is connected to the other ends of switch S5 and switch S8, and the other end of resistor R2 is connected to the other ends of switch S6 and switch S7.

[0014] Preferably, it further includes the control signals SI, SIN, SQ, and SQN provided by the digital module;

[0015] In the first quadrant selection unit, the control signal SI is used to control switches S1, S3, S6, and S8, and the control signal SIN is used to control switches S2, S4, S5, and S7;

[0016] In the second quadrant selection unit, the control signal SQ is used to control switches S1, S3, S6, and S8, and the control signal SQN is used to control switches S2, S4, S5, and S7.

[0017] Preferably, inverters INV1~INV4 use the same structure, inverters INV5~INV6 use the same structure, the power supply voltage of inverters INV1~INV6 is provided by the amplitude VS1, the low potential is connected to the ground terminal, and the maximum output voltage amplitude range is GND~VS1.

[0018] Preferably, in the first quadrant selection unit, one end of the capacitor C1 is used to input the clock signal CLK0, one end of the capacitor C2 is used to input the clock signal CLK180, the output end of the inverter INV5 is used to output the differential clock signal CLKI, and the output end of the inverter INV6 is used to output the differential clock signal CLKIN;

[0019] In the second quadrant selection unit, one end of the capacitor C1 is used to input the clock signal CLK90, one end of the capacitor C2 is used to input the clock signal CLK270, the output end of the inverter INV5 is used to output the differential clock signal CLKQ, and the output end of the inverter INV6 is used to output the differential clock signal CLKQN.

[0020] Preferably, the amplitude adjustment module uses an LDO for amplitude adjustment, which specifically includes: an operational amplifier AMP1, a driving transistor M1, and a feedback resistor R5; the positive input terminal of the operational amplifier AMP1 is connected to the input signal VP1, and the input signal VP1 is a voltage generated by the reference module. The negative input terminal of the operational amplifier AMP1 is connected to one end of the feedback resistor R5 and the current IBIAS1. The other end of the current IBIAS1 is grounded, and the current IBIAS1 is an adjustable current generated by the reference module. The output terminal of the operational amplifier AMP1 is connected to the gate terminal of the driving transistor M1. The source terminal of the driving transistor M1 is connected to the voltage VDD1, and the drain terminal of the driving transistor M1 is connected to the other end of the feedback resistor R5 and the amplitude VS1. The amplitude VS1 is the output voltage of the amplitude adjustment module and serves as the power supply voltage of the quadrant selection module, and VS1 = VP1 + IBIAS1 × R5.

[0021] Preferably, the core interpolation circuit module is a phase interpolation structure of an equal-value tail current array, and the unit reference current of the tail current is an adjustable reference current I0, which specifically includes:

[0022] The I-channel reference current part and the Q-channel reference current part have the same structure, and both include M pairs of NMOS transistors. Each pair of NMOS transistors consists of a first NMOS transistor and a second NMOS transistor. The gate terminals of the first NMOS transistor and the second NMOS transistor are connected to the reference voltage VREF and input signals. The source terminals of the first NMOS transistor and the second NMOS transistor are connected and connected to the grounded reference current I0 through a control switch. The drain terminal of the first NMOS transistor is connected to one end of the resistor RI and outputs a signal, and the other end of the resistor RI is connected to the voltage VDD1. The drain terminal of the second NMOS transistor is connected to one end of the resistor RQ and outputs a signal, and the other end of the resistor RQ is connected to the voltage VDD1.

[0023] The I-channel interpolation current part and the Q-channel interpolation current part have the same structure, and both include N pairs of NMOS transistors. Each pair of NMOS transistors consists of a third NMOS transistor and a fourth NMOS transistor. The gate terminal of the third NMOS transistor is connected to the differential clock signal and serves as a differential input signal, and the gate terminal of the fourth NMOS transistor is connected to the differential clock signal and serves as a differential input signal. The source terminals of the third NMOS transistor and the fourth NMOS transistor are connected and connected to the grounded reference current I0 through an interpolation current switch. The drain terminal of the third NMOS transistor is connected to one end of the resistor RI and outputs a signal, and the other end of the resistor RI is connected to the voltage VDD1. The drain terminal of the fourth NMOS transistor is connected to one end of the resistor RQ and outputs a signal, and the other end of the resistor RQ is connected to the voltage VDD1.

[0024] Preferably, the tail current selection function of the I-channel reference current part is realized by controlling switches DI0~DIM, and the tail current selection function of the I-channel interpolation current part is realized by interpolation current switches AI0~AIN.

[0025] Similarly, the tail current selection function of the Q-channel reference current part is realized by controlling switches DQ0~DQM, and the tail current selection function of the Q-channel interpolation current part is realized by interpolation current switches AQ0~AQN.

[0026] Preferably, a control signal is provided by a digital module as the input signal of the tail current control bit module, and the output signal of the tail current control bit module serves as the control signal for the control switches DI0~DIM, the control switches DQ0~DQM, the interpolation current switches AI0~AIN, and the interpolation current switches AQ0~AQN.

[0027] The present invention also provides a CDR for a high-speed SERDES interface, which adopts a phase interpolator circuit with wideband high linearity as described above.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] Based on the traditional phase interpolator, the overall phase interpolator of the present invention has the characteristics of a wide output clock frequency range and high linearity. First, the four-phase clock generated by the PLL is coarsely adjusted. The quadrant selection module is used to achieve the coarse adjustment of the output clock phase, and the amplitude adjustment module is used to achieve the clock amplitude adjustment. Then, the core interpolation circuit module and the tail current adjustment module are used to achieve the fine adjustment of the clock phase. Finally, the entire phase interpolator can achieve phase adjustment from 0° to 360°, and the phase interpolator applied to the clock data recovery circuit (CDR) of the high-speed SERDES interface has the characteristics of wide frequency and high linearity. Description of the Drawings

[0030] Figure 1 It is a schematic diagram of the overall structure of the phase interpolator of the present invention.

[0031] Figure 2 It is a schematic diagram of the structure of the first quadrant selection unit in the quadrant selection module of the present invention.

[0032] Figure 3 It is a schematic diagram of the structure of the second quadrant selection unit in the quadrant selection module of the present invention.

[0033] Figure 4 It is a schematic diagram of the structure of the amplitude adjustment module of the present invention.

[0034] Figure 5 It is a schematic diagram of the structure of the I-channel and Q-channel interpolation current parts in the core interpolation circuit module of the present invention.

[0035] Figure 6 It is a specific schematic diagram of the structure of the I-channel interpolation current part in the core interpolation circuit module of the present invention.

[0036] Figure 7 It is a specific schematic diagram of the structure of the Q-channel interpolation current part in the core interpolation circuit module of the present invention.

[0037] Figure 8 It is a specific schematic diagram of the structure of the I-channel reference current part in the core interpolation circuit module of the present invention.

[0038] Figure 9 It is a specific schematic diagram of the structure of the Q-channel reference current part in the core interpolation circuit module of the present invention.

[0039] Figure 10 It is a schematic diagram of the structure of the tail current control bit module of the present invention. Detailed Embodiments

[0040] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the embodiments of the present invention.

[0041] As Figure 1 shown, the embodiment of the present invention specifically provides a phase interpolator circuit with wide frequency and high linearity in a clock data recovery circuit (CDR) applied to a high-speed SERDES interface, which includes a quadrant selection module, an amplitude adjustment module, a core interpolation circuit module, and a tail current control bit module.

[0042] The quadrant selection module realizes the coarse adjustment of the output clock phase of the phase interpolator, realizes the phase offset in the four quadrant intervals of 0~90°, 90~180°, 180~270°, and 270~360°. The input is a four-phase clock signal CLK0, CLK90, CLK180, CLK270 with a wide range of frequencies provided by the PLL, and the output signals are CLKQ, CLKQN, CLKI, CLKIN. Among them, CLKQ and CLKQN have the same clock frequency and opposite phases. Similarly, CLKI and CLKIN have the same clock frequency and opposite phases. The differential clock signal reduces the common-mode interference.

[0043] The amplitude adjustment module adjusts the output clock amplitude VS1 of the amplitude adjustment module. By adjusting the amplitude VS1, the voltage conversion rate of the output signals CLKQ, CLKQN, CLKI, and CLKIN is adjusted. An appropriate voltage conversion rate can improve the linearity of the output clock of the phase interpolator.

[0044] The tail current control bit module provides the phase weight selection of the core interpolation circuit, solves the non-linearity of the output clock caused by the setup time of the tail current switching during fine adjustment in the core interpolation circuit through the M-bit control signal, realizes the fine adjustment of the output phase of the phase interpolator through the N-bit control signal, and the fine adjustment phase accuracy is 90° / N. Through the combination of the M+N-bit control bit adjustment signal, the goal of ensuring high linearity and high accuracy of the output clock of the phase interpolator in the full range of the four quadrant intervals is realized.

[0045] The core interpolation circuit uses a CML (Current Mode Logic) circuit to perform interpolation operations on the input quadrature differential clock signals CLKQ, CLKQN, CLKI, and CLKIN, adjusts the tail current through the M+N-bit control bit adjustment signal, and realizes the output differential clock signals CLK_OUT and CLK_OUTN. The differential clock signals CLK_OUT and CLK_OUTN output by the entire phase interpolator have the characteristics of wide frequency, high linearity, and high phase shift accuracy.

[0046] such as Figure 2 and Figure 3As shown, the input signals CLK0, CLK90, CLK180, and CLK270 of the quadrant selection module are provided by the PLL, with the provided clock frequency range being 1 GHz to 20 GHz, and the output clock frequencies of CLKI, CLKIN, CLKQ, and CLKQN can also reach 1 GHz to 20 GHz. The circuit structure description: The input signal CLK0 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to one end of the switch S1, switch S4, and resistor R1. The other end of the switch S1 is connected to the input end of the inverter INV1. The output end of the inverter INV1 is connected to one end of the capacitor C3, switch S7, switch S8, and the output end of the inverter INV2. The other end of the capacitor C3 is connected to one end of the resistor R3 and the input end of the inverter INV5. The output end of the inverter INV5 is connected to the other end of the resistor R3 and outputs the signal CLKI. The input signal CLK180 is connected to one end of the capacitor C2, and the other end of the capacitor C2 is connected to one end of the switch S2, switch S3, and resistor R2. The other end of the switch S3 is connected to the input end of the inverter INV3. The output end of the inverter INV3 is connected to one end of the capacitor C4, switch S5, switch S6, and the output end of the inverter INV4. The other end of the capacitor C4 is connected to one end of the resistor R4 and the input end of the inverter INV6. The output end of the inverter INV6 is connected to the other end of the resistor R4 and outputs the signal CLKIN. One end of the switch S2 is connected to one end of the capacitor C2, switch S3, and the input end of the inverter INV2. The output end of the inverter INV2 is connected to the output end of the inverter INV1, one end of the capacitor C3, switch S7, and switch S8. One end of the switch S4 is connected to one end of the capacitor C2, switch S1, and the input end of the inverter INV4. The output end of the inverter INV4 is connected to the output end of the inverter INV3, one end of the capacitor C4, switch S5, and switch S6. One end of the resistor R1 is connected to C1, and the other end is connected to switch S5 and switch S8. One end of the resistor R2 is connected to the capacitor C2, and the other end is connected to switch S6 and switch S7. The control signal SI provided by the digital module is used to control the switches S1, S3, S6, and S8. The control signal SIN has an opposite relationship with the control signal SI, and SIN is used to control the switches S2, S4, S5, and S7. The inverters INV1, INV2, INV3, and INV4 use the same structure. The power supply voltage is provided by VS1, the low potential is connected to the ground terminal, and the maximum output voltage amplitude range is GND to VS1. The inverters INV5 and INV6 use the same structure. The input signals CLK90 and CLK270 pass through the same structure and can obtain the output signals CLKQ and CLKQN. The difference in the structure lies in the control signals SQ and SQN provided by the digital module. The four-quadrant selection function is realized through the control signals SI, SIN, SQ, and SQN provided by the digital module, realizing the link selection from the input clock signal to the output clock signal.For example, SI and SQ simultaneously give the same low-level control signal, causing switches S1, S3, S6, and S8 to open simultaneously. SIN and SQN correspond to the same high-level signal, causing switches S2, S4, S5, and S7 to close simultaneously. This enables the clock signal CLK0 to reach the DC-blocking capacitor C1, pass through switch S2 to the input terminal of the inverter INV4, change the driving ability of the signal, then reach the DC-blocking capacitor C4, and obtain the output signal CLKIN after being driven and amplified by INV6. The closing of switch S7 enables the resistor R1 to serve as the feedback resistor of the inverter INV4, thereby realizing the output link from CLK0 to CLKIN. Similarly, the output links from CLK180 to CLKIN, CLK90 to CLKQN, and CKL270 to CLKQ are realized.

[0047] As Figure 4 shown, the amplitude adjustment module uses an LDO for amplitude adjustment. The input signal VP1 is the voltage generated by the reference module. VP1 is connected to the positive input terminal of the operational amplifier AMP1. The negative input terminal VN1 of the operational amplifier AMP1 is connected to one end of the resistor R5 to form a feedback. The current IBIAS1 is the adjustable current generated by the reference module and is connected to the resistor R5 and the negative input terminal VN1 of the operational amplifier AMP1. The gate terminal of the output driving transistor M1 is connected to the output terminal of the operational amplifier. The source terminal of the output driving transistor M1 is connected to the voltage VDD1. The output voltage VS1 of the amplitude adjustment module is VS1 = VP1 + IBIAS1 × R5. Taking the output voltage VS1 as the power supply voltage of the quadrant selection module, through the structures of the quadrant selection module and the amplitude adjustment module, the function of different swing capabilities of the differential output signals CLKI and CLKIN, CLKQ and CLKQN can be realized, serving as the input differential signals for the next-stage core interpolation circuit. Ideally, the adjusted clock signals CLKI, CLKIN, CLKQ, and CLKQN are approximately triangular waves.

[0048] As Figures 5 to 9As shown, the core interpolation circuit module is a phase interpolation structure of an equivalent tail current array. The unit reference current of the tail current is I0, which is an adjustable reference current. The I-channel control switches DI0~DIM implement the function of selecting the tail current for the I-channel reference current part, and the I-channel interpolation current switches AI0~AIN implement the function of selecting the tail current for the I-channel interpolation current part. Similarly, the Q-channel control switches DQ0~DQM implement the function of selecting the tail current for the Q-channel reference current part, and the Q-channel interpolation current switches AQ0~AQN implement the function of selecting the tail current for the Q-channel interpolation current part. Under different conditions of closing or opening the switches DI0~DIM, AI0~AIN, DQ0~DQM, and AQ0~AQN in the equivalent tail current structure, the overall tail current value is the same, the currents flowing through the resistors RI and RQ are the same, the output swing is guaranteed to be the same, and the linearity of the interpolation output is improved. The input signal of the I-channel reference current part is the reference voltage VREF, which is connected to the gate terminals of the NMOS transistors MDI00, MDI01, MDI10, MDI11…MDIM0, MDIM1. In the I-channel interpolation current part, CLKI is connected to the gate terminals of the NMOS transistors MAI00, MAI10…MAIN0, and the differential input signal CLKIN is connected to the gate terminals of the NMOS transistors MAI01, MAI11…MAIN1. Similarly, the input signal of the Q-channel reference current part is the reference voltage VREF, which is connected to the gate terminals of the NMOS transistors MDQ00, MDQ01, MDQ10, MDQ11…MDQM0, MDQM1. In the Q-channel interpolation current part, CLKQ is connected to the gate terminals of the NMOS transistors MAQ00, MAQ10…MAQN0, and the differential input signal CLKQN is connected to the gate terminals of the NMOS transistors MAQ01, MAQ11…MAQN1. The gate terminals of a total of M+N NMOS transistors MDI00, MDI10…MDIM0, MAI00, MAI10…MAIN0, MDQ00, MDQ10…MDQM0, and MAQ00, MAQ10…MAQN0 are connected to one end of the resistor RI, and the other end of the resistor RI is connected to the voltage VDD1. Similarly, for M+N NMOS transistors connected to one end of the resistor RQ, the other end of RQ is connected to the voltage VDD1. By controlling the tail current through AI0~AIN and AQ0~AQM, phase adjustment with N-bit precision can be achieved, and fine adjustment with a step size of 90° / N can be realized within the 0~360° four-quadrant range. Through the cooperation of the control signals DI0~DIM, DQ0~DQM and AI0~AIN, AQ0~AQM, the phase change within the 0~360° four-quadrant range can be made more linear, reducing clock jitter.

[0049] As Figure 10As shown, the input signal of the tail current control bit module is the control signal provided by the digital module, which realizes the output control signals DI0~DIM, AI0~AIN, DQ0~DQM, AQ0~AQM. The output control signals DI0~DIM are given to the I-channel reference current part of the core interpolation circuit module, and the output control signals AI0~AIN are given to the I-channel interpolated current part of the core interpolation circuit module. Similarly, the output control signals DQ0~DQM are given to the Q-channel reference current part of the core interpolation circuit module, and the output control signals DQ0~DQM are given to the Q-channel interpolated current part of the core interpolation circuit module.

[0050] In summary, when the phase interpolator of the present invention is used, first, the four-phase clocks CLK0, CLK90, CLK180, and CLK270 generated by the PLL are coarsely adjusted. The quadrant selection module is used to realize the selection of four quadrants, and the amplitude adjustment module is used to realize the clock amplitude adjustment. Then, the core interpolation circuit module and the tail current adjustment module are used to finally realize the phase adjustment of the clock CLK_OUT from 0° to 360°. The phase interpolator applied to the clock data recovery circuit (CDR) of the high-speed SERDES interface has the characteristics of wide frequency, high linearity, and low jitter.

[0051] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the field of the present invention according to the above disclosure are within the scope of protection of the claims.

Claims

1. A phase interpolator circuit with wideband and high linearity, characterized in that: include: A quadrant selection module is used to shift the phases of the four quadrant intervals between 0° and 90°, 90° and 180°, 180° and 270° and 270° and 360° to achieve coarse phase adjustment; the input signal of the quadrant selection module is the four-phase clock signals CLK0, CLK90, CLK180 and CLK270 with a wide range of frequencies provided by the PLL, and the output signal is the orthogonal differential clock signals CLKQ, CLKQN, CLKI and CLKIN; An amplitude adjustment module, which adjusts the output voltage VS1 of the amplitude adjustment module to adjust the voltage conversion rate of the differential clock signals CLKQ, CLKQN, CLKI and CLKIN, thereby improving the linearity of the output clock of the phase interpolator; The core interpolation circuit module uses a CML circuit to perform interpolation operations on the input differential clock signals CLKQ, CLKQN, CLKI and CLKIN, and adjusts the tail current through the control bit adjustment signal of 0~M bits and 0~N bits to output differential clock signals CLK_OUT and CLK_OUTN; The tail current control bit module provides phase weight selection for the core interpolation circuit module, solves the nonlinearity of the output clock of the core interpolation circuit module caused by the establishment time of the tail current switching during fine adjustment through the 0~M bit control signal, and realizes the fine adjustment of the output phase of the phase interpolator through the 0~N bit control signal, and the fine adjustment phase accuracy is 90° / (N+1); The quadrant selection module is composed of a first quadrant selection unit and a second quadrant selection unit, wherein the first quadrant selection unit and the second quadrant selection unit both include: capacitors C1-C4, switches S1-S8, inverters INV1-INV6 and resistors R1-R4; Among them, one end of the capacitor C1 is used as the clock signal input end, the other end of the capacitor C1 is connected to the switch S1, the switch S4 and one end of the resistor R1, the other end of the switch S1 is connected to the input end of the inverter INV1, the output end of the inverter INV1 is connected to the output end of the inverter INV2 and to one end of the capacitor C3, the switch S7 and the switch S8, the other end of the capacitor C3 is connected to one end of the resistor R3 and the input end of the inverter INV5, the output end of the inverter INV5 is connected to the other end of the resistor R3 and outputs a differential clock signal; One end of the capacitor C2 serves as a clock signal input end, the other end of the capacitor C2 is connected to the switch S2, the switch S3 and one end of the resistor R2, the other end of the switch S2 is connected to the input end of the inverter INV2, the other end of the switch S3 is connected to the input end of the inverter INV3, the output end of the inverter INV3 is connected to the output end of the inverter INV4 and to one end of the capacitor C4, the switch S5 and the switch S6, the other end of the switch S4 is connected to the input end of the inverter INV4, the other end of the capacitor C4 is connected to one end of the resistor R4 and the input end of the inverter INV6, the output end of the inverter INV6 is connected to the other end of the resistor R4 and outputs a differential clock signal; The other end of the resistor R1 is connected to the other ends of the switch S5 and the switch S8 , and the other end of the resistor R2 is connected to the other ends of the switch S6 and the switch S7 .

2. A phase interpolator circuit with wideband and high linearity as claimed in claim 1, characterized in that: Also included are control signals SI, SIN, SQ and SQN provided by the digital module; In the first quadrant selection unit, the control signal SI is used to control switches S1, S3, S6 and S8, and the control signal SIN is used to control switches S2, S4, S5 and S7; In the second quadrant selection unit, the control signal SQ is used to control switches S1, S3, S6 and S8, and the control signal SQN is used to control switches S2, S4, S5 and S7.

3. A phase interpolator circuit with wideband and high linearity as claimed in claim 1, characterized in that: Inverters INV1~INV4 use the same structure, inverters INV5~INV6 use the same structure, the power supply voltage of inverters INV1~INV6 is provided by amplitude VS1, the low potential is connected to the ground, and the maximum output voltage amplitude range is GND~VS1.

4. A phase interpolator circuit with wideband and high linearity as claimed in claim 1, characterized in that: In the first quadrant selection unit, one end of the capacitor C1 is used to input the clock signal CLK0, one end of the capacitor C2 is used to input the clock signal CLK180, the output end of the inverter INV5 is used to output the differential clock signal CLKI, and the output end of the inverter INV6 is used to output the differential clock signal CLKIN; In the second quadrant selection unit, one end of the capacitor C1 is used to input the clock signal CLK90, one end of the capacitor C2 is used to input the clock signal CLK270, the output end of the inverter INV5 is used to output the differential clock signal CLKQ, and the output end of the inverter INV6 is used to output the differential clock signal CLKQN.

5. A phase interpolator circuit with wideband and high linearity as claimed in claim 1, characterized in that: The amplitude adjustment module uses LDO for amplitude adjustment, and specifically includes: an operational amplifier AMP1, a driving tube M1 and a feedback resistor R5; the positive input terminal of the operational amplifier AMP1 is connected to the input signal VP1, and the input signal VP1 is a voltage generated by the reference module, the negative input terminal of the operational amplifier AMP1 is connected to the feedback resistor R5 and one end of the current IBIAS1, the other end of the current IBIAS1 is grounded, and the current IBIAS1 is an adjustable current generated by the reference module, the output terminal of the operational amplifier AMP1 is connected to the gate terminal of the driving tube M1, the source terminal of the driving tube M1 is connected to the voltage VDD1, the drain terminal of the driving tube M1 is connected to the other end of the feedback resistor R5 and the amplitude VS1, the amplitude VS1 is the output voltage of the amplitude adjustment module, and is used as the power supply voltage of the quadrant selection module, and VS1=VP1+IBIAS1×R5.

6. A phase interpolator circuit with wideband and high linearity as claimed in claim 1, characterized in that: The core interpolation circuit module is a phase interpolation structure of an equal value tail current array, and the unit reference current of the tail current is an adjustable reference current I0, specifically including: The I-channel reference current part and the Q-channel reference current part have the same structure and both include M NMOS tube pairs, each of which is composed of a first NMOS tube and a second NMOS tube; the gate terminals of the first NMOS tube and the second NMOS tube are connected to the reference voltage VREF and input signals; the source terminals of the first NMOS tube and the second NMOS tube are connected and connected to the grounded reference current I0 through a control switch; the drain terminal of the first NMOS tube is connected to one end of the resistor RI and outputs a signal, and the other end of the resistor RI is connected to the voltage VDD1; the drain terminal of the second NMOS tube is connected to one end of the resistor RQ and outputs a signal, and the other end of the resistor RQ is connected to the voltage VDD1; The I-path interpolation current part and the Q-path interpolation current part have the same structure, both of which include N NMOS tube pairs, each of which is composed of a third NMOS tube and a fourth NMOS tube; the gate end of the third NMOS tube is connected to the differential clock signal and used as a differential input signal, and the gate end of the fourth NMOS tube is connected to the differential clock signal and used as a differential input signal; the source ends of the third NMOS tube and the fourth NMOS tube are connected and connected to the grounded reference current I0 through the interpolation current switch; the drain end of the third NMOS tube is connected to one end of the resistor RI and outputs a signal, and the other end of the resistor RI is connected to the voltage VDD1; the drain end of the fourth NMOS tube is connected to one end of the resistor RQ and outputs a signal, and the other end of the resistor RQ is connected to the voltage VDD1.

7. A phase interpolator circuit with wideband and high linearity as claimed in claim 6, characterized in that: The tail current selection function of the reference current part of the I channel is realized by controlling the switches DI0~DIM, and the tail current selection function of the interpolation current part of the I channel is realized by the interpolation current switches AI0~AIN; Similarly, the tail current selection function of the Q-path reference current part is realized by controlling the switches DQ0~DQM, and the tail current selection function of the Q-path interpolation current part is realized by the interpolation current switches AQ0~AQN.

8. A phase interpolator circuit with wideband and high linearity as claimed in claim 7, characterized in that: A control signal is provided through a digital module as an input signal of the tail current control bit module, and an output signal of the tail current control bit module is used as a control signal of control switches DI0~DIM, control switches DQ0~DQM, interpolation current switches AI0~AIN and interpolation current switches AQ0~AQN.

9. A CDR for a high-speed SERDES interface, characterized in that: A phase interpolator circuit with wide bandwidth and high linearity as described in any one of claims 1 to 8 is used.

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