Level conversion circuit

Abstract

The invention discloses a level conversion circuit, which is characterized in that a bias voltage VBIAS circuit is adopted, and logic level signals of a low voltage domain are input from source ends of NMOS (N-channel Metal Oxide Semiconductor) tubes M21 and M22, so that the current output capability of the NMOS tubes M21 and M22 is enhanced, the speed of the level conversion circuit is improved, and the level conversion circuit can work at a lower power supply voltage. When the level conversion circuit is enabled, the bias tube MBIAS does not have a body effect, the NMOS tube M21 or M22 has a body effect, the NMOS tube M21 or M22 is closed due to a threshold voltage difference brought by the body effect of the MOS tube, and the level conversion circuit has zero static power consumption; the bias tube MBIAS and the NMOS tubes M21 and M22 are both thick-gate NMOS tubes and have good matching performance, so that the speed and static leakage current of the level conversion circuit are small in change along with the process. When the number of the level conversion circuits is large, the same bias circuit can be shared, and the power consumption of the circuit is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a level conversion circuit. Background Art

[0002] Level conversion circuits are widely used in the field of integrated circuits, such as memory, input / output interface circuits or analog circuits (power management, charge pumps, analog-to-digital / digital-to-analog converters, etc.). In these integrated circuits, different module circuits may operate in different voltage domains, and the logic signals of these different voltage domains can interact through level conversion circuits. Since level conversion circuits introduce additional delays, high-speed circuits often require level conversion circuits with small delays, that is, fast speeds. In addition, in some integrated circuits, the number of level conversion circuits may be very large, so the level conversion circuits are also required to have low power consumption.

[0003] Conventional level conversion circuits such as Figure 1 As shown, the NMOS tube M 11 and M 12 、PMOS tube M 13 and M 14 , and inverter I 10 The logic signal D and its inverted signal DZ and the inverter I 10 Working in low voltage domain V DDL MOS tube M 11 、M 12 、M 13 、M 14 Working in high voltage domain V DDH , so they generally use thick-grid tubes.

[0004] When D=0, that is, D is V DDL When the low voltage domain is at a logic low level, DZ = 1, that is, DZ is V DDL Low voltage domain logic high level, M 11 Close, M 12 Open → OUT = 0, output V DDH The high voltage domain logic low level, that is, the level conversion circuit converts the low voltage domain logic low level into the high voltage domain logic low level; in addition, due to the M 13 Open, the voltage of OUTN is V DDH , so that M 14 Closed; due to M 11 In the off state, there is no static leakage current in the whole circuit.

[0005] When D=1, that is, D is V DDL When the low voltage domain is at a logic high level, DZ = 0, that is, DZ is V DDL Low voltage domain logic low level, M 11 Open, M12 Close → OUTN = 0 → M 14 Open, OUT=1, output V DDH The high voltage domain logic high level, that is, the level conversion circuit converts the low voltage domain logic high level into the high voltage domain logic high level; in addition, due to the M 14 Open, the voltage at OUT is V DDH , so that M 13 Closed; due to M 12 In the off state, there is no static leakage current in the whole circuit.

[0006] From the above, we can see that the correct flipping condition of the traditional level conversion circuit is that the NMOS tube M 11 and M 12 The current output capability is stronger than that of PMOS tube M 13 and M 14 Assume that M 11 and M 12 Same size, M 13 and M 14 For MOS tubes of the same size, the I / V characteristics conform to the square law, that is, I(M 11 )=I(M 12 )= (1) I(M 13 )=I(M 14 )= = (2) and are the mobilities of electrons and holes, respectively, is the unit capacitance of the gate oxide layer, and is the gate width of NMOS and PMOS tubes, and They are the gate lengths of NMOS and PMOS transistors respectively. and They are the voltages between the gate and source of the NMOS tube and the PMOS tube respectively. and They are the threshold voltages of NMOS and PMOS tubes respectively.

[0007] The disadvantage of the traditional level conversion circuit is that it is affected by V DDL The influence of V DDL =1.2V, V DDH =3.3V, due to M 11 and M 12 All of them are thick gate transistors, and their threshold voltage is relatively high. From equations (1) and (2), we can see that in order to ensure the correct flipping of the level conversion circuit, it is generally necessary to use Larger, Smaller. But when V DDL Slightly higher When the driving current is too small, the level conversion speed becomes very slow and cannot meet the requirements of some high-speed integrated circuits. DDL <= When this happens, traditional level conversion circuits will not work properly. Summary of the invention

[0008] The object of the present invention is to provide a level conversion circuit to solve the problems in the background technology.

[0009] In order to solve the above technical problems, the present invention provides a level conversion circuit, including an NMOS tube M 21 and M 22 、PMOS tube M 23 and M 24 , Inverter I 20 and I 21 , switches SW1~SW5, bias tube M BIAS , bias current I BIAS ; NMOS tube M 21 The substrate end and NMOS tube M 22 The substrate ends of the inverter I 20 The input end is connected to the logic signal D, and the output end is connected to the NMOS tube M 21 The source terminal and inverter I 21 The input terminal of the inverter I 21 The output terminal is connected to NMOS tube M 22 The source end of NMOS tube M 21 The gate terminal and NMOS tube M 22 The gate end of NMOS tube M 21 The drain end is connected to the PMOS tube M 23 The drain end and PMOS tube M 24 The gate terminal of NMOS tube M 22 The drain end is connected to the PMOS tube M 24 The drain end and PMOS tube M 23 Gate terminal of PMOS tube M 23 and M 24 The source terminals are connected to the high voltage domain V DDH ; Bias Current I BIAS The input terminal is connected to the high voltage domain V DDH , the output end is connected to the bias tube M BIAS The drain end of the switch SW3, the first end of the NMOS tube M 21 The gate terminal and NMOS tube M 22The gate terminal of the switch SW3 is connected to the ground; the second terminal of the bias tube M BIAS The gate end is connected to the first end of the switch SW3, the substrate end is connected to the first end of the switch SW1 and the first end of the switch SW2, the second end of the switch SW1 is connected to the bias transistor M BIAS The source terminals are connected to the low voltage domain V DDL , the second end of the switch SW2 is grounded; The first terminal of the switch SW5 is connected to the high voltage domain V DDH The second terminal is connected to NMOS tube M 22 The first terminal of the switch SW4 is connected to the NMOS tube M 22 The drain terminal of the device is connected to the ground, and the second terminal is connected to the ground.

[0010] In one embodiment, the NMOS transistor M 21 and M 22 、PMOS tube M 23 and M 24 and bias tube M BIAS All are thick-gate devices.

[0011] In one embodiment, the switch SW4 and the switch SW5 are a pull-down switch and a pull-up switch, respectively; when the level conversion circuit is not enabled, the switch SW4 is opened by a PD control signal so that the output terminal OUT of the level conversion circuit is a fixed low level, or the switch SW5 is opened by a PU control signal so that the output terminal OUT of the level conversion circuit is a fixed high level.

[0012] The present invention provides a level conversion circuit that can convert a low voltage domain, such as a 1.2V digital logic level, into a high voltage domain, such as a 3.3V digital logic level signal, and has the characteristics of small delay, high speed and low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a structural diagram of a traditional level conversion circuit.

[0014] Figure 2 It is a structural schematic diagram of the level conversion circuit provided by the present invention. DETAILED DESCRIPTION

[0015] The following is a further detailed description of a level conversion circuit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0016] The present invention provides a level conversion circuit, such as Figure 2 As shown, including NMOS tube M 21 and M22 、PMOS tube M 23 and M 24 , Inverter I 20 and I 21 , switches SW1~SW5, bias tube M BIAS , bias current I BIAS Among them, NMOS tube M 21 and M 22 、PMOS tube M 23 and M 24 , Inverter I 20 and I 21 Composition of the core circuit, NMOS tube M 21 The substrate end and NMOS tube M 22 The substrate ends of the NMOS tubes are grounded, and the low voltage domain logic signal DZ is transmitted from the NMOS tube M 21 The source input of the low voltage domain logic signal DZZ is from the NMOS tube M 22 The bias current I BIAS 、Bias tube M BIAS Together with switches SW1, SW2, and SW3, a bias circuit is formed. EN is the enable signal, and ENB is the inverted signal of the enable signal. When the circuit is enabled, the bias tube M BIAS The substrate is connected to V through switch SW1 DDL , the circuit cannot be used, bias tube M BIAS The substrate of the NMOS tube is connected to the ground through the switch SW2. 21 and M 22 、PMOS tube M 23 and M 24 and bias tube M BIAS All are thick gate devices. Therefore, NMOS tube M 21 、M 22 and bias tube M BIAS The characteristics of the circuit are well matched, and the variation with the process is small. Switches SW4 and SW5 are pull-down switches and pull-up switches respectively. When the level conversion circuit is not enabled, the output OUT of the level conversion circuit can be made fixed low or high through the PD or PU control signal.

[0017] Here’s how it works: When the level conversion circuit is enabled, that is, EN = 1, ENB = 0, switch SW1 is turned on, switches SW2, SW3, SW4, and SW5 are turned off, and the bias tube M BIAS The source and substrate terminals are connected to V DDL , bias current I BIAS Generally, a very small value is taken, and the bias voltage is: V BIAS =V DDL +V GS (MBIAS )~V DDL +V THN0 (3) Where V THN0 For bias tube M BIAS Threshold voltage without body effect, V GS (M BIAS ) is the bias tube M BIAS The gate-source voltage.

[0018] When D=0, DZ=1, DZZ=0, NMOS tube M 21 and M 22 The gate-source voltages are: V GS (M 21 )=V BIAS -V DDL =V THN0 (4) V GS (M 22 )=V BIAS -0=V DDL +V THN0 (5) Since the NMOS tube M 21 The source-substrate voltage V SB (M 21 )=V DDL , under the body effect of threshold voltage, its threshold voltage is: V TH (M 21 )>V GS (M 21 )=V THN0 , so NMOS tube M 21 closure.

[0019] Since the NMOS tube M 22 The source-substrate voltage V SB (M 22 ) = 0, no body effect, threshold voltage V TH (M 22 )=V THN0 , NMOS tube M 22 When it is turned on, its current output capability is: I(M 22 )= (6) The output terminal OUT is driven to a high voltage domain logic low level, and the voltage of OUTN is V DDH , so the PMOS tube M 24 When turned off, the level-shifting core circuit has no static leakage current.

[0020] When D=1, DZ=0, DZZ=1, NMOS tube M 21 and M 22 The gate-source voltages are: V GS (M 21 )=V BIAS -0=V DDL +V THN0 (7) V GS (M 22 )=V BIAS -V DDL =V THN0 (8) Similarly, due to the NMOS tube M 22 The source-substrate voltage V SB (M 22 )=V DDL , under the body effect of threshold voltage, its threshold voltage V TH (M 22 )>V GS (M 22 )=V THN0 , so NMOS tube M 22 closure.

[0021] Since the NMOS tube M 21 The source-substrate voltage V SB (M 21 ) = 0, no body effect, threshold voltage V TH (M 21 )=V THN0 , M 21 When it is turned on, its current output capability is: I(M 21 )= (9) The voltage of OUTN is 0, and the PMOS tube M 24 The output terminal OUT is driven to a high voltage domain logic high level. 23 When turned off, the level-shifting core circuit has no static leakage current.

[0022] By comparing equations (1), (2), (6), and (9), it can be seen that the level conversion circuit proposed in the present invention has a stronger current output capability than the traditional level conversion circuit, and therefore has a faster speed and can operate at a lower power supply voltage.

[0023] When the level conversion circuit is not enabled, that is, EN = 0, ENB = 1, switch SW1 is closed, switches SW2 and SW3 are opened, and bias tube M BIAS The substrate end of the NMOS tube is connected to the ground, and the bias voltage is 0. 21 and M22 By controlling the PD or PU signal, the switch SW4 or SW5 is turned on, so that the output terminal OUT of the level conversion circuit can be fixed at a low level or a high level.

[0024] The present invention uses a bias voltage V BIAS circuit, and the logic level signal of the low voltage domain is provided by the NMOS tube M 21 and M 22 The source input of NMOS tube M 21 and M 22 The current output capability of the level conversion circuit is improved, and the speed of the level conversion circuit can be operated at a lower power supply voltage. When the level conversion circuit is enabled, the bias tube M BIAS There is no body effect, and the NMOS tube M 21 or M 22 The body effect is used to cause the threshold voltage difference of the NMOS tube M. 21 or M 22 shut down, allowing the level-shifting circuit to have zero quiescent power consumption.

[0025] Bias tube M BIAS and NMOS tube M 21 、M 22 All are thick-gate NMOS tubes with good matching, so the speed and static leakage current of the level conversion circuit vary little with the process. When there are a large number of level conversion circuits, they can share the same bias circuit, reducing the power consumption of the circuit; when the level conversion circuit is not enabled, the PD or PU control signal can be used to make the level conversion circuit output a fixed low or high level.

[0026] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A level conversion circuit, characterized in that: Including NMOS tube M 21 and M 22 、PMOS tube M 23 and M 24 、Inverter I 20 and I 21 , switches SW1~SW5, bias tube M BIAS , bias current I BIAS ; NMOS tube M 21 The substrate end and NMOS tube M 22 The substrate ends of the inverter I 20 The input end is connected to the logic signal D, and the output end is connected to the NMOS tube M 21 The source terminal and inverter I 21 The input terminal of the inverter I 21 The output terminal is connected to NMOS tube M 22 The source end of NMOS tube M 21 The gate terminal and NMOS tube M 22 The gate end of NMOS tube M 21 The drain end is connected to the PMOS tube M 23 The drain end and PMOS tube M 24 The gate terminal of NMOS tube M 22 The drain end is connected to the PMOS tube M 24 The drain end and PMOS tube M 23 Gate terminal of PMOS tube M 23 and M 24 The source terminals are connected to the high voltage domain V DDH ; Bias Current I BIAS The input terminal is connected to the high voltage domain V DDH , the output end is connected to the bias tube M BIAS The drain end of the switch SW3, the first end of the NMOS tube M 21 The gate terminal and NMOS tube M 22 The gate terminal of the switch SW3 is connected to the ground; the second terminal of the bias tube M BIAS The gate end is connected to the first end of the switch SW3, the substrate end is connected to the first end of the switch SW1 and the first end of the switch SW2, the second end of the switch SW1 is connected to the bias transistor M BIAS The source terminals are connected to the low voltage domain V DDL , the second end of the switch SW2 is grounded; The first terminal of the switch SW5 is connected to the high voltage domain V DDH The second terminal is connected to NMOS tube M 22 The first terminal of the switch SW4 is connected to the NMOS tube M 22 The drain terminal of the device is connected to the ground, and the second terminal is connected to the ground.

2. The level conversion circuit according to claim 1, characterized in that: The NMOS tube M 21 and M 22 、PMOS tube M 23 and M 24 and bias tube M BIAS All are thick-gate devices.

3. The level conversion circuit according to claim 2, characterized in that: The switch SW4 and the switch SW5 are respectively a pull-down switch and a pull-up switch; When the level conversion circuit is disabled, the switch SW4 is opened by the PD control signal to make the output terminal OUT of the level conversion circuit a fixed low level, or the switch SW5 is opened by the PU control signal to make the output terminal OUT of the level conversion circuit a fixed high level.

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