Variable resistors and digital-to-analog converters

Abstract

The present invention provides a variable resistor and a digital analog converter. The variable resistor includes a main resistor, a plurality of switches and a plurality of standby resistors. The switches are respectively composed of a plurality of non-volatile storage units. The switches are coupled to the main resistor. The standby resistors are respectively coupled to the main resistor through the switches.

Description

Technical Field

[0001] The invention relates to a variable resistor and a digital-to-analog converter, and in particular to a variable resistor and a digital-to-analog converter which can be used for output voltage correction. Background Art

[0002] In digital-to-analog converters, a certain number of resistors are often required as the basis for digital-to-analog conversion. However, in integrated circuits, if the resistors in the digital-to-analog converter differ, it will affect the matching between the internal resistors and cause incorrect output voltages. This is especially true for digital-to-analog converters in audio products. Digital-to-analog converters in audio products often require the use of long strings of polysilicon resistors. Once the resistance value of the polysilicon resistor varies, the product will not function properly. Summary of the invention

[0003] The present invention is directed to a variable resistor and a digital-to-analog converter. By adjusting the resistance value of the variable resistor, the mismatch state of the output voltage of the digital-to-analog converter can be corrected.

[0004] According to an embodiment of the present invention, a variable resistor includes a main resistor, a plurality of switches and a plurality of standby resistors. The plurality of switches are respectively formed by a plurality of non-volatile memory cells. The switches are coupled to the main resistor. The standby resistors are respectively coupled to the main resistor through the switches.

[0005] According to an embodiment of the present invention, a digital-to-analog converter includes a plurality of circuit chips. Each circuit chip includes a three-voltage switch, a first resistor, a second resistor, a first transistor, and a second transistor. The first transistor and the first resistor are connected in series between the power supply terminal of the three-voltage switch and the operating power supply terminal of the digital-to-analog converter. The second transistor and the second resistor are connected in series between the reference terminal of the three-voltage switch and the ground terminal of the digital-to-analog converter. The first resistor and the second resistor are variable resistors as described above.

[0006] Based on the above, the variable circuit of the present invention constructs multiple switches through multiple non-volatile memory cells. The connection relationship between the main resistor and multiple backup resistors is adjusted by turning on or off each switch, thereby adjusting the resistance value of the variable resistor. The variable resistor of the present invention can be set in a digital-to-analog converter and used to perform output voltage correction to reduce the output voltage mismatch. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A circuit diagram of a variable resistor according to an embodiment of the present invention is shown.

[0008] Figure 2 A circuit diagram showing a variable resistor according to another embodiment of the present invention.

[0009] Figure 3 A circuit diagram showing a variable resistor according to another embodiment of the present invention.

[0010] Figure 4 A circuit diagram showing a variable resistor according to another embodiment of the present invention.

[0011] Figure 5 A schematic diagram showing the structure of a variable resistor according to an embodiment of the present invention is shown.

[0012] Figure 6 A schematic diagram showing a digital-to-analog converter according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0013] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0014] Please refer to Figure 1 , Figure 1 A circuit diagram of a variable resistor according to an embodiment of the present invention is shown. The variable resistor 100 includes a main resistor Rm, a plurality of switches SW1-SWA, and a plurality of standby resistors Rr1-Rra. In this embodiment, the switches SW1-SWA may be formed by a plurality of non-volatile memory cells. Among them, the switch SW1 may be coupled between the standby resistor Rr1 and the main resistor Rm, the switch SW2 may be coupled between the standby resistor Rr2 and the main resistor Rm, ..., and the switch SWA may be coupled between the standby resistor Rra and the main resistor Rm.

[0015] In the present embodiment, the non-volatile memory cell used to construct the switches SW1-SWA may be a resistive random-access memory cell (ReRAM cell), a magnetoresistive random access memory cell (MRAM cell), a phase change random access memory cell (PCRAM cell) or a ferroelectric random access memory cell (FeRAM cell). The above non-volatile memory cells can adjust the equivalent resistance values ​​provided by them to a high resistance state (HRS) or a low resistance state (LRS) through programming. Taking the switch SW1 as an example, when the non-volatile memory cell serving as the switch SW1 is programmed to a high resistance state, the switch SW1 can be regarded as being in a cut-off state. Conversely, when the non-volatile memory cell serving as the switch SW1 is programmed to a low resistance state, the switch SW1 can be regarded as being in a turned-on state.

[0016] In this embodiment, the switch SW1 and the backup resistor Rr1 are connected in series to form a first resistor set 110. The switch SW2 and the backup resistor Rr2 are connected in series to form a second resistor set 120, ..., and the switch SWA and the backup resistor Rra are connected in series to form an Ath resistor set 1A0. The first resistor set 110 to the Ath resistor set 1A0 and the main resistor Rm are connected in parallel to each other.

[0017] When the resistance value of the variable resistor 100 is to be adjusted, a programming operation can be performed on at least one of the nonvolatile memory cells as switches SW1 to SWA, and the resistance value of the variable resistor 100 can be changed by adjusting the on or off state of at least one of the switches SW1 to SWA. For example, in this embodiment, when the variable resistor 100 is to provide a relatively large resistance value, a programming operation can be performed on the nonvolatile memory cells as switches SW1 to SWA, and all of them can be in a high impedance state, so that the switches SW1 to SWA are turned off. At this time, the resistance value of the variable resistor 100 is substantially equal to the resistance value of the main resistor Rm.

[0018] When the resistance value of the variable resistor 100 is to be lowered, one of the nonvolatile memory cells serving as switches SW1 to SWA can be programmed to a low impedance state and turned on (the remaining switches remain in an off state). Taking the case where switch SW1 is turned on as an example, the resistance value of the variable resistor 100 is substantially equal to the resistance value of the main resistor Rm and the backup resistor Rr1 connected in parallel.

[0019] Continuing with the above-mentioned embodiment, when the resistance value of the variable resistor 100 is to be further lowered, the nonvolatile memory cell serving as the switch SW2 can also be programmed to a low impedance state, and the switch SW2 can also be turned on. At this time, the resistance value of the variable resistor 100 is substantially equal to the resistance value of the main resistor Rm, the backup resistor Rr1, and the backup resistor Rr2 connected in parallel. In this embodiment, when all the switches SW1 to SWA are turned on, the variable resistor 100 can have the lowest resistance value.

[0020] Please note that the high and low impedance states of the non-volatile storage units of the switches SW1-SWA in this embodiment can be changed multiple times. In other words, the on or off state of the switches SW1-SWA can be adjusted at any time according to actual needs.

[0021] It is worth mentioning that in this embodiment, the resistance values ​​of the standby resistors Rr1 to Rra may be the same or different from each other without any specific restrictions. The resistance values ​​of the standby resistors Rr1 to Rra may be the same or different from the resistance value of the main resistor Rm, and there is no fixed restriction.

[0022] In addition, in the embodiment of the present invention, the number of the standby resistors and the corresponding switches may be more than two, without any specific limitation. A person skilled in the art may set any number of standby resistors and the corresponding switches according to the range of the resistance value of the variable resistor 100 to be adjusted, without any fixed limitation.

[0023] The variable resistor 100 of the present invention can be applied to various types of circuits, such as a digital-to-analog converter. By changing the on or off state of each switch SW1-SWA, the resistance value of the variable resistor 100 can be adjusted, and the output voltage of the digital-to-analog converter can be adjusted to correct the mismatch of the output voltage.

[0024] Please refer to the following Figure 2 , Figure 2 The circuit diagram of a variable resistor according to another embodiment of the present invention is shown. The variable resistor 200 includes a main resistor Rm, a plurality of switches SW1-SWN and a plurality of backup resistors Rr1-Rrn. The switches SW1-SWN and the backup resistors Rr1-Rrn respectively form a plurality of resistor groups 210-2N0.

[0025] In this embodiment, the resistor group 210-2N0 is coupled in series with the main resistor Rm, wherein the first end E1 of the main resistor Rm is coupled to the resistor group 210. The resistance value provided by the variable resistor 200 between the end points E2 and E3 can be adjusted by turning on or off each switch SW1-SWN.

[0026] Similarly, the on or off state of each switch SW1-SWN can be adjusted by programming the non-volatile memory cells serving as each switch SW1-SWN to a high impedance state or a low impedance state. When the non-volatile memory cells are programmed to a high impedance state, the corresponding switches are in an off state; conversely, when the non-volatile memory cells are programmed to a low impedance state, the corresponding switches are in an on state.

[0027] In this embodiment, the switches SW1-SWN are used to bypass the corresponding standby resistors Rr1-RrN respectively. When any one of the switches SW1-SWN is turned on, the standby resistor (one of the standby resistors Rr1-RrN) will be bypassed. Based on the above, when all the corresponding switches SW1-SWN are in the on state, the resistance value of the variable resistor 200 is equal to the resistance value of the main resistor Rm. When the resistance value of the variable resistor 200 is to be increased, at least one of the switches SW1-SWN can be turned off. For example, when the switch SW1 is turned off and the remaining switches SW2-SWN are turned on, the resistance value of the variable resistor 200 is equal to the sum of the resistance values ​​of the main resistor Rm and the standby resistor Rr1. When all the switches SW1-SWN are turned off, the variable resistor 200 can have a maximum resistance value, which is equal to the sum of the resistance values ​​of the main resistor Rm and all the standby resistors Rr1-Rrn.

[0028] and Figure 1 Similar to the embodiment, the resistance values ​​of the standby resistors Rr1 to Rrn in this embodiment can be the same or different from each other, without any specific restrictions. The resistance values ​​of the standby resistors Rr1 to Rrn can be the same or different from the resistance value of the main resistor Rm, and there is no fixed restriction. The number of standby resistors Rr1 to Rrn and switches SW1 to SWN can be set according to the range of the resistance value of the variable resistor 200 to be adjusted, and there is no fixed restriction.

[0029] Please refer to the following Figure 3 , Figure 3 FIG. 1 is a circuit diagram of a variable resistor according to another embodiment of the present invention. Figure 1 In the embodiment of FIG. 1 , the plurality of resistor groups 110 - 1A0 may be configured in parallel with each other. Figure 2In the embodiment of the present invention, the plurality of resistor groups 210 to 2N0 can be connected in series. Figure 1 as well as Figure 2 The variable resistor 300 includes a plurality of resistor groups 311-313, 320 and 330. The resistor groups 320 and 330 are connected in series. The resistor groups 311-313 are connected in parallel with each other and are connected in series between the resistor string formed by the resistor groups 320 and 330 and the main resistor Rm.

[0030] In this embodiment, the resistor groups 311-313 respectively include switches SW11-SW13 and backup resistors Rr11-Rr13. The switches SW11-SW13 are respectively coupled in series with the backup resistors Rr11-Rr13. Figure 1 The resistor groups 320 and 330 respectively have switches SW20, SW30 and backup resistors Rr20, Rr30. The switches SW20, SW30 can be respectively coupled in parallel with the backup resistors Rr20, Rr30. The resistor groups 320 and 330 can be as follows: Figure 2 The embodiments are coupled in series with each other.

[0031] Similar to the above-mentioned embodiment, by controlling the on or off state of each switch SW11-SW13, SW20 and SW30, the resistance value of the variable resistor 300 can be adjusted. It is worth mentioning that in other embodiments of the present invention, the series and parallel states of multiple resistor groups can be adjusted according to the needs of the designer. Figures 1 to 3 The examples shown are only for illustrative purposes and are not intended to limit the scope of the present invention.

[0032] Please refer to Figure 4 , Figure 4 A circuit diagram of a variable resistor according to another embodiment of the present invention is shown. The variable resistor 400 includes a main resistor Rm, switches SW1, SW2, and standby resistors Rr1-Rr2. The switches SW1 and SW2 correspond to the standby resistors Rr1-Rr2, respectively. The switches SW1 and SW2 are coupled in series with the standby resistors Rr1-Rr2, respectively. In this embodiment, the switches SW1 and SW2 are non-volatile storage units, and are coupled to the transistors T1 and T2, respectively. Among them, one end of the switch SW1 can be coupled to the voltage rail VR1, the other end of the switch SW1 can be coupled to the first end of the transistor T1, and the second end of the transistor T1 can be coupled to another voltage rail VR2. Similarly, one end of the switch SW2 can be coupled to the voltage rail VR1, the other end of the switch SW2 can be coupled to the first end of the transistor T2, and the second end of the transistor T2 can be coupled to another voltage rail VR2.

[0033] When programming is to be performed on the non-volatile memory cell serving as switch SW1, a bias voltage may be applied through the control terminal of transistor T1 to turn on transistor T1. Then, a suitable voltage difference may be provided between the two ends of the non-volatile memory cell serving as switch SW1 through voltage rail VR1 and voltage rail VR2, so that the non-volatile memory cell serving as switch SW1 may be programmed to a high impedance state or a low impedance state. When programming is to be performed on the non-volatile memory cell serving as switch SW2, transistor T2 may be turned on, and by applying a suitable bias voltage to voltage rail VR1 and voltage rail VR2, the programming of the non-volatile memory cell serving as switch SW2 may be completed.

[0034] Please refer to Figure 5 , Figure 5 The schematic diagram of the structure of the variable resistor of the embodiment of the present invention is shown. The variable resistor 500 includes a main resistor Rm, switches SW1-SW6, and backup resistors Rr1 and Rr2. Each of the switches SW1-SW6 can be formed by applying a non-volatile memory cell, and is equivalent to a disconnected state when programmed to a high impedance state, and is equivalent to a conductive state when programmed to a low impedance state.

[0035] In terms of connection relationship, the main resistor Rm can be coupled to the metal structure M1 through the conductive via VIA1. The metal structure M1 can be coupled to one end of the metal structure M5 through the conductive via VIA2. In addition, the other end of the metal structure M5 can be coupled to one end of the switch SW2, and the other end of the switch SW2 can be coupled to the upper surface of the metal structure M2. One end of the lower surface of the metal structure M2 can be coupled to the standby resistor Rr1 through the conductive via VIA4, and the other end of the lower surface of the metal structure M2 can be coupled to the switch SW1 through the conductive via VIA3.

[0036] In addition, the backup resistor Rr1 can be coupled to the lower surface of the metal structure M3 through the conductive via VIA5. The lower surface of the metal structure M3 can be coupled to the switch SW4 and the backup resistor Rr2 through the conductive vias VIA6 and VIA7, respectively. The upper surface of the metal structure M3 can be coupled to the switch SW3, and coupled to the metal structure M6 through the switch SW3.

[0037] The backup resistor Rr2 can be further coupled to the lower surface of the metal structure M4 through the conductive via VIA8. The lower surface of the metal structure M4 can be further coupled to the switch SW6 through the conductive via VIA9. The upper surface of the metal structure M4 can be coupled to the switch SW5, and coupled to the metal structure M6 through the switch SW5.

[0038] It is worth mentioning that the switches SW1 , SW4 , SW6 respectively coupled in parallel with the backup resistors Rr1 , Rr2 can be used to bypass the backup resistors Rr1 , Rr2 .

[0039] Regarding the adjustment details of the resistance value of the variable resistor 500, when the switch SW2 is in the cut-off state, the resistance value of the variable resistor 500 can be equal to the resistance value of the main resistor Rm. On the other hand, when the switch SW2 is in the turned-on state, the main resistor Rm can be coupled to the backup resistors Rr1 and Rr2 of the subsequent section. At this time, if the switches SW1, SW4, and SW6 are in the disconnected state, and at least one of the switches SW3 and SW5 is in the disconnected state, the resistance value of the variable resistor 500 can be equal to the sum of the resistance values ​​of the main resistor Rm and the backup resistors Rr1 and Rr2.

[0040] In addition, by turning on the switches SW3 and SW5 at the same time, the backup resistor Rr2 can be bypassed, and the resistance value of the variable resistor 500 can be reduced. By turning on at least one of the switches SW1, SW4, and SW6, at least one of the corresponding backup resistors Rr1 and Rr2 can be bypassed, and the resistance value of the variable resistor 500 can be reduced.

[0041] It is worth mentioning that in this embodiment, the metal structures M1-M4 can be disposed on the same first metal layer in the integrated circuit, and the metal structures M5 and M6 can be disposed on the same second metal layer in the integrated circuit, wherein the height of the second metal layer can be higher than the first metal layer.

[0042] Please note that Figure 5 The configuration of the embodiment is only an example for explanation and is not intended to limit the scope of implementation of the present invention. In the embodiment of the present invention, the configuration relationship between the multiple switches and the multiple standby resistors can be adjusted and set by the designer according to actual needs, and there is no fixed form. Among them, the main resistor, the switch and the standby resistor can be connected in any form through the metal layer and the conductive through hole in the integrated circuit, so that each switch and the corresponding standby resistor are connected in parallel or in series, and the multiple resistor groups formed by the multiple switches and the corresponding multiple standby resistors are connected in parallel or in series.

[0043] Please refer to Figure 6 , Figure 6A schematic diagram of a digital-to-analog converter according to an embodiment of the present invention is shown. The digital-to-analog converter 600 includes a plurality of slices 611-61B and a bias generator 630. The output ends of the slices 611-61B are commonly coupled to the output end OUT of the digital-to-analog converter 600. The slices 611-61B receive a plurality of digital input signals IN1-INB respectively. Each of the slices 611-61B may have a similar circuit architecture. In which, taking the slice 611 as an example, the slice 611 includes a tri-level switch 620, resistors R1, R2, and transistors T61 and T62. The transistor T61 and the resistor R1 are connected in series between the power supply end PE of the tri-level switch 620 and the operating power supply end VDD of the digital-to-analog converter 600. The transistor T62 and the resistor R2 are connected in series between the reference end GE of the tri-level switch 620 and the ground end GND2 of the digital-to-analog converter 600. The three-voltage switch 620 receives an input signal IN1 and can output signals of three voltage levels to the output terminal OUT of the digital-to-analog converter 600 according to the input signal IN1 .

[0044] The control terminals of the transistors T61 and T62 receive bias voltages Vb1 and Vb2 , respectively. The bias voltages Vb1 and Vb2 may be provided by a bias generator 630 .

[0045] It is worth noting that, in this embodiment, the resistors R1 and R2 can be used Figures 1 to 5 The output voltage mismatch phenomenon generated by the digital-to-analog converter 600 can be effectively corrected by adjusting the resistance values ​​of the resistors R1 and R2.

[0046] The output terminal OUT of the digital-to-analog converter 600 of the present embodiment is further coupled to the output terminal of the operational amplifier OP2. The negative input terminal of the operational amplifier OP2 is coupled to its output terminal to form a voltage follower. The positive input terminal of the operational amplifier OP2 can receive a default shared voltage VCM, and the operational amplifier OP2 can provide an output voltage equal to the shared voltage VCM to the output terminal OUT of the digital-to-analog converter 600.

[0047] The bias generator 630 includes resistors R3 to R6 and transistors T63 to T66. The first ends of the resistors R3 and R4 are coupled to the operating power supply terminal VDD to receive the operating power supply. The first end of the transistor T63 is coupled to the second end of the resistor R3, and the control end of the transistor T63 is coupled to the second end thereof to form a diode connection configuration. The first end of the transistor T64 is coupled to the second end of the resistor R4, and the control end of the transistor T64 is coupled to the control end of the transistor T63. The transistor T65 and the resistor R5 are connected in series between the second end of the transistor T63 and the ground terminal GND1, and the control end of the transistor T65 receives the reference voltage VR. The transistor T66 and the resistor R6 are connected in series between the second end of the transistor T64 and the ground terminal GND1. The control end of the transistor T66 is coupled to its first end to form a diode connection configuration.

[0048] In this embodiment, the reference voltage VR can be provided by an operational amplifier OP1. The positive input terminal of the operational amplifier OP1 receives the reference voltage Vref, and the negative input terminal of the operational amplifier OP1 is coupled to the second terminal of the transistor T65. The output terminal of the operational amplifier OP1 can dynamically adjust the output reference voltage VR, and maintain the second terminal of the transistor T65 equal to the reference voltage Vref. The reference voltage Vref can have a preset voltage value.

[0049] By limiting the second terminal of transistor T65 to be equal to reference voltage Vref, resistor R5 can provide a reference current IR. Transistors T65 and T64 can form a current mirror and generate a mirror current IM through transistor T66 according to the reference current IR on mirror resistor R5. In this way, transistor T63 configured for diode connection can receive reference current IR and generate bias voltage Vb1. Transistor T65 configured for diode connection can receive mirror current IM and generate bias voltage Vb2.

[0050] It is worth noting that, in this embodiment, the resistors R3, R5 and R6 can be used Figures 1 to 5 By adjusting the resistance value of at least one of the resistors R3, R5, and R6, the bias generator 630 can provide the correct bias voltages Vb1 and Vb2.

[0051] In summary, the variable resistor of the present invention is composed of a plurality of switches composed of non-volatile memory cells and a plurality of backup resistors connected to each other. The switch is turned on or off by programming the non-volatile memory cells, and the resistance value of the variable resistor is adjusted by adjusting the connection relationship between the main resistor and the backup resistor. The variable resistor of the present invention can be applied to a digital-to-analog converter. By adjusting the resistance value of one or more resistors in the digital-to-analog converter, the mismatch of the output voltage can be corrected to maintain the stability of the system performance.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A variable resistor, comprising: Main resistor; A plurality of switches, each consisting of a plurality of non-volatile storage units and coupled to the main resistor; as well as A plurality of standby resistors are respectively coupled to the main resistor through the plurality of switches.

2. The variable resistor according to claim 1, wherein each of the backup resistors is connected in series or in parallel with the main resistor.

3. The variable resistor according to claim 1, wherein each of the nonvolatile memory cells is programmed to a high impedance state to cut off the connection relationship between the main resistor and the corresponding backup resistors.

4. The variable resistor according to claim 1, wherein each of the nonvolatile memory cells is programmed to a low impedance state to connect the main resistor to the corresponding backup resistor. 5 . The variable resistor according to claim 1 , wherein any two of the plurality of backup resistors are connected in series or in parallel.

6. The variable resistor according to claim 1, wherein the first end of each of the switches is coupled to a first metal structure, the second end of each of the switches is coupled to a second metal structure, the first metal structure is coupled to the main resistor, and the second metal structure is coupled to the corresponding backup resistors. 7 . The variable resistor according to claim 1 , wherein each of the nonvolatile memory cells is a resistive memory cell, a magnetoresistive memory cell, a phase change memory cell or a ferroelectric memory cell.

8. The variable resistor according to claim 1, wherein the variable resistor is provided in a digital-to-analog converter.

9. The variable resistor according to claim 1, wherein each of the switches and the corresponding backup resistors are connected in parallel or in series.

10. The variable resistor according to claim 1, wherein the plurality of switches and the plurality of standby resistors respectively form a plurality of resistor groups, and the plurality of resistor groups are connected in series or in parallel with each other.

11. A digital-to-analog converter, comprising: A plurality of circuit chips, each of the circuit chips comprising: Three voltage switches; a first resistor and a second resistor; and a first transistor and a second transistor, The first transistor and the first resistor are connected in series between the power supply terminal of the three-voltage switch and the operation power supply terminal of the digital-to-analog converter, and the second transistor and the second resistor are connected in series between the reference terminal of the three-voltage switch and the first ground terminal. The first resistor and the second resistor are variable resistors according to claim 1.

12. The digital-to-analog converter according to claim 11, further comprising: The bias generator provides a first bias voltage and a second bias voltage to the control terminals of the first transistor and the second transistor respectively.

13. The digital-to-analog converter of claim 12, wherein the bias generator comprises: A third resistor having a first end receiving an operating power supply; a fourth resistor having a first end receiving the operating power supply; A third transistor having a first end coupled to the second end of the third resistor, and a control end of the third transistor coupled to the second end of the third transistor; a fourth transistor having a first end coupled to the second end of the fourth resistor, and a control end of the fourth transistor coupled to the control end of the third transistor; A fifth transistor and a fifth resistor are connected in series between the second terminal of the third transistor and the second ground terminal, and a control terminal of the fifth transistor receives a reference voltage; and The sixth transistor and the sixth resistor are connected in series between the second end of the fourth transistor and the second ground end. The control end of the sixth transistor is coupled to the first end of the sixth transistor. 14 . The digital-to-analog converter according to claim 13 , wherein each of the third resistor, the fifth resistor, and the sixth resistor is the variable resistor.

Images