Silicon capacitor based on end seal and manufacturing method and manufacturing equipment thereof

Abstract

The embodiment of the invention provides a silicon capacitor based on end sealing and a manufacturing method and manufacturing equipment thereof, and the method comprises the steps: determining to carry out the scribing processing corresponding to an end sealing technology on a wafer based on the end sealing technology, electroplating treatment is carried out after the scribing treatment and the end sealing process corresponding to the scribing treatment are completed; and different electroplating is carried out under the condition of a physical vapor deposition sputtering process or a slurry dipping process, and the silicon capacitor based on the end seal is manufactured.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a silicon capacitor based on end sealing and a manufacturing method and manufacturing equipment thereof. Background Art

[0002] Silicon capacitors, manufactured using semiconductor technology, have significant advantages such as small size, high capacity density, good reliability and long life. Existing packaging methods mainly include vertical and horizontal types, and the internal electrodes are led out in the same plane or in different planes. After the packaging is completed, the subsequent assembly and use of silicon capacitors requires bonding and wire bonding, or ball planting on the pads PAD of the silicon capacitor before mounting.

[0003] In view of this, the silicon capacitor packaging structure in the prior art has the following problems: the electrodes can only be led out from the surface of the silicon capacitor and are difficult to connect to the end face. Therefore, the double-sided structure silicon capacitor must rely on the through silicon via (TSV) process to achieve interconnection, and this manufacturing process is complex and has high manufacturing costs. At the same time, the bonding wire or ball planting process has strict requirements on the operating equipment and environmental conditions, and the operating process is cumbersome. Summary of the invention

[0004] The present invention provides a silicon capacitor based on end sealing and a manufacturing method and manufacturing equipment thereof, aiming to solve at least the following technical problems: on the one hand, the electrode can only be led out from the surface of the silicon capacitor and is difficult to connect to the end face, so the double-sided structure silicon capacitor must rely on the through silicon via TSV process to achieve interconnection, and this manufacturing process is complex and has high manufacturing cost; on the other hand, the bonding wire bonding or ball planting process has strict requirements on the operating equipment and environmental conditions, and the operating process is cumbersome.

[0005] Specifically, the embodiment of the present invention provides the following technical solutions: In a first aspect, an embodiment of the present invention provides a method for manufacturing a silicon capacitor based on end sealing, comprising: Based on the end sealing process, it is determined that a dicing process corresponding to the end sealing process is performed on the wafer, and an electroplating process is performed after the dicing process and the end sealing process corresponding to the dicing process are completed, wherein the end sealing process includes a physical vapor deposition sputtering process or a slurry dipping process, In the case of the physical vapor deposition sputtering process, Divide the wafer into a plurality of substrates of long strips along a direction perpendicular to the upper surface of the wafer, each of the plurality of substrates being constructed to have an upper surface and a lower surface, the upper surface being provided with a first front electrode and a second front electrode, the lower surface being provided with a first back electrode and a second back electrode, the first front electrode extending along a side of the substrate close to a first dicing processing surface, the second front electrode extending along a side of the substrate close to a second dicing processing surface, the first back electrode extending along a side of the substrate close to the first dicing processing surface, the second back electrode extending along a side of the substrate close to the second dicing processing surface, the first front electrode and the second front electrode being spaced apart at a predetermined interval, and the first back electrode and the second back electrode being spaced apart at the predetermined interval; stack and fix the plurality of substrates to align the first dicing processing surface and the second A scribing process surface; for the plurality of substrates after being stacked and fixed, a first end surface electrode is prepared on the first scribing process surface by the physical vapor deposition sputtering process, so that the first end surface electrode interconnects the first front electrode with the first back electrode, and a second end surface electrode is prepared on the second scribing process surface by the physical vapor deposition sputtering process, so that the second end surface electrode interconnects the second front electrode with the second back electrode; through the scribing process, the plurality of stacked substrates processed by the physical vapor deposition sputtering process are further divided into a plurality of silicon capacitor particles of a long strip along a direction perpendicular to the upper surface of the wafer; through the electroplating process, the first front electrode, the first end surface electrode, the first back electrode, the second front electrode, the second end surface electrode, and the second back electrode on each of the plurality of silicon capacitor particles are electroplated to obtain the silicon capacitor based on end sealing; or, In the case of the slurry dipping process, Along a direction perpendicular to the upper surface of the wafer, the wafer is divided into a plurality of silicon capacitor particles in a long strip, each of the plurality of silicon capacitor particles is constructed to have at least one of an upper surface or a lower surface, the upper surface is provided with a first front electrode and a second front electrode, the lower surface is provided with a first back electrode and a second back electrode, the first front electrode is arranged along a side of the silicon capacitor particle close to a first dicing processing surface, the second front electrode is arranged along a side of the silicon capacitor particle close to a second dicing processing surface, the first back electrode is arranged along a side of the silicon capacitor particle close to the first dicing processing surface, the second back electrode is arranged along a side of the silicon capacitor particle close to the second dicing processing surface, the first front electrode and the second front electrode are spaced apart at a predetermined interval, and the first back electrode and the second back electrode are spaced apart at the predetermined interval; for the plurality of silicon capacitor particles, the slurry process is used to form a first dicing electrode on the first dicing surface. A first end surface electrode is prepared on the slice processing surface so that the first end surface electrode interconnects the first front electrode with the first back electrode, and a second end surface electrode is prepared on the second dicing processing surface through the slurry process so that the second end surface electrode interconnects the second front electrode with the second back electrode; through electroplating treatment, the first front electrode, the first end surface electrode, the first back electrode, the second front electrode, the second end surface electrode, and the second back electrode on each silicon capacitor particle treated by the slurry process are electroplated, and the first part of the side surface of each silicon capacitor particle surrounded by the first front electrode, the first end surface electrode, and the first back electrode is electroplated, and the second part of the side surface of each silicon capacitor particle surrounded by the second front electrode, the second end surface electrode, and the second back electrode is electroplated to obtain the end-sealed silicon capacitor physical vapor deposition.

[0006] Furthermore, an embodiment of the present invention provides a method for manufacturing a silicon capacitor based on end sealing, comprising: The first front electrode, the second front electrode, the first back electrode, and the second front electrode have the same size; The materials of the first front electrode, the second front electrode, the first back electrode, and the second front electrode include copper, aluminum, gold, silver, platinum, palladium, iridium, copper alloy, aluminum alloy, gold alloy, silver alloy, platinum alloy, palladium alloy, and iridium alloy.

[0007] Furthermore, an embodiment of the present invention provides a method for manufacturing a silicon capacitor based on end sealing, comprising: In the physical vapor deposition sputtering process, sputtering a first sputtering material onto the first scribing processed surface and the second scribing processed surface, further sputtering a second sputtering material onto the first scribing processed surface and the second scribing processed surface on which the first sputtering material is sputtered; After the sputtering of the first sputtering material and the second sputtering material is completed, an annealing process is further performed.

[0008] Furthermore, an embodiment of the present invention provides a method for manufacturing a silicon capacitor based on end sealing, comprising: The first sputtering material at least includes titanium, chromium, tungsten, titanium alloy, chromium alloy, tungsten alloy, The second sputtering material includes at least nickel, platinum, tungsten, copper, aluminum, gold, silver, palladium, iridium, nickel alloy, platinum alloy, tungsten alloy, copper alloy, aluminum alloy, gold alloy, silver alloy, palladium alloy, and iridium alloy.

[0009] Furthermore, an embodiment of the present invention provides a method for manufacturing a silicon capacitor based on end sealing, comprising: In the slurry dipping process, Using a slurry material, performing a slurry treatment on the first scribe processing surface and the second scribe processing surface; The first dicing processing surface and the second dicing processing surface after the slurry processing are dried to solidify the slurry material.

[0010] Furthermore, an embodiment of the present invention provides a method for manufacturing a silicon capacitor based on end sealing, comprising: The slurry material includes a solution containing silver ions or copper ions.

[0011] Furthermore, an embodiment of the present invention provides a method for manufacturing a silicon capacitor based on end sealing, comprising: The electroplating process includes barrel plating or ion plating.

[0012] Furthermore, an embodiment of the present invention provides a method for manufacturing a silicon capacitor based on end sealing, comprising: After the electroplating, the manufacturing method further includes: performing a surface mounting process on the end-cap-based silicon capacitor.

[0013] In a second aspect, an embodiment of the present invention provides a manufacturing device for a silicon capacitor based on end sealing, comprising: a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein when the processor executes the program, the steps of the manufacturing method for the silicon capacitor based on end sealing are implemented to manufacture the silicon capacitor based on end sealing.

[0014] In a third aspect, an embodiment of the present invention provides a silicon capacitor based on end sealing, including: the silicon capacitor based on end sealing is manufactured according to the above-mentioned silicon capacitor manufacturing method and based on the above-mentioned silicon capacitor manufacturing equipment based on end sealing.

[0015] It can be seen from the above technical scheme that the silicon capacitor based on end sealing and its manufacturing method and manufacturing equipment provided by the embodiment of the present invention are intended to solve at least the following technical problems: on the one hand, the electrode can only be led out from the surface of the silicon capacitor and it is difficult to connect to the end face. Therefore, the double-sided silicon capacitor must rely on the silicon through-hole TSV process to achieve interconnection, and this manufacturing process is complex and the manufacturing cost is high; on the other hand, the bonding wire bonding or ball planting process has strict requirements on the operating equipment and environmental conditions, and the operation process is cumbersome. In other words, it is intended to reduce the requirements for the use environment, simplify the operation process, and realize the convenient interconnection of the electrodes of the double-sided silicon capacitor structure, thereby improving the overall performance and reliability of the silicon capacitor. The silicon capacitor based on end sealing and its manufacturing method and manufacturing equipment provided by the embodiment of the present invention enable silicon capacitors to be applied in more fields and promote the development of electronic equipment towards smaller size and high performance. The embodiment of the present invention combines the SMT end sealing process, and the upper and lower electrodes of the silicon capacitor are electrically connected and the electrodes are led out by preparing the end electrode on the end face, so that the electrode interconnection of the double-sided silicon capacitor structure can be realized, forming a new SMT end sealing structure of a silicon capacitor product, and manufacturing a silicon capacitor product that can be directly mounted using SMT surface mounting technology. The embodiment of the present invention realizes the electrode interconnection of the double-sided silicon capacitor structure by end face connection, and the obtained silicon capacitor end-sealed product has low cost and combines the advantages of excellent performance of silicon capacitor products and convenient installation of ceramic capacitors. The silicon capacitor product after end sealing can be directly mounted using conventional SMT surface mounting technology, thereby realizing convenient and reliable SMT surface mounting use of silicon capacitors. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A flow chart of a method for manufacturing a silicon capacitor based on termination provided in an embodiment of the present invention.

[0018] Figure 2 A schematic diagram of a silicon capacitor wafer involved in a method for manufacturing a silicon capacitor based on end sealing provided in an embodiment of the present invention.

[0019] Figure 3A schematic diagram of process variations of a method for manufacturing a silicon capacitor based on termination sealing provided in an embodiment of the present invention.

[0020] Figure 4 A schematic structural diagram of a long strip substrate obtained after slicing in the method for manufacturing a silicon capacitor based on end sealing provided in an embodiment of the present invention.

[0021] Figure 5 A schematic diagram of a structure obtained after stacking and fixing in a method for manufacturing a silicon capacitor based on end sealing provided in an embodiment of the present invention.

[0022] Figure 6 A schematic diagram of an end surface electrode in a method for manufacturing a silicon capacitor based on end sealing provided by an embodiment of the present invention.

[0023] Figure 7 A schematic diagram of the structure of silicon capacitor particles obtained after slicing in the method for manufacturing a silicon capacitor based on end sealing provided in an embodiment of the present invention.

[0024] Figure 8 A schematic structural diagram of a silicon capacitor based on end sealing obtained after electroplating in the case of a first end sealing process provided in an embodiment of the present invention.

[0025] Fig. 9 A schematic diagram of the structure of a silicon capacitor based on terminal sealing obtained after electroplating in the case of a second terminal sealing process provided by an embodiment of the present invention.

[0026] Fig.10 A schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] In addition, in the present invention, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations, such as the first front electrode, the second front electrode, the first back electrode, the second front electrode, the first dicing processing surface, the second dicing processing surface, the first end sealing process, the second end sealing process, the first sputtering material, and the second sputtering material involved in the embodiments of the present invention.

[0029] The various terms or phrases used in the present invention have the general meanings known to those of ordinary skill in the art. Even so, the present invention still hopes to provide a more detailed description and explanation of these terms or phrases. If the terms and phrases involved in this article are inconsistent with the commonly known meanings, the meanings expressed in the present invention shall prevail; and if not defined in this application, they have the meanings commonly understood by those of ordinary skill in the art.

[0030] In the prior art, there are many problems including but not limited to the following: on the one hand, the electrode can only be led out from the surface of the silicon capacitor and is difficult to connect to the end face. Therefore, the double-sided silicon capacitor must rely on the through silicon via (TSV) process to achieve interconnection, and this manufacturing process is complex and has high manufacturing costs; on the other hand, the bonding wire or ball planting process has strict requirements on the operating equipment and environmental conditions, and the operating process is cumbersome.

[0031] In view of this, in a first aspect, an embodiment of the present invention provides a method for manufacturing a silicon capacitor based on end sealing.

[0032] Combine the following Figure 1 The method of manufacturing the capping-based silicon capacitor of the present invention is described.

[0033] Figure 1 A flow chart of a method for manufacturing a silicon capacitor based on termination provided in an embodiment of the present invention.

[0034] In a first aspect, an embodiment of the present invention provides a method for manufacturing a silicon capacitor based on end sealing, comprising: S110: Determine, based on the end sealing process, to perform a dicing process corresponding to the end sealing process on the wafer, and perform an electroplating process after the dicing process and the end sealing process corresponding to the dicing process are completed. The end sealing process includes a physical vapor deposition sputtering process or a slurry dipping process. S120: In the case of a physical vapor deposition sputtering process, a wafer is divided into a plurality of substrates of long strips along a direction perpendicular to the upper surface of the wafer, each of the plurality of substrates is constructed to have an upper surface and a lower surface, the upper surface is provided with a first front electrode and a second front electrode, the lower surface is provided with a first back electrode and a second back electrode, the first front electrode is extended along a side of the substrate close to the first dicing processing surface, the second front electrode is extended along a side of the substrate close to the second dicing processing surface, the first back electrode is extended along a side of the substrate close to the first dicing processing surface, the second back electrode is extended along a side of the substrate close to the second dicing processing surface, the first front electrode and the second front electrode are spaced apart at a predetermined interval, and the first back electrode and the second back electrode are spaced apart at a predetermined interval; the plurality of substrates are stacked and fixed to align the first and second electrodes of each of the plurality of substrates. a scribing treatment surface and a second scribing treatment surface; for the stacked and fixed multiple substrates, a first end surface electrode is prepared on the first scribing treatment surface by a physical vapor deposition sputtering process, so that the first end surface electrode interconnects the first front electrode with the first back electrode, and a second end surface electrode is prepared on the second scribing treatment surface by a physical vapor deposition sputtering process, so that the second end surface electrode interconnects the second front electrode with the second back electrode; through scribing, the multiple stacked substrates processed by the physical vapor deposition sputtering process are further divided into multiple silicon capacitor particles of long strips along a direction perpendicular to the upper surface of the wafer; through electroplating, the first front electrode, the first end surface electrode, the first back electrode, the second front electrode, the second end surface electrode, and the second back electrode on each of the multiple silicon capacitor particles are electroplated to obtain a silicon capacitor based on end sealing; S130: In the case of a slurry dipping process, the wafer is divided into a plurality of silicon capacitor particles in a long strip along a direction perpendicular to the upper surface of the wafer, each of the plurality of silicon capacitor particles is constructed to have at least one of an upper surface or a lower surface, the upper surface is provided with a first front electrode and a second front electrode, the lower surface is provided with a first back electrode and a second back electrode, the first front electrode is arranged along a side of the silicon capacitor particle close to the first dicing processing surface, the second front electrode is arranged along a side of the silicon capacitor particle close to the second dicing processing surface, the first back electrode is arranged along a side of the silicon capacitor particle close to the first dicing processing surface, the second back electrode is arranged along a side of the silicon capacitor particle close to the second dicing processing surface, the first front electrode and the second front electrode are spaced apart at a predetermined interval, and the first back electrode and the second back electrode are spaced apart at a predetermined interval; for the plurality of silicon capacitor particles, A first end face electrode is prepared on the first scribe processing surface by a slurry dipping process, so that the first end face electrode interconnects the first front electrode with the first back electrode, and a second end face electrode is prepared on the second scribe processing surface by a slurry dipping process, so that the second end face electrode interconnects the second front electrode with the second back electrode; through electroplating treatment, the first front electrode, the first end face electrode, the first back electrode, the second front electrode, the second end face electrode, and the second back electrode on each silicon capacitor particle treated by the slurry dipping process are electroplated, and the first part of the side surface of each silicon capacitor particle surrounded by the first front electrode, the first end face electrode, and the first back electrode is electroplated, and the second part of the side surface of each silicon capacitor particle surrounded by the second front electrode, the second end face electrode, and the second back electrode is electroplated to obtain a silicon capacitor based on end sealing.

[0035] Specifically, the execution order of S120 and S130 can be interchanged, and there is no chronological relationship between the two, but a logical OR relationship.

[0036] Figure 2 A schematic diagram of a silicon capacitor wafer involved in a method for manufacturing a silicon capacitor based on end sealing provided in an embodiment of the present invention.

[0037] Combination Figure 2 , with respect to S110 , further explanation is given as follows: the silicon capacitor wafer involved in the method for manufacturing a silicon capacitor based on end sealing may be referred to as a wafer for short.

[0038] Figure 3 A schematic diagram of process variations of a method for manufacturing a silicon capacitor based on termination sealing provided in an embodiment of the present invention.

[0039] Combination Figure 3Regarding the scribing or slicing process involved in S110, S120 and S130, it is further explained as follows: the scribing process involved in the manufacturing method of the end-capped silicon capacitor may include but is not limited to slicing the wafer or the intermediate product after one or more process treatments using a device such as a dicing machine.

[0040] Specifically, in Figure 3 In the embodiment, for the convenience of illustration, the first end surface electrode is also referred to as end surface electrode 1, and the second end surface electrode is also referred to as end surface electrode 2. In addition, in one embodiment, Figure 3 The end surface electrode 1 in the circuit can also be the end surface electrode 2, and the end surface electrode 2 can also be the end surface electrode 1. It should be noted that for the silicon capacitor product based on end sealing after the final electroplating, its two ends respectively include two end electrodes, such as the first end electrode and the second end electrode (also referred to as the end electrode 1 and the end electrode 2). Correspondingly, the first end electrode can include a first end surface electrode, a first front electrode, and a first back electrode. Similarly, the second end electrode can include a second end surface electrode, a second front electrode, and a second back electrode.

[0041] Figure 4 A schematic structural diagram of a long strip substrate obtained after slicing in the method for manufacturing a silicon capacitor based on end sealing provided in an embodiment of the present invention.

[0042] Combination Figures 1 to 4 Specifically, in S110, electrode terminals of a silicon capacitor product may be provided on the upper and lower surfaces of each strip substrate, a first front electrode and a second front electrode may be provided on the upper surface, and a first back electrode and a second back electrode may be provided on the lower surface. The first front electrode may be extended along a side of the substrate close to the first dicing processing surface, the second front electrode may be extended along a side of the substrate close to the second dicing processing surface, the first back electrode may be extended along a side of the substrate close to the first dicing processing surface, the second back electrode may be extended along a side of the substrate close to the second dicing processing surface, the first front electrode and the second front electrode may be spaced apart at a predetermined interval, and the first back electrode and the second back electrode may be spaced apart at a predetermined interval.

[0043] More specifically, an embodiment of the present invention provides a method for manufacturing a silicon capacitor based on end sealing, which may include that the sizes of the first front electrode, the second front electrode, the first back electrode, and the second front electrode may be constructed to be the same, and the materials of the first front electrode, the second front electrode, the first back electrode, and the second front electrode may include but are not limited to copper, aluminum, gold, silver, platinum, palladium, iridium, copper alloy, aluminum alloy, gold alloy, silver alloy, platinum alloy, palladium alloy, and iridium alloy.

[0044] More specifically, the predetermined spacing interval may be set differently according to actual process requirements.

[0045] In addition, it should be noted that, in one embodiment, Figure 4 The front electrode shown in the figure may be a first front electrode or a second front electrode, and Figure 4 The back electrode shown in can be the first back electrode or the second back electrode.

[0046] In addition, it should be noted that Figure 4 The silicon base shown in may also be referred to as a silicon substrate, or may be simply referred to as a substrate.

[0047] Figure 5 A schematic diagram of a structure obtained after stacking and fixing in a method for manufacturing a silicon capacitor based on end sealing provided in an embodiment of the present invention.

[0048] Figure 6 A schematic diagram of an end surface electrode in a method for manufacturing a silicon capacitor based on end sealing provided by an embodiment of the present invention.

[0049] Reference Figure 5 and Figure 6 It can be seen that after the S120 process in the method for manufacturing a silicon capacitor based on termination, a plurality of substrates are stacked and fixed, and a first dicing process surface and a second dicing process surface of each of the plurality of substrates are aligned.

[0050] Specifically, the dicing processed surface may be understood as a surface formed by the end portion of the substrate or wafer that has been diced.

[0051] Refer again Figure 6 Regarding S120, it should be noted that an embodiment of the present invention provides a method for manufacturing a silicon capacitor based on end sealing, which may include, in a physical vapor deposition sputtering process, sputtering a first sputtering material on a first scribe processing surface and a second scribe processing surface, and further sputtering a second sputtering material on the first scribe processing surface and the second scribe processing surface sputtered with the first sputtering material; after the sputtering of the first sputtering material and the second sputtering material is completed, further performing an annealing process.

[0052] Furthermore, an embodiment of the present invention provides a method for manufacturing a silicon capacitor based on end sealing, including: the first sputtering material may include but is not limited to titanium, chromium, tungsten, titanium alloy, chromium alloy, tungsten alloy, and the second sputtering material may include but is not limited to nickel, platinum, tungsten, copper, aluminum, gold, silver, palladium, iridium, nickel alloy, platinum alloy, tungsten alloy, copper alloy, aluminum alloy, gold alloy, silver alloy, palladium alloy, iridium alloy.

[0053] Specifically, a PVD sputtering process such as a sputtering coating machine can be used to sputter a metal film layer on the end faces of the stacked substrates. The sputtering materials include NiCr, Pt, W, etc. To ensure that the film layer has good adhesion after sputtering, ① the cleanliness of the end face needs to be checked before the sputtering process to ensure that there is no attachment on the surface; ② before sputtering the metal film layer, a layer of Ti metal film is first sputtered to improve the bonding strength between the metal film layer and the silicon substrate; ③ after sputtering, an annealing process can also be applied. Through the above sputtering process, the end face electrode obtained has good film quality and adhesion, and the end face after sputtering can achieve good electrical connection with the front electrode and back electrode of the silicon capacitor. Figure 6 As shown, the end surface electrodes are connected to the electrodes on the same side of the front electrode and the back electrode, respectively, to achieve the connection between the front electrode and the back electrode of the silicon capacitor, and at the same time, the capacitance value of the capacitor is increased by interconnecting the upper and lower electrodes. In addition, the end surface electrode acts as a seed layer to form an effective connection between the front and back electrodes and the end surface electrode, laying the foundation for the effective encapsulation of nickel, tin / lead in the subsequent electroplating process.

[0054] Refer again Figure 6 Regarding S130, it should be noted that an embodiment of the present invention provides a method for manufacturing a silicon capacitor based on end sealing, which may include: in a slurry process, using a slurry material to slurry the first slicing processing surface and the second slicing processing surface; and drying the first slicing processing surface and the second slicing processing surface after the slurry treatment to solidify the slurry material.

[0055] Refer again Figure 6 Regarding S130, it should be noted that an embodiment of the present invention provides a method for manufacturing a silicon capacitor based on end sealing, which may include: the slurry material includes a solution containing silver ions or copper ions.

[0056] Specifically, put the silicon capacitor product into a fixture with holes that match the product size, arrange them neatly, and use the end-sealing machine to dip the product with the end face down (for example, a solution containing silver ions or copper ions); after one side is completed, dry it, turn it over and dip it with the other side (for example, a solution containing silver ions or copper ions), set the temperature to at least 200°C in a nitrogen environment for drying, so that the end electrode slurry is fully solidified and forms a good connection with the front electrode and the back electrode, so as to achieve the end-sealing of the slurry. Figure 6 As shown, the end surface electrodes are connected to the electrodes on the same side of the front electrode and the back electrode, respectively, to achieve the connection between the front electrode and the back electrode of the silicon capacitor, and at the same time, the capacitance value of the capacitor is increased by interconnecting the upper and lower electrodes. In addition, the end surface electrode acts as a seed layer to form an effective connection between the front and back electrodes and the end surface electrode, laying the foundation for the effective encapsulation of nickel, tin / lead in the subsequent electroplating process.

[0057] Figure 7A schematic diagram of the structure of silicon capacitor particles obtained after slicing in the method for manufacturing a silicon capacitor based on end sealing provided in an embodiment of the present invention.

[0058] exist Figure 7 In the present invention, the front electrode on the upper surface of the silicon capacitor particle product can be referred to as the upper electrode, and the back electrode on the lower surface of the silicon capacitor particle product can be referred to as the back electrode.

[0059] Figure 8 A schematic structural diagram of a silicon capacitor based on end sealing obtained after electroplating in the case of a first end sealing process provided in an embodiment of the present invention.

[0060] like Figure 8 As shown, in the case of the first end-sealing process, that is, in the case of the physical vapor deposition sputtering process, the electroplating layer of the silicon capacitor based on the end-sealing obtained after the electroplating treatment is wrapped on three sides. Specifically, at one end of the silicon capacitor particle, the three-sided electroplating layer may include a front electrode, an end surface electrode, and a back electrode. It should be noted that for the silicon capacitor product based on the end-sealing after the final electroplating, its two ends respectively include two end electrodes, such as a first end electrode and a second end electrode (also referred to as end electrode 1 and end electrode 2). Accordingly, the first end electrode may include a first end surface electrode, a first front electrode, and a first back electrode. Similarly, the second end electrode may include a second end surface electrode, a second front electrode, and a second back electrode.

[0061] Combination Figure 8 Regarding S120 and S130, it should be noted that the method for manufacturing a silicon capacitor based on end sealing proposed in the embodiment of the present invention may include: the electroplating treatment includes roller plating or ion plating.

[0062] Specifically, the products after slurry end sealing are electroplated, and the process of roller plating or ion plating can be selected to wrap the front electrode, back electrode and end electrode of the silicon capacitor with Ni, Sn / Pb or other metals such as Cu, Zn, Sn, Ag, etc., so as to realize the lead-out of the silicon capacitor electrode and the reliable interconnection of the double-sided silicon capacitor structure electrodes, and improve the solderability of the silicon capacitor product. For example, nickel plating protects the electrode end from corrosion, and electroplating tin increases the solderability, so as to realize the lead-out of the silicon capacitor electrode and the reliable interconnection of the double-sided silicon capacitor structure electrodes.

[0063] Fig. 9 A schematic diagram of the structure of a silicon capacitor based on terminal sealing obtained after electroplating in the case of a second terminal sealing process provided by an embodiment of the present invention.

[0064] like Fig. 9As shown, in the case of the second end-sealing process, that is, in the case of the slurry dipping process, the electroplating layer of the silicon capacitor based on the end-sealing obtained after the electroplating treatment is wrapped on 5 sides. Specifically, at one end of the silicon capacitor particle, the 5-sided electroplating layer includes a front electrode, an end surface electrode, a back electrode, and two partial side surfaces surrounded by the front electrode, the end surface electrode, and the back electrode among the two complete side surfaces of the silicon capacitor particle. It should be noted that for the silicon capacitor product based on the end-sealing after the final electroplating, its two ends respectively include two end electrodes, such as a first end electrode and a second end electrode (also referred to as end electrode 1 and end electrode 2). Accordingly, the first end electrode may include a first end surface electrode, a first front electrode, a first back electrode, and two first partial side surfaces. Similarly, the second end electrode may include a second end surface electrode, a second front electrode, a second back electrode, and two second partial side surfaces.

[0065] Combination Fig. 9 It should be noted that the manufacturing method of the end-sealed silicon capacitor proposed in the embodiment of the present invention may include: after electroplating, the manufacturing method further includes: performing surface mounting processing on the end-sealed silicon capacitor.

[0066] The manufacturing method of the silicon capacitor based on end sealing provided by the embodiment of the present invention at least solves the following technical problems: on the one hand, the electrode can only be led out from the surface of the silicon capacitor and it is difficult to connect to the end face, so the double-sided silicon capacitor must rely on the through silicon via TSV process to achieve interconnection, and this manufacturing process is complex and the manufacturing cost is high; on the other hand, the bonding wire bonding or ball planting process has strict requirements on the operating equipment and environmental conditions, and the operation process is cumbersome. In other words, it is intended to reduce the requirements for the use environment, simplify the operation process, and realize the convenient interconnection of the electrodes of the double-sided silicon capacitor structure, thereby improving the overall performance and reliability of the silicon capacitor. The silicon capacitor based on end sealing provided by the embodiment of the present invention and its manufacturing method and manufacturing equipment enable silicon capacitors to be applied in more fields and promote the development of electronic equipment towards smaller size and higher performance. The embodiment of the present invention combines the SMT end sealing process, and the upper and lower electrodes of the silicon capacitor are electrically connected and the electrodes are led out by preparing the end electrode on the end face, so that the electrode interconnection of the double-sided silicon capacitor structure can be realized, forming a new SMT end sealing structure of a silicon capacitor product, and manufacturing a silicon capacitor product that can be directly mounted using SMT surface mounting technology. The embodiment of the present invention realizes the electrode interconnection of the double-sided silicon capacitor structure by end face connection, and the obtained silicon capacitor end-sealed product has low cost and combines the advantages of excellent performance of silicon capacitor products and convenient installation of ceramic capacitors. The silicon capacitor product after end sealing can be directly mounted using conventional SMT surface mounting technology, thereby realizing convenient and reliable SMT surface mounting use of silicon capacitors.

[0067] Based on the same inventive concept, on the other hand, an embodiment of the present invention provides a silicon capacitor based on terminal sealing.

[0068] Specifically, the end-sealed silicon capacitor uses a single crystal silicon wafer as a substrate and uses a semiconductor process to complete wafer production. The end-sealed silicon capacitor is small in size, has excellent high-frequency characteristics, low equivalent series resistance and low equivalent series inductance, a wide temperature operating range of -55~200°C, high reliability, and a ten-year lifespan at 100°C under the operating voltage. The typical maximum rated voltage scenario that can be applied can reach 100V, and it can be customized according to requirements to improve the capacitor's withstand voltage performance, and is suitable for radio frequency, power amplifiers, optical communications and other fields. The end-sealed silicon capacitor uses photolithography and deep silicon etching processes to prepare a 3D structure on the wafer surface to increase the effective plate area of ​​the capacitor, thereby achieving an increase in the capacitance density per unit area of ​​the capacitor. The embodiments of the present invention use PVD, CVD, ALD and other processes to prepare electrode layers and dielectric layers. Typical dielectric layer materials include but are not limited to silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, barium titanate, strontium titanate, etc. Due to the characteristics of semiconductor technology, the process accuracy can be controlled below micron accuracy, based on which the capacity accuracy of silicon capacitors is controlled below ±1%. The electrode is patterned through RIE and other processes to complete the lead-out of the capacitor electrode on the surface. The metal surface electrode is prepared using sputtering and evaporation coating processes, and the metal material, process and graphics are selected according to the product packaging form. The silicon capacitor products prepared by the end-sealing process have the advantages of small size, direct mounting and use, and convenience and speed, which solves the limitation that conventional silicon capacitors can only be used for patching, wire bonding or ball planting.

[0069] The manufacturing method of the silicon capacitor based on end sealing provided in the embodiment of the present invention is manufactured based on the above-mentioned manufacturing method of the silicon capacitor based on end sealing, and therefore at least solves the following technical problems: on the one hand, the electrode can only be led out from the surface of the silicon capacitor and is difficult to connect to the end face, so the double-sided structure silicon capacitor must rely on the silicon through-hole TSV process to achieve interconnection, and this manufacturing process is complex and has high manufacturing costs; on the other hand, the bonding wire bonding or ball planting process has strict requirements on the operating equipment and environmental conditions, and the operating process is cumbersome. In other words, it is intended to reduce the requirements for the use environment, simplify the operating process, and realize the convenient interconnection of the electrodes of the double-sided silicon capacitor structure, thereby improving the overall performance and reliability of the silicon capacitor. The silicon capacitor based on end sealing and its manufacturing method and manufacturing equipment provided in the embodiment of the present invention enable silicon capacitors to be applied in more fields and promote the development of electronic equipment towards smaller size and higher performance. The embodiment of the present invention combines the SMT end-sealing process, and the upper and lower electrodes of the silicon capacitor are electrically connected and the electrodes are led out by preparing the end electrodes on the end faces, so that the electrode interconnection of the double-sided silicon capacitor structure can be realized, forming a new SMT end-sealing structure for silicon capacitor products, and manufacturing silicon capacitor products that can be directly mounted using SMT surface mounting technology. The embodiment of the present invention realizes the electrode interconnection of the double-sided silicon capacitor structure by end-face connection, and the obtained silicon capacitor end-sealing product has low cost, and combines the advantages of excellent performance of silicon capacitor products and convenient installation of ceramic capacitors. The silicon capacitor product after end-sealing can be directly mounted using conventional SMT surface mounting technology, realizing convenient and reliable SMT surface mounting use of silicon capacitors.

[0070] On the other hand, based on the same inventive concept, another embodiment of the present invention provides a manufacturing device for a silicon capacitor.

[0071] Fig.10 A schematic diagram of a manufacturing device for a silicon capacitor based on terminal sealing provided in accordance with an embodiment of the present invention.

[0072] In this embodiment, it should be noted that the manufacturing equipment of the end-capped silicon capacitor may include: a processor (processor) 1010, a communication interface (Communications Interface) 1020, a memory (memory) 1030 and a communication bus 1040, wherein the processor 1010, the communication interface 1020, and the memory 1030 communicate with each other through the communication bus 1040. The processor 1010 can call the logic instructions in the memory 1030 to execute the manufacturing method of the silicon capacitor based on end sealing, including: S110: based on the end sealing process, determine to perform a dicing process corresponding to the end sealing process on the wafer, and perform an electroplating process after the dicing process and the end sealing process corresponding to the dicing process are completed, the end sealing process includes a physical vapor deposition sputtering process or a slurry dipping process; S120: in the case of the physical vapor deposition sputtering process, the wafer is divided into a plurality of substrates of a long strip along a direction perpendicular to the upper surface of the wafer, each of the plurality of substrates is constructed to have an upper surface and a lower surface, the upper surface is provided with a first front electrode and a second front electrode, the lower surface is provided with a first back electrode and a second back electrode, the first front electrode is extended along a side of the substrate close to the first dicing process surface, the second front electrode is extended along a side of the substrate close to the second dicing process surface, the first back electrode is extended along a side of the substrate close to the first dicing process surface, the second back electrode is extended along a side of the substrate close to the second dicing process surface, the first front electrode is The electrode and the second front electrode are spaced apart at a predetermined interval, and the first back electrode and the second back electrode are spaced apart at a predetermined interval; a plurality of substrates are stacked and fixed to align the first scribe processing surface and the second scribe processing surface of each of the plurality of substrates; for the plurality of substrates after being stacked and fixed, a first end surface electrode is prepared on the first scribe processing surface by a physical vapor deposition sputtering process, so that the first end surface electrode interconnects the first front electrode with the first back electrode, and a second end surface electrode is prepared on the second scribe processing surface by a physical vapor deposition sputtering process, so that the second end surface electrode interconnects the second front electrode with the second back electrode; through a scribe process, the plurality of stacked substrates processed by the physical vapor deposition sputtering process are further divided into a plurality of silicon capacitor particles of a long strip along a direction perpendicular to the upper surface of the wafer; through an electroplating process, the first front electrode, the first end surface electrode, the first back electrode, the second front electrode, the second end surface electrode, and the second back electrode on each of the plurality of silicon capacitor particles are electroplated to obtain a silicon capacitor based on end sealing;S130: In the case of a slurry dipping process, the wafer is divided into a plurality of silicon capacitor particles in a long strip along a direction perpendicular to the upper surface of the wafer, each of the plurality of silicon capacitor particles is constructed to have at least one of an upper surface or a lower surface, the upper surface is provided with a first front electrode and a second front electrode, the lower surface is provided with a first back electrode and a second back electrode, the first front electrode is arranged along a side of the silicon capacitor particle close to the first dicing processing surface, the second front electrode is arranged along a side of the silicon capacitor particle close to the second dicing processing surface, the first back electrode is arranged along a side of the silicon capacitor particle close to the first dicing processing surface, the second back electrode is arranged along a side of the silicon capacitor particle close to the second dicing processing surface, the first front electrode and the second front electrode are spaced apart at a predetermined interval, and the first back electrode and the second back electrode are spaced apart at a predetermined interval; for the plurality of silicon capacitor particles, A first end surface electrode is prepared on the first scribe processing surface by a slurry process, so that the first end surface electrode interconnects the first front electrode with the first back electrode, and a second end surface electrode is prepared on the second scribe processing surface by a slurry process, so that the second end surface electrode interconnects the second front electrode with the second back electrode; through electroplating, the first front electrode, the first end surface electrode, the first back electrode, the second front electrode, the second end surface electrode, and the second back electrode on each silicon capacitor particle treated by the slurry process are electroplated, and the first part of the side surface surrounded by the first front electrode, the first end surface electrode, and the first back electrode of each silicon capacitor particle is electroplated, and the second part of the side surface surrounded by the second front electrode, the second end surface electrode, and the second back electrode of each silicon capacitor particle is electroplated to obtain a silicon capacitor based on end sealing. ;

[0073] In addition, the logic instructions in the above-mentioned memory 1030 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0074] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0075] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0076] In addition, in the present invention, the description with reference to the terms "embodiment", "present embodiment", "another embodiment", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a silicon capacitor based on end sealing, characterized in that: include: Based on the end sealing process, it is determined that a dicing process corresponding to the end sealing process is performed on the wafer, and an electroplating process is performed after the dicing process and the end sealing process corresponding to the dicing process are completed, wherein the end sealing process includes a physical vapor deposition sputtering process or a slurry dipping process, In the case of the physical vapor deposition sputtering process, Divide the wafer into a plurality of substrates of long strips along a direction perpendicular to the upper surface of the wafer, each of the plurality of substrates being constructed to have an upper surface and a lower surface, the upper surface being provided with a first front electrode and a second front electrode, the lower surface being provided with a first back electrode and a second back electrode, the first front electrode extending along a side of the substrate close to a first dicing processing surface, the second front electrode extending along a side of the substrate close to a second dicing processing surface, the first back electrode extending along a side of the substrate close to the first dicing processing surface, the second back electrode extending along a side of the substrate close to the second dicing processing surface, the first front electrode and the second front electrode being spaced apart by a predetermined interval, and the first back electrode and the second back electrode being spaced apart by the predetermined interval; stacking and fixing the plurality of substrates to align the first dicing processing surface and the second dicing processing surface of each of the plurality of substrates; For the stacked and fixed multiple substrates, a first end surface electrode is prepared on the first scribing surface by the physical vapor deposition sputtering process, so that the first end surface electrode interconnects the first front electrode with the first back electrode, and a second end surface electrode is prepared on the second scribing surface by the physical vapor deposition sputtering process, so that the second end surface electrode interconnects the second front electrode with the second back electrode by physical vapor deposition; through the scribing process, the stacked multiple substrates processed by the physical vapor deposition sputtering process are further divided into a plurality of silicon capacitor particles in a long strip along a direction perpendicular to the upper surface of the wafer; Electroplating the first front electrode, the first end surface electrode, the first back surface electrode, the second front electrode, the second end surface electrode, and the second back surface electrode on each of the plurality of silicon capacitor particles through electroplating to obtain the end-sealed silicon capacitor; or, In the case of the slurry dipping process, Divide the wafer into a plurality of silicon capacitor particles in a strip along a direction perpendicular to the upper surface of the wafer, each of the plurality of silicon capacitor particles being constructed to have at least one of an upper surface or a lower surface, the upper surface being provided with a first front electrode and a second front electrode, the lower surface being provided with a first back electrode and a second back electrode, the first front electrode being arranged along a side of the silicon capacitor particle close to a first scribe processing surface, the second front electrode being arranged along a side of the silicon capacitor particle close to a second scribe processing surface, the first back electrode being arranged along a side of the silicon capacitor particle close to the first scribe processing surface, the second back electrode being arranged along a side of the silicon capacitor particle close to the second scribe processing surface, the first front electrode and the second front electrode being spaced apart at a predetermined interval, and the first back electrode and the second back electrode being spaced apart at the predetermined interval; for the plurality of silicon capacitor particles, prepare a first end surface electrode on the first scribe processing surface by the slurry dipping process, so that the first end surface electrode interconnects the first front electrode with the first back electrode, and prepare a second end surface electrode on the second scribe processing surface by the slurry dipping process, so that the second end surface electrode interconnects the second front electrode with the second back electrode; Through electroplating treatment, the first front electrode, the first end surface electrode, the first back electrode, the second front electrode, the second end surface electrode, and the second back surface electrode on each silicon capacitor particle treated by the slurry process are electroplated, and the first part of the side surface of the two side surfaces of each silicon capacitor particle surrounded by the first front electrode, the first end surface electrode, and the first back surface electrode is electroplated, and the second part of the side surface of the two side surfaces of each silicon capacitor particle surrounded by the second front electrode, the second end surface electrode, and the second back surface electrode is electroplated to obtain the end-sealed silicon capacitor.

2. The method for manufacturing a silicon capacitor based on end sealing according to claim 1, characterized in that: The first front electrode, the second front electrode, the first back electrode, and the second front electrode have the same size; The materials of the first front electrode, the second front electrode, the first back electrode, and the second front electrode include copper, aluminum, gold, silver, platinum, palladium, iridium, copper alloy, aluminum alloy, gold alloy, silver alloy, platinum alloy, palladium alloy, and iridium alloy.

3. The method for manufacturing a silicon capacitor based on end sealing according to claim 1, characterized in that: In the physical vapor deposition sputtering process, sputtering a first sputtering material onto the first scribing processed surface and the second scribing processed surface, further sputtering a second sputtering material onto the first scribing processed surface and the second scribing processed surface sputtered with the first sputtering material; After the sputtering of the first sputtering material and the second sputtering material is completed, an annealing process is further performed.

4. The method for manufacturing a silicon capacitor based on end sealing according to claim 3, characterized in that: The first sputtering material at least includes titanium, chromium, tungsten, titanium alloy, chromium alloy, tungsten alloy, The second sputtering material includes at least nickel, platinum, tungsten, copper, aluminum, gold, silver, palladium, iridium, nickel alloy, platinum alloy, tungsten alloy, copper alloy, aluminum alloy, gold alloy, silver alloy, palladium alloy, and iridium alloy.

5. The method for manufacturing a silicon capacitor based on end sealing according to claim 1, characterized in that: In the slurry dipping process, Using a slurry material, performing a slurry treatment on the first scribe processing surface and the second scribe processing surface; The first dicing processing surface and the second dicing processing surface after the slurry processing are dried to solidify the slurry material.

6. The method for manufacturing a silicon capacitor based on end sealing according to claim 5, characterized in that: The slurry material includes a solution containing silver ions or copper ions.

7. The method for manufacturing a silicon capacitor based on end sealing according to claim 1, characterized in that: The electroplating process includes barrel plating or ion plating.

8. The method for manufacturing a silicon capacitor based on terminal sealing according to any one of claims 1 to 7, characterized in that: After the electroplating, the manufacturing method further includes: performing a surface mounting process on the end-cap-based silicon capacitor.

9. A manufacturing device for silicon capacitors based on end sealing, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of the method for manufacturing a silicon capacitor based on end sealing as described in any one of claims 1 to 8 are implemented to manufacture the silicon capacitor based on end sealing.

10. A silicon capacitor based on end sealing, characterized in that: The silicon capacitor based on end sealing is manufactured according to the method for manufacturing a silicon capacitor according to any one of claims 1 to 8 and based on the manufacturing equipment for a silicon capacitor based on end sealing according to claim 9.

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