Semiconductor wafer cutting method
By using scribing knives of different widths for multiple cuts and wet etching, the problems of high mechanical stress and lots of debris during cutting of mercury cadmium tellurium infrared devices are solved, and a more efficient and accurate cutting process is achieved.
Patent Information
- Application Number
- CN202510243405.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-03
- Publication Date
- 2025-04-11
AI Technical Summary
In the process of cutting mercury cadmium telluride infrared devices, the mechanical stress is high, which can easily lead to edge collapse and cracks in the chip base material and film layer. Moreover, more debris are generated when cutting thicker substrate materials, affecting the subsequent cleaning process.
Cutting blades of different widths are used to cut multiple times to form a first line trough and a second line trough, and wet etching is performed at the second line trough to separate multiple mercury cadmium tellurium chips one by one.
The pressure on the slashing knife to the mercury cadmium tellurium chip is reduced, the mechanical swing and edge collapse problems are reduced, the generation of debris is reduced, and the cutting accuracy and efficiency are improved.
Smart Images
Figure CN119795401A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of infrared refrigeration detectors, and in particular to a semiconductor wafer cutting method. Background Art
[0002] With the continuous promotion and development of infrared applications, advanced infrared detection technology requires detectors to have higher spatial resolution and better target recognition capabilities. Infrared detectors are photoelectric devices that convert infrared radiation into electronic signals. The photoelectric reaction only occurs on the photosensitive element, and the subsequent signal processing process only involves electronic technology. Therefore, infrared detection chips are the core components of infrared detectors.
[0003] In the preparation of HgCdTe infrared devices, the mainstream method of cutting HgCdTe material chips is currently mechanical diamond cutting. The diamond blade directly cuts the chip along the cutting path at a high speed of 30,000 to 40,000 revolutions per minute. Since the chip is directly cut, the cutting will produce greater mechanical stress, which is easy to cause chip bottom material and film layer to collapse and crack. The thicker the substrate material, the greater the impact. If the HgCdTe chip substrate is thicker, a blade with a higher blade edge must be selected. A dicing knife with a higher blade edge / blade width ratio will swing during cutting, which will cause greater front stratification and back edge collapse. In addition, direct cutting produces more debris, which makes subsequent cleaning processes difficult. Existing technologies cannot solve this problem. Summary of the invention
[0004] In order to solve the problems existing in the prior art, the present invention provides a method for cutting a semiconductor wafer.
[0005] The present invention provides a semiconductor wafer cutting method, comprising the steps of: providing a wafer, wherein the wafer comprises a plurality of mercury cadmium telluride chips; using a first dicing blade to perform a first dicing on the gaps between the plurality of mercury cadmium telluride chips to form a first line groove; using a second dicing blade to perform a second dicing along the first line groove to form a second line groove, wherein the width of the second line groove is smaller than the width of the first line groove, and the sum of the depth of the second line groove and the depth of the first line groove is smaller than the thickness of the wafer; and wet etching the wafer at the second line groove to separate the plurality of mercury cadmium telluride chips one by one.
[0006] Optionally, before the first scribing, the method further includes: disposing a photoresist on the first surface of the wafer; and forming a cutting pattern on the photoresist, wherein the cutting pattern is located at a gap between the plurality of mercury cadmium telluride chips.
[0007] Optionally, the depth of the first scribing is 1 / 10-1 / 3 of the thickness of the wafer.
[0008] Optionally, the depth of the first scribing is 1 / 5 of the thickness of the wafer.
[0009] Optionally, the semiconductor wafer cutting method further comprises: before the second cutting, placing the wafer in an oven for baking, the baking temperature range is 60-120° C., and the baking time is 1-5 hours.
[0010] Optionally, the blade width of the second dicing knife is less than 2 / 3 of the blade width of the first dicing knife.
[0011] Optionally, the using a second dicing knife to perform a second dicing along the first line groove includes: performing multiple dicing along the first line groove until the thickness of the wafer at the bottom of the second line groove is 1 / 10-1 / 3 of the thickness of the wafer at the undiced position.
[0012] Optionally, the solution used for the wet etching is a bromine methanol solution with a ratio of 1%-10%.
[0013] Optionally, the etching depth of the wet etching is 1 / 10-1 / 3 of the wafer thickness.
[0014] Optionally, the etching depth of the wet etching is 1 / 5 of the wafer thickness.
[0015] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0016] The present invention provides a semiconductor wafer cutting method, which uses dicing knives of different widths, and separates multiple mercury cadmium telluride chips on the semiconductor wafer one by one by using a wet etching process after multiple dicing, thereby reducing the pressure applied by the dicing knife to the mercury cadmium telluride chips during direct dicing, reducing the mechanical swing and edge collapse problems caused by using a dicing knife with a higher blade height / blade width ratio, and reducing the large amount of debris generated when thick materials are diced. At the same time, since the thickness of the dicing knives used for the two dicings is different, after the dicing is completed, a "convex" step is formed at the edge of each mercury cadmium telluride chip, which can prevent the effective area from being affected by external forces such as collisions during the transportation and processing of the mercury cadmium telluride chips. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0018] Figure 1 It is a schematic diagram of the intermediate structure of the semiconductor wafer cutting process in the prior art;
[0019] Figure 2A top view of an intermediate structure in a semiconductor wafer cutting process in the prior art;
[0020] Figure 3 A schematic diagram of a process of cutting a semiconductor wafer in one embodiment of the present invention;
[0021] Figure 4 It is a schematic diagram of an intermediate structure of a semiconductor wafer cutting process in one embodiment of the present invention;
[0022] Figure 5 The figure is a top view of an intermediate structure of a semiconductor wafer cutting process according to an embodiment of the present invention. DETAILED DESCRIPTION
[0023] The preferred embodiments of the present invention will be described in more detail below. Although the preferred embodiments of the present invention are described below, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.
[0024] In the present invention, unless otherwise specified, the directional words used, such as "upper and lower", generally refer to the upper and lower parts of the device in normal use, and "inside and outside" refer to the outline of the device. In addition, the terms "first, second, third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first, second, third" may explicitly or implicitly include one or more of the features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined. In the present invention, it is an electrical device, so connection and interconnection both refer to conductive interconnection. Since the accompanying drawings are descriptions of the same device, the same numbers in the drawings represent the same components.
[0025] At present, in the process of preparing HgCdTe infrared devices, the cutting method of HgCdTe material chips mainly adopts mechanical diamond blade cutting. Figure 1 and Figure 2 As shown, in the prior art, a dicing blade 230 is used to diced the semiconductor wafer 100 along the cutting pattern, and the gaps between the HgCdTe chips 110 on the semiconductor wafer 100 are directly cut off, so that the multiple HgCdTe chips 110 are separated one by one. Since the HgCdTe chips are directly cut off, dicing will generate greater mechanical stress, which is easy to cause chipping and cracks to the chip bottom material and film layer; the thicker the substrate material, the greater the impact. If the HgCdTe chip substrate is thicker, a blade with a longer blade is required. A dicing blade with a higher blade / blade width ratio will swing during cutting, which will cause greater front stratification and back edge collapse. Direct cutting generates more debris, which makes the subsequent cleaning process difficult.
[0026] Therefore, the present invention provides a semiconductor wafer cutting method, which can effectively solve the above problems and greatly improve the performance of infrared detection chips.
[0027] The present invention provides a semiconductor wafer cutting method, comprising the steps of: providing a wafer, wherein the wafer comprises a plurality of mercury cadmium telluride chips; using a first dicing blade to perform a first dicing on the gaps between the plurality of mercury cadmium telluride chips to form a first line groove; using a second dicing blade to perform a second dicing along the first line groove to form a second line groove, wherein the width of the second line groove is smaller than the width of the first line groove, and the sum of the depth of the second line groove and the depth of the first line groove is smaller than the thickness of the wafer; and wet etching the wafer at the second line groove to separate the plurality of mercury cadmium telluride chips one by one.
[0028] The specific examples of the present invention are further described in detail below in conjunction with the accompanying drawings. Wherein, the substances not listed in detail in the embodiments can be selected from any substances on the market that can achieve corresponding functions.
[0029] The present invention provides a method for cutting a semiconductor wafer. In one embodiment, the specific steps are as follows: Figure 3 As shown, combined Figure 3-Figure 5 , the semiconductor wafer cutting method comprises the following steps:
[0030] S1: providing a wafer, wherein the wafer comprises a plurality of mercury cadmium telluride chips.
[0031] Specifically, a wafer 100 is provided. The wafer 100 includes a plurality of HgCdTe chips 110. In some embodiments, the wafer may be a HgCdTe substrate with a thickness of 600um-1600um.
[0032] In one embodiment of the present invention, the wafer 100 is a semiconductor wafer, a photoresist 120 is spin-coated on a first surface of the wafer 100 , and a cutting pattern is formed on the photoresist 120 . The cutting pattern is located at the gap between the HgCdTe chips 110 .
[0033] S2: using a first dicing blade to perform a first dicing on the gaps between the plurality of HgCdTe chips to form a first line groove.
[0034] In one embodiment of the present invention, the first dicing knife 210 uses a thicker and wider dicing knife to cut a line groove with a depth of 1 / 10-1 / 3 of the wafer thickness along the cutting pattern, that is, the first line groove 101. In the embodiment of the present disclosure, the blade width of the dicing knife refers to the thickness of the blade, that is, the width of the line groove formed after dicing.
[0035] The first dicing blade is thicker and wider, and the first line groove formed is wider, which can effectively prevent the second dicing blade from touching the chip film layer and causing damage to the chip film layer during the second dicing.
[0036] In some embodiments, the depth of the first scribing may be 1 / 10-1 / 3 of the wafer thickness. Preferably, in the disclosed embodiment, the depth of the first scribing is 1 / 5 of the wafer thickness, because the first scribing depth is relatively small, and the mechanical stress generated during scribing is relatively small, which reduces the edge collapse and cracks caused by the first scribing on the chip film layer.
[0037] For example, in some embodiments, the first dicing blade is a diamond blade with an outer diameter of 35-50 mm, a blade length of 0.8-15 mm, and a blade width of 200-300 um, and performs the first dicing of the chip along the cutting pattern at a high speed of 25,000 to 40,000 rpm.
[0038] S3: Use a second dicing knife to perform a second dicing along the first line groove to form a second line groove, wherein the width of the second line groove is smaller than the width of the first line groove, and the sum of the depth of the second line groove and the depth of the first line groove is smaller than the thickness of the wafer.
[0039] In one embodiment of the present invention, the second dicing blade 220 uses a dicing blade with a blade width smaller than that of the first dicing blade 210 to perform a second dicing on the wafer 100 along the first line groove 101 to form a second line groove 102 .
[0040] In one embodiment of the present invention, the second dicing knife performs a second dicing along the first line groove, comprising: performing multiple dicing along the first line groove until the thickness of the wafer at the bottom of the second line groove is 1 / 10-1 / 3 of the thickness of the wafer at the undiced position. Since the second dicing does not directly disconnect the chip but forms a second line groove, a margin is reserved below the second line groove, and the thickness of the margin is 1 / 10-1 / 3 of the wafer thickness. This not only avoids the back edge collapse problem caused by the dicing knife, but also reduces the large amount of debris generated when thicker materials are diced. Because the second line groove is formed by multiple dicing methods, the dicing depth is reduced each time, which can also avoid the selection of a blade with a higher blade, and reduces the swing of a dicing knife with a higher blade / blade width ratio when dicing the wafer. In particular, when it is necessary to cut semiconductor wafers with thicker substrate materials, the thicker the substrate material, the greater the impact. Multiple dicing and each dicing with a smaller depth can reduce the swing and stress of the dicing knife when dicing the wafer, and reduce the impact of the dicing knife swing on the chip.
[0041] For example, in some embodiments, the second dicing knife is a diamond blade with an outer diameter of 35-50 mm, a blade length of 1-2 mm, and a blade width of 150-200 um. The chip is diced for the second time along the cutting pattern at a high speed of 20,000 to 30,000 rpm, and the dicing amount each time does not exceed 300 um.
[0042] In different embodiments, the number of cuts of the second cut can be determined according to actual needs, and the present invention is not limited to this.
[0043] In some embodiments, the blade width of the second dicing knife is less than 2 / 3 of the blade width of the first dicing knife. Since the blade width of the dicing knife used for the second dicing is less than 2 / 3 of the width of the dicing knife used for the first dicing, when dicing the bottom of the first line groove along the first line groove in the first line groove, the second dicing knife can be prevented from touching the chip film layer and causing damage to the chip film layer, thereby reducing the edge chipping and cracks caused by dicing on the front film layer of the chip.
[0044] Preferably, in the embodiment of the present disclosure, the width of the second dicing blade is less than 1 / 3 of the width of the first dicing blade.
[0045] In some embodiments, before the wafer is diced for the second time, the wafer that has been diced for the first time can be placed in an oven for baking to release internal stress. The baking temperature in the oven ranges from 60 to 120° C. and the baking time is 1 to 5 hours.
[0046] Preferably, in the embodiment of the present disclosure, the baking temperature in the oven is 90° C., and the baking time is preferably 3 hours.
[0047] In some embodiments, the second scribing is performed multiple times along the first line groove until 1 / 10-1 / 3 of the thickness of the semiconductor wafer remains at the bottom of the second line groove.
[0048] Preferably, in the embodiment of the present disclosure, after the second dicing, the thickness of the semiconductor wafer remaining at the bottom of the second line groove is 1 / 5 of the thickness of the semiconductor wafer at the undiced portion.
[0049] S4: wet-etching the wafer at the second wire groove to separate the plurality of mercury cadmium telluride chips one by one.
[0050] In one embodiment of the present invention, a 1%-10% bromine methanol solution is used to wet etch the semiconductor wafer 100 to remove the semiconductor wafer 103 remaining at the bottom of the second wire slot, and the plurality of HgCdTe chips 110 are disconnected to form a plurality of independent HgCdTe chips 110 .
[0051] In some embodiments, the etching depth of the wet etching is 1 / 10-1 / 3 of the wafer thickness. In other words, the wet etching needs to completely etch through the semiconductor wafer at the bottom of the second slot, and after the second dicing is completed, the remaining semiconductor wafer 103 at the bottom of the second slot is removed by wet etching. This can effectively reduce the mechanical swing caused by the dicing knife directly cutting the semiconductor wafer, thereby reducing the edge collapse and cracks caused by mechanical swing to the bottom material of the chip, and improve the large amount of debris generated when directly cutting the semiconductor wafer of thicker material, reducing the difficulty of subsequent cleaning processes.
[0052] Preferably, in the embodiment of the present disclosure, wet etching is used to remove the remaining wafer at the bottom of the second wire slot, and the etching solution that can be used is a 5% bromine methanol solution.
[0053] Preferably, in the embodiment of the present disclosure, the etching depth of the wet etching is 1 / 5 of the wafer thickness.
[0054] During the wafer cutting process, due to the use of dicing knives of different widths, the width of the first line groove formed by the first cutting is different from the width of the second line groove formed by the second cutting. The width of the second line groove is less than 1 / 3 of the width of the first line groove. After the wafer cutting is completed, a "convex" step will be formed at the edge of each mercury cadmium telluride chip. The "convex" step can prevent the effective area of the mercury cadmium telluride chip from being affected by external forces such as collision during transportation and processing.
[0055] The above descriptions are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structural or equivalent process transformations made using the contents of the specification and drawings of the present application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.
Claims
1. A method for cutting a semiconductor wafer, characterized in that: Includes steps: Providing a wafer, wherein the wafer comprises a plurality of mercury cadmium telluride chips; Using a first dicing blade, dicing the gaps between the plurality of HgCdTe chips for the first time to form first line grooves; Using a second dicing blade to perform a second dicing along the first line groove to form a second line groove, wherein the width of the second line groove is smaller than the width of the first line groove, and the sum of the depth of the second line groove and the depth of the first line groove is smaller than the thickness of the wafer; The wafer at the second wire groove is wet-etched to separate the plurality of mercury cadmium telluride chips one by one.
2. The semiconductor wafer cutting method according to claim 1, characterized in that: Before the first cutting, the method further includes: Disposing a photoresist on a first surface of the wafer; A cutting pattern is formed on the photoresist, wherein the cutting pattern is located at a gap between the plurality of HgCdTe chips.
3. The semiconductor wafer cutting method according to claim 1, wherein: The depth of the first dicing is 1 / 10-1 / 3 of the wafer thickness.
4. The semiconductor wafer cutting method according to claim 3, characterized in that: The depth of the first dicing is 1 / 5 of the wafer thickness.
5. The semiconductor wafer dicing method according to claim 1, wherein: Also includes: Before the second dicing, the wafer is placed in an oven for baking, the baking temperature range is 60-120° C., and the baking time is 1-5 hours.
6. The semiconductor wafer dicing method according to claim 1, wherein: The blade width of the second dicing knife is less than 2 / 3 of the blade width of the first dicing knife.
7. The semiconductor wafer dicing method according to claim 1, wherein: The second scribing along the first line groove using the second scribing knife includes: performing multiple scribing along the first line groove until the thickness of the wafer at the bottom of the second line groove is 1 / 10-1 / 3 of the thickness of the wafer at the un-scribed position.
8. The semiconductor wafer dicing method according to claim 1, wherein: The solution used for the wet etching is a bromine methanol solution with a ratio of 1%-10%.
9. The semiconductor wafer dicing method according to claim 1, wherein: The etching depth of the wet etching is 1 / 10-1 / 3 of the wafer thickness.
10. The semiconductor wafer dicing method according to claim 9, wherein: The etching depth of the wet etching is 1 / 5 of the wafer thickness.