Two-stage fault simulation method based on multi-core CPU

Abstract

The invention provides a two-stage fault simulation method based on a multi-core CPU, and the method comprises the steps: obtaining a circuit model, a test vector set and a fault list, the vector set comprises a plurality of test vectors, and the fault list comprises a plurality of faults; the number N of threads of the multi-core CPU is obtained, the multiple test vectors are distributed to the N threads in a balanced mode, the multiple faults are divided into M fault blocks, a fault block set is obtained, and M is larger than N; simulation is carried out by N threads according to a preset simulation mode, and the mode comprises that each thread executes the following operations: executing simulation of a first stage: each thread obtains a remaining fault block for testing each time, when the self-acquired fault blocks are tested and no residual fault blocks exist, switching to second-stage simulation, and updating undetected faults according to the faults detected during simulation and the fault list; and executing simulation of a second stage, wherein the simulation comprises the step of testing all the faults which are not detected by utilizing the self-assigned test vectors.

Description

Technical Field

[0001] The present invention relates to the technical field related to integrated circuits, in particular to the field of fault simulation and testing of integrated circuits, and more particularly to a two-stage fault simulation method based on a multi-core CPU. Background Art

[0002] There are many fault models for digital circuits, such as stuck-at fault, bridge fault, permanent fault and transient fault.

[0003] With the development of nano-integrated circuit technology, a single Very Large Scale Integration Circuit (VLSI) can integrate more than 1 billion transistors. In order to discover defects that may be missed during the design or manufacturing process, fault simulation plays a vital role in the test development stage of the VLSI design process. The fault simulation algorithm evaluates the behavior of the circuit by inputting the generated test vector into the circuit and simulating various faults injected into the circuit, thereby detecting faults in the circuit. With the rapid growth of VLSI scale, the performance of the fault simulation algorithm directly affects the efficiency of test generation and fault diagnosis. The long running time of fault simulation has become a key issue in the current design test development stage.

[0004] In order to improve the speed and effectiveness of fault simulation algorithms, researchers have conducted in-depth research on various aspects. Many works use the powerful parallel computing capabilities of GPU to accelerate fault simulation. In addition, some studies aim to speed up multi-core fault simulation by minimizing memory usage during fault simulation or adopting shared memory strategies. In the field of distributed computing, some scholars have also explored the acceleration effect of distributed computing on fault simulation. In addition, some research works have optimized fault simulation based on traditional parallel vector single fault propagation (PPSFP) or parallel fault simulation methods.

[0005] In today's research field, various methods have been proposed for fault simulation, but a single method is often unable to cope with the multiple challenges brought by the field of fault simulation. Fault simulation faces many complexities and uncertainties, such as the continuous expansion of the scale of integrated circuits, the increase in design complexity, and the continuous advancement of manufacturing processes. These factors make it difficult for a single fault simulation optimization method to meet actual needs. At the same time, in the research of multi-threaded simulation algorithms, there is currently a lack of effective algorithm design, and the load balancing and task scheduling strategies between threads need to be improved. So far, no effective method has been found to effectively combine various optimization strategies with multi-threaded algorithms.

[0006] In the process of investigating the previous fault simulation acceleration algorithms, it was found that the single-thread model used in them would cause high communication costs in multi-threads, and the task allocation strategy adopted would also cause a large number of invalid waiting and load imbalance problems among multi-threads.

[0007] It should be noted that this background technology is only used to introduce the relevant information of the present invention to help understand the technical solution of the present invention, but it does not mean that the relevant information is necessarily the prior art. The relevant information is submitted and disclosed together with the present invention solution. If there is no evidence that the relevant information has been disclosed before the application date of the present invention, the relevant information shall not be regarded as the prior art. Summary of the invention

[0008] Therefore, the purpose of the present invention is to overcome the defects of the prior art and provide a two-stage fault simulation method based on a multi-core CPU.

[0009] The objective of the present invention is achieved through the following technical solutions:

[0010] According to a first aspect of the present invention, a two-stage fault simulation method based on a multi-core CPU is provided, comprising: obtaining a circuit model to be tested, a test vector set and a fault list, wherein the test vector set includes multiple test vectors, and the fault list includes multiple faults to be injected; obtaining the number of threads N of the multi-core CPU, evenly distributing multiple test vectors to the N threads, dividing multiple faults into M fault blocks, and obtaining a fault block set, wherein M>N; simulating by the N threads in accordance with a preset two-stage fault simulation method, the method comprising each thread performing the following operations respectively: executing the first stage of simulation, which comprises: each thread obtains one remaining fault block each time for testing, until the fault block obtained by itself has completed the test and there are no remaining fault blocks, then entering the second stage of simulation, wherein undetected faults are updated according to the faults detected during the simulation and the fault list; and executing the second stage of simulation, which comprises: testing all undetected faults using the test vectors allocated to itself.

[0011] Optionally, the simulation of the first stage includes: maintaining the remaining fault block set and the shared undetected fault set shared by each thread, wherein the remaining fault block set is initially a set of M fault blocks, and the undetected fault set is initially a set of all faults in the fault list; each thread is configured to perform the following processing: each thread obtains a remaining fault block from the remaining fault block set each time and removes it from the remaining fault block set; inputs the test vector assigned to itself into the circuit model to obtain a first result; injects each fault in the acquired fault block into the circuit model separately to obtain a corresponding circuit fault model; uses the test vector assigned to itself to input the circuit fault model to obtain a second result; and detects each fault, wherein it is determined whether the fault is detected based on the first result and the second result, and if the fault is detected, the undetected fault set is updated. This scheme can at least achieve the following beneficial technical effects: the present invention uses a new fault block allocation strategy to balance the workload between threads to improve the performance and effectiveness of fault simulation.

[0012] Optionally, the simulation of the second stage includes repeatedly performing the following processing: obtaining the latest undetected fault set, and extracting only one undetected fault from it; injecting the undetected fault into a separate injection circuit model to obtain a circuit fault model corresponding to the undetected fault; using the test vector assigned to itself to input the circuit fault model corresponding to the undetected fault, to obtain a third result; detecting the undetected fault, wherein it is determined whether the fault is detected based on the first result and the third result, and if the fault is detected, the undetected fault set is updated. This scheme can at least achieve the following beneficial technical effects: the second stage still maintains the test vectors originally assigned to each thread, and only changes the granularity of fault acquisition, from acquiring multiple faults in a fault block at a time to acquiring only a single fault, so as to better optimize fault allocation when the remaining undetected faults are relatively small, and to ensure the accuracy of the results as much as possible through the second stage.

[0013] Optionally, the method further includes: maintaining a processed thread list for each undetected fault, in which the thread IDs that have been injected with the fault but have not detected the fault are recorded; when each thread performs the second-stage simulation, the undetected faults of itself are shielded according to each processed thread list, and the uninjected faults are selected for simulation. This solution can at least achieve the following beneficial technical effects: This solution allows the thread to effectively identify the faults it has simulated when entering the second stage, so as to effectively reduce ineffective work.

[0014] Optionally, the method further includes: after all threads have completed the second stage of simulation, marking the detected faults and undetected faults on the fault list. This solution can at least achieve the following beneficial technical effects: marking the detected faults and undetected faults can help users better analyze how to optimize the circuit and improve the performance of the circuit.

[0015] Optionally, when a thread completes its first stage of simulation, the thread directly enters the second stage of simulation without waiting for other threads to complete their first stage of simulation. This solution can at least achieve the following beneficial technical effects: avoid the situation where a thread completes its task first and needs to wait for other threads to complete the first stage of simulation, and improve the utilization rate of computing resources.

[0016] Optionally, the value range of M is [2N, 3N]. This solution can at least achieve the following beneficial technical effects: Experiments show that when the value of M is about 2-3 times the number of threads, the overall simulation performance is better.

[0017] According to a second aspect of the present invention, there is provided an electronic device comprising: one or more processors; and a memory, wherein the memory is used to store executable instructions; the one or more processors are configured to implement the steps of the method described in the first aspect by executing the executable instructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The embodiments of the present invention are further described below with reference to the accompanying drawings, in which:

[0019] Figure 1 Schematic diagram of test vector and fault allocation for the first stage of existing Algorithm 1;

[0020] Figure 2 A schematic diagram of a flow chart of a two-stage fault simulation method based on a multi-core CPU according to an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of test vectors and fault allocation in the first stage of a two-stage fault simulation method based on a multi-core CPU according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0023] As mentioned in the background technology section, there is currently a lack of effective algorithm design, and the load balancing and task scheduling strategies between threads need to be improved. So far, no effective method has been found to effectively combine various optimization strategies and multi-threaded algorithms. The existing technology usually divides all test vectors and faults equally and distributes them all at once, and the time for different threads to complete the divided faults may be different, resulting in some threads having to wait for other threads to complete the remaining calculations before starting the next stage of calculations, resulting in resource waste and affecting the overall simulation efficiency. See the multi-threaded scheduling method shown in the following existing algorithm 1:

[0024]

[0025] The meaning of each line of the algorithm is as follows:

[0026] Input: test set partition Ti, fault list partition Fi, where the test set refers to the test vector set;

[0027] Line 01: For all test vectors t in the test set partition Ti, start processing.

[0028] Line 02: Select w test vectors from the test set Ti to form a subset Tw.

[0029] Line 03: Perform bit-parallel simulation in a fault-free circuit on the subset Tw to obtain the correct reference result after each test vector is input.

[0030] Line 04: Initialize Fdi to an empty set for storing detected faults.

[0031] Line 05: For each test vector tk in the test set Ti, perform the following operations.

[0032] Line 06: Select w faults from the fault list partition Fi to form a fault subset Fw.

[0033] Line 07: Perform bit-parallel simulation of the faulty circuit on the test tk and the fault subset Fw, and compare the result with the reference result to detect the fault, and obtain the detected fault set Fdet.

[0034] Line 08: Update Fi, removing the fault Fw that has been selected for simulation.

[0035] Line 09: Add the detected fault Fdet to Fdi.

[0036] Line 10: If the ratio of the number of detected faults to the number of faults in Fi is less than the set drop rate (DropRate), then exit the loop.

[0037] Line 11: Breaks out of the loop without performing any further tests.

[0038] Line 12: Lock the shared fault list F to ensure data consistency during the update process.

[0039] Line 13: Update the shared fault list F, removing the faults in Fdi, since they have been detected.

[0040] Line 14: Unlock the shared fault list F, releasing the lock.

[0041] Line 15: Return the updated shared fault list F.

[0042] Algorithm 1 is based on the parallel fault model. Each thread has its own test vector and fault sublist, and they are independent of each other. Figure 1 . The distribution of test vectors t1-t12 and faults 1-12 to threads 1-3 is balanced. However, a potential problem occurs near the end of the simulation process when the number of remaining faults is small. When using a parallel fault model, threads need to obtain a certain number of fault instances associated with parallel bit positions for simulation, which causes a large amount of mutual waiting time for other threads while waiting for faults to be released. For example, if the machine is able to process 8 bits of data simultaneously, each thread can simulate 8 faults in parallel. However, when the number of fault instances obtained by a thread is less than 8, it needs to wait for other threads to complete the simulation and release the undetected fault instances. These undetected fault instances are added to the fault set of the current thread so that simulation can continue. This mechanism causes a large amount of mutual waiting time between threads, which affects the overall simulation efficiency.

[0043] It can be seen that the balanced distribution of test vectors and faults in Algorithm 1 will affect the overall performance. Because when a thread completes its simulation task earlier than other threads, it must wait until other threads complete their tasks before all threads enter the second stage. This does not fully utilize the efficiency of multi-threading. Although the DropRate metric is introduced to terminate this stage early to solve this problem, there is still a lot of idle waiting time for most threads.

[0044] In this regard, the present invention optimizes the existing multi-thread fault simulation acceleration technology to improve the performance and effectiveness of fault simulation and meet the growing simulation needs. The embodiment of the present invention sets the number of fault blocks M to be larger than the number of threads N, and does not allocate the fault blocks to each thread at one time, optimizes the mechanism of task allocation and inter-thread collaboration, and has a lower inter-thread communication cost. In the first stage, each thread acquires and tests a single fault block as the granularity, and acquires the next fault block after testing each fault block, so as to avoid each thread balancing and acquiring multiple fault blocks, but due to the processing speed deviation, some threads may complete the processing of their own assigned fault blocks first and have to wait for other threads to complete the relevant calculations; the thread that completes the relevant simulation of the acquired fault block first can continue to acquire the fault blocks (remaining fault blocks) that have not been acquired by the thread for processing until all fault blocks are acquired. Moreover, after each thread completes the first stage of simulation, it can enter the next stage without waiting for other threads to complete the test, and detect undetected faults separately to improve detection efficiency and ensure the accuracy of the results; in addition, in the first stage, due to the large number of faults at this time, they are acquired in units of fault blocks to avoid excessive overhead in the early stage of fault allocation; and in the second stage, they are acquired in units of faults to avoid a single thread locking too many faults to improve simulation efficiency.

[0045] According to one embodiment of the present invention, see Figure 2 , a two-stage fault simulation method based on a multi-core CPU is provided, comprising steps S1, S2, and S3.

[0046] Step S1: Obtain a circuit model to be tested, a test vector set and a fault list, wherein the test vector set includes a plurality of test vectors, and the fault list includes a plurality of faults to be injected.

[0047] According to an embodiment of the present invention, the circuit model refers to a simulation model corresponding to the integrated circuit to be tested, such as TC01, TC02, TC03, TC04, TC05, TC06, TC07, TC08, TC09 or a model corresponding to an integrated circuit designed by the implementer.

[0048] According to one embodiment of the present invention, a test vector set is a set of specific input signal sequences for applying to the input end of a digital circuit. Typically, a series of test vectors are generated based on the design description of the circuit and the fault model information, which can maximize the test coverage and detect all possible faults. Subsequently, by observing the output response of the circuit under the action of these input signal sequences, it is possible to verify whether the circuit meets the design specifications or detect whether there is a fault in the circuit.

[0049] According to one embodiment of the present invention, a fault refers to a fault point artificially introduced in a circuit model to simulate defects that may occur in the actual operation of the circuit. By injecting these faults and observing the behavior of the circuit, the testability of the circuit can be evaluated, the validity of the test vector can be verified, and potential problems can be located. The fault list includes, for example: stuck-at fault, bridge fault, transient fault and / or open / closed fault.

[0050] Step S2: Obtain the number of threads N of the multi-core CPU, evenly distribute multiple test vectors to the N threads, divide multiple faults into M fault blocks, and obtain a fault block set, where M>N.

[0051] According to one embodiment of the present invention, for test vectors, a one-by-one allocation method can be adopted to make the number of test vectors allocated to each thread as equal as possible (the difference is 0 or 1). For example: Assume that there are 99 test vectors in total, which need to be evenly allocated to 4 threads: thread 1 is allocated to 25 vectors, thread 2 is allocated to 25 vectors, thread 3 is allocated to 25 vectors, and thread 4 is allocated to 24 vectors. Of course, if there are many test vectors, the implementer can also allocate more test vectors (2, 3 or 4, etc.) to one thread each time according to the specific situation until all test vectors are allocated, so as to improve the allocation efficiency.

[0052] According to an embodiment of the present invention, for the division of fault blocks, the present invention no longer performs balanced division, but divides more fault blocks than the number of threads, so that when some threads complete the simulation of the acquired fault blocks first, the remaining fault blocks can be acquired for simulation, thereby avoiding invalid waiting and making more efficient use of computing resources. Figure 3 , it can be seen that threads 1-3 still evenly distribute test vectors t1-t12 at one time, but do not distribute all fault blocks f1-f12. Preferably, the value range of M is [2N, 3N]. The technical solution of this embodiment can at least achieve the following beneficial technical effects: Experiments show that when the value of M is about 2-3 times the number of threads, the overall simulation performance is better.

[0053] According to an embodiment of the present invention, when dividing the faulty blocks, all the faulty blocks may be divided into the same size, thereby simplifying the difficulty of division.

[0054] If there are too many fault lists, a single fault block may be larger, and if the fault blocks are divided too small, frequent reading of the fault blocks will result in a large access overhead. Further improvements can be considered. According to one embodiment of the present invention, the method also includes: when dividing the fault blocks, different fault block sizes are set to divide X first fault blocks of the same size and Y second fault blocks that are smaller than the first fault blocks, where X is greater than zero and is an integer multiple of the number of threads, and X+Y=M. For example; the fault list is divided into N fault blocks of the first size and MN fault blocks of the second size, where the first size is larger than the second size. The size is measured by the number of faults. Thus, each thread can be allowed to obtain a larger fault block at the beginning to reduce access overhead, and the size of the remaining fault blocks is relatively smaller, which can reduce the situation where a thread obtains more tasks in the later stage, causing the simulation progress to lag behind other threads too much, thereby improving the overall simulation performance.

[0055] Step S3: N threads perform simulation according to a preset two-stage fault simulation method, which includes each thread performing the following operations respectively: performing the first stage of simulation, which includes: each thread obtains one remaining fault block each time for testing, until the fault block obtained by itself has completed the test and there are no remaining fault blocks, and then entering the second stage of simulation, wherein undetected faults are updated according to the faults detected during the simulation and the fault list; and performing the second stage of simulation, which includes: using the test vectors allocated to itself to test all undetected faults.

[0056] According to one embodiment of the present invention, the simulation of the first stage includes: maintaining the remaining fault block set and the shared undetected fault set shared by each thread, wherein the remaining fault block set is initially a set of M fault blocks, and the undetected fault set is initially a set of all faults in the fault list; each thread is configured to perform the following processing: each thread obtains a remaining fault block from the remaining fault block set each time and removes it from the remaining fault block set; inputs the test vector assigned to itself into the circuit model to obtain a first result; injects each fault in the acquired fault block into the circuit model separately to obtain a corresponding circuit fault model; uses the test vector assigned to itself to input the circuit fault model to obtain a second result; and detects each fault, wherein it is determined whether the fault is detected according to the first result and the second result, and if the fault is detected, the undetected fault set is updated. In VLSI simulation, the test vector is an input signal sequence used to activate and detect circuit faults. By inputting the test vector into the circuit, it can be observed whether the output response is consistent with the expectation, thereby judging whether the circuit has a fault. That is, if the first result obtained when simulating a certain fault is inconsistent with the second result, it indicates that the fault is detected. In addition, when a thread completes its first stage of simulation, the thread directly enters the second stage of simulation without waiting for other threads to complete their first stage of simulation. The solution can at least achieve the following beneficial technical effects: The present invention uses a new fault block allocation strategy to balance the workload between threads to improve the performance and effectiveness of fault simulation.

[0057] According to an example of the present invention, the schematic process of the simulation of the first stage of the method of the present invention is shown in Algorithm 2:

[0058]

[0059] The meaning of each line of the algorithm is as follows:

[0060] Data: test vector Ti assigned to thread i, fault block list Fb, detected fault set Fdi;

[0061] Result: An updated shared fault list F, where F is the set of undetected faults.

[0062] Line 01: Initialize the detected fault set Fdi to an empty set.

[0063] Line 02: For each faulty block fbj in the faulty block list Fb, start processing:

[0064] Line 03: Perform a mutex lock operation on fbj.

[0065] Line 04: If fbj has already been assigned:

[0066] Line 05: Unlock fbj.

[0067] Line 06: Continue to the next fault block.

[0068] Line 07: Otherwise:

[0069] Line 08: Assigns fbj to thread with thread ID i.

[0070] Line 09: Unlock fbj.

[0071] Line 10: For all test vectors in the test vector set Ti, start processing:

[0072] Line 11: Select w test vectors from Ti to form Tw.

[0073] Line 12: Simulate Tw under a fault-free circuit to obtain the correct reference result.

[0074] Line 13: For each fault f in fbj:

[0075] Line 14: Call the function PPSPF model, input Tw to perform fault simulation under the faulty circuit, and compare the result with the reference result to detect the fault, and obtain the detected fault set Fdet.

[0076] Line 15: Merge Fdet into Fdi.

[0077] Line 16: Perform a mutual exclusion lock operation on the remaining fault list F shared by all threads.

[0078] Line 17: Update the remaining fault list F to F minus Fdi.

[0079] Line 18: Unlock the remaining fault list F.

[0080] Line 19: Return.

[0081] According to one embodiment of the present invention, the simulation of the second stage includes repeatedly performing the following processing: obtaining the latest undetected fault set, and extracting only one undetected fault from it; injecting the undetected fault into a separate injection circuit model to obtain a circuit fault model corresponding to the undetected fault; using the test vector assigned to itself to input the circuit fault model corresponding to the undetected fault, and obtaining a third result; detecting the undetected fault, wherein it is determined whether the fault is detected according to the first result and the third result, and if the fault is detected, the undetected fault set is updated. Since only certain test vectors can detect the corresponding fault, and this point is not considered during the division, the present invention uses each thread to use the assigned test vector to detect the fault of the undetected fault set in the second stage to ensure the accuracy of the result. Moreover, the second stage still maintains the test vector originally assigned to each thread, and only changes the granularity of fault acquisition, from acquiring multiple faults in the fault block at one time to acquiring only a single fault, so as to better optimize the fault allocation when the remaining undetected faults are relatively small.

[0082] According to an embodiment of the present invention, the method further includes: maintaining a processed thread list for each undetected fault, in which the thread IDs that have been injected with the fault but have not been detected are recorded; when each thread performs the second stage of simulation, the faults that have not been detected by itself are shielded according to each processed thread list, and the faults that have not been injected are selected for simulation. For example, assuming that there are 4 threads (Thread 0-3), the number of faults is 80 (faults 0-79), and 8 fault blocks are divided, among which the fault block containing fault 0 is assigned to thread 0, and thread 0 does not detect fault 0. A processed thread list [Thread 0] will be maintained for the undetected fault 0, and thread 0 will shield fault 0 in the second stage, that is, fault 0 will not be selected for simulation again. The technical solution of this embodiment can at least achieve the following beneficial technical effects: the solution allows the thread to effectively identify the faults that it has simulated when entering the second stage to reduce invalid work.

[0083] According to one embodiment of the present invention, the method further includes: after all threads have completed the second stage of simulation, the detected faults and undetected faults are marked on the fault list. For example: assuming there are faults 0-79, the undetected faults are marked as faults 0 and faults 78, and the remaining faults are marked as detected faults. Of course, more detailed results can also be given, that is, the first result, the second result, and the third result obtained for each fault during simulation, which is convenient for implementers to compare. The technical solution of this embodiment can at least achieve the following beneficial technical effects: marking the detected faults and undetected faults can facilitate users to better analyze how to optimize the circuit and improve the performance of the circuit.

[0084] According to an example of the present invention, a schematic two-stage fault simulation method is provided, comprising:

[0085] In the first stage, the test vectors are evenly distributed to each thread according to the number of threads, and the faults are divided into blocks at twice the number of threads. Each thread takes a fault block and simulates it with the test vector assigned to it. After the simulation of the assigned fault block is completed, each thread dynamically obtains the remaining fault blocks that have not been obtained to implement the load balancing task allocation strategy for fault simulation.

[0086] In the second stage, each thread uses the test vectors assigned to it in the first stage to test all remaining undetected faults to ensure the correctness of the results.

[0087] In addition, the method of the present invention can be obtained by improving Algorithm 1 and adjusting as follows:

[0088] (1) For test vectors, the original test vector allocation strategy is retained, that is, uniform distribution based on the number of threads;

[0089] (2) For faults, divide them into independent sub-blocks, the number of which is twice the number of threads (2 * number of threads). This value is an empirical value determined through our experiments;

[0090] (3) In the independent phase, when all faulty sub-blocks are assigned, each thread enters the dynamic cooperation phase immediately after completing its own simulation task without waiting for the entire independent phase to end;

[0091] (4) By checking the thread ID assigned to each faulty sub-block during independent phase allocation, each thread in the dynamic cooperation phase can determine whether it has previously processed the faulty sub-block in the first phase to avoid redundant work;

[0092] (5) Replace the parallel fault simulation model of Algorithm 1 with the PPSFP model. In the PPSFP model, only one fault is simulated at a time, which significantly reduces the communication cost between threads and increases the parallelism between threads;

[0093] (6) Delete the drop rate indicator introduced in Algorithm 1 because it is no longer applicable. Because the optimized algorithm uses fault blocks, the simulation of the first stage ends when all fault blocks are simulated. The single simulation fault detection rate before optimization is no longer used as the standard. The drop rate (DropRate) is the original single simulation fault detection rate indicator, so it is no longer needed.

[0094] This example optimizes the existing multi-threaded fault simulation method to improve the performance and effectiveness of fault simulation and meet the growing simulation needs. Based on the existing multi-threaded fault simulation scheduling algorithm, the task allocation and thread scheduling strategy are optimized, and the original parallel fault simulation model is replaced by the parallel pattern single fault propagation (PPSFP) model, which has a lower inter-thread communication cost. Compared with previous solutions, multi-dimensional acceleration results are achieved. A new fault block allocation strategy is proposed to balance the workload between threads.

[0095] In order to verify the effect of the method of the present invention, the inventors also conducted the following experiments:

[0096] Experimental conditions: Nine test circuits provided by EDA² were tested on the Kunpeng920 processor, and the acceleration effect of the fault simulation synthesis model in small and large circuits was comprehensively evaluated.

[0097] The experimental results are shown in Table 1:

[0098] Table 1 Performance of multithreaded algorithms under different numbers of threads

[0099] In Table 1, the multithreaded algorithm is compared with the single-threaded algorithm with excellent performance. The choice of the number of threads will affect the effectiveness of the multithreaded algorithm. Too few threads may not fully utilize the advantages of the multi-core system, while too many threads may reduce efficiency due to the high cost of inter-thread communication. Given that the test server has 32 cores, the experiment started with 32 threads and gradually increased by 16 threads, eventually reaching 80 threads. Then, the speedup ratio of each thread count was calculated to compare the results. The experimental results show that as the number of threads increases from 32 to 64, the performance of the algorithm gradually improves. However, when the number of threads reaches 80, the efficiency begins to decline. Therefore, it can be concluded that in the experiment, the optimal number of threads to maximize the effectiveness of the multithreaded algorithm model is 64, and the average speedup ratio of all circuits is 2.986. The results show that the performance of this study is similar to that of the traditional multithreaded simulation optimization strategy in small circuits, but it shows obvious advantages in large circuits, indicating that even when the performance of the single-threaded simulation algorithm is good enough, the invention can still achieve a speedup ratio of about 3 times in most circuits. This finding provides important empirical support for the advancement of fault simulation technology and also highlights the potential of the present invention in large-scale circuit simulation.

[0100] It should be noted that although the above describes the various steps in a specific order, it does not mean that the various steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently or even in a different order as long as the required functions can be achieved.

[0101] The present invention may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0102] A computer-readable storage medium may be a tangible device that holds and stores instructions used by an instruction execution device. Computer-readable storage media may include, for example, but are not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a protruding structure in a groove on which instructions are stored, and any suitable combination thereof.

[0103] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A two-stage fault simulation method based on a multi-core CPU, comprising: Obtaining a circuit model to be tested, a test vector set and a fault list, wherein the test vector set includes a plurality of test vectors, and the fault list includes a plurality of faults to be injected; Obtain the number of threads N of the multi-core CPU, evenly distribute multiple test vectors to the N threads, divide multiple faults into M fault blocks, and obtain a fault block set, where M>N; The N threads perform simulation according to a preset two-stage fault simulation method, which includes each thread performing the following operations respectively: Executing the first phase of simulation, which includes: each thread acquires one remaining fault block each time for testing, until the fault block acquired by itself has completed testing and there are no remaining fault blocks, and then switching to the second phase of simulation, wherein undetected faults are updated according to the faults detected during the simulation and the fault list; and The second stage of simulation is performed, which includes: testing all undetected faults using the test vectors assigned to them.

2. The method according to claim 1, characterized in that The first phase of simulation includes: Maintain the remaining fault block set and the shared undetected fault set shared by each thread, where the remaining fault block set is initially a set of M fault blocks, and the undetected fault set is initially a set of all faults in the fault list; each thread is configured to perform the following processing: Each thread obtains one remaining fault block from the remaining fault block set at a time and removes it from the remaining fault block set; Input the test vector assigned to the circuit model to obtain a first result; Inject each fault in the acquired fault block into the circuit model separately to obtain a corresponding circuit fault model; Using the test vector assigned to itself as input into the circuit fault model, a second result is obtained; A detection is performed for each fault, wherein it is determined whether the fault is detected according to the first result and the second result; if the fault is detected, the undetected fault set is updated.

3. The method according to claim 1 or 2, characterized in that: The second stage of simulation consists of repeatedly executing the following processes: Get the latest set of undetected faults and extract only one undetected fault from them; Injecting the undetected fault into a separate injection circuit model to obtain a circuit fault model corresponding to the undetected fault; Using the test vector assigned to itself to input the circuit fault model corresponding to the undetected fault, to obtain a third result; A detection is performed on the undetected fault, wherein it is determined whether the fault is detected according to the first result and the third result, and if the fault is detected, the undetected fault set is updated.

4. The method according to claim 1, characterized in that: The method further comprises: Maintain a processed thread list for each undetected fault, which records the thread IDs that have been injected with the fault but not detected; When each thread performs the second stage of simulation, it masks the faults that it has never detected according to the list of each processed thread, and selects the faults that have not been injected for simulation.

5. The method according to claim 1, characterized in that The method further comprises: When all threads have completed the second stage of simulation, the detected faults and undetected faults are marked on the fault list.

6. The method according to claim 1, characterized in that When a thread completes its first phase of simulation, the thread directly enters the second phase of simulation without waiting for other threads to complete their first phase of simulation.

7. The method according to claim 1, characterized in that The value range of M is [2N, 3N].

8. A computer program product, comprising a computer program / instruction, which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and the computer program can be executed by a processor to implement the steps of the method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: include: one or more processors; as well as A memory, wherein the memory is used to store executable instructions; The one or more processors are configured to implement the steps of the method of any one of claims 1-7 by executing the executable instructions.

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