Extra-high voltage MOSFET-oriented packaging optimization method and system

Abstract

The invention provides a packaging optimization method and system for an extra-high voltage MOSFET, and relates to the technical field of semiconductor manufacturing, and the method comprises the steps: determining a preset packaging layout of an extra-high voltage MOSFET element; analyzing parasitic capacitance and the influence of the parasitic capacitance on the switching speed, and parasitic inductance and the influence of the parasitic inductance on voltage overshoot, and establishing a parasitic capacitance optimization network and a parasitic inductance optimization network in combination with energy loss correlation analysis; a plurality of equivalent RC circuits are prepared and are equivalently combined, and a performance optimization model is established according to the optimization network; and based on the performance optimization model, performing compromise backtracking iteration in combination with the packaging demand information, and meanwhile, adjusting a preset packaging layout to obtain an optimal packaging layout. The technical problem that the overall packaging performance is difficult to improve due to the lack of systematic optimization of parasitic effects in the packaging process in the prior art is solved, and the technical effect of remarkably improving the performance and the reliability of the extra-high voltage MOSFET is achieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a packaging optimization method and system for ultra-high voltage MOSFETs. Background Art

[0002] UHV MOSFET is a key power electronic component, widely used in high-voltage power transmission, inverters, electric vehicle drive systems and other fields. Existing UHV MOSFET packaging optimization methods mainly focus on improving the packaging process, reducing the impact of parasitic effects by improving the packaging materials, layout and structure, and improving the performance of power modules. However, in the existing UHV MOSFET packaging technology, the optimization of parasitic parameters is mainly focused on the adjustment of single or partial parasitic parameters, lacking consideration of the systematic relationship between parasitic parameters and other important factors. For example, when optimizing parasitic capacitance and parasitic inductance, independent methods are often used, such as improving parasitic capacitance through specific ceramic substrate design and optimizing parasitic inductance by changing the layout structure. These optimization methods only focus on the optimization of parasitic parameters in local areas, without considering the impact of optimization measures on surrounding circuits, which may lead to the parasitic effects in the entire circuit not being effectively controlled, limiting the improvement of the overall performance of UHV MOSFET. Summary of the invention

[0003] The present application provides a packaging optimization method and system for UHV MOSFET, which solves the technical problem that the prior art lacks systematic optimization of parasitic effects in the UHV MOSFET packaging process, making it difficult to improve the overall packaging performance, and achieves the technical effect of significantly improving the performance and reliability of UHV MOSFET.

[0004] In view of the above problems, on the one hand, the present application provides a packaging optimization method for ultra-high voltage MOSFET, the method comprising: determining a preset packaging layout according to an ultra-high voltage MOSFET component, the ultra-high voltage MOSFET component comprising a high-side MOSFET source pin, a motor winding, and a low-side MOSFET drain pin; analyzing parasitic capacitance and the influence of parasitic capacitance on switching speed according to the preset packaging layout, obtaining a first impact assessment combination, and performing an energy loss correlation analysis according to the first impact assessment combination, and establishing a parasitic capacitance optimization network using the first energy loss correlation analysis result; analyzing parasitic inductance and the influence of parasitic inductance on voltage overshoot according to the preset packaging layout, obtaining a second impact assessment combination, and performing an energy loss correlation analysis according to the second impact assessment combination. A parasitic inductance optimization network is established by using the result of the second energy loss correlation analysis; a plurality of equivalent RC circuits are proposed through the high-side MOSFET source pin, the motor winding, and the low-side MOSFET drain pin in the UHV MOSFET element, and the plurality of equivalent RC circuits include a series equivalent RC circuit and a parallel equivalent RC circuit; the series equivalent RC circuit and the parallel equivalent RC circuit in the plurality of equivalent RC circuits are equivalently combined, and a performance optimization model is established according to the parasitic capacitance optimization network and the parasitic inductance optimization network; based on the performance optimization model, a compromise backtracking iteration is performed in combination with the packaging requirement information of the UHV MOSFET element, and at the same time, the preset packaging layout is adjusted to obtain the optimal packaging layout.

[0005] On the other hand, the present application also provides a packaging optimization system for ultra-high voltage MOSFET, the system comprising: a preset packaging layout module, used to determine a preset packaging layout according to an ultra-high voltage MOSFET element, wherein the ultra-high voltage MOSFET element comprises a high-side MOSFET source pin, a motor winding, and a low-side MOSFET drain pin; a parasitic capacitance analysis module, used to analyze parasitic capacitance and the influence of parasitic capacitance on switching speed according to the preset packaging layout, obtain a first impact assessment combination, and perform energy loss correlation analysis according to the first impact assessment combination, and establish a parasitic capacitance optimization network using the first energy loss correlation analysis result; a parasitic inductance analysis module, used to analyze parasitic inductance and the influence of parasitic inductance on voltage overshoot according to the preset packaging layout, obtain a second impact assessment combination, and perform energy loss correlation analysis according to the second impact assessment combination. Correlation analysis, using the second energy loss correlation analysis result to establish a parasitic inductance optimization network; an equivalent RC circuit module, used to formulate multiple equivalent RC circuits through the high-side MOSFET source pin, motor winding, and low-side MOSFET drain pin in the ultra-high voltage MOSFET element, and the multiple equivalent RC circuits include series equivalent RC circuits and parallel equivalent RC circuits; a circuit equivalent combination module, used to perform equivalent combination of the series equivalent RC circuits and parallel equivalent RC circuits in the multiple equivalent RC circuits, and establish a performance optimization model based on the parasitic capacitance optimization network and the parasitic inductance optimization network; a package layout optimization module, used to perform compromise backtracking iteration based on the performance optimization model and the package requirement information of the ultra-high voltage MOSFET element, and at the same time, adjust the preset package layout to obtain the optimal package layout.

[0006] One or more technical solutions provided in this application have at least the following technical effects or advantages: According to the UHV MOSFET components, the preset package layout is determined, and the initial position relationship and electrical connection method of each part of the UHV MOSFET components are clarified, providing a reference framework for the package layout for subsequent parasitic effect analysis and optimization. By analyzing the influence of parasitic capacitance and parasitic capacitance on switching speed, and constructing a parasitic capacitance optimization network, the optimization direction and basis for parasitic capacitance are provided for the subsequent comprehensive optimization performance. By analyzing the influence of parasitic inductance and parasitic inductance on voltage overshoot, and constructing a parasitic inductance optimization network, the optimization direction and basis for parasitic inductance are provided for the subsequent comprehensive optimization performance. Using the key components of the UHV MOSFET components, multiple equivalent RC circuits are proposed, and the actual circuit structure is converted into an equivalent circuit model that is easy to analyze, providing a basic circuit model unit for the subsequent establishment of a performance optimization model, so that complex actual circuits can be uniformly analyzed through these equivalent circuits. Equivalent combinations of equivalent RC circuits are performed and combined with the established parasitic capacitance and parasitic inductance optimization network to construct a mathematical model that can fully describe the packaging performance optimization relationship. Based on the performance optimization model and the packaging requirements, we conduct compromise and backtracking iterations, comprehensively consider the mutual constraints of various factors, and continuously adjust the preset packaging layout so that the entire packaging layout can achieve comprehensive performance optimization in electrical, thermal, mechanical and other aspects while meeting the packaging requirements.

[0007] To summarize, this application determines a preset package layout, gradually and deeply analyzes the impact of parasitic capacitance and parasitic inductance on the performance of UHV MOSFET components, constructs a corresponding optimization network, proposes an equivalent RC circuit and establishes a performance optimization model, and finally obtains the optimal package layout through a series of steps such as compromise backtracking iteration. This achieves comprehensive performance optimization of UHV MOSFET packaging from electrical, thermal and mechanical aspects, which can not only effectively reduce the adverse effects of parasitic capacitance on switching speed and parasitic inductance on voltage overshoot, thereby reducing energy loss, but also can comprehensively improve the overall performance of UHV MOSFET components by optimizing the package layout while meeting the packaging requirements, so that UHV MOSFET can operate more efficiently and stably in complex working environments.

[0008] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A schematic flow chart of a packaging optimization method for ultra-high voltage MOSFET provided in an embodiment of the present application.

[0010] Figure 2A schematic diagram of a process for obtaining an optimal packaging layout in a packaging optimization method for ultra-high voltage MOSFET provided in an embodiment of the present application.

[0011] Figure 3 A schematic diagram of a process for determining thermal resistance constraints in a packaging optimization method for ultra-high voltage MOSFETs provided in an embodiment of the present application.

[0012] Figure 4 A schematic diagram of the structure of a packaging optimization system for ultra-high voltage MOSFET provided in an embodiment of the present application.

[0013] Explanation of the reference numerals: preset package layout module 10 , parasitic capacitance analysis module 20 , parasitic inductance analysis module 30 , equivalent RC circuit module 40 , circuit equivalent combination module 50 , package layout optimization module 60 . DETAILED DESCRIPTION

[0014] The embodiments of the present application provide a packaging optimization method and system for UHV MOSFET, thereby solving the technical problem that the prior art lacks systematic optimization of parasitic effects in the UHV MOSFET packaging process, resulting in difficulty in improving the overall packaging performance, and achieves the technical effect of significantly improving the performance and reliability of UHV MOSFET.

[0015] Embodiment 1, as Figure 1 As shown, the embodiment of the present application provides a packaging optimization method for ultra-high voltage MOSFET, the method comprising: Step S1: determining a preset package layout according to an ultra-high voltage MOSFET component, wherein the ultra-high voltage MOSFET component includes a high-side MOSFET source pin, a motor winding, and a low-side MOSFET drain pin.

[0016] Specifically, UHV MOSFET is a semiconductor device used to handle high voltages, and its main components include high-side MOSFET source pins, motor windings, and low-side MOSFET drain pins. The high-side MOSFET source pin, that is, the pin on the MOSFET device that is connected to the source and is on the higher potential side in the circuit, is the input end of the current in the MOSFET, controls the inflow of current, and acts as a current switch. The low-side MOSFET drain pin, that is, the pin on the MOSFET device that is connected to the drain and is on the lower potential side in the circuit. It is the output end of the current in the MOSFET, controls the outflow of current, and affects the on-off of the current. The motor winding is the electromagnetic coil part of the motor, which is associated with the MOSFET component and controls the operation of the motor by controlling the current flow. The preset package layout is a preliminary package structure arrangement that is pre-set according to the characteristics and requirements of the UHV MOSFET component before package optimization, including the relative position of each pin, component, etc., connection method and other layout methods.

[0017] According to the characteristics of the UHV MOSFET components themselves, such as the functions and electrical connection requirements of the high-side MOSFET source pins, motor windings, and low-side MOSFET drain pins, refer to the UHV MOSFET electrical parameter manual and the historical packaging experience of similar products to determine an initial preset package layout. For example, if the UHV MOSFET is applied to a motor drive circuit, according to the power requirements of the motor, the operating voltage range, etc., the high-side MOSFET source pin is arranged close to the power input side, the low-side MOSFET drain pin is arranged close to the motor winding side, and the motor winding is arranged in a way that optimizes electromagnetic coupling. The preset package layout provides a basic framework for subsequent performance analysis and optimization, determines the relative position relationship of each component, and preliminarily plans the electrical connection path.

[0018] Step S2: According to the preset package layout, analyze the parasitic capacitance and the influence of the parasitic capacitance on the switching speed, obtain a first influence evaluation combination, perform energy loss correlation analysis according to the first influence evaluation combination, and establish a parasitic capacitance optimization network using the first energy loss correlation analysis result.

[0019] Specifically, parasitic capacitance refers to the unexpected capacitance generated in electronic components or circuits due to the physical proximity or electric field between wires, pins, chips, etc. Parasitic capacitance usually affects high-frequency signals and switching processes, which may cause signal delays, energy loss and interference. Switching speed refers to the speed at which the MOSFET switches from on to off or from off to on. Switching speed is one of the important performance indicators of MOSFET, which directly affects the response speed and working efficiency of the circuit. The parasitic capacitance optimization network is an optimization network model established by combining the first impact assessment and energy loss correlation analysis results. It is used to optimize switching speed and energy loss by adjusting capacitance value, layout and component configuration.

[0020] Based on the preset package layout, the parasitic capacitance is analyzed. The size of the parasitic capacitance is calculated through electromagnetic simulation software (such as Ansys Maxwell) or based on circuit theory formulas. Then the effect of parasitic capacitance on switching speed is studied. For example, when the parasitic capacitance is large, the switching speed will be slowed down. Based on the results of this impact assessment, a first impact assessment combination is formed. Then, an energy loss correlation analysis is performed using circuit analysis methods (such as Kirchhoff's law), which links parasitic capacitance with energy loss and generates the first energy loss correlation analysis results. Finally, based on these analysis results, an optimization network for parasitic capacitance is established. This network can be a structure based on mathematical relationships to describe how to optimize parasitic capacitance to reduce the impact on switching speed.

[0021] By analyzing parasitic capacitance and its influence on switching speed, an optimized network is established, which provides a theoretical basis for reducing the adverse effects of parasitic capacitance on switching speed and reducing energy loss.

[0022] Step S3: According to the preset packaging layout, analyze the parasitic inductance and the influence of the parasitic inductance on the voltage overshoot, obtain the second influence evaluation combination, and perform energy loss correlation analysis according to the second influence evaluation combination, and use the second energy loss correlation analysis result to establish a parasitic inductance optimization network.

[0023] Specifically, parasitic inductance refers to the unexpected inductance generated in the circuit due to the physical structure of the wires, pins, lines or components and the changes in current in the circuit. Parasitic inductance affects the high-frequency response of the circuit and may cause voltage fluctuations or overshoot. Among them, voltage overshoot refers to the phenomenon that the voltage exceeds the target value during the switching process. The second impact assessment combination refers to the combination of all key influencing factors obtained by analyzing the impact of parasitic inductance on voltage overshoot, including the amplitude and duration of the voltage overshoot caused by parasitic inductance and its impact on the overall circuit performance. The parasitic inductance optimization network is an optimization model established through the second impact assessment combination and the energy loss correlation analysis results. It is used to reduce the impact of parasitic inductance by adjusting factors such as package layout and pin configuration, and optimize voltage overshoot and energy loss during switching.

[0024] Similar to step S2, based on the preset package layout, the magnitude of the parasitic inductance is determined by magnetic field simulation software (such as Ansys HFSS) or inductance calculation formula, and the influence of the parasitic inductance on the voltage overshoot is studied. For example, when the parasitic inductance is large, a large voltage overshoot will be caused at the switching moment. The second impact assessment combination is obtained by analyzing the parasitic inductance, and then the energy loss correlation analysis is performed, and the parasitic inductance optimization network is established using the analysis results.

[0025] By analyzing the parasitic inductance and its effect on voltage overshoot, an optimized network is established, which helps to reduce the effect of parasitic inductance on voltage overshoot, thereby reducing energy loss.

[0026] Step S4: multiple equivalent RC circuits are prepared through the high-side MOSFET source pin, motor winding, and low-side MOSFET drain pin in the ultra-high voltage MOSFET element, and the multiple equivalent RC circuits include series equivalent RC circuits and parallel equivalent RC circuits.

[0027] Specifically, an equivalent RC circuit is a circuit model composed of a resistor (R) and a capacitor (C), which is used to represent some electrical characteristics in an actual circuit, including a series equivalent RC circuit and a parallel equivalent RC circuit. Among them, the series equivalent RC circuit is an equivalent circuit in which a resistor and a capacitor are connected in series, while the parallel equivalent RC circuit is an equivalent circuit in which a resistor and a capacitor are connected in parallel.

[0028] Using the high-side MOSFET source pin, motor winding, low-side MOSFET drain pin and other components in the UHV MOSFET element, multiple equivalent RC circuits are proposed according to the circuit principle. For example, the resistance of the motor winding and the parasitic capacitance associated with it form an equivalent RC circuit in series, or the parasitic capacitance near the high-side MOSFET source pin and the equivalent resistance form an equivalent RC circuit in parallel. By constructing an equivalent RC circuit, the analysis of complex circuits is simplified, and the electrical characteristics of UHV MOSFET elements can be studied more conveniently.

[0029] Step S5: performing equivalent combination of the series equivalent RC circuits and the parallel equivalent RC circuits in the multiple equivalent RC circuits, and establishing a performance optimization model according to the parasitic capacitance optimization network and the parasitic inductance optimization network.

[0030] Specifically, the performance optimization model is a mathematical model for optimizing the UHV MOSFET packaging performance based on the analysis results of factors such as parasitic capacitance and parasitic inductance, and comprehensive consideration of various influencing relationships.

[0031] The series equivalent RC circuits and parallel equivalent RC circuits in multiple equivalent RC circuits are equivalently combined according to the circuit connection relationship. Then the relevant parameter relationships in the previously established parasitic capacitance optimization network and parasitic inductance optimization network are integrated into the circuit after the equivalent combination to establish a performance optimization model. This model can be a mathematical expression containing multiple variables and constraints, which is used to describe the relationship between circuit performance and each optimization network.

[0032] By establishing a performance optimization model, the optimization relationship between parasitic capacitance and parasitic inductance can be comprehensively considered, providing a unified mathematical framework for comprehensively optimizing the UHV MOSFET packaging performance.

[0033] Step S6: Based on the performance optimization model, a compromise backtracking iteration is performed in combination with the packaging requirement information of the UHV MOSFET component, and at the same time, the preset packaging layout is adjusted to obtain an optimal packaging layout.

[0034] Specifically, during the optimization process, since there may be contradictions between different performance indicators, for example, reducing parasitic capacitance may increase parasitic inductance, it is necessary to use the performance optimization model as a basis, combined with the packaging requirements information of the UHV MOSFET components, such as packaging size restrictions, heat dissipation requirements, electrical insulation requirements, etc., to perform compromise backtracking iterations. By adjusting various parameters in the preset packaging layout, such as component spacing, wiring direction, etc., and then recalculating the relevant parameters in the performance optimization model, comparing the results before and after the adjustment, and repeating this process continuously until the optimal packaging layout that meets the packaging requirements is obtained. For example, if the packaging requirement is to achieve the lowest energy loss in a limited space while meeting certain voltage overshoot limits. During the iteration process, it may be found that reducing the parasitic capacitance of a certain area will cause the parasitic inductance of another area to increase, exceeding the voltage overshoot limit. At this time, it is necessary to go back to the previous steps of adjusting the layout, readjust the layout of the components, and calculate the performance optimization model again until an optimal packaging layout is found that can meet the voltage overshoot requirements and achieve lower energy loss in a limited space.

[0035] Through compromise and backtracking iteration, the mutual constraints between various packaging requirements and performance indicators can be comprehensively considered to obtain the optimal packaging layout, thereby achieving comprehensive performance optimization of UHV MOSFET packaging in electrical, thermal, mechanical and other aspects.

[0036] Further, such as Figure 2 As shown, step S6 includes: Step S61: Introduce peripheral electronic components and formulate a peripheral circuit set.

[0037] Step S62: Perform layout compaction guidance based on the peripheral circuit set and the power distribution network, and set a layout guidance vector.

[0038] Step S63: using the layout guiding vectors to optimize the relative positions and connection paths between components to obtain the optimal package layout.

[0039] Specifically, peripheral electronic components refer to other electronic components that are directly connected to or work with UHV MOSFETs but are not part of the MOSFET itself, such as resistors, capacitors, inductors, diodes, sensors, drivers, etc. The peripheral circuit set refers to a circuit set that combines all peripheral electronic components connected to UHV MOSFETs according to design requirements and functional relationships. These circuits work together with MOSFETs to form a system circuit framework. The power distribution network refers to the power supply system in the circuit, which is responsible for distributing power from batteries, power adapters or other power sources to various components. The layout guidance vector is a vector representation used to guide the direction and degree of optimization of circuit component layout, which contains multiple parameters, such as the direction of component movement, spacing adjustment direction, etc.

[0040] On the basis of the UHV MOSFET components, the entire circuit system is analyzed to determine all peripheral electronic components that work with the UHV MOSFET. Such as power filters, drivers, voltage regulators, temperature sensors, etc. Then, based on the electrical connection relationship between these components, a peripheral circuit set containing all peripheral electronic components and their connection relationships is formulated. For example, in a circuit where a UHV MOSFET is used for motor drive, in addition to the MOSFET itself, there are also peripheral electronic components such as capacitors for filtering, resistors for current limiting, and diodes for protection. According to the connection relationship between these components in the circuit, a peripheral circuit set is formulated. For example, the capacitor is connected to the source and ground of the MOSFET, the resistor is connected in series in the gate circuit of the MOSFET, and the diode is connected in parallel with the drain of the MOSFET. These peripheral circuit sets provide more comprehensive circuit structure information for subsequent layout optimization, so that the layout optimization is no longer limited to the UHV MOSFET components themselves, but considers the coordinated optimization of the entire circuit system.

[0041] Based on the proposed peripheral circuit set and power distribution network, the electrical relationship between the peripheral electronic components and the UHV MOSFET components is analyzed, and the layout compactness is used as the optimization direction to set the layout guidance vector. That is, in the subsequent packaging optimization process, the corresponding layout rules are set to arrange the various components in the circuit as compactly as possible, thereby reducing the circuit footprint and reducing the influence of factors such as parasitic capacitance and inductance in the current path. These layout rules are identified in the form of vectors to obtain the layout guidance vector.

[0042] According to the layout guidance vector, the relative position and connection path between the UHV MOSFET components and the peripheral electronic components are adjusted. For example, if the layout guidance vector indicates that a certain component needs to be moved to the left, the position of the component is adjusted according to this instruction, and the connection path is optimized at the same time, and unnecessary wiring length and bends are reduced, and finally the optimal package layout is obtained. The optimal package layout is a layout scheme that optimizes the relative position and connection path between components under the premise of meeting the circuit performance requirements. The layout adjustment process can use an automatic layout and routing tool to optimize the layout and routing under the constraints of the layout guidance vector. Exemplarily, in a preset package layout, the connection path between a resistor and the UHV MOSFET component is long and passes through multiple bends. According to the instructions of the layout guidance vector, the resistor is moved to a position closer to the MOSFET, and the connection path is replanned to make it a straight line connection, which reduces parasitic inductance and resistance and improves circuit performance.

[0043] By optimizing the relative positions and connection paths between components, the optimal packaging layout is obtained, which improves the electrical performance of the circuit (such as reducing parasitic parameters) and space utilization.

[0044] Further, step S62 includes: Step S621: collecting circuit interconnection parameters through the circuit interconnection mode between the UHV MOSFET component and the peripheral electronic component.

[0045] Step S622: Based on the peripheral circuit set, signal mutual recognition parameters are collected through the signal mutual recognition method between the UHV MOSFET component and the peripheral electronic component.

[0046] Step S623: Taking the power distribution network as a direction, combining the circuit interconnection parameters and the signal mutual recognition parameters to guide layout compactness, and configuring the layout guidance vector.

[0047] Specifically, the circuit interconnection method refers to the form of electrical connection between UHV MOSFET components and peripheral electronic components, including series connection, parallel connection, direct connection, connection through a specific circuit structure (such as a bridge circuit), etc. The circuit interconnection method determines the transmission path and direction of current, voltage, and signal, affecting the working performance and stability of the circuit. The circuit interconnection parameters are parameters that describe the circuit interconnection characteristics between UHV MOSFET components and peripheral electronic components, including the length, width, thickness of the interconnection line, the resistivity of the interconnection line material, the spacing between the interconnection lines, etc. These parameters will affect the circuit's parasitic resistance, parasitic inductance, capacitance and other electrical properties.

[0048] Signal mutual recognition mode refers to the way of identifying and processing signals when exchanging signals between UHV MOSFET components and peripheral electronic components. For example, in digital circuits, it includes level matching, signal encoding and decoding, etc.; in analog circuits, it includes signal amplification, filtering, modulation and demodulation, etc. Signal mutual recognition parameters are used to describe the characteristic parameters of signal transmission, including signal frequency, amplitude, phase, rise time, fall time, signal noise tolerance, etc. These parameters reflect the characteristics of the signal when it is transmitted between components.

[0049] According to the circuit schematics in the peripheral circuit set, the circuit interconnection method between the UHV MOSFET component and each peripheral electronic component is identified, and the relevant circuit interconnection parameters are measured or calculated for different connection situations. For example, if the connection is through a wire on a printed circuit board (PCB), it is necessary to measure the length and width of the wire, query the resistivity of the wire material, etc., so as to obtain circuit interconnection parameters such as interconnection line resistance. Collecting circuit interconnection parameters can accurately quantify the electrical characteristics of the circuit connection between the UHV MOSFET component and the peripheral electronic components, provide key information about the physical connection of the circuit for subsequent layout compaction guidance, and help optimize the layout to reduce unnecessary electrical losses.

[0050] Based on the proposed peripheral circuit set, determine the signal mutual recognition method between the UHV MOSFET components and the peripheral electronic components. In digital circuits, it is necessary to check the level conversion relationship between logic gate circuits; in analog circuits, it is necessary to analyze the amplification, filtering and other processing processes when the signal passes through different components. Then, the frequency and amplitude of the signal are measured by instruments such as oscilloscopes, and the logic state conversion of the signal is analyzed by logic analyzers, so as to collect signal mutual recognition parameters. For example, in an amplifier circuit containing UHV MOSFET, the peripheral electronic component is an amplifier. The signal is output from the drain of the MOSFET and amplified by the amplifier. The amplitude of the signal measured by an oscilloscope at the drain of the MOSFET is 1V, and the output amplitude after amplification by the amplifier is 5V. This 1V and 5V are part of the signal mutual recognition parameters, and other related parameters such as the frequency of the signal are measured at 1kHz. Collecting signal mutual recognition parameters helps to fully understand the characteristics of signal transmission between UHV MOSFET components and peripheral electronic components, ensure that the accuracy and stability of signal transmission can be taken into account during the layout optimization process, and avoid errors or performance degradation in signal transmission due to layout adjustments.

[0051] The power distribution network is regarded as the main direction of layout compaction guidance, and the collected circuit interconnection parameters (such as the resistance and inductance of the interconnection line) and signal mutual recognition parameters (such as the frequency and amplitude of the signal) are comprehensively considered. For example, if the resistance of the interconnection line in the circuit interconnection parameter is large, and the signal amplitude in the signal mutual recognition parameter is more sensitive to the resistance, it is necessary to minimize the length of the interconnection line when guiding the layout compaction. According to these comprehensive factors, the layout guidance vector is configured through the circuit layout optimization algorithm software. This vector contains information such as the direction and degree of component layout adjustment. The circuit layout optimization algorithm software can calculate the layout guidance vector based on the input circuit interconnection parameters and signal mutual recognition parameters. Exemplarily, the power distribution network is concentrated on one side of the circuit board, and the circuit interconnection parameters between a peripheral electronic component and an ultra-high voltage MOSFET component show that the interconnection line is longer, resulting in a larger parasitic inductance, and the signal mutual recognition parameters show that the signal has a large attenuation when transmitting on this interconnection line. According to these situations, the layout guidance vector is configured to indicate that the peripheral electronic component is moved a certain distance in the direction close to the power distribution network and the ultra-high voltage MOSFET component to reduce parasitic inductance and signal attenuation.

[0052] By taking the power distribution network as the direction, combining circuit interconnection parameters and signal mutual recognition parameters to guide layout compactness and configure layout guidance vectors, it is possible to comprehensively consider multiple factors such as the circuit's electrical performance and signal transmission, provide comprehensive and accurate guidance for component layout optimization, and help improve the overall performance of the circuit and the rationality of the layout.

[0053] Further, such as Figure 3 As shown, step S6 also includes: Step S64: Obtain the heat loss characteristics of the UHV MOSFET element.

[0054] Step S65: Based on the preset packaging layout, an integrated heat pipe heat dissipation structure is determined, wherein the integrated heat pipe heat dissipation structure has a combination of heat pipes of various specifications and heat sinks of various specifications.

[0055] Step S66: Determine a thermal resistance constraint condition according to the heat loss characteristics and in combination with the integrated heat pipe heat dissipation structure, wherein the thermal resistance constraint condition is used to determine whether the heat dissipation requirement standard in the packaging requirement information is met.

[0056] Specifically, the heat loss characteristics refer to the characteristics of heat generated by ultra-high voltage MOSFET components during operation due to factors such as current flow and internal electron movement, including the rate of heat generation and the distribution of heat inside the component. The heat loss characteristics are closely related to the operating current, voltage, operating frequency, internal structure and other factors of the component. The integrated heat pipe heat dissipation structure is a structure for heat dissipation that is composed of a combination of heat pipes of various specifications and heat sinks of various specifications. Among them, the heat pipe is an efficient heat conduction element that transfers heat by using the phase change of the internal working medium; the heat sink accelerates the heat dissipation by increasing the heat dissipation area. Thermal resistance is an important parameter in the heat transfer process. The smaller the thermal resistance, the easier it is to transfer heat. The thermal resistance constraint refers to the thermal resistance limit that the heat dissipation structure needs to meet in order to ensure that the MOSFET is at a safe operating temperature. It is used to determine whether the current heat dissipation structure can meet the heat dissipation requirement standard in the packaging requirement information, that is, whether the heat can be effectively dissipated from the MOSFET component through the heat dissipation structure to avoid excessive component temperature.

[0057] The heat loss characteristics of UHV MOSFET components are obtained by analyzing various factors such as the electrical characteristics, physical structure, and working conditions of the components. For example, thermal simulation software (such as ANSYS Icepak or Flotherm) can be used to simulate the thermal behavior of MOSFET under different working conditions, and a thermal imager or temperature sensor can be used to measure the actual junction temperature and surface temperature, or the power loss formula of the component (such as P=I 2 R, where P is power loss, I is operating current, and R is equivalent resistance) calculates the power loss under different working conditions and converts the power loss into heat loss. Obtaining the heat loss characteristics can accurately understand the heat generated by the UHV MOSFET components during operation, providing basic data for determining the appropriate heat dissipation structure and judging whether the heat dissipation meets the requirements.

[0058] Based on the preset package layout that has been obtained, the integrated heat pipe heat dissipation structure is determined by considering factors such as the position of the UHV MOSFET component in the package and the spacing with other components. This process requires analyzing the heat dissipation capacity of heat pipes and heat sinks of different specifications, and selecting suitable heat pipes and heat sinks for combination according to the size of the package space, the heat dissipation requirements of the components, etc. For example, if the package space is limited but the heat dissipation requirements are high, a heat pipe with a small diameter but high thermal conductivity and a heat sink with a large heat dissipation area but thin thickness can be selected for combination. For example, in a compact UHV MOSFET package layout, there is a certain space restriction around the MOSFET component in the preset package layout. Through the heat dissipation simulation software, different combinations of heat pipes and heat sinks are simulated, and it is found that an integrated heat pipe heat dissipation structure consisting of a heat pipe with a diameter of 3mm and a length of 50mm and a heat sink with an area of ​​10cm² and a thickness of 2mm can provide a better heat dissipation effect in this space, so this combination is determined to be an integrated heat pipe heat dissipation structure. Determining a suitable integrated heat pipe heat dissipation structure can effectively improve the heat dissipation efficiency of UHV MOSFET components, ensure that the temperature of the components is within a reasonable range during operation, and improve the reliability and service life of the components.

[0059] According to the heat loss characteristics of the UHV MOSFET components and the determined integrated heat pipe heat dissipation structure, the thermal resistance constraint is determined by the heat conduction formula (such as Q=ΔT / R, where Q is the heat transfer rate, ΔT is the temperature difference, and R is the thermal resistance). The calculated thermal resistance is compared with the heat dissipation requirement standard (such as the maximum allowable thermal resistance) in the packaging requirement information to determine whether the heat dissipation requirement is met. Determining the thermal resistance constraint can effectively evaluate whether the current heat dissipation structure can meet the heat dissipation requirements of the UHV MOSFET components, thereby ensuring that the packaged components meet the requirements in terms of heat dissipation and avoiding performance degradation or damage of the components due to insufficient heat dissipation.

[0060] Further, step S65 includes: Step S651: performing thermal stress analysis according to the preset packaging layout to obtain a first expansion coefficient combination.

[0061] Step S652: performing thermal stress analysis according to the integrated heat pipe heat dissipation structure to obtain a second expansion coefficient combination.

[0062] Step S653: performing a two-way balance analysis between heat dissipation requirements and packaging reliability based on the first expansion coefficient combination and the second expansion coefficient combination, determining a structural compatibility constraint standard, and performing verification during the process of adjusting the preset packaging layout.

[0063] Specifically, in circuit packaging, thermal stress will be generated when the temperature changes due to the different thermal expansion coefficients of different materials. Thermal stress analysis calculates and analyzes the stress distribution inside the object by considering factors such as the thermal expansion characteristics of the material, temperature distribution, and structural constraints. An expansion coefficient combination refers to a set of thermal expansion coefficients associated with a specific structure (such as a preset package layout or an integrated heat pipe heat dissipation structure) in thermal stress analysis. The thermal expansion coefficient indicates the degree of expansion or contraction of a material when the temperature changes. An expansion coefficient combination may contain the thermal expansion coefficients of multiple materials, which interact with each other and affect the stress state of the entire structure when the temperature changes. Structural compatibility constraint standards refer to specific requirements for material selection, design parameters, etc. in order to ensure the reliability and heat dissipation performance of the packaging structure.

[0064] For the preset package layout, first determine the various materials involved in the layout, such as packaging materials, chip materials, connection materials, etc. Then, based on the thermal expansion coefficient characteristics of these materials and the structural relationship in the preset package layout, consider the expansion and contraction of these materials under different operating temperature conditions, and use the relevant theories and methods of thermal stress analysis to calculate the stress distribution inside the structure due to temperature changes, thereby obtaining the first expansion coefficient combination related to the preset package layout. For example, finite element analysis software (such as ANSYS, etc.) can be used for thermal stress analysis. Finite element analysis software can accurately simulate the stress state of the structure under thermal load based on input information such as material properties, geometric structure, and boundary conditions.

[0065] For the integrated heat pipe heat dissipation structure, the various materials in the structure, such as heat pipe materials, heat sink materials, etc., are also determined. The thermal expansion behavior of these materials when the temperature changes, as well as the interaction between them, are analyzed. Using the thermal stress analysis method, considering factors such as the operating temperature range of the heat pipe and the temperature change during the heat dissipation of the heat sink, the stress distribution inside the integrated heat pipe heat dissipation structure is calculated, and then the second expansion coefficient combination is obtained. This thermal stress analysis process can also be completed with the help of finite element analysis software.

[0066] The first expansion coefficient combination and the second expansion coefficient combination are used as key data to conduct a two-way balance analysis of heat dissipation requirements and package reliability. In the analysis process, considering the heat dissipation requirements, it is necessary to ensure that the integrated heat pipe heat dissipation structure can effectively dissipate the heat generated by the UHV MOSFET components; in terms of package reliability, it is necessary to ensure that the preset package layout and the integrated heat pipe heat dissipation structure will not cause structural damage or performance degradation due to excessive thermal stress when the temperature changes. Through this two-way analysis, the structural compatibility constraint standard is determined. This structural compatibility constraint standard includes constraints on material selection, structural size, component layout, etc. When adjusting the preset package layout, it is necessary to verify it according to this standard to ensure that each adjustment can meet the heat dissipation requirements while ensuring the reliability of the package.

[0067] Determining the structural compatibility constraint standards and verifying them during the preset package layout adjustment process can effectively balance the heat dissipation requirements and package reliability, avoid ignoring the stability of the package structure due to excessive pursuit of heat dissipation, or affect the heat dissipation effect due to emphasis on package reliability, thereby improving the overall performance of the entire package structure.

[0068] Further, step S653 includes: Step S653-1: matching the first expansion coefficient combination and the second expansion coefficient combination, collecting expansion difference parameters when the temperature changes, and determining a first difference index and stress concentration risk.

[0069] Step S653 - 2 : matching the first expansion coefficient combination and the second expansion coefficient combination, collecting shrinkage difference parameters when the temperature changes, and determining a second difference index and a packaging failure risk.

[0070] Step S653-3: Formulate a structural compatibility constraint standard based on the first difference index and stress concentration risk, the second difference index and packaging failure risk.

[0071] Specifically, the expansion difference parameter is a quantitative indicator of the difference in expansion degree caused by the different thermal expansion characteristics of materials in different structures (preset packaging layout and integrated heat pipe heat dissipation structure) represented by the first expansion coefficient combination and the second expansion coefficient combination when the temperature rises. The expansion difference parameter reflects the inconsistency of the expansion behavior of different structures when the temperature changes. The first difference index is an index calculated based on the expansion difference parameter, which is used to more intuitively represent the degree of expansion difference between different structures. This index can serve as an important basis for judging the risk of stress concentration. The risk of stress concentration is that when there is an expansion difference between different structures, stress concentration may occur at the connection parts or stress-sensitive areas of the structure, resulting in excessive local stress, thereby increasing the risk of structural damage or performance degradation.

[0072] The shrinkage difference parameter is similar to the expansion difference parameter. It is a quantitative indicator of the difference in shrinkage degree caused by the different thermal shrinkage characteristics of materials in different structures when the temperature drops. The second difference index is an index determined based on the shrinkage difference parameter. It is used to indicate the degree of shrinkage difference and is an important basis for judging the risk of package failure. The risk of package failure is the risk of problems such as cracks, looseness or poor electrical connection in the package structure due to shrinkage differences between different structures.

[0073] First, according to the preset package layout, the corresponding coefficients in the first expansion coefficient combination and the second expansion coefficient combination are matched. When the temperature rises, the difference in the expansion amount of each corresponding part is calculated according to the thermal expansion coefficients of different materials, and the set of these differences is the expansion difference parameter. According to the expansion difference parameter, the first difference index is calculated, which can be a weighted average of the expansion difference parameter or other statistical calculation method. Then, the stress concentration risk is evaluated according to the first difference index. If the first difference index is large, it means that the expansion difference is large, and the risk of stress concentration at the structural connection part is high. For example, when the first difference index exceeds a certain empirical threshold, it is determined that the stress concentration risk is high, and measures may need to be taken to adjust the structure or material. Exemplarily, in a packaging structure, the expansion coefficient of the chip bonding material in the preset packaging layout is α, and the expansion coefficient of the material near the chip bonding part in the integrated heat pipe heat dissipation structure is β. When the temperature changes ΔT, the expansion difference parameter ΔL=L α -L β =(α−β)×L×ΔT (where L is the length of the bonding part). By determining the expansion difference parameter and the first difference index, the risk of stress concentration caused by the expansion difference of different structures when the temperature rises can be quantitatively evaluated, providing data support on the expansion difference for the subsequent formulation of structural compatibility constraint standards.

[0074] A similar method to that used to determine the first difference index and stress concentration risk is used to determine the second difference index and the risk of package failure. The first expansion coefficient combination and the second expansion coefficient combination are matched, and the shrinkage difference parameter is calculated based on the thermal shrinkage coefficients of different materials. The second difference index is calculated based on the shrinkage difference parameter, and algorithms such as weighted average can also be used. The risk of package failure is evaluated based on the second difference index. If the second difference index is large, it means that the shrinkage difference is large, and the risk of package failure is high. For example, package cracks, disconnected electrical connections, and other problems may occur. Determining the shrinkage difference parameter and the second difference index can quantitatively evaluate the risk of package failure caused by shrinkage differences of different structures when the temperature is reduced, and provide data support on shrinkage differences for formulating structural compatibility constraint standards.

[0075] The structural compatibility constraint standard is formulated by comprehensively considering the first difference index and stress concentration risk, the second difference index and the packaging failure risk. If the stress concentration risk and packaging failure risk are high (i.e., the first difference index and the second difference index are large), the structural compatibility constraint standard will impose stricter requirements on the selection of materials and the design of the structure (such as component spacing, layout of heat pipes and heat sinks, etc.). For example, if the stress concentration risk is high, the structural compatibility constraint standard may stipulate the use of more elastic adhesive materials at certain key connection parts or the addition of buffer structures at the connection parts; if the packaging failure risk is high, it may be required to adjust the relative position of the heat pipe and other components to reduce the impact of shrinkage differences during temperature changes.

[0076] The proposed structural compatibility constraint standard can ensure that the preset package layout and integrated heat pipe cooling structure have good compatibility when the temperature changes, balance the heat dissipation requirements and packaging reliability, and reduce the risk of structural problems and performance degradation caused by differences in thermal expansion and contraction.

[0077] Furthermore, step S4 further includes: Step S41: for the connection between the high-side MOSFET source pin and the low-side MOSFET drain pin, collect a type of sensitive circuit behavior and add a first marking instruction.

[0078] Step S42: for the connection between the source pin of the high-side MOSFET and the motor winding, collect the second type of sensitive circuit behavior and add a second marking instruction.

[0079] Step S43: Obtaining compatible constraint supplementary conditions through the first type of sensitive circuit behavior and the first marking instruction, the second type of sensitive circuit behavior and the second marking instruction.

[0080] Step S44: Based on the compatibility constraint supplementary condition, conflict points of the structural compatibility constraint standard are identified and checked.

[0081] Specifically, sensitive circuit behaviors are circuit operating states or phenomena that occur in specific connection parts of the circuit (such as between the high-side MOSFET source pin and the low-side MOSFET drain pin, and between the high-side MOSFET source pin and the motor winding), which have a significant impact on the circuit performance, stability or reliability, including current mutations, voltage fluctuations, signal interference, etc. The marking instruction is an instruction code used to identify and distinguish different types of sensitive circuit behaviors. The first marking instruction is used to mark a type of sensitive circuit behavior, and the second marking instruction is used to mark a type of sensitive circuit behavior, which is convenient for subsequent processing and analysis of these behaviors. Compatibility constraint supplementary conditions are conditions obtained by analyzing and sorting out different types of sensitive circuit behaviors with marking instructions. These conditions supplement the existing structural compatibility constraint standards, making them more comprehensive and better able to adapt to various special situations in the circuit.

[0082] Use circuit testing equipment (such as an oscilloscope, current probe, etc.) to monitor the connection line between the source pin of the high-side MOSFET and the drain pin of the low-side MOSFET. Observe and record the sensitive circuit behaviors that occur when the circuit is operating normally and in various simulated abnormal operating conditions (recorded as a type of sensitive circuit behavior). For example, it may be found that when the circuit switches states, a short current spike appears on the connection line between the two points. This is a type of sensitive circuit behavior. Add a first marking instruction for a type of sensitive circuit behavior. This instruction can be a specific code or symbol used to uniquely identify a type of sensitive circuit behavior.

[0083] The connection between the high-side MOSFET source pin and the motor winding is also monitored using circuit test equipment. Under different operating conditions, such as different motor speeds and load changes, the second-class sensitive circuit behavior that occurs is collected. For example, when the motor load suddenly increases, a brief drop in the voltage on this connection line may be found, which is a second-class sensitive circuit behavior. Add a second tag instruction for this sensitive circuit behavior, A comprehensive analysis is performed on the behavior of a sensitive circuit of type I with the first tag instruction and the behavior of a sensitive circuit of type II with the second tag instruction. For example, the impact of the current spike in the behavior of a sensitive circuit of type I on other components in the circuit and the chain reaction that the voltage drop in the behavior of a sensitive circuit of type II may cause are considered. Based on these analysis results, the compatibility constraint supplementary conditions are obtained. These compatibility constraint supplementary conditions include the adjustment range of component parameters, special requirements for circuit wiring, etc. For example, if the current spike may shorten the life of a capacitor, the compatibility constraint supplementary conditions will stipulate that the withstand voltage value of this capacitor needs to be increased by a certain proportion; if the voltage drop may affect the performance of the motor, the compatibility constraint supplementary conditions will require the addition of a voltage stabilization circuit to the connecting line. This analysis process can use circuit analysis software (such as SPICE software) to simulate and analyze the circuit after comprehensively considering the sensitive circuit behavior to determine the compatibility constraint supplementary conditions.

[0084] Compare and analyze the compatibility constraint supplementary conditions with the existing structural compatibility constraint standards, find out the possible contradictions or points that do not conform to the actual situation (i.e., conflict points) in the standards, and make corrections and adjustments to ensure the accuracy and effectiveness of the structural compatibility constraint standards. For example, check whether the voltage stabilization circuit requirements in the supplementary conditions conflict with the power distribution network layout in the structural compatibility constraint standards. If the addition of the voltage stabilization circuit changes the original characteristics of the power distribution network, it is marked as a conflict point. Circuit design rule checking tools can be used to assist in identifying conflict points. For the identified conflict points, check them according to the actual needs and performance requirements of the circuit. For example, if the addition of the voltage stabilization circuit does affect the optimized layout of the power distribution network, but it is very necessary to ensure the stable operation of the motor, then it may be necessary to fine-tune the layout of the power distribution network or re-evaluate the relevant clauses in the structural compatibility constraint standards.

[0085] By identifying and checking conflict points, it is possible to ensure that the structural compatibility constraint standards and the newly acquired compatibility constraint supplementary conditions are coordinated and consistent with each other, thereby improving the rationality and feasibility of the entire circuit design.

[0086] In summary, the packaging optimization method for UHV MOSFET provided in the embodiment of the present application has the following technical effects: By determining the preset package layout and analyzing the influence of parasitic capacitance and inductance, the switching speed and voltage overshoot of the UHV MOSFET are optimized, the energy loss is reduced, and the stability and reliability of the circuit are improved. Secondly, by formulating an equivalent RC circuit and establishing a performance optimization model, the circuit behavior can be accurately simulated, providing a theoretical basis for performance optimization. Further, the introduction of compact layout guidance of peripheral electronic components and power distribution networks achieves maximum space utilization and optimization of signal transmission. In addition, by collecting sensitive circuit behaviors and adding marking instructions, compatible constraint supplementary conditions are obtained, and the robustness of the circuit design is enhanced. Finally, combined with the heat loss characteristics and the integrated heat pipe heat dissipation structure, the thermal resistance constraint conditions are determined to ensure that the heat dissipation requirements and the reliability of the packaging structure are met. Overall, the embodiment of the present application achieves comprehensive optimization of the UHV MOSFET package by comprehensively considering electrical performance, thermal management, structural compatibility and sensitive circuit behavior, and improves the overall performance of the UHV MOSFET.

[0087] Embodiment 2, as Figure 4 As shown, the embodiment of the present application provides a packaging optimization system for ultra-high voltage MOSFET, the system comprising: The preset package layout module 10 is used to determine the preset package layout according to the ultra-high voltage MOSFET component, wherein the ultra-high voltage MOSFET component includes a high-side MOSFET source pin, a motor winding, and a low-side MOSFET drain pin.

[0088] The parasitic capacitance analysis module 20 is used to analyze the parasitic capacitance and the influence of the parasitic capacitance on the switching speed according to the preset packaging layout, obtain a first influence evaluation combination, and perform energy loss correlation analysis according to the first influence evaluation combination, and use the first energy loss correlation analysis result to establish a parasitic capacitance optimization network.

[0089] The parasitic inductance analysis module 30 is used to analyze the parasitic inductance and the influence of the parasitic inductance on the voltage overshoot according to the preset packaging layout, obtain the second influence evaluation combination, and perform energy loss correlation analysis according to the second influence evaluation combination, and use the second energy loss correlation analysis result to establish a parasitic inductance optimization network.

[0090] The equivalent RC circuit module 40 is used to formulate multiple equivalent RC circuits through the high-side MOSFET source pin, motor winding, and low-side MOSFET drain pin in the ultra-high voltage MOSFET element. The multiple equivalent RC circuits include series equivalent RC circuits and parallel equivalent RC circuits.

[0091] The circuit equivalent combination module 50 is used to perform equivalent combination of the series equivalent RC circuits and the parallel equivalent RC circuits in the multiple equivalent RC circuits, and establish a performance optimization model based on the parasitic capacitance optimization network and the parasitic inductance optimization network.

[0092] The package layout optimization module 60 is used to perform a compromise backtracking iteration based on the performance optimization model and the package requirement information of the UHV MOSFET element, and at the same time, adjust the preset package layout to obtain an optimal package layout.

[0093] Furthermore, the execution steps of the package layout optimization module 60 in the embodiment of the present application include: Introduce peripheral electronic components and formulate a peripheral circuit set; guide layout compactness based on the peripheral circuit set and power distribution network, and set layout guidance vectors; use the layout guidance vectors to optimize the relative positions and connection paths between components to obtain the optimal packaging layout.

[0094] Further, based on the peripheral circuit set and the power distribution network, layout compaction guidance is performed, and a layout guidance vector is set. The execution steps include: The circuit interconnection parameters are collected through the circuit interconnection method between the UHV MOSFET component and the peripheral electronic component; based on the peripheral circuit set, the signal mutual recognition parameters are collected through the signal mutual recognition method between the UHV MOSFET component and the peripheral electronic component; with the power distribution network as the direction, the layout compaction guidance is combined with the circuit interconnection parameters and the signal mutual recognition parameters to configure the layout guidance vector.

[0095] Furthermore, the execution steps of the package layout optimization module 60 in the embodiment of the present application also include: Obtain the heat loss characteristics of the UHV MOSFET element; determine an integrated heat pipe heat dissipation structure based on the preset package layout, wherein the integrated heat pipe heat dissipation structure has a combination of heat pipes of various specifications and heat sinks of various specifications; determine a thermal resistance constraint condition according to the heat loss characteristics and in combination with the integrated heat pipe heat dissipation structure, wherein the thermal resistance constraint condition is used to determine whether the heat dissipation requirement standard in the package requirement information is met.

[0096] Further, based on the preset packaging layout, an integrated heat pipe heat dissipation structure is determined, wherein the integrated heat pipe heat dissipation structure has a combination of heat pipes of various specifications and heat sinks of various specifications, and the execution steps include: A thermal stress analysis is performed according to the preset packaging layout to obtain a first expansion coefficient combination; a thermal stress analysis is performed according to the integrated heat pipe heat dissipation structure to obtain a second expansion coefficient combination; a two-way balance analysis of heat dissipation requirements and packaging reliability is performed based on the first expansion coefficient combination and the second expansion coefficient combination, and a structural compatibility constraint standard is determined, which is verified during the process of adjusting the preset packaging layout.

[0097] Furthermore, based on the first expansion coefficient combination and the second expansion coefficient combination, a two-way balance analysis between heat dissipation requirements and packaging reliability is performed to determine a structural compatibility constraint standard, and the execution steps include: Matching is performed based on the first expansion coefficient combination and the second expansion coefficient combination, and expansion difference parameters are collected when the temperature changes to determine a first difference index and a stress concentration risk; matching is performed based on the first expansion coefficient combination and the second expansion coefficient combination, and contraction difference parameters are collected when the temperature changes to determine a second difference index and a packaging failure risk; a structural compatibility constraint standard is formulated based on the first difference index and the stress concentration risk, the second difference index and the packaging failure risk.

[0098] Furthermore, the execution steps of the equivalent RC circuit module 40 in the embodiment of the present application further include: For the connection between the high-side MOSFET source pin and the low-side MOSFET drain pin, a first type of sensitive circuit behavior is collected and a first marking instruction is added; for the connection between the high-side MOSFET source pin and the motor winding, a second type of sensitive circuit behavior is collected and a second marking instruction is added; through the first type of sensitive circuit behavior and the first marking instruction, the second type of sensitive circuit behavior and the second marking instruction, the compatible constraint supplementary condition is obtained; based on the compatible constraint supplementary condition, the conflict point identification and proofreading of the structural compatible constraint standard are performed.

[0099] Through the above-mentioned detailed description of the packaging optimization method for ultra-high voltage MOSFET in this specification, those skilled in the art can clearly understand the packaging optimization system for ultra-high voltage MOSFET in this embodiment. For the system disclosed in Example 2, since it corresponds to the method disclosed in Example 1 and has corresponding functional modules and beneficial effects, the relevant parts can be referred to the description of the method part.

[0100] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A packaging optimization method for ultra-high voltage MOSFET, characterized in that: The method comprises: Determining a preset package layout according to an ultra-high voltage MOSFET component, wherein the ultra-high voltage MOSFET component includes a high-side MOSFET source pin, a motor winding, and a low-side MOSFET drain pin; According to the preset package layout, analyzing the parasitic capacitance and the influence of the parasitic capacitance on the switching speed, obtaining a first influence assessment combination, performing an energy loss correlation analysis according to the first influence assessment combination, and establishing a parasitic capacitance optimization network using the first energy loss correlation analysis result; According to the preset package layout, analyzing the parasitic inductance and the influence of the parasitic inductance on the voltage overshoot, obtaining a second influence assessment combination, performing an energy loss correlation analysis according to the second influence assessment combination, and establishing a parasitic inductance optimization network using the second energy loss correlation analysis result; By means of the high-side MOSFET source pin, the motor winding, and the low-side MOSFET drain pin in the UHV MOSFET element, a plurality of equivalent RC circuits are proposed, wherein the plurality of equivalent RC circuits include a series equivalent RC circuit and a parallel equivalent RC circuit; Equivalently combining the series equivalent RC circuits and the parallel equivalent RC circuits in the multiple equivalent RC circuits, and establishing a performance optimization model according to the parasitic capacitance optimization network and the parasitic inductance optimization network; Based on the performance optimization model, a compromise backtracking iteration is performed in combination with the packaging requirement information of the UHV MOSFET element, and at the same time, the preset packaging layout is adjusted to obtain an optimal packaging layout.

2. The packaging optimization method for UHV MOSFET according to claim 1, characterized in that: The preset packaging layout is adjusted to obtain an optimal packaging layout, the method comprising: Introduce peripheral electronic components and formulate peripheral circuit sets; Performing layout compaction guidance based on the peripheral circuit set and the power distribution network, and setting a layout guidance vector; The layout guiding vectors are used to optimize the relative positions and connection paths between components to obtain the optimal package layout.

3. The packaging optimization method for UHV MOSFET according to claim 2, characterized in that: Based on the peripheral circuit set and the power distribution network, layout compaction guidance is performed, and a layout guidance vector is set. The method includes: Collecting circuit interconnection parameters through the circuit interconnection mode between the UHV MOSFET component and the peripheral electronic component; Based on the peripheral circuit set, signal mutual recognition parameters are collected through a signal mutual recognition method between the UHV MOSFET component and the peripheral electronic component; Taking the power distribution network as a direction, the circuit interconnection parameters and the signal mutual recognition parameters are combined to guide the layout compactness, and the layout guidance vector is configured.

4. The packaging optimization method for UHV MOSFET according to claim 2, characterized in that: The preset packaging layout is adjusted to obtain an optimal packaging layout, and the method further includes: Obtaining heat loss characteristics of the UHV MOSFET element; Based on the preset packaging layout, an integrated heat pipe heat dissipation structure is determined, wherein the integrated heat pipe heat dissipation structure has a combination of heat pipes of various specifications and heat sinks of various specifications; According to the heat loss characteristics and in combination with the integrated heat pipe heat dissipation structure, a thermal resistance constraint condition is determined, and the thermal resistance constraint condition is used to determine whether the heat dissipation requirement standard in the packaging requirement information is met.

5. The packaging optimization method for UHV MOSFET according to claim 4, characterized in that: Based on the preset packaging layout, an integrated heat pipe heat dissipation structure is determined, wherein the integrated heat pipe heat dissipation structure has a combination of heat pipes of various specifications and heat sinks of various specifications, and the method includes: Performing thermal stress analysis according to the preset packaging layout to obtain a first expansion coefficient combination; Performing thermal stress analysis according to the integrated heat pipe heat dissipation structure to obtain a second expansion coefficient combination; A two-way balance analysis between heat dissipation requirements and packaging reliability is performed based on the first expansion coefficient combination and the second expansion coefficient combination, a structural compatibility constraint standard is determined, and verification is performed during the process of adjusting the preset packaging layout.

6. The packaging optimization method for UHV MOSFET according to claim 5, characterized in that: Based on the first expansion coefficient combination and the second expansion coefficient combination, a two-way balance analysis between heat dissipation requirements and packaging reliability is performed to determine a structural compatibility constraint standard, the method comprising: Matching is performed according to the first expansion coefficient combination and the second expansion coefficient combination, collecting expansion difference parameters when the temperature changes, and determining a first difference index and stress concentration risk; Matching the first expansion coefficient combination and the second expansion coefficient combination, collecting shrinkage difference parameters when the temperature changes, and determining a second difference index and a packaging failure risk; A structural compatibility constraint standard is formulated based on the first difference index and stress concentration risk, the second difference index and packaging failure risk.

7. The packaging optimization method for UHV MOSFET according to claim 6, characterized in that: By using the high-side MOSFET source pin, the motor winding, and the low-side MOSFET drain pin in the UHV MOSFET element, a plurality of equivalent RC circuits are proposed, and the method further includes: For the connection between the high-side MOSFET source pin and the low-side MOSFET drain pin, collect a class of sensitive circuit behaviors and add a first marking instruction; For the connection between the source pin of the high-side MOSFET and the motor winding, collect the second type of sensitive circuit behavior and add a second marking instruction; Obtaining a compatible constraint supplementary condition through the first type of sensitive circuit behavior and the first marking instruction, the second type of sensitive circuit behavior and the second marking instruction; Based on the compatibility constraint supplementary conditions, conflict points of the structural compatibility constraint standard are identified and proofread.

8. A packaging optimization system for UHV MOSFET, characterized in that: The system is used to execute the packaging optimization method for ultra-high voltage MOSFET according to any one of claims 1 to 7, comprising: A preset package layout module, used to determine a preset package layout according to an ultra-high voltage MOSFET component, wherein the ultra-high voltage MOSFET component includes a high-side MOSFET source pin, a motor winding, and a low-side MOSFET drain pin; A parasitic capacitance analysis module, configured to analyze parasitic capacitance and the influence of parasitic capacitance on switching speed according to the preset package layout, obtain a first influence assessment combination, perform energy loss correlation analysis according to the first influence assessment combination, and establish a parasitic capacitance optimization network using the first energy loss correlation analysis result; A parasitic inductance analysis module, configured to analyze the parasitic inductance and the influence of the parasitic inductance on the voltage overshoot according to the preset package layout, obtain a second influence assessment combination, perform an energy loss correlation analysis according to the second influence assessment combination, and establish a parasitic inductance optimization network using the second energy loss correlation analysis result; An equivalent RC circuit module, used to formulate multiple equivalent RC circuits through the high-side MOSFET source pin, the motor winding, and the low-side MOSFET drain pin in the ultra-high voltage MOSFET element, wherein the multiple equivalent RC circuits include a series equivalent RC circuit and a parallel equivalent RC circuit; A circuit equivalent combination module, used for equivalently combining the series equivalent RC circuits and the parallel equivalent RC circuits in the multiple equivalent RC circuits, and establishing a performance optimization model according to the parasitic capacitance optimization network and the parasitic inductance optimization network; The package layout optimization module is used to perform a compromise backtracking iteration based on the performance optimization model and the package requirement information of the ultra-high voltage MOSFET element, and at the same time, adjust the preset package layout to obtain an optimal package layout.

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