Chip Interconnection Method, Device and Equipment for Multilayer Stacked Memory Packaging Structure

Abstract

The present invention relates to a chip interconnection method, device and equipment for a multi-layer stacked memory package structure, including the following steps: arranging the positions of a plurality of thinned memory dies based on a preset chip layout diagram to obtain an arranged chip array; performing bonding surface alignment on each target memory die in the arranged chip array through a high-precision alignment device to obtain an aligned chip array; performing thermocompression bonding operation on the aligned chip array to obtain a bonded chip stack; performing edge cutting on the bonded chip stack to obtain a cut chip stack; performing metal filling interconnection on the cut chip stack through a micro-pitch interconnection technology to obtain an interconnected chip stack; and performing vacuum resin packaging on the interconnected chip stack by using a heterogeneous integration packaging technology to obtain a target packaged memory chip stack structure, which solves the technical problem of how to ensure stable and efficient electrical connection between multi-layer stacked memories.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-layer stacked memory, and in particular to a chip interconnection method, device and equipment of a multi-layer stacked memory packaging structure. Background Art

[0002] With the rapid development of information technology, the demand for data storage continues to rise, and the traditional two-dimensional chip layout can no longer meet the needs of modern computing systems for high-performance and high-density storage. In order to overcome the physical limitations of planar expansion and improve performance, three-dimensional stacking technology came into being and became one of the important directions for exploration in the semiconductor industry. However, there are many challenges in the process of realizing multi-layer stacked memory packaging structures. For example, the mechanical strength of the die is reduced after thinning, making it easy to break or deform in subsequent processing; at the same time, due to the difference in thermal expansion coefficients between different materials, the stress generated during the bonding process may cause interface separation or crack formation. These problems greatly affect the reliability and yield of the final product.

[0003] Another key issue in the research background is the selection and implementation of interconnection technology. When multiple memory dies are stacked together, how to ensure that a stable and efficient electrical connection can be established between them is a technical problem that needs to be solved urgently. Existing interconnection methods are often limited by limited wiring space and signal transmission delays, which not only limits the performance of the chip, but also increases the cost of design and manufacturing. In addition, as the number of stacked layers increases, the heat accumulation effect becomes more significant, which puts higher requirements on heat dissipation management. Therefore, developing a new type of micro-pitch interconnection technology to improve these problems has become the main goal of researchers in this field.

[0004] Finally, considering the impact of packaging process on the performance of the entire memory, the application of heterogeneous integrated packaging technology is particularly important. Traditional packaging methods usually cannot provide sufficient protection to cope with the increasingly complex internal structure, and may introduce additional parasitic parameters, thereby weakening the functional performance of the device. In order to achieve high-performance multi-layer stacked memory, advanced packaging methods must be adopted, such as vacuum resin packaging, which can effectively reduce the interference of external environmental factors (such as temperature changes, humidity, etc.) on the working state of the chip. But at the same time, new packaging technology also brings new problems such as increased process complexity and rising costs. Therefore, this study aims to propose an innovative chip interconnection method to overcome the shortcomings of existing technologies by optimizing various manufacturing steps, including precise position arrangement, high-precision alignment bonding, edge cutting and three-dimensional through-hole interconnection, and lay a solid foundation for future high-performance storage solutions. Summary of the invention

[0005] The main object of the present invention is to provide a chip interconnection method, device and equipment for a multi-layer stacked memory packaging structure, which solves the technical problem of how to ensure a stable and efficient electrical connection between multi-layer stacked memories.

[0006] To achieve the above object, the present invention provides a chip interconnection method for a multi-layer stacked memory packaging structure, including the following steps:

[0007] Based on a preset chip layout diagram, arrange the positions of multiple thinned memory dies to obtain an arranged chip array;

[0008] Use a high-precision alignment device to align the bonding surfaces of each target memory die in the arranged chip array to obtain an aligned chip array;

[0009] Apply thermocompression bonding technology to perform thermocompression bonding operations on the aligned chip array to obtain a bonded chip stack;

[0010] Use femtosecond laser micromachining technology to perform edge cutting on the bonded chip stack to obtain a cut chip stack;

[0011] Perform metal filling interconnection on the cut chip stack through micro-pitch interconnection technology to obtain an interconnected chip stack;

[0012] Adopt heterogeneous integration packaging technology to perform vacuum resin packaging on the interconnected chip stack to obtain a target packaged memory chip stack structure.

[0013] Further, the arranging the positions of multiple thinned memory dies based on a preset chip layout diagram to obtain an arranged chip array includes:

[0014] Perform interlayer interconnection path analysis on the preset chip layout diagram through a preset parsing algorithm to obtain an interconnection density distribution map and a chip function division table;

[0015] Based on the interconnection density distribution map, perform initial position allocation on the multiple thinned memory dies to obtain an initial arranged chip array;

[0016] Based on the chip function division table, perform hierarchical division on the initial arranged chip array to obtain a hierarchical chip array;

[0017] Control a preset high-precision robotic arm through a space filling curve algorithm to arrange the chips in each layer of the hierarchical chip array to obtain an arranged chip array.

[0018] Further, the using a high-precision alignment device to align the bonding surfaces of each target memory die in the arranged chip array to obtain an aligned chip array includes:

[0019] Perform dual-wavelength optical interference measurement on the arranged chip array to obtain chip surface profile data;

[0020] Extract edge features from the chip surface profile data through a sub-pixel edge detection algorithm to obtain a chip edge feature map;

[0021] Perform six-degree-of-freedom pose analysis on each of the target storage dies in the arranged chip array based on the chip edge feature map to obtain chip spatial pose data;

[0022] Through a piezoelectric nano-displacement platform, perform real-time closed-loop feedback control on the chip spatial pose data to obtain a set of displacement compensation parameters; wherein, the set of displacement compensation parameters includes X-Y plane displacement, Z-axis height error, and angle correction value;

[0023] Generate a sequence of alignment execution instructions for multi-axis linkage control within a preset high-precision alignment device based on the set of displacement compensation parameters;

[0024] Control the high-precision alignment of each target storage die in the arranged chip array through the alignment execution instruction sequence to obtain an aligned chip array.

[0025] Further, perform thermocompression bonding operation on the aligned chip array using thermocompression bonding technology, to obtain a bonded chip stack, including:

[0026] Perform preheating treatment on the aligned chip array through a preset temperature curve to obtain a preheated chip array, and perform simulation of the temperature field in the bonding area of the preheated chip array to obtain temperature field distribution data;

[0027] Set parameters for a preset thermocompression bonding device based on the temperature field distribution data to obtain set parameters, and perform real-time temperature monitoring and feedback control on the set parameters to obtain a temperature control curve;

[0028] Use thermocompression bonding technology to perform thermocompression bonding operation on the aligned chip array through the set pressure curve and the temperature control curve to obtain an initial bonded chip stack, and perform stress analysis on the bonding interface of the initial bonded chip stack to obtain stress distribution data;

[0029] Perform ultrasonic-assisted bonding treatment on the bonding interface in the aligned chip array based on the stress distribution data to obtain a strengthened bonded chip stack, and perform bonding strength testing on the strengthened bonded chip stack to obtain bonding strength data;

[0030] Through vacuum annealing process technology, eliminate residual stress on the strengthened bonded chip stack based on the bonding strength data to obtain a bonded chip stack.

[0031] Further, the edge cutting of the bonded chip stack by using femtosecond laser micromachining technology to obtain a cut chip stack includes:

[0032] Performing three-dimensional X-ray tomography on the bonded chip stack to obtain a stack structure image, and planning a femtosecond laser scanning path based on the stack structure image to obtain a laser scanning path map;

[0033] Performing thermal effect simulation analysis on the laser scanning path map to obtain thermal influence area distribution data, and setting parameters of a preset femtosecond laser based on the thermal influence area distribution data to obtain laser processing parameters;

[0034] Controlling the femtosecond laser to perform femtosecond laser cutting on the bonded chip stack based on the laser processing parameters to obtain a roughly cut chip stack, and characterizing the morphology of the cutting edge of the roughly cut chip stack to obtain cutting edge morphology data;

[0035] Performing plasma-assisted etching on the roughly cut chip stack based on the cutting edge morphology data to obtain a finely cut chip stack;

[0036] Performing chemical mechanical polishing and edge cutting on the finely cut chip stack to obtain a cut chip stack.

[0037] Further, the metal filling interconnection of the cut chip stack by using micro-pitch interconnection technology to obtain an interconnected chip stack includes:

[0038] Planning the via hole positions of the cut chip stack based on a preset interconnection circuit diagram to obtain a via hole position distribution map, and performing electromagnetic field simulation analysis on the via hole position distribution map to obtain electromagnetic interference distribution data;

[0039] Performing blind hole processing on the cut chip stack based on the electromagnetic interference distribution data by using femtosecond laser ablation technology to obtain a blind hole chip stack, and measuring the depth of the blind holes of the blind hole chip stack to obtain blind hole depth data;

[0040] Performing deep silicon etching process on the blind hole chip stack based on the blind hole depth data to obtain a via hole chip stack, and analyzing the roughness of the side walls of the via holes of the via hole chip stack to obtain side wall roughness data;

[0041] Depositing an insulating layer on the via hole chip stack by using selective atomic layer deposition technology based on the side wall roughness data and the via hole depth data to obtain an insulating coating chip stack, and calculating the thickness uniformity of the insulating layer of the insulating coating chip stack to obtain thickness uniformity data;

[0042] Based on the thickness uniformity data, perform a planarization process on the insulated coating chip stack to obtain a planarized chip stack;

[0043] Perform metal filling interconnection on the planarized chip stack through an electrochemical deposition technique to obtain an interconnected chip stack.

[0044] Furthermore, perform vacuum resin encapsulation on the interconnected chip stack by using a heterogeneous integration packaging technique to obtain a target packaged memory chip stack structure, including:

[0045] Perform a three-dimensional structure scan on the interconnected chip stack to obtain three-dimensional structure data, and based on the three-dimensional structure data, design the structure of the packaging cavity of the interconnected chip stack to obtain a packaging cavity model;

[0046] Perform vacuum resin pouring encapsulation on the packaging cavity model by using a heterogeneous integration packaging technique to obtain a resin-filled chip stack, and perform filling uniformity detection on the resin-filled chip stack to obtain resin filling uniformity data;

[0047] Based on the resin filling uniformity data, perform ultraviolet curing on the resin-filled chip stack to obtain a cured resin chip stack, and perform curing degree detection on the cured resin chip stack to obtain curing degree data;

[0048] When the curing degree data reaches a preset curing degree range, then perform laser demolding on the cured resin chip stack through a preset femtosecond laser precision control system to obtain a demolded chip stack;

[0049] Perform plasma cleaning on the demolded chip stack to obtain a cleaned chip stack, and perform external lead connection on the cleaned chip stack through a wire bonding technique to obtain a target packaged memory chip stack structure.

[0050] The present invention also provides a chip interconnection device for a multi-layer stacked memory packaging structure, including:

[0051] An arrangement module, configured to arrange the positions of a plurality of thinned memory dies based on a preset chip layout diagram to obtain an arranged chip array;

[0052] An alignment module, configured to align the bonding surfaces of each target memory die in the arranged chip array through a high-precision alignment device to obtain an aligned chip array;

[0053] A hot pressing module, configured to perform a hot pressing bonding operation on the aligned chip array by using a thermocompression bonding technique to obtain a bonded chip stack;

[0054] A cutting module, which is used to perform edge cutting on the bonded chip stack by using femtosecond laser micromachining technology to obtain a cut chip stack;

[0055] An interconnection module, which is used to perform metal-filled interconnection on the cut chip stack by using micro-pitch interconnection technology to obtain an interconnected chip stack;

[0056] A packaging module, which is used to perform vacuum resin packaging on the interconnected chip stack by using heterogeneous integration packaging technology to obtain a target packaged memory chip stack structure.

[0057] The present invention also provides a computer device, including a memory and a processor. A computer program is stored in the memory, and when the processor executes the computer program, the steps of the method described in any one of the above are implemented.

[0058] The present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method described in any one of the above are implemented.

[0059] The chip interconnection method of the multi-layer stacked memory packaging structure provided by the present invention includes the following steps: arranging the positions of multiple thinned memory dies based on a preset chip layout diagram to obtain an arranged chip array; performing bonding surface alignment on each target memory die in the arranged chip array through a high-precision alignment device to obtain an aligned chip array; performing thermocompression bonding operation on the aligned chip array to obtain a bonded chip stack; performing edge cutting on the bonded chip stack to obtain a cut chip stack; performing metal-filled interconnection on the cut chip stack by using micro-pitch interconnection technology to obtain an interconnected chip stack; performing vacuum resin packaging on the interconnected chip stack by using heterogeneous integration packaging technology to obtain a target packaged memory chip stack structure, which solves the technical problem of how to ensure stable and efficient electrical connection between multi-layer stacked memories, and realizes that through the combination of micro-pitch interconnection technology and three-dimensional via interconnection, an efficient electrical connection path can be established in a limited space, reducing signal transmission delay and power consumption. This not only improves the data reading and writing speed, but also helps to maintain a stable communication link, especially more prominent in a high-speed computing environment. Description of the Drawings

[0060] Figure 1 is a schematic diagram of the steps of the chip interconnection method of the multi-layer stacked memory packaging structure in an embodiment of the present invention;

[0061] Figure 2 is a structural block diagram of the chip interconnection device of the multi-layer stacked memory packaging structure in an embodiment of the present invention;

[0062] Figure 3It is a schematic block diagram of a computer device according to an embodiment of the present invention.

[0063] The implementation of the object, functional features and advantages of the present invention will be further described with reference to the embodiments and the accompanying drawings. Detailed implementation manners

[0064] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0065] As Figure 1 shown, Figure 1 It is a schematic diagram of the steps of a chip interconnection method for a multi-layer stacked memory package structure according to an embodiment of the present invention;

[0066] An embodiment of the present invention provides a chip interconnection method for a multi-layer stacked memory package structure, including the following steps:

[0067] Step S1, arranging the positions of a plurality of thinned memory dies based on a preset chip layout diagram to obtain an arranged chip array.

[0068] Specifically, when implementing the step of "arranging multiple thinned memory dies according to a preset chip layout diagram to obtain an arranged chip array" mentioned above, a detailed planning and design process is first required. The chip layout diagram here refers to a blueprint carefully designed in advance based on factors such as required performance parameters, space limitations, and electrical characteristics. It determines the relative positions and arrangement patterns of each memory die in the stack body ultimately. For example, in the application scenario of a high-performance computing module, to ensure data access speed and reduce signal latency, the designer may place the dies with higher read frequencies closer to the central processing unit, while considering the heat dissipation path to avoid local overheating problems. After determining such a layout scheme, the actual operation stage follows. In this process, memory dies that have been significantly thinned through specific processes are used to construct the target structure. These thinned dies are not only thinner and lighter but also can be stacked more closely together, thus achieving higher integration. However, since they become more fragile, extra care must be taken during handling and positioning. Technicians will use specialized equipment to assist in completing this step, such as high-precision robotic arms or suction cup tools, to ensure that each die is accurately placed in position according to the predetermined coordinates. Once all the specified dies are properly arranged, the so-called arranged chip array is formed, which is the basis for a series of subsequent processing steps, including bonding face alignment, thermocompression bonding, etc. Each link is closely connected and works together to ultimately form a stable and reliable multi-layer stacked memory package structure. For example, when manufacturing a high-speed solid-state drive (SSD) for a data center server, engineers will arrange different types of NAND flash dies according to the preset chip layout diagram. Through this precise position arrangement, not only can the direction of the internal data flow be optimized, but also sufficient space can be left for future expansion, thereby improving the efficiency and flexibility of the entire storage system. Throughout the process, from the initial design to the final product shaping, every detail is to ensure that the end user can obtain the best usage experience.

[0069] Step S2: Align the bonding faces of each target memory die in the arranged chip array through a high-precision alignment device to obtain an aligned chip array.

[0070] Specifically, when implementing the key step of "bonding surface alignment of each target storage die in the arranged chip array through a high-precision alignment device to obtain an aligned chip array" described above, it is first necessary to emphasize that this process is carried out after the position arrangement of multiple thinned storage dies has been completed based on a preset chip layout diagram. After the arranged chip array is formed, in order to ensure that each layer can be accurately bonded together and to guarantee the quality and reliability of electrical connections, it is necessary to use a high-precision alignment device for the next operation. The high-precision alignment device mentioned here is usually equipped with an advanced optical system or a laser measurement system. These systems can identify the tiny marks or feature points on each target storage die, and then calculate the correct relative positions through complex algorithms. For example, when constructing a high-speed solid-state drive (SSD) for a data center server, engineers will use this device to ensure that each NAND flash die can be accurately aligned with other layers. This is because even a very small misalignment may lead to bonding failure or affect the performance of the finished product. Especially in the case of multi-layer stacking, the deviation of any layer will be amplified, thus affecting the function of the entire stack. Therefore, using a high-precision alignment device is crucial. It not only improves production efficiency but also significantly reduces the scrap rate caused by misalignment. Once the correct positions of all target storage dies are determined, they need to be fixed in this specific posture so that the subsequent thermocompression bonding process can proceed smoothly. During this process, the device may apply a slight pressure to keep the contact surface between the dies stable, and may also combine with a visual monitoring system to adjust the alignment situation in real time to ensure the best bonding effect. Finally, the arranged chip array after this step is transformed into an aligned chip array, providing a solid foundation for the subsequent thermocompression bonding. Throughout the process, from the initial arrangement to the final alignment, each link is closely connected, jointly working towards manufacturing a high-performance and high-quality multi-layer stacked memory package structure. In this way, not only the integration and performance of the product are improved, but also the growing demand of modern information technology for high-performance storage solutions is met.

[0071] Step S3, perform a thermocompression bonding operation on the aligned chip array using thermocompression bonding technology to obtain a bonded chip stack.

[0072] Specifically, in the process of "performing a thermocompression bonding operation on the aligned chip array using thermocompression bonding technology to obtain a bonded chip stack", thermocompression bonding technology plays a crucial role. It not only ensures the physical connection between individual memory dies but also achieves reliable electrical contact. After alignment is completed by a high-precision alignment device, the next step is the key process of fixing these precisely arranged dies into an integrated structure. To achieve this, in actual operation, a special fixture is first prepared to hold the aligned chip array, ensuring that all target memory dies maintain their relative positions unchanged throughout the thermocompression process. This fixture usually has a fine adjustment mechanism that can fine-tune the position of each die before it is placed in the thermocompression machine to ensure the best bonding effect. Once the fixture is ready and loaded into the thermocompression machine, the technician will start the machine and operate according to the pre-set temperature, pressure, and time parameters. For example, when constructing a high-speed solid-state drive (SSD) for a data center server, engineers will carefully adjust these parameters based on the specific properties of the materials used, such as the thermal expansion coefficient of silicon-based NAND flash dies, to ensure that sensitive components are not damaged due to excessive temperature or pressure, while achieving the desired bonding strength. During the thermocompression process, uniform heating is one of the important factors to ensure high-quality bonding. The thermocompression machine is equipped with a precise temperature control system that can provide a consistent and stable heat distribution, enabling each bonding area to receive the same processing conditions. This not only avoids damage caused by local overheating but also promotes atomic-level diffusion at the interface, forming a solid chemical bond. At the same time, an appropriate cooling rate cannot be ignored because it affects the final quality and performance of the finished product. If the cooling is too fast, it may cause stress concentration and cracks; conversely, if the cooling is too slow, it may extend the production cycle and affect efficiency. Therefore, during the cooling stage, the thermocompression machine also uses a step-by-step cooling method to ensure the stability and durability of the bonded chip stack. After the above series of precisely controlled operations, the originally separately arranged memory dies form a solid whole - the bonded chip stack. This integrated structure not only has excellent mechanical stability but also provides a solid foundation for subsequent three-dimensional through-hole interconnection, further enhancing the speed and reliability of signal transmission. The multi-layer stacked memory manufactured in this way can significantly improve the data read and write speed and reduce latency, making it very suitable for application in high-performance computing environments and meeting the requirements of modern information technology for high-performance storage solutions.

[0073] Step S4: Use femtosecond laser micromachining technology to perform edge cutting on the bonded chip stack to obtain a cut chip stack.

[0074] Specifically, in the step of "using femtosecond laser micromachining technology to perform edge cutting on the bonded chip stack to obtain a cut chip stack" mentioned above, the application of femtosecond laser micromachining technology is the key to achieving high-precision and high-quality edge processing. The selection of this technology is based on its ability to provide extremely high temporal and spatial resolution, thus ensuring that the cutting process is both precise and efficient. After the thermocompression bonding operation is completed, the formed bonded chip stack needs to be further processed to meet the requirements of the final size and shape. At this time, femtosecond laser is required to perform fine edge cutting. Specifically, before preparing for edge cutting, the bonded chip stack is first fixed on a special workbench, which has high-precision positioning function to ensure that the stack does not displace during the cutting process. Then, technicians will set various parameters of the femtosecond laser according to the design requirements, including laser pulse width, energy density, and scanning speed, etc. For example, when manufacturing high-speed solid-state drives (SSDs) for data center servers, engineers will pay special attention to the distance between NAND flash dies and the stability of the overall structure. Therefore, when setting the cutting parameters, these factors must be taken into account to ensure that the performance of the cut product is not affected. The characteristic of femtosecond laser is that it can release a huge amount of energy in a very short time. This characteristic enables it to instantaneously melt or vaporize the material surface. At the same time, due to the extremely short action time, the generated heat hardly transfers to the surrounding materials, thus avoiding the common thermal damage problems in traditional cutting methods. Once all parameters are carefully calibrated, the femtosecond laser starts to cut the bonded chip stack along the preset path. During this process, the laser beam forms a series of tiny grooves on the material surface. As the laser head moves along the specified route, these grooves gradually connect into a complete cutting line, finally removing the excess material to obtain the desired cut chip stack. It is worth mentioning that femtosecond laser micromachining technology is not limited to straight cutting. It can also achieve precise cutting of complex geometric shapes, which is particularly important for product designs in some special application scenarios. In addition, since almost no mechanical stress is generated during the cutting process, the cracks or other defects caused by cutting can be greatly reduced, significantly improving the yield rate. In this way, the edge cutting completed by using femtosecond laser micromachining technology can not only meet the strict dimensional tolerance requirements, but also maintain the smoothness and flatness of the cutting surface, providing a good foundation for subsequent processes such as three-dimensional through-hole interconnection. Finally, the carefully cut chip stack will exhibit higher integration and better electrical performance, further improving the efficiency and reliability of the entire storage system, perfectly meeting the requirements of modern information technology for high-performance storage solutions.

[0075] Step S5, perform metal filling interconnection on the cut chip stack through micro-spacing interconnection technology to obtain an interconnected chip stack.

[0076] Specifically, in the key step of "performing metal-filled interconnection on the diced chip stack using micro-pitch interconnection technology to obtain an interconnected chip stack", the metal-filled interconnection technology is the core process for achieving efficient and stable electrical connections. After the edge dicing of the bonded chip stack using femtosecond laser micromachining technology is completed, the next thing to solve is how to establish reliable conductive paths between these closely arranged memory die to ensure that data can be transmitted quickly and accurately. This process is crucial for constructing high-performance multi-layer stacked memories. Specifically, before preparing for metal filling, through-holes penetrating through each layer need to be fabricated on the diced chip stack first. These through-holes will serve as conductive channels between different layers, enabling the circuits to be directly connected. For example, when manufacturing high-speed solid-state drives (SSDs) for data center servers, engineers will use advanced etching techniques and deposition processes to form these through-holes. In this process, tiny holes are first drilled at selected positions, and then metal materials are filled into these holes using methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or electroplating. Commonly used metal materials include copper, tungsten, etc., which have excellent electrical conductivity and mechanical properties, ensuring low-resistance conductive paths, thereby reducing signal transmission delay and improving overall performance. Once the through-holes are successfully constructed and metal filling is completed, micro-pitch interconnection technology needs to be used to ensure that there are precisely arranged solder joints or contact pads around each through-hole and connect them to other circuit components through ultra-fine wires or redistribution layers (RDL). This technology allows a large number of interconnect lines to be arranged in an extremely small space, greatly increasing the connection density per unit area. Since the diameters of the through-holes and the interconnect lines around them are very small, usually ranging from a few microns to dozens of microns, not only is the occupied space reduced, but also the system integration and reliability are enhanced. To ensure the quality and reliability of the interconnection, the entire system also needs to undergo strict testing and verification, including electrical characteristic inspection, thermal cycle testing, etc., to ensure that there are no potential problems affecting the performance of the finished product. The finally formed interconnected chip stack not only has higher integration and faster data transmission speed, but also significantly enhances the reliability and durability of the system. This advanced interconnection technology is particularly suitable for high-performance computing environments, such as SSDs used in data center servers, and it can meet the requirements of modern information technology for large-capacity and high-speed storage solutions. In this way, not only efficient electrical connections between different layers are achieved, but also a stable communication link is provided for subsequent data reading and writing operations, further promoting the development of information technology.

[0077] Step S6: Vacuum resin encapsulation is performed on the interconnected chip stack using heterogeneous integration packaging technology to obtain the target packaged memory chip stack structure.

[0078] Specifically, in the final step of "using heterogeneous integration packaging technology to perform vacuum resin packaging on the interconnected chip stack to obtain the target packaged memory chip stack structure" described above, the heterogeneous integration packaging technology and vacuum resin packaging work together to ensure that the multi-layer stacked memory not only has high performance, but also excellent reliability and environmental adaptability. After metal-filled interconnection is completed through micro-pitch interconnection technology, the closely connected chip stacks then need to be packaged to protect the internal complex circuits from external factors. Specifically, before preparing for packaging, it is first necessary to select suitable packaging materials and processes. The vacuum resin packaging mentioned here refers to using a specific type of resin material and injecting it into a pre-designed packaging cavity under a vacuum environment, and then allowing it to cure to form a solid whole. For example, when manufacturing high-speed solid-state drives (SSDs) for data center servers, engineers will choose resin materials with excellent electrical insulation properties, low hygroscopicity, and good thermal stability. This material can not only provide physical protection against external contaminants such as dust and moisture, but also effectively reduce stress caused by temperature changes, thereby extending the service life of the device. During the actual operation process, to ensure that the resin can be evenly filled into every tiny corner and avoid introducing air bubbles, the entire packaging process is usually carried out under high vacuum conditions. This can maximize the exclusion of gas components in the resin and ensure its density and integrity after curing. In addition, due to the use of heterogeneous integration packaging technology, chips with different functions or process nodes, such as logic control units and storage units, can be integrated within the same package. This not only improves the system integration density, but also simplifies the subsequent design and assembly processes. At the same time, heterogeneous integration packaging can also optimize the signal transmission path and reduce the impact of parasitic parameters, further enhancing the overall performance. Once the packaging process is completed, the target packaged memory chip stack structure is formed. This structure not only inherits all the advantages of the original stack, such as high density and fast data transmission, but also additionally obtains many benefits brought by vacuum resin packaging. For example, it can maintain stable operation in harsh working environments and perform well under both high and low temperature conditions. In addition, the packaged chip stack is also more convenient for installation and maintenance, and is very suitable for applications in data centers and servers where extremely high requirements are placed on reliability and stability. In this way, not only the goal of an energy-efficient storage solution is achieved, but also sufficient space is reserved for future system upgrades and expansions, meeting the needs of the continuous development of modern information technology.

[0079] In a specific embodiment, the arranging the positions of a plurality of thinned memory dies based on a preset chip layout diagram to obtain an arranged chip array includes:

[0080] Interlayer interconnection path analysis is performed on the preset chip layout diagram through a preset parsing algorithm to obtain an interconnection density distribution diagram and a chip function division table;

[0081] Based on the interconnection density distribution diagram, initial position allocation is performed on the multiple thinned memory dies to obtain an initial arranged chip array;

[0082] Based on the chip function division table, hierarchical division is performed on the initial arranged chip array to obtain a hierarchical chip array;

[0083] The position arrangement of each layer of chips in the hierarchical chip array is controlled by a preset high-precision robotic arm through a space-filling curve algorithm to obtain an arranged chip array.

[0084] Specifically, the complex and precise process of "arranging the positions of multiple thinned memory dies based on the preset chip layout diagram to obtain an arranged chip array" described above includes multiple interrelated steps, which together ensure that the final chip array not only has high-density interconnection, but also can be reasonably distributed according to functional requirements. Specifically, the whole process starts with the analytical algorithm, and the interconnection density distribution map and the chip function division table are generated by parsing the inter-layer interconnection path of the preset chip layout diagram. These two results will provide important guidance information for subsequent position allocation and hierarchical division. First, the analytical algorithm is introduced in this process, the purpose of which is to analyze and optimize the electrical connection method between each layer in the multi-layer stacking structure. Through the algorithm, the interconnection density in different areas can be calculated by deeply parsing the preset chip layout diagram, and the interconnection density distribution map can be drawn accordingly. At the same time, the analytical algorithm will also identify the functional characteristics of each memory die, and then form a chip function division table. For example, when manufacturing high-speed solid-state drives (SSDs) for data center servers, engineers will use this analytical algorithm to determine which areas require more interconnection to support high-frequency data transmission, and which parts can use lower interconnection density to save space. In addition, the chip function partition table can help clarify the specific tasks of each die, such as some dies are dedicated to data reading, while others are responsible for writing operations or executing control logic. With the interconnection density distribution map and the chip function partition table, the next step is to make initial position allocation based on the former. At this stage, technicians will make preliminary position arrangements for multiple thinned storage dies based on the information in the interconnection density distribution map to form the so-called initial arrangement chip array. The key here is to try to concentrate the interconnection dense areas in places where efficient connections can be easily achieved, reduce signal transmission delays and improve overall performance. For example, in the process of building an SSD, those dies that need to communicate frequently may be placed together first to facilitate the subsequent implementation of the three-dimensional through-hole interconnection process. After completing the initial arrangement, the initial arrangement chip array is divided into levels based on the chip function partition table to obtain a layered chip array. This link aims to further refine the role of each die in the entire system and ensure that dies with the same or similar functions can work together at the same level. For example, in a multi-layer stacked SSD design, all the dies used for data caching may be placed at the bottom layer because they usually need to interact directly with external interfaces; higher layers may contain more dies involved in data processing and management. Such a hierarchical division not only helps to simplify the internal architecture, but also improves the modularity of the system, making it easier to maintain and upgrade. Finally, when the layered chip array is determined, it is necessary to use a space filling curve algorithm to accurately control the preset high-precision robotic arm to arrange the final position of each layer of chips, thereby obtaining an arranged chip array.A space-filling curve is a mathematical model that can effectively traverse every point within a two-dimensional or three-dimensional space, ensuring that no corner is missed. In actual operation, this means that the robotic arm can accurately place each stored die at the designated position according to a predefined path, maintaining a high degree of consistency and accuracy even in a very limited space. For example, in SSD manufacturing, in this way, even the slightest deviation can be guaranteed not to affect the quality and performance of the finished product. The final formed array of arranged chips not only achieves efficient interconnection and reasonable functional partitioning but also lays a solid foundation for subsequent processes such as bonding, cutting, and interconnection, promoting the development of high-performance storage solutions. In summary, this series of steps are closely linked and jointly act on constructing a multilayer stacked memory that is both compact and efficient. From the initial design and planning to the final actual arrangement, each link is to ensure that the final product can meet strict performance indicators while also meeting the requirements of modern information technology for large-capacity and high-speed storage.

[0085] In a specific embodiment, the step of performing bonding surface alignment on each target storage die in the arranged chip array through a high-precision alignment device to obtain an aligned chip array includes:

[0086] Performing dual-wavelength optical interference measurement on the arranged chip array to obtain chip surface profile data;

[0087] Extracting edge features from the chip surface profile data through a sub-pixel edge detection algorithm to obtain a chip edge feature map;

[0088] Performing six-degree-of-freedom pose analysis on each target storage die in the arranged chip array based on the chip edge feature map to obtain chip spatial pose data;

[0089] Through a piezoelectric nano-displacement platform, performing real-time closed-loop feedback control on the chip spatial pose data to obtain a set of displacement compensation parameters; wherein, the set of displacement compensation parameters includes X-Y plane displacement amounts, Z-axis height errors, and angle correction values;

[0090] Generating a preset alignment execution instruction sequence for multi-axis linkage control within a high-precision alignment device based on the set of displacement compensation parameters;

[0091] Controlling the high-precision alignment device to perform bonding surface alignment on each target storage die in the arranged chip array through the alignment execution instruction sequence to obtain an aligned chip array.

[0092] Specifically, in the process of "bonding surface alignment of each target storage die in the arranged chip array by the high-precision alignment device to obtain an aligned chip array" described above, a series of precise technical steps are involved to ensure that each storage die in the multi-layer stacked structure can be accurately aligned with other layers. First, by performing dual-wavelength optical interference measurement on the arranged chip array, chip surface profile data can be obtained, which is the basis for achieving high-precision alignment. Dual-wavelength optical interference measurement is an advanced optical measurement technology that uses two light sources with different wavelengths to detect subtle height changes on the object surface, thereby generating a three-dimensional image with high height resolution. For example, when manufacturing high-speed solid-state drives (SSDs) for data center servers, engineers use this technology to obtain detailed surface information of each NAND flash die, including any minor undulations or irregular shapes. Next, in order to further process these surface profile data, a sub-pixel edge detection algorithm is adopted to extract edge features, and finally a chip edge feature map is formed. This process can be understood as screening out key information points from a large amount of raw data, that is, the data that defines the boundaries and important geometric features of each die. The sub-pixel edge detection algorithm can identify and mark edge positions that are finer than a single pixel, which helps to improve the accuracy of subsequent analysis. For example, in the process of constructing an SSD, in this way, the outer edges of each die can be accurately captured, and even if the differences between them are extremely small, they can be clearly presented. The chip edge feature map not only provides an intuitive visual reference but also lays the foundation for the next pose analysis. Based on the obtained chip edge feature map, technicians can perform six-degree-of-freedom pose analysis on each target storage die in the arranged chip array, and then obtain chip spatial pose data. The six degrees of freedom mentioned here refer to the three translational directions of X, Y, and Z and the rotation angles around these three axes. Through such analysis, the exact position and orientation of each die in three-dimensional space can be determined, which is crucial for ensuring their correct alignment in the subsequent bonding process. For example, in SSD manufacturing, even the slightest angular deviation may lead to bonding failure or affect the performance of the finished product, so precise calculation tools are needed to evaluate and correct the spatial pose of each die. Once the chip spatial pose data is obtained, real-time closed-loop feedback control needs to be performed on it to achieve precise position adjustment. This step depends on a piezoelectric nano-displacement platform, which can provide sub-nanometer displacement accuracy and can respond quickly according to the input signal. Specifically, by analyzing the chip spatial pose data, a series of displacement compensation parameter sets can be obtained, and these parameter sets include X-Y plane displacement amounts, Z-axis height errors, and angle correction values. This means that for each die, the distance and direction it needs to move can be calculated to achieve the ideal alignment state.After receiving these instructions, the piezoelectric nano-displacement stage will perform corresponding actions within an extremely short period of time, enabling the die to be finely adjusted according to the predetermined requirements. Finally, based on the above-generated set of displacement compensation parameters, engineers will compile a sequence of alignment execution instructions for multi-axis linkage control within a preset high-precision alignment device. These instruction sequences specify in detail how to coordinate the actions of different axes to ensure that all target storage dies can complete the bonding surface alignment synchronously. Through the control of the alignment execution instruction sequence, the high-precision alignment device will precisely adjust the position of each die until they fully meet the design requirements. For example, in SSD manufacturing, when all NAND flash dies are successfully aligned, a so-called aligned chip array is formed. This integrated structure not only has good mechanical stability but also provides a solid foundation for subsequent thermocompression bonding and other processing steps. The entire process demonstrates a series of complex and precise technical means from data acquisition to the final alignment operation, ensuring the high performance and reliability of the multi-layer stacked memory and meeting the requirements of modern information technology for high-performance storage solutions. In summary, through the above series of carefully designed and technically implemented steps, not only is the highly precise bonding surface alignment between individual target storage dies achieved, but also the production efficiency and product quality are greatly improved. This method is particularly suitable for application scenarios that require strict alignment accuracy, such as high-speed solid-state drives (SSDs) in data center servers, and the result is a significant enhancement of the overall performance and reliability of the system, promoting the development of the information technology field.

[0093] In a specific embodiment, the operation of thermocompression bonding the aligned chip array to obtain a bonded chip stack includes:

[0094] Performing a preheating process on the aligned chip array through a preset temperature curve to obtain a preheated chip array, and performing a simulation of the temperature field distribution in the bonding region of the preheated chip array to obtain temperature field distribution data;

[0095] Setting parameters for a preset thermocompression bonding device based on the temperature field distribution data to obtain set parameters, and performing real-time temperature monitoring and feedback control on the set parameters to obtain a temperature control curve;

[0096] Using the thermocompression bonding technology, performing a thermocompression bonding operation on the aligned chip array through a set pressure curve and the temperature control curve to obtain an initial bonded chip stack, and performing a stress analysis of the bonding interface of the initial bonded chip stack to obtain stress distribution data;

[0097] Performing an ultrasonic-assisted bonding process on the bonding interface in the aligned chip array based on the stress distribution data to obtain a strengthened bonded chip stack, and performing a bonding strength test on the strengthened bonded chip stack to obtain bonding strength data;

[0098] Through the vacuum annealing process technology, residual stress elimination is performed on the strengthened bonded chip stack based on the bond strength data to obtain a bonded chip stack.

[0099] Specifically, in the process of "performing a thermocompression bonding operation on the aligned chip array using the thermocompression bonding technique to obtain a bonded chip stack", multiple precise and interrelated technical steps are involved, ensuring that each memory die in the multi-layer stacked structure can be firmly connected together. The entire process starts from preheating treatment and ends with the final elimination of residual stress. Each step is crucial and jointly ensures the quality and performance of the finished product. First of all, to ensure the success of the thermocompression bonding operation, the aligned chip array needs to be preheated through a preset temperature curve to obtain a preheated chip array. This step aims to make each die reach a uniform and suitable initial temperature for bonding, so as to avoid stress concentration or material damage caused by excessive temperature gradient. For example, when manufacturing high-speed solid-state drives (SSDs) for data center servers, engineers will adjust the preheating curve according to specific material characteristics to ensure that the silicon-based NAND flash dies are in the best state before entering the formal bonding process. At the same time, to evaluate the preheating effect, technicians will perform a simulation of the temperature field of the bonding area on the preheated chip array to obtain temperature field distribution data. This simulation analysis not only provides an intuitive view of the temperature distribution but also helps to identify possible hot or cold spots, providing a basis for subsequent parameter setting. Based on the above-obtained temperature field distribution data, the next step is to set the parameters of the preset thermocompression bonding equipment to obtain set parameters, and perform real-time temperature monitoring and feedback control on these set parameters to form a temperature control curve. This step is crucial because it directly relates to the consistency and stability of the temperature during the bonding process. For example, in SSD manufacturing, by precisely setting the parameters of the thermocompression bonding equipment, such as the heating rate and holding time, and combining real-time monitoring and feedback control systems, it can be ensured that the temperature remains within the ideal range throughout the bonding process. The temperature control curve not only reflects the temperature change situation in actual operation but also provides a guarantee for the subsequent bonding quality, avoiding adverse effects caused by temperature fluctuations. Once the temperature control curve is determined, the thermocompression bonding technique can be used to perform a thermocompression bonding operation on the aligned chip array through the set pressure curve and temperature control curve to obtain an initial bonded chip stack. At this stage, the design of the pressure curve is also crucial, which determines the pressure distribution on the contact surface between different layers, thus affecting the bonding effect. For example, in SSD manufacturing, appropriate pressure can promote atomic-level diffusion at the interface to form a solid chemical bond; while excessive pressure may cause material deformation or damage. To further optimize the bonding effect, technicians will perform a stress analysis of the bonding interface on the initial bonded chip stack to obtain stress distribution data. These data not only reveal the specific stress conditions of the bonding interface but also provide a scientific basis for subsequent improvement. Based on the above-obtained stress distribution data, the next step is to perform ultrasonic-assisted bonding treatment on the bonding interface in the aligned chip array to obtain a strengthened bonded chip stack.Ultrasonic-assisted bonding is a method that uses high-frequency vibration energy to enhance the bonding strength. It can effectively reduce the voids between interfaces and increase the contact area, thereby enhancing the firmness of the bond. For example, in SSD manufacturing, ultrasonic-assisted bonding can significantly improve the quality of the bonding interface without increasing additional pressure. After ultrasonic-assisted bonding treatment, it is also necessary to test the bonding strength of the strengthened bonded chip stack to obtain bonding strength data. These test results not only verify whether the bonding effect meets the expected standards but also provide important references for subsequent process adjustments. Finally, in order to eliminate the stress that may remain during the bonding process, it is necessary to process the strengthened bonded chip stack through a vacuum annealing process technology to obtain the final bonded chip stack. Vacuum annealing is a process of heating and slowly cooling materials in a low-pressure environment, which can effectively release internal stress and improve the physical properties of materials. For example, in SSD manufacturing, vacuum annealing can eliminate the tiny stress generated during the bonding process and ensure that the finished product will not experience performance degradation or failures due to stress accumulation during long-term use. The vacuum annealing process design based on the bonding strength data makes the entire bonding process more perfect and reliable. In summary, this series of carefully designed and technically implemented steps not only achieve highly precise bonding of the aligned chip array but also greatly improve production efficiency and product quality. This method is particularly suitable for application scenarios that require strict bonding accuracy, such as high-speed solid-state drives (SSDs) in data center servers, and the result is a significant enhancement of the overall performance and reliability of the system, promoting the development of the information technology field. Through the above series of operations, it is ensured that the finished product not only has excellent electrical performance but also can operate stably in various working environments, fully meeting the ever-developing needs of modern information technology.

[0100] In a specific embodiment, the edge cutting of the bonded chip stack using the femtosecond laser micromachining technology to obtain a cut chip stack includes:

[0101] Performing three-dimensional X-ray tomography on the bonded chip stack to obtain a stack structure image, and planning a femtosecond laser scanning path based on the stack structure image to obtain a laser scanning path map;

[0102] Performing thermal effect simulation analysis on the laser scanning path map to obtain thermal influence area distribution data, and setting the parameters of a preset femtosecond laser based on the thermal influence area distribution data to obtain laser processing parameters;

[0103] Controlling the femtosecond laser to perform femtosecond laser cutting on the bonded chip stack based on the laser processing parameters to obtain a rough cut chip stack, and characterizing the morphology of the cut edge of the rough cut chip stack to obtain cut edge morphology data;

[0104] Performing plasma-assisted etching on the rough-cut chip stack based on the cutting edge topography data to obtain a fine-cut chip stack;

[0105] Performing chemical mechanical polishing and edge cutting on the fine-cut chip stack to obtain a cut chip stack.

[0106] Specifically, in the process of "using femtosecond laser micromachining technology to perform edge cutting on the bonded chip stack to obtain a cut chip stack" described above, a series of precise technical steps are involved, aiming to ensure that the cutting process is both efficient and does not damage the internal structure of the chips. The entire process starts from three-dimensional X-ray tomography and finally achieves chemical mechanical polishing cutting. Each step is closely linked to jointly ensure the quality and performance of the finished product. First, in order to accurately plan the scanning path of the femtosecond laser, three-dimensional X-ray tomography of the bonded chip stack is required to obtain a detailed image of the stacking structure. This technology can provide a high-resolution view of the internal structure, enabling engineers to clearly understand the position, number of layers, and possible subtle defects of each die. For example, when manufacturing high-speed solid-state drives (SSDs) for data center servers, this imaging technology can identify which areas need to be handled with special care to avoid any unnecessary damage caused by cutting. Based on these stacking structure images, technicians can develop an optimized femtosecond laser scanning path map to ensure that the cutting path covers all the edges that need to be cut without accidentally damaging the internal circuits. Next, in order to evaluate the possible thermal effects during the cutting process, a thermal effect simulation analysis is required for the planned laser scanning path map to obtain the distribution data of the thermally affected area. This step is crucial because it helps determine which areas may be at risk of material deformation or damage due to high temperatures. According to the simulation results, engineers will adjust the preset femtosecond laser parameters to set the most suitable laser processing parameters. These parameters include but are not limited to laser pulse energy, frequency, focal spot size, etc., aiming to minimize the thermally affected zone while ensuring cutting efficiency and protecting sensitive components from damage. For example, in SSD manufacturing, this way can ensure that the temperature change during the cutting process remains within a safe range and does not affect the storage performance. Once the laser processing parameters are determined, the femtosecond laser can be controlled to perform actual cutting on the bonded chip stack according to the predetermined path to obtain a roughly cut chip stack. At this stage, the main goal of cutting is to remove the excess material and form a rough edge profile. However, although femtosecond laser cutting has high precision, there may still be slight irregularities or rough surfaces, so further processing is required. In order to evaluate the cutting effect, technicians will perform cutting edge morphology characterization on the roughly cut chip stack to obtain cutting edge morphology data. These data not only provide intuitive visual feedback but also provide a basis for subsequent improvement. For example, in SSD manufacturing, by checking the smoothness and flatness of the cutting edge, it can be determined whether the laser parameters need to be adjusted or the cutting path needs to be optimized. Based on the obtained cutting edge morphology data above, the next step is to perform plasma-assisted etching on the roughly cut chip stack to achieve a more refined cutting effect.Plasma-assisted etching is a method that uses plasma to chemically react with the material surface to remove excess substances. It can further improve the quality of the cutting edge without damaging the internal structure of the chip. For example, in SSD manufacturing, this method can effectively remove the tiny burrs or protrusions remaining after femtosecond laser cutting, making the cutting edge smoother. After plasma-assisted etching treatment, a finely cut chip stack is obtained, and its edge is already very close to the final ideal state. Finally, in order to ensure that the cutting edge fully meets the design requirements and has good electrical and physical properties, chemical mechanical polishing cutting is required for the finely cut chip stack. Chemical mechanical polishing (CMP) is a process that combines chemical etching and mechanical grinding. It can eliminate the fine unevenness on the surface and endow the cutting edge with extremely high smoothness. For example, in SSD manufacturing, chemical mechanical polishing cutting can not only make the cutting edge look perfect, but also significantly improve the uniformity and reliability of the contact resistance. The finally formed cutting chip stack not only has a beautiful appearance, but more importantly, it has excellent electrical performance, providing a solid foundation for subsequent processes such as three-dimensional through-hole interconnection. In summary, this series of carefully designed and technically implemented steps not only achieve precise edge cutting of the bonded chip stack, but also greatly improve production efficiency and product quality. This method is particularly suitable for application scenarios that require strict cutting accuracy, such as high-speed solid-state drives (SSDs) in data center servers. The result is a significant enhancement of the overall performance and reliability of the system, promoting the development of the information technology field. Through the above series of operations, it is ensured that the finished product not only has excellent electrical performance, but also can operate stably in various working environments, fully meeting the ever-developing needs of modern information technology.

[0107] In a specific embodiment, the metal filling interconnection of the cutting chip stack by the micro-spacing interconnection technology to obtain an interconnected chip stack includes:

[0108] Based on a preset interconnection circuit diagram, the through-hole position of the cutting chip stack is planned to obtain a through-hole position distribution diagram, and electromagnetic field simulation analysis is performed on the through-hole position distribution diagram to obtain electromagnetic interference distribution data;

[0109] Through femtosecond laser ablation technology, based on the electromagnetic interference distribution data, blind hole machining is performed on the cutting chip stack to obtain a blind hole chip stack, and the blind hole depth of the blind hole chip stack is measured to obtain blind hole depth data;

[0110] Based on the blind hole depth data, deep silicon etching process treatment is performed on the blind hole chip stack to obtain a through-hole chip stack, and the sidewall roughness of the through-hole chip stack is analyzed to obtain sidewall roughness data;

[0111] Using the selective atomic layer deposition technique, an insulating layer is deposited on the through-hole chip stack based on the sidewall roughness data and the through-hole depth data to obtain an insulating coating chip stack, and the thickness uniformity of the insulating layer of the insulating coating chip stack is calculated to obtain thickness uniformity data;

[0112] Based on the thickness uniformity data, a planarization process is performed on the insulating coating chip stack to obtain a planarized chip stack;

[0113] The planarized chip stack is filled with metal by electrochemical deposition technology to obtain an interconnected chip stack.

[0114] Specifically, in the process of "performing metal filling interconnection on the diced chip stack by micro-pitch interconnection technology to obtain an interconnected chip stack" described above, it involves multiple precise and interrelated technical steps, ensuring efficient and stable electrical connections between different levels inside the multi-layer stacked memory. The whole process starts from the via position planning of the diced chip stack based on a preset interconnection circuit diagram and ends with the final completion of metal filling interconnection. Each step is crucial and jointly ensures the quality and performance of the finished product. First of all, in order to ensure the rationality and optimal distribution of via positions, it is necessary to perform a detailed via position planning on the diced chip stack based on a preset interconnection circuit diagram, so as to obtain a via position distribution map. This step not only takes into account the electrical connection requirements between individual dies, but also must consider factors such as the stability of the overall structure and heat dissipation performance. For example, when manufacturing high-speed solid-state drives (SSDs) for data center servers, engineers will determine which areas require more vias to support high-frequency data transmission according to the specific interconnection design, and which parts can use a lower interconnection density to save space. At the same time, in order to evaluate the potential electromagnetic interference problems brought by these vias, technicians will perform electromagnetic field simulation analysis on the via position distribution map to obtain electromagnetic interference distribution data. This kind of simulation analysis helps to identify potential interference sources and take measures in advance to avoid them, such as adjusting the via layout or optimizing the interconnection path, etc., so as to improve the reliability and anti-interference ability of the system. After obtaining the via position distribution map and electromagnetic interference distribution data, the next step is to use femtosecond laser ablation technology to perform blind hole processing on the diced chip stack to form a so-called blind hole chip stack. Femtosecond laser ablation is an extremely precise material removal method. It can release a huge amount of energy in an extremely short time, instantly melting or vaporizing the material surface. At the same time, due to the extremely short action time, the generated heat hardly transfers to the surrounding materials, avoiding the common thermal damage problems in traditional drilling methods. For example, in SSD manufacturing, femtosecond laser ablation can precisely form tiny and uniform blind holes at specified positions, ensuring the quality of subsequent interconnection processes. In order to ensure that each blind hole can reach the expected depth, it is also necessary to measure the blind hole depth to obtain blind hole depth data. These data are not only important references for subsequent deep silicon etching processes, but also directly related to the final interconnection effect. Based on the above-obtained blind hole depth data, the next step is to perform deep silicon etching process on the blind hole chip stack to form a through-hole chip stack. Deep silicon etching is a high-precision material removal technology. It can further penetrate along the pre-formed blind holes until it penetrates the entire chip stack, forming through-holes that penetrate through each layer. This process is crucial for ensuring reliable electrical connections between different levels. For example, in SSD manufacturing, the deep silicon etching process can create low-resistance conductive paths, thereby reducing signal transmission delay and improving the overall performance.To evaluate the quality of the vias, it is also necessary to perform roughness analysis on the sidewalls of the vias to obtain sidewall roughness data. The smoothness of the sidewalls directly affects the effect of subsequent insulation layer deposition, so it must be strictly controlled. Once the sidewall roughness data of the vias is obtained, selective atomic layer deposition (ALD) technology is needed to deposit an insulation layer on the via chip stack to form an insulated coated chip stack. Selective atomic layer deposition is a technology that can precisely control the film thickness at the nanoscale. It can uniformly deposit a thin layer of insulating material, such as silicon dioxide or other high-performance insulating materials, on the sidewalls of the vias. For example, in SSD manufacturing, ALD technology can ensure that each via sidewall is covered with a dense and uniform insulation layer to prevent current leakage or short-circuit phenomena. To verify the quality of the insulation layer, it is also necessary to calculate the thickness uniformity of the insulation layer to obtain thickness uniformity data. These data not only provide intuitive visual feedback but also provide a basis for subsequent planarization processes. Based on the thickness uniformity data obtained above, the next step is to perform a planarization process on the insulated coated chip stack to form a planarized chip stack. The planarization process aims to eliminate the fine unevenness on the surface and endow the chip stack with extremely high smoothness. For example, in SSD manufacturing, methods such as chemical mechanical polishing (CMP) can make the surface of the insulation layer smoother, providing ideal conditions for subsequent metal filling interconnects. The quality of planarization is directly related to the final interconnect effect, so every detail must be ensured to meet the design requirements. Finally, electrochemical deposition technology is used to perform metal filling interconnects on the planarized chip stack to obtain an interconnected chip stack. Electrochemical deposition is a method of reducing metal ions to metal atoms and depositing them on the electrode surface. It can arrange a large number of interconnect lines in a very small space, greatly increasing the connection density per unit area. For example, in SSD manufacturing, metal materials such as copper or tungsten can be uniformly filled into each via through electrochemical deposition to form a low-resistance conductive path. This method not only reduces the occupied space but also enhances the system's integration and reliability. The finally formed interconnected chip stack not only has higher integration and faster data transfer speed but also significantly enhances the system's reliability and durability. In summary, this series of carefully designed and technically implemented steps not only achieve efficient and stable electrical connections between different layers inside the diced chip stack but also greatly improve production efficiency and product quality. This method is particularly suitable for application scenarios that require strict interconnect accuracy, such as high-speed solid-state drives (SSDs) in data center servers. The result is a significant enhancement of the overall performance and reliability of the system, promoting the development of the information technology field. Through the above series of operations, it is ensured that the finished product not only has excellent electrical performance but also can operate stably in various working environments, fully meeting the ever-developing needs of modern information technology.

[0115] In a specific embodiment, the heterogeneous integration packaging technology is used to perform vacuum resin packaging on the interconnected chip stack to obtain a target packaged memory chip stack structure, including:

[0116] Perform a three-dimensional structure scan on the interconnected chip stack to obtain three-dimensional structure data, and design the structure of the packaging cavity of the interconnected chip stack based on the three-dimensional structure data to obtain a packaging cavity model;

[0117] Perform vacuum resin pouring packaging on the packaging cavity model by using the heterogeneous integration packaging technology to obtain a resin-filled chip stack, and perform filling uniformity detection on the resin-filled chip stack to obtain resin filling uniformity data;

[0118] Perform ultraviolet curing on the resin-filled chip stack based on the resin filling uniformity data to obtain a cured resin chip stack, and perform curing degree detection on the cured resin chip stack to obtain curing degree data;

[0119] When the curing degree data reaches a preset curing degree range, then perform laser demolding on the cured resin chip stack through a preset femtosecond laser precision control system to obtain a demolded chip stack;

[0120] Perform plasma cleaning on the demolded chip stack to obtain a cleaned chip stack, and perform external lead connection on the cleaned chip stack through wire bonding technology to obtain a target packaged memory chip stack structure.

[0121] Specifically, in the process of "using heterogeneous integration packaging technology to perform vacuum resin packaging on the interconnected chip stack to obtain the target packaged memory chip stack structure" described above, it involves multiple precise and interrelated technical steps, ensuring that the multi-layer stacked memory not only has high performance but also excellent reliability and environmental adaptability. The entire process starts from three-dimensional structure scanning and ends with the final external lead connection. Each step is crucial and jointly guarantees the quality and performance of the finished product. First, in order to accurately design the packaging cavity suitable for the interconnected chip stack, it is necessary to perform three-dimensional structure scanning on it to obtain detailed three-dimensional structure data. This technology uses high-resolution imaging equipment to capture every detail of the chip stack, including its external dimensions, internal via distribution, and the relative positions between layers. For example, when manufacturing high-speed solid-state drives (SSDs) for data center servers, engineers use this scanning method to comprehensively understand the specific layout and connection methods of each NAND flash die. Based on these three-dimensional structure data, technicians can further design the structure of the packaging cavity for the interconnected chip stack to form a packaging cavity model. This step not only takes into account the physical characteristics of the chip stack itself but also must consider factors such as heat dissipation and shock resistance to ensure that the packaged device can operate stably under various working conditions. Next, by using heterogeneous integration packaging technology to perform vacuum resin potting on the packaging cavity model, a resin-filled chip stack is obtained. Heterogeneous integration packaging technology allows chips with different functions or process nodes, such as logic control units and memory units, to be integrated within the same package, thereby improving the system integration and simplifying the subsequent design and assembly processes. In actual operation, vacuum resin potting is to inject a specific type of resin material into the pre-designed packaging cavity under a high-vacuum environment and let it cure to form a solid whole. This material can not only provide physical protection to prevent external contaminants such as dust and moisture from invading but also effectively reduce the stress caused by temperature changes and extend the service life of the device. To ensure the packaging quality, it is also necessary to detect the filling uniformity of the resin-filled chip stack to obtain filling uniformity data. These data not only provide intuitive visual feedback but also provide important references for subsequent processing. For example, in SSD manufacturing, uniform resin filling helps maintain the consistency and stability of the internal circuit. Once the filling uniformity data of the resin-filled chip stack is obtained, it is necessary to perform ultraviolet curing on the resin-filled chip stack to obtain a cured resin chip stack. Ultraviolet curing is a fast and efficient material hardening method. It makes the resin undergo a chemical reaction through the irradiation of ultraviolet light with a specific wavelength and quickly turns into a hard solid state. To ensure the curing effect, technicians will detect the curing degree of the cured resin chip stack to obtain curing degree data. These data are directly related to the mechanical strength and electrical performance of the packaged device, so they must be strictly controlled.For example, in SSD manufacturing, an appropriate degree of curing can ensure that the resin can firmly fix the internal structure without causing any damage to it. When the curing degree data reaches the preset curing degree range, it means that the encapsulation has reached the expected quality standard. Next, a femtosecond laser precision control system is used to perform laser demolding on the cured resin chip stack to obtain a demolded chip stack. The femtosecond laser precision control system can release a huge amount of energy in an extremely short time, accurately cutting or peeling off the excess material. At the same time, due to the extremely short action time, the generated heat hardly transfers to the surrounding materials, avoiding the common thermal damage problems in traditional cutting methods. For example, in SSD manufacturing, the femtosecond laser can accurately remove the excess resin at the edge of the encapsulation, enabling the chip stack to be smoothly removed from the mold without affecting its internal structure. The demolding process not only improves production efficiency but also creates favorable conditions for subsequent processes. Finally, in order to ensure that the encapsulated chip stack has good electrical connection performance, it needs to be subjected to plasma cleaning to obtain a clean chip stack. Plasma cleaning is a method that uses plasma to react chemically with the material surface to remove minute impurities, which can significantly improve the surface cleanliness and flatness. For example, in SSD manufacturing, in this way, possible residual particulate matter or organic pollutants can be removed, providing an ideal contact surface for wire bonding. After the cleaning is completed, technicians will perform external lead connection on the clean chip stack through wire bonding technology to obtain the target encapsulated memory chip stack structure. Wire bonding is a process of connecting a fine metal wire between the pads on the chip and the external pins to achieve electrical connection. This method can not only ensure the reliability of signal transmission but also reserve sufficient space for future system upgrades and expansions. In summary, this series of carefully designed and technically implemented steps not only achieve the efficient encapsulation of the interconnected chip stack but also greatly improve production efficiency and product quality. This method is particularly suitable for application scenarios that require strict encapsulation accuracy, such as high-speed solid-state drives (SSDs) in data center servers. As a result, the overall performance and reliability of the system are significantly enhanced, promoting the development of the information technology field. Through the above series of operations, it is ensured that the finished product not only has excellent electrical performance but also can operate stably in various working environments, fully meeting the ever-developing needs of modern information technology.

[0122] The above describes the chip interconnection method for the multi-layer stacked memory encapsulation structure in the embodiments of the present invention. Next, the chip interconnection device for the multi-layer stacked memory encapsulation structure in the embodiments of the present invention will be described. Please refer to Figure 2 , an embodiment of the chip interconnection device for the multi-layer stacked memory encapsulation structure in the embodiments of the present invention includes:

[0123] The arranging module 21 is configured to arrange a plurality of thinned memory dies based on a preset chip layout diagram to obtain an arranged chip array;

[0124] The alignment module 22 is configured to align the bonding surfaces of the target memory dies in the arranged chip array through a high-precision alignment device to obtain an aligned chip array;

[0125] The thermocompression module 23 is configured to perform thermocompression bonding operations on the aligned chip array by using thermocompression bonding technology to obtain a bonded chip stack;

[0126] The cutting module 24 is configured to perform edge cutting on the bonded chip stack by using femtosecond laser micromachining technology to obtain a cut chip stack;

[0127] The interconnection module 25 is configured to perform three-dimensional through-hole interconnection on the cut chip stack by using micro-pitch interconnection technology to obtain an interconnected chip stack;

[0128] The packaging module 26 is configured to perform vacuum resin packaging on the interconnected chip stack by using heterogeneous integration packaging technology to obtain a target packaged memory chip stack structure.

[0129] In this embodiment, for the specific implementation of each unit in the above device embodiment, please refer to that described in the above method embodiment, and details are not described herein again.

[0130] Refer to Figure 3 , in the embodiment of the present invention, a computer device is further provided. The internal structure of the computer device may be as Figure 3 shown. The computer device includes a processor, a memory, a display screen, an input device, a network interface, and a database connected through a system bus. Among them, the processor of the computer design is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the corresponding data in this embodiment. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the above method is implemented.

[0131] Those skilled in the art can understand that Figure 3 the structure shown in

[0132] An embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the above method is implemented. It can be understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0133] Those of ordinary skill in the art can understand that all or part of the processes of implementing the methods in the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the above method embodiments. Among them, any reference to a memory, storage, database, or other medium provided by the present invention and used in the embodiments can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM, etc.

[0134] It should be noted that in this article, the terms "including", "comprising", or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, apparatus, article, or method including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such a process, apparatus, article, or method. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, apparatus, article, or method including that element.

[0135] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent structural or equivalent process transformation made by using the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. A chip interconnection method for a multi-layer stacked memory packaging structure, characterized in that: The following steps are involved: Arranging the positions of the plurality of thinned memory dies based on a preset chip layout diagram to obtain an arranged chip array; Aligning the bonding surfaces of the target storage dies in the arranged chip array by a high-precision alignment device to obtain an aligned chip array; Performing a thermal compression bonding operation on the alignment chip array using a thermal compression bonding technology to obtain a bonded chip stack; Using femtosecond laser micromachining technology to perform edge cutting on the bonded chip stack to obtain a cut chip stack; Performing metal filling interconnection on the cut chip stack by a micro-pitch interconnection technology to obtain an interconnected chip stack; Using heterogeneous integrated packaging technology to perform vacuum resin packaging on the interconnected chip stack to obtain a target packaged memory chip stack structure; The preset chip layout diagram is analyzed for inter-layer interconnection paths by using a preset analysis algorithm to obtain an interconnection density distribution diagram and a chip function division table; Performing initial position allocation for the plurality of thinned memory dies based on the interconnection density distribution map to obtain an initial arrangement chip array; Based on the chip function division table, the initially arranged chip array is divided into layers to obtain a layered chip array; Controlling a preset high-precision robotic arm through a space filling curve algorithm to arrange the positions of each layer of chips in the layered chip array to obtain an arranged chip array; Performing through-hole position planning on the cut chip stack based on a preset interconnection circuit diagram to obtain a through-hole position distribution map, and performing electromagnetic field simulation analysis on the through-hole position distribution map to obtain electromagnetic interference distribution data; Performing blind hole processing on the cut chip stack based on the electromagnetic interference distribution data by femtosecond laser ablation technology to obtain a blind hole chip stack, and measuring the blind hole depth of the blind hole chip stack to obtain blind hole depth data; Based on the blind hole depth data, the blind hole chip stack is subjected to a deep silicon etching process to obtain a through hole chip stack, and a through hole side wall roughness analysis is performed on the through hole chip stack to obtain side wall roughness data; Depositing an insulating layer on the through-hole chip stack based on the sidewall roughness data and the through-hole depth data by a selective atomic layer deposition technique to obtain an insulating coating chip stack, and calculating the thickness uniformity of the insulating layer on the insulating coating chip stack to obtain thickness uniformity data; Performing a planarization process on the insulating coating chip stack based on the thickness uniformity data to obtain a planarized chip stack; The planarized chip stack is metal-filled and interconnected by electrochemical deposition technology to obtain an interconnected chip stack.

2. The chip interconnection method of the multi-layer stacked memory package structure according to claim 1, characterized in that: The step of aligning the bonding surfaces of the target storage dies in the arranged chip array by a high-precision alignment device to obtain an aligned chip array includes: Performing dual-wavelength light interference measurement on the arranged chip array to obtain chip surface profile data; Extracting edge features from the chip surface contour data using a sub-pixel edge detection algorithm to obtain a chip edge feature map; Based on the chip edge feature map, a six-degree-of-freedom posture analysis is performed on each of the target storage dies in the arranged chip array to obtain chip spatial posture data; Through the piezoelectric nano-displacement platform, the spatial position data of the chip is subjected to real-time closed-loop feedback control to obtain a displacement compensation parameter set; wherein the displacement compensation parameter set includes XY plane displacement, Z axis height error and angle correction value; Generate a preset alignment execution instruction sequence of multi-axis linkage control in a high-precision alignment device based on the displacement compensation parameter set; The alignment execution instruction sequence is used to control the high-precision bonding surface alignment of each target storage die in the arranged chip array to obtain an aligned chip array.

3. The chip interconnection method of the multi-layer stacked memory package structure according to claim 1, characterized in that: The method of using a thermal compression bonding technology to perform a thermal compression bonding operation on the alignment chip array to obtain a bonded chip stack includes: Preheating the aligned chip array using a preset temperature curve to obtain a preheated chip array, and simulating the bonding area temperature field of the preheated chip array to obtain temperature field distribution data; Based on the temperature field distribution data, parameters of a preset thermal compression bonding device are set to obtain set parameters, and real-time temperature monitoring and feedback control are performed on the set parameters to obtain a temperature control curve; Using the thermal compression bonding technology, the alignment chip array is subjected to thermal compression bonding operation through the set pressure curve and the temperature control curve to obtain an initial bonded chip stack, and a bonding interface stress analysis is performed on the initial bonded chip stack to obtain stress distribution data; Based on the stress distribution data, an ultrasonic-assisted bonding process is performed on the bonding interface in the alignment chip array to obtain a reinforced bonded chip stack, and a bonding strength test is performed on the reinforced bonded chip stack to obtain bonding strength data; The vacuum annealing process technology is used to eliminate residual stress of the reinforced bonded chip stack based on the bonding strength data to obtain a bonded chip stack.

4. The chip interconnection method of the multi-layer stacked memory package structure according to claim 1, characterized in that: The method of cutting the edges of the bonded chip stack using femtosecond laser micromachining technology to obtain a cut chip stack comprises: Performing three-dimensional X-ray tomography on the bonded chip stack to obtain a stacking structure image, and performing femtosecond laser scanning path planning based on the stacking structure image to obtain a laser scanning path diagram; Performing thermal effect simulation analysis on the laser scanning path diagram to obtain heat-affected zone distribution data, and setting parameters of a preset femtosecond laser based on the heat-affected zone distribution data to obtain laser processing parameters; Based on the laser processing parameters, the femtosecond laser is controlled to perform femtosecond laser cutting on the bonded chip stack to obtain a rough-cut chip stack, and a cutting edge morphology characterization is performed on the rough-cut chip stack to obtain cutting edge morphology data; Performing plasma-assisted etching on the rough-cut chip stack based on the cutting edge morphology data to obtain a fine-cut chip stack; The finely cut chip stack is subjected to chemical mechanical polishing and edge cutting to obtain a cut chip stack.

5. The chip interconnection method of the multi-layer stacked memory package structure according to claim 1, characterized in that: The method of using the heterogeneous integrated packaging technology to perform vacuum resin packaging on the interconnected chip stack to obtain a target packaged memory chip stack structure includes: Performing a three-dimensional structural scan on the interconnected chip stack to obtain three-dimensional structural data, and performing a structural design on the packaging cavity of the interconnected chip stack based on the three-dimensional structural data to obtain a packaging cavity model; The packaging cavity model is vacuum-sealed with resin by adopting heterogeneous integrated packaging technology to obtain a resin-filled chip stack, and a filling uniformity test is performed on the resin-filled chip stack to obtain resin filling uniformity data; Based on the resin filling uniformity data, ultraviolet curing is performed on the resin-filled chip stack to obtain a cured resin chip stack, and a curing degree detection is performed on the cured resin chip stack to obtain curing degree data; When the curing degree data reaches a preset curing degree range, the cured resin chip stack is laser demoulded by a preset femtosecond laser precision control system to obtain a demoulded chip stack; The demoulded chip stack is plasma cleaned to obtain a clean chip stack, and the clean chip stack is externally connected with wires by wire bonding technology to obtain a target packaged memory chip stack structure.

6. A chip interconnection device of a multi-layer stacked memory packaging structure, characterized in that: include: An arrangement module, used for arranging the positions of a plurality of thinned memory dies based on a preset chip layout diagram to obtain an arranged chip array; An alignment module, used for aligning the bonding surfaces of the target storage dies in the arranged chip array by means of a high-precision alignment device to obtain an aligned chip array; A thermal compression module, used for performing thermal compression bonding operation on the alignment chip array using thermal compression bonding technology to obtain a bonded chip stack; A cutting module, used for cutting the edges of the bonded chip stack using femtosecond laser micromachining technology to obtain a cut chip stack; An interconnection module, used to perform metal filling interconnection on the cut chip stack by a micro-pitch interconnection technology to obtain an interconnected chip stack; A packaging module, used to perform vacuum resin packaging on the interconnected chip stack using heterogeneous integrated packaging technology to obtain a target packaged memory chip stack structure; The preset chip layout diagram is analyzed for inter-layer interconnection paths by using a preset analysis algorithm to obtain an interconnection density distribution diagram and a chip function division table; Performing initial position allocation for the plurality of thinned memory dies based on the interconnection density distribution map to obtain an initial arrangement chip array; Based on the chip function division table, the initially arranged chip array is divided into layers to obtain a layered chip array; Controlling a preset high-precision robotic arm through a space filling curve algorithm to arrange the positions of each layer of chips in the layered chip array to obtain an arranged chip array; Performing through-hole position planning on the cut chip stack based on a preset interconnection circuit diagram to obtain a through-hole position distribution map, and performing electromagnetic field simulation analysis on the through-hole position distribution map to obtain electromagnetic interference distribution data; Performing blind hole processing on the cut chip stack based on the electromagnetic interference distribution data by femtosecond laser ablation technology to obtain a blind hole chip stack, and measuring the blind hole depth of the blind hole chip stack to obtain blind hole depth data; Based on the blind hole depth data, the blind hole chip stack is subjected to a deep silicon etching process to obtain a through hole chip stack, and a through hole side wall roughness analysis is performed on the through hole chip stack to obtain side wall roughness data; Depositing an insulating layer on the through-hole chip stack based on the sidewall roughness data and the through-hole depth data by a selective atomic layer deposition technique to obtain an insulating coating chip stack, and calculating the thickness uniformity of the insulating layer on the insulating coating chip stack to obtain thickness uniformity data; Performing a planarization process on the insulating coating chip stack based on the thickness uniformity data to obtain a planarized chip stack; The planarized chip stack is metal-filled and interconnected by electrochemical deposition technology to obtain an interconnected chip stack.

7. A computer device comprising a memory and a processor, wherein a computer program is stored in the memory, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 are implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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