Novel on-chip isolation transformer

Abstract

The invention belongs to the technical field of isolation, and particularly provides a novel on-chip isolation transformer which is used for solving the problems that the isolation capacity between coils is limited, parasitic capacitance between the coils is large, the manufacturing process is complex, and the manufacturing cost is high in an existing on-chip isolation transformer. The on-chip isolation transformer comprises a coil assembly and an isolation layer, the coil assembly is wrapped in the isolation layer, the coil assembly at least comprises a first inner side coil and a first outer side coil, the first inner side coil and the first outer side coil are both located on a first metal layer, the first outer side coil is arranged on the periphery of the first inner side coil, and the first metal layer is located on a second metal layer. A transverse interval is kept between the first outer side coil and the first inner side coil, and the transverse interval is filled with an isolation layer. According to the invention, the two coils of the isolation transformer are creatively arranged on the same graphical metal layer to form a structure of the outer coil and the inner coil, so that a large isolation distance is easy to realize, stray capacitance between the coils is smaller, the manufacturing process is simple, and the manufacturing cost is low.

Description

Technical Field

[0001] The invention belongs to the field of isolation technology, and specifically provides a novel on-chip isolation transformer. Background Art

[0002] The isolation transformer is a key component for achieving isolated signal transmission and power transmission between different voltage domains. As electronic equipment develops towards high-density integration and miniaturization, the miniaturization and integration advantages of on-chip isolation transformers are highlighted and have been widely used.

[0003] At present, the structure of the existing on-chip isolation transformer is as follows Figure 1 As shown, it is composed of two coils stacked up and down on the surface of the substrate, and the upper coil and the lower coil are separated by an isolation layer, which provides isolation between the coils; the upper coil and the lower coil both include a planar spiral winding and a pad connecting the inner and outer ends of the planar spiral winding. Since the pad needs to be wire-bonded, there can be no isolation layer above the pad. Therefore, the pad connecting the inner end of the lower coil needs to be led out and set on the outside of the lower coil, and connected to the inner end of the lower coil through a lower through metal line of another patterned metal layer set below the planar spiral winding of the lower coil; it can be seen that, as Figure 1 The on-chip isolation transformer shown needs to use three layers of patterned metal layers to realize the lower metal lines, the lower coil, and the upper coil respectively. Its manufacturing process is complicated and the cost is high. In addition, the upper coil and the lower coil of the on-chip isolation transformer are longitudinally isolated, and the isolation distance is determined by the thickness of the isolation layer. The thickness of the isolation layer is limited by process factors such as surface step height and stress, and usually does not exceed 35 microns, which greatly limits the isolation ability of the isolation layer. In addition, the upper coil and the lower coil adopt an up-and-down stacking structure. Although better magnetic field coupling between coils and a smaller device area can be achieved, the longitudinal overlapping area of ​​the two coils is large, which will lead to a larger parasitic capacitance between the coils. When the voltage difference between the ground potentials of different voltage domains changes rapidly (that is, when a large common-mode transient occurs), the larger parasitic capacitance between the coils will cause a larger displacement current to flow between the coils. The displacement current will generate a large interference voltage on the secondary coil, affecting the correct transmission of the signal. Summary of the invention

[0004] The purpose of the present invention is to provide a new on-chip isolation transformer to solve the problems of limited isolation capability between coils, large parasitic capacitance between coils, complex manufacturing process, high manufacturing cost, etc. in existing on-chip isolation transformers. The present invention creatively arranges two coils of the isolation transformer on the same patterned metal layer to form a structure of an outer coil and an inner coil, which is easy to achieve a large isolation distance, and the parasitic capacitance between the coils is smaller. At the same time, the manufacturing process is simple and the manufacturing cost is low.

[0005] To achieve the above object, the technical solution adopted by the present invention is:

[0006] A novel on-chip isolation transformer comprises: a coil group and an isolation layer; the characteristic is that the coil group is enclosed in the isolation layer, the coil group comprises at least a first inner coil and a first outer coil, the first inner coil and the first outer coil are both located in the first metal layer, the first outer coil is arranged outside the first inner coil, a lateral interval is maintained between the first outer coil and the first inner coil, and the lateral interval is filled with the isolation layer.

[0007] Furthermore, a lateral isolation distance between the outer coil and the inner coil in the coil group is between 5 and 200 microns.

[0008] Furthermore, the first metal layer is formed by a single-layer patterned metal layer, the first inner coil and the first outer coil are planar spiral windings, the inner end and the outer end of the planar spiral winding are connected to the inner end pad and the outer end pad respectively, and the isolation layer is provided with lead windows corresponding to the inner end pad and the outer end pad respectively. Furthermore, the thickness of the single-layer patterned metal layer is between 0.5 microns and 10 microns.

[0009] Furthermore, the isolation layer includes a bottom isolation layer and a top isolation layer; the coil group is arranged on the bottom isolation layer, the top isolation layer covers the coil group and the bottom isolation layer, and the top isolation layer and the bottom isolation layer together constitute a covering structure for the coil group. Furthermore, when the on-chip isolation transformer adopts a non-insulating substrate, the bottom isolation layer is arranged on the non-insulating substrate, and its thickness is between 5 microns and 50 microns; when the on-chip isolation transformer adopts an insulating substrate, the insulating substrate serves as the bottom isolation layer, and its thickness is between 100 microns and 1000 microns. Furthermore, the thickness of the top isolation layer is between 5 microns and 50 microns.

[0010] Furthermore, the coil group also includes: a second inner coil and a second outer coil, both of which are located in the second metal layer, a longitudinal interval is maintained between the first metal layer and the second metal layer, and the longitudinal interval is also filled with an isolation layer; the second inner coil is located below the first inner coil, the second inner coil is connected to the outer end of the first inner coil through a metallized hole, the inner ends of the second inner coil and the first inner coil are respectively connected to the inner end pads, and the two inner end pads are both located inside the inner coil; the second outer coil is located below the first outer coil, the second outer coil is connected to the inner end of the first outer coil through a metallized hole, the outer ends of the second outer coil and the first outer coil are respectively connected to the outer end pads, and the two outer end pads are both located outside the outer coil. Furthermore, the second inner coil and the second outer coil also use planar spiral windings. Furthermore, the isolation layer includes a bottom isolation layer, a middle isolation layer and a top isolation layer, the second metal layer is arranged on the bottom isolation layer, the middle isolation layer covers the second metal layer and the bottom isolation layer, the first metal layer is arranged on the middle isolation layer, the top isolation layer covers the first metal layer and the middle isolation layer, the top isolation layer and the middle isolation layer together constitute a coating structure for the first metal layer, and the middle isolation layer and the bottom isolation layer together constitute a coating structure for the second metal layer. Further, the thickness of the middle isolation layer is between 0.5 microns and 10 microns, and the thickness of the middle isolation layer is greater than the thickness of the second metal layer.

[0011] Based on the above technical solution, the beneficial effects of the present invention are:

[0012] The present invention provides a novel on-chip isolation transformer, which creatively arranges two coils of the isolation transformer on the same patterned metal layer to form a structure of an outer coil and an inner coil, and changes the longitudinal isolation distance of the prior art structure into a lateral isolation distance between the outer coil and the inner coil, so that a large isolation distance can be easily achieved, thereby improving the isolation capability between the coils; at the same time, the lateral facing area of ​​the inner coil and the outer coil is small, and because the lateral isolation distance between the two is large, the parasitic capacitance between the coils can be significantly reduced, thereby reducing the interference voltage generated by common-mode transients; on this basis, the present invention further introduces a second metal layer of similar structure, and the routing capability provided by the second metal layer enables the two pads of the coil group to be arranged on the same side of the coil, that is, the two pads of the inner coil are both arranged on the inner side of themselves, and the two pads of the outer coil are both arranged on the outer side of themselves, thereby increasing the distance between the inner coil pad and the outer coil and the distance between the outer coil pad and the inner coil, thereby preventing breakdown through other paths outside the lateral isolation distance; and, compared with a single metal layer structure, the number of winding turns required to be achieved by each patterned metal layer under the same inductance value is reduced, which can effectively reduce the device area.

[0013] In summary, the novel on-chip isolation transformer provided by the present invention is easier to achieve a large isolation distance, and the parasitic capacitance between coils is smaller; moreover, the manufacturing process is simple and the manufacturing cost is low, which is conducive to commercial application. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of the cross-sectional structure of a traditional on-chip isolation transformer in the prior art.

[0015] Figure 2 It is a schematic diagram of the three-dimensional structure of the novel on-chip isolation transformer in Example 1 of the present invention.

[0016] Figure 3 This is a schematic cross-sectional structural diagram of the novel on-chip isolation transformer in Example 1 of the present invention.

[0017] Figure 4 This is a schematic cross-sectional structural diagram of the novel on-chip isolation transformer in Example 2 of the present invention.

[0018] Figure 5 It is a schematic diagram of the three-dimensional structure of the novel on-chip isolation transformer in Example 3 of the present invention.

[0019] Figure 6 This is a schematic cross-sectional structural diagram of the novel on-chip isolation transformer in Example 3 of the present invention.

[0020] Figure 7 This is a schematic cross-sectional structural diagram of the novel on-chip isolation transformer in Example 4 of the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and beneficial effects of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0022] Example 1

[0023] This embodiment provides a novel on-chip isolation transformer, whose structure is as follows: Figure 2 , Figure 3As shown, it includes: a coil group, an isolation layer and a substrate; wherein the coil group is wrapped in the isolation layer, the coil group includes a first inner coil and a first outer coil, the first inner coil and the first outer coil are located in the same metal layer, specifically the first metal layer; the first outer coil is arranged on the periphery of the first inner coil, a lateral interval is maintained between the first outer coil and the first inner coil, and the lateral interval is filled with an isolation layer; further, the coil group is formed by a single-layer patterned metal layer, the first inner coil and the first outer coil adopt a planar spiral winding, the inner end and the outer end of the planar spiral winding are correspondingly connected to the inner end pad and the outer end pad, and the isolation layer opens lead windows corresponding to the inner end pad and the outer end pad respectively; the isolation layer includes a bottom isolation layer and a top isolation layer, the bottom isolation layer is arranged on the substrate, the coil group is arranged on the bottom isolation layer, the top isolation layer covers the coil group, and the top isolation layer and the bottom isolation layer together constitute a coating structure for the coil group.

[0024] In this embodiment, an independent non-insulating substrate is used, such as a silicon substrate; therefore, the bottom isolation layer can be a combination of one or more isolation material layers such as a silicon oxide layer, a silicon nitride layer, a polyimide layer, a benzocyclobutene layer, etc., such as a silicon dioxide layer and a polyimide layer sequentially arranged on the substrate; preferably, the total thickness of the bottom isolation layer is between 5 microns and 50 microns. The metal layer material can be one or more conductor material layers such as an aluminum layer, an aluminum-copper alloy layer, a copper layer, a gold layer, etc., such as a patterned metal copper layer; preferably, the metal thickness of the patterned metal layer is between 0.5 microns and 10 microns. The top isolation layer is also a combination of one or more isolation material layers such as a silicon oxide layer, a silicon nitride layer, a polyimide layer, a benzocyclobutene layer, etc., such as a polyimide layer, and lead windows are respectively opened at the inner end pad and the outer end pad of the corresponding coil; preferably, the thickness of the top isolation layer is between 5 microns and 50 microns.

[0025] In this embodiment, the manufacturing process of the novel on-chip isolation transformer includes the following steps:

[0026] 1) preparing a bottom isolation layer on a substrate, including: preparing a silicon dioxide layer by thermal oxidation of silicon or chemical vapor deposition, preparing a polyimide layer by spin coating and annealing curing, preparing a benzocyclobutene layer by spin coating and annealing curing, or a single step process or a combination thereof; preferably, the thickness of the silicon dioxide layer is between 0.5 and 10 microns, and the thickness of the polyimide layer is between 0.5 and 30 microns;

[0027] 2) preparing a patterned metal layer on the bottom isolation layer, sequentially evaporating or sputtering an aluminum layer or an aluminum-copper alloy layer, photolithography to form a patterned photoresist layer, etching the aluminum or the aluminum-copper alloy, and removing the photoresist to obtain a patterned metal aluminum layer or a patterned metal aluminum-copper alloy layer; or, sequentially sputtering a seed layer, photolithography to form a patterned photoresist layer, electroplating copper or gold, removing the photoresist, and removing the seed layer to obtain a patterned metal copper layer or a patterned metal gold layer;

[0028] 3) A patterned top isolation layer is prepared on the bottom isolation layer and the patterned metal layer, and a patterned polyimide layer or a patterned benzocyclobutene layer is prepared by a photolithography process of spin coating, hot plate baking, exposure, hot plate baking, and development, and then annealing and curing.

[0029] Example 2

[0030] This embodiment provides a novel on-chip isolation transformer, whose structure is as follows: Figure 4 As shown, the difference from Example 1 is that an insulating substrate is directly used as the bottom isolation layer, and an independent non-insulating substrate and an insulating material bottom isolation layer thereon are not required; the insulating substrate can be a glass substrate or a quartz substrate with a thickness between 100 microns and 1000 microns.

[0031] Example 3

[0032] This embodiment provides a novel on-chip isolation transformer, whose structure is as follows: Figure 5 , Figure 6 As shown; for the novel on-chip isolation transformer in Example 1, as Figure 2 As shown, the structure is bound to have: the inner end pad of the first outer coil is adjacent to the first inner coil, and the outer end pad of the first inner coil is adjacent to the first outer coil, resulting in a small distance between the solder joint between the bonding wire and the pad, and between the bonding wire itself and the coil on the other side, and there may be a breakdown through other paths other than the lateral isolation distance; therefore, this embodiment further proposes a double metal layer structural design, moving the two end pads of the outer coil to the outside, and moving the two end pads of the inner coil to the inside, thereby increasing the distance between the outer coil pad, solder joint and corresponding bonding wire and the inner coil, and increasing the distance between the inner coil pad, solder joint and corresponding bonding wire and the outer coil to prevent breakdown through other paths other than the lateral isolation distance; and, for the same inductance value, the number of winding turns required to be implemented in each metal layer is reduced, which can reduce the device area.

[0033] Specifically, on the basis of Example 1, the coil group also includes: a second inner coil and a second outer coil, the second inner coil and the second outer coil are located in the same metal layer, specifically the second metal layer; the second inner coil is located directly below the first inner coil, and the second outer coil is located directly below the first outer coil, that is: the second outer coil is arranged on the periphery of the second inner coil, the second outer coil and the second inner coil maintain the same lateral interval, and the lateral interval is also filled with an isolation layer; at the same time, the longitudinal interval between the first metal layer and the second metal layer is also filled with an isolation layer; the outer ends of the second inner coil and the first inner coil are connected through metallized holes, and the inner ends of the second inner coil and the first inner coil are respectively connected to inner end pads, and the two inner end pads are both located on the inner side of the inner coil; the second outer coil and the inner end of the first outer coil are connected through metallized holes, and the outer ends of the second outer coil and the first outer coil are respectively connected to outer ends Pad, and the two outer end pads are both located on the outside of the outer coil; further, the second inner coil and the second outer coil also adopt a planar spiral winding; the isolation layer includes a bottom isolation layer, a middle isolation layer and a top isolation layer, the bottom isolation layer is arranged on the substrate, the second metal layer is arranged on the bottom isolation layer, the middle isolation layer covers the second metal layer and the bottom isolation layer, the first metal layer is arranged on the middle isolation layer, the top isolation layer covers the first metal layer and the middle isolation layer, the top isolation layer, the middle isolation layer and the bottom isolation layer together constitute a covering structure for the coil group of the double metal layer; accordingly, the top isolation layer opens a pad window corresponding to the inner end of the first inner coil in the first metal layer, and opens a pad window corresponding to the outer end of the first outer coil in the first metal layer, and the top isolation layer and the middle isolation layer both open a pad window corresponding to the inner end of the second inner coil in the second metal layer, and open a pad window corresponding to the outer end of the second outer coil in the second metal layer.

[0034] In this embodiment, the substrate is a non-insulating substrate, such as a silicon substrate; the bottom isolation layer can be one or more isolation material layers such as a silicon oxide layer, a silicon nitride layer, a polyimide layer, a benzocyclobutene layer, etc., such as a silicon dioxide layer and a polyimide layer sequentially arranged on the substrate; preferably, the total thickness of the bottom isolation layer is between 5 microns and 50 microns. The second patterned metal layer material can be one or more conductor material layers such as an aluminum layer, an aluminum-copper alloy layer, a copper layer, a gold layer, etc., such as a patterned metal copper layer; preferably, the metal thickness of the first patterned metal layer is between 0.5 microns and 10 microns. The middle isolation layer can be one or more isolation material layers such as a silicon oxide layer, a silicon nitride layer, a polyimide layer, a benzocyclobutene layer, etc. with a window opened at the metal through hole, such as a patterned polyimide layer; the middle isolation layer is mainly used to achieve the insulation requirements between the first patterned metal layer and the second patterned metal layer. Preferably, the thickness of the middle isolation layer is between 0.5 microns and 10 microns. Obviously, the thickness of the middle isolation layer is not less than the metal thickness of the second patterned metal layer. The metal via can be formed of a conductive material such as aluminum, aluminum-copper alloy, copper, gold, tungsten, etc., and can be formed alone or together with a second patterned metal layer. The first patterned metal layer material can be one or more conductive material layers such as an aluminum layer, an aluminum-copper alloy layer, a copper layer, a gold layer, etc., for example: a patterned metal copper layer; preferably, the metal thickness of the first patterned metal layer is between 0.5 microns and 10 microns. The top isolation layer can be one or more isolation material layers such as a silicon oxide layer, a silicon nitride layer, a polyimide layer, a benzocyclobutene layer, etc. with a window opened at the pad, for example: a patterned polyimide layer; preferably, the thickness of the top isolation layer is between 5 microns and 50 microns.

[0035] In this embodiment, the manufacturing process of the novel on-chip isolation transformer includes the following steps:

[0036] 1) preparing a bottom isolation layer on a substrate, including: preparing a silicon dioxide layer by silicon thermal oxidation or chemical vapor deposition, preparing a polyimide layer by spin coating and annealing curing, preparing a benzocyclobutene layer by spin coating and annealing curing, or a single step process or a combination thereof; preferably, the thickness of the silicon dioxide layer is between 0.5 and 10 microns, the thickness of the polyimide layer is between 0.5 and 30 microns, and the thickness of the benzocyclobutene layer is between 0.5 and 30 microns;

[0037] 2) preparing a second patterned metal layer on the bottom isolation layer, sequentially evaporating or sputtering an aluminum layer or an aluminum-copper alloy layer, photolithography to form a patterned photoresist layer, etching the aluminum or the aluminum-copper alloy, and removing the photoresist to obtain a patterned metal aluminum layer or a patterned metal aluminum-copper alloy layer; or, sequentially sputtering a seed layer, photolithography to form a patterned photoresist layer, electroplating copper or gold, removing the photoresist, and removing the seed layer to obtain a patterned metal copper layer or a patterned metal gold layer;

[0038] 3) preparing a patterned middle isolation layer on the bottom isolation layer and the second patterned metal layer, sequentially through chemical vapor deposition of a silicon oxide layer, photolithography to form a patterned photoresist layer, etching silicon oxide, removing the photoresist, to obtain a patterned silicon oxide layer; or, sequentially through a photolithography process of spin coating, hot plate baking, exposure, hot plate baking, and development, and then annealing and curing to obtain a patterned polyimide layer or a patterned benzocyclobutene layer;

[0039] 4) preparing metal through holes and a first patterned metal layer at the opening of the middle isolation layer and on the middle isolation layer, and sequentially evaporating or sputtering an aluminum layer or an aluminum-copper alloy layer, photolithography to form a patterned photoresist layer, etching the aluminum or the aluminum-copper alloy, and removing the photoresist to prepare aluminum metal through holes, patterned metal aluminum layer or aluminum-copper alloy metal through holes, and patterned metal aluminum-copper alloy layer; or, sequentially sputtering a seed layer, photolithography to form a patterned photoresist layer, copper or gold electroplating, removing the photoresist, and removing the seed layer to prepare copper metal through holes, patterned metal copper layer or gold metal through holes, and patterned metal gold layer;

[0040] 5) A patterned top isolation layer is prepared on the middle isolation layer and the first patterned metal layer, and a patterned polyimide layer or a patterned benzocyclobutene layer is prepared by a photolithography process of spin coating, hot plate baking, exposure, hot plate baking, and development, and then annealing and curing.

[0041] Example 4

[0042] This embodiment provides a novel on-chip isolation transformer, whose structure is as follows: Figure 7 As shown, the difference from Example 3 is that an insulating substrate is directly used as the bottom isolation layer, and an independent non-insulating substrate and an insulating material bottom isolation layer thereon are not required; the insulating substrate can be a glass substrate or a quartz substrate with a thickness between 100 microns and 1000 microns.

[0043] In summary, the present invention creatively arranges the two coils of the isolation transformer on the same patterned metal layer to form a structure of an outer coil and an inner coil, which not only has a simple manufacturing process and low manufacturing cost, but also is easy to achieve a large isolation distance, and the parasitic capacitance between the coils is smaller.

[0044] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other alternative features that are equivalent or have similar purposes; all the disclosed features, or all the steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A novel on-chip isolation transformer, comprising: Coil group and isolation layer; characterized in that the coil group is wrapped in an isolation layer, and the coil group includes at least a first inner coil and a first outer coil, the first inner coil and the first outer coil are both located in the first metal layer, the first outer coil is arranged outside the first inner coil, a lateral gap is maintained between the first outer coil and the first inner coil, and the isolation layer is filled in the lateral gap.

2. According to the novel on-chip isolation transformer of claim 1, it is characterized in that: The lateral separation distance between the outer coil and the inner coil in the coil group is between 5 and 200 microns.

3. The novel on-chip isolation transformer according to claim 1, characterized in that: The isolation layer includes a bottom isolation layer and a top isolation layer; the first metal layer is arranged on the bottom isolation layer, the top isolation layer covers the coil group and the bottom isolation layer, and the top isolation layer and the bottom isolation layer together constitute a covering structure for the coil group.

4. The novel on-chip isolation transformer according to claim 1, characterized in that: The coil group also includes: a second inner coil and a second outer coil, both of which are located in the second metal layer, a longitudinal interval is maintained between the first metal layer and the second metal layer, and the longitudinal interval is also filled with an isolation layer; the second inner coil is located below the first inner coil, and the outer ends of the second inner coil and the first inner coil are connected through a metallized hole; the second outer coil is located below the first outer coil, and the inner ends of the second outer coil and the first outer coil are connected through a metallized hole.

5. The novel on-chip isolation transformer according to claim 4, characterized in that: The isolation layer includes a bottom isolation layer, a middle isolation layer and a top isolation layer. The second metal layer is arranged on the bottom isolation layer, the middle isolation layer covers the second metal layer and the bottom isolation layer, the first metal layer is arranged on the middle isolation layer, the top isolation layer covers the first metal layer and the middle isolation layer, the top isolation layer and the middle isolation layer together constitute a coating structure for the first metal layer, and the middle isolation layer and the bottom isolation layer together constitute a coating structure for the second metal layer.

6. The novel on-chip isolation transformer according to claim 2 or 5, characterized in that: When the on-chip isolation transformer adopts a non-insulating substrate, the bottom isolation layer is arranged on the non-insulating substrate, and its thickness is between 5 microns and 50 microns; when the on-chip isolation transformer adopts an insulating substrate, the insulating substrate serves as the bottom isolation layer, and its thickness is between 100 microns and 1000 microns.

7. The novel on-chip isolation transformer according to claim 2 or 5, characterized in that: The thickness of the top isolation layer is between 5 microns and 50 microns.

8. The novel on-chip isolation transformer according to claim 5, characterized in that: The thickness of the middle isolation layer is between 0.5 micrometers and 10 micrometers, and the thickness of the middle isolation layer is greater than the thickness of the second metal layer.

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