Package and method of forming same

Abstract

The package includes a die. The die includes: a substrate; an electrical component at the front side of the substrate; an interconnect structure at a front side of the substrate and electrically coupled to the electrical component, where an uppermost wire of the interconnect structure is an aluminum wire; and a via extending from the uppermost conductive line to the backside of the substrate. The package further includes a molding material around the die; a first redistribution structure (RDS) underlying the die and the molding material; a second RDS over the die and the molding material, where the first RDS and the second RDS each include a dielectric layer and a conductive feature in the dielectric layer, where the via of the die is electrically coupled to the first RDS and the second RDS; and a second die over and electrically coupled to the second RDS. Embodiments of the application also include a package and a method of forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to packages and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density comes from repeated reductions in the size of the smallest components (e.g., shrinking semiconductor process nodes toward sub-20nm nodes), which allows more components to be integrated into a given area. With the recent growth in demand for miniaturization, higher speeds and greater bandwidth, as well as lower power consumption and latency, the demand for smaller and more creative packaging technologies for semiconductor dies is also growing.

[0003] As semiconductor technology further develops, stacked semiconductor devices, such as three-dimensional integrated circuits (3DIC), have become an effective alternative to further reduce the physical size of semiconductor devices. In stacked semiconductor devices, active circuits such as logic, memory, processor circuits, etc. are manufactured on different semiconductor wafers. Two or more semiconductor components can be mounted on top of each other to further reduce the form factor of the semiconductor device. Summary of the invention

[0004] Some embodiments of the present application provide a package, comprising: a first redistribution structure (RDS), comprising one or more dielectric layers and conductive features in the one or more dielectric layers; a first tube core, located above a first side of the first redistribution structure and electrically coupled to the first side of the first redistribution structure, wherein the first tube core comprises: a substrate; a first electrical component, located above the substrate; an interconnect structure, located above the substrate at a front side of the first tube core, wherein the interconnect structure is located above the first electrical component and electrically coupled to the first electrical component, wherein the topmost wire of the interconnect structure away from the substrate comprises aluminum; a first conductive bump, located at a back side of the first tube core, wherein the first conductive bump is bonded to the conductive feature of the first redistribution structure; and a through hole, extending from the topmost wire of the interconnect structure to the first conductive bump; a first molding material, located above the first side of the first redistribution structure around the first tube core; a second redistribution structure, located above the first molding material and the first tube core, wherein the second redistribution structure is electrically coupled to the first tube core and the through hole; and a second tube core, located above the second redistribution structure and electrically coupled to the second redistribution structure.

[0005] Some other embodiments of the present application provide a package, comprising: a first die, comprising: a substrate; an electrical component located at the front side of the substrate; an interconnect structure located at the front side of the substrate and electrically coupled to the electrical component, wherein the uppermost conductive wire of the interconnect structure away from the substrate is an aluminum wire; and a through-hole extending from the uppermost conductive wire of the interconnect structure to the back side of the substrate; a first molding material located around the first die; a first redistribution structure (RDS) located below the first die and the first molding material, wherein the first redistribution structure includes a first dielectric layer and a first conductive component in the first dielectric layer; a second redistribution structure located above the first die and the first molding material, wherein the second redistribution structure includes a second dielectric layer and a second conductive component in the second dielectric layer, wherein the through-hole of the first die is electrically coupled to the first redistribution structure and the second redistribution structure; and a second die located above the second redistribution structure and electrically coupled to the second redistribution structure.

[0006] Some other embodiments of the present application provide a method for forming a package, the method comprising: forming a first redistribution structure (RDS) above a carrier, wherein the first redistribution structure includes a first dielectric layer and a first conductive component in the first dielectric layer; attaching a first die to an upper surface of the first redistribution structure away from the carrier, wherein the first die is formed using a first process node; forming a first molding material on the upper surface of the first redistribution structure around the first die; forming a second redistribution structure above the first molding material and the first die, wherein the second redistribution structure includes a second dielectric layer and a second conductive component in the second dielectric layer; and attaching a second die to an upper surface of the second redistribution structure away from the carrier, wherein the second die is formed using a second process node, wherein a first critical dimension (CD) of the first process node is greater than a second critical dimension of the second process node. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 A cross-sectional view of a professional technology semiconductor device according to an embodiment is shown.

[0009] Figure 2 A cross-sectional view of an expert technology semiconductor device according to another embodiment is shown.

[0010] Figures 3 to 8 Cross-sectional views of a three-dimensional integrated circuit (3DIC) device at different fabrication stages according to an embodiment are shown.

[0011] Fig. 9 A cross-sectional view of a semiconductor package according to an embodiment is shown.

[0012] Fig.10 A cross-sectional view of a semiconductor package according to another embodiment is shown.

[0013] Fig.11 A cross-sectional view of a semiconductor package according to yet another embodiment is shown.

[0014] Fig.12 A cross-sectional view of a silicon local interconnect (LSI) interposer is shown in accordance with an embodiment.

[0015] Fig.13 A flow chart of a method of forming a semiconductor package according to an embodiment is shown. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for realizing the different features of the embodiments of the present disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted to form, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. Throughout the discussion herein, unless otherwise stated, the same or similar reference numerals in different drawings refer to the same or similar components formed by the same or similar formation methods using the same or similar materials. In addition, in the discussion herein, unless otherwise stated, the term "conductive" refers to electrical conduction (e.g., rather than thermal conduction), and the term "conductive component" refers to a conductive component.

[0017] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0018] In some embodiments, the professional technology device is vertically integrated with other semiconductor devices to form a 3DIC device. The molding material surrounds the professional technology device. A backside redistribution structure (RDS) and a frontside RDS are formed at the back side and front side of the professional technology device, respectively. One or more semiconductor devices are physically and electrically coupled to the first side of the front side RDS away from the professional technology device. The professional technology device includes a substrate, an electrical component formed above the substrate, an interconnection structure above the electrical component, and a through hole extending from the topmost wire (e.g., an aluminum wire) of the interconnection structure to the back side of the professional technology device. The through hole provides a vertical electrical connection between the front side RDS and the back side RDS. The disclosed through-hole structure allows a unified method to integrate professional technology devices with other semiconductor devices, regardless of the type or function of the professional technology device. In some embodiments, the semiconductor device and the professional technology device in the 3DIC device are formed using different process nodes, which allows flexibility in the selection of devices integrated in the 3DIC device and allows the 3DIC device to be formed inexpensively.

[0019] Figure 1 A cross-sectional view of a specialized technology semiconductor device 100A (also referred to as a specialized technology device or specialized technology die) according to an embodiment is shown. In the discussion herein, a specialized technology device may refer to a semiconductor device formed using non-CMOS technology, such as gallium nitride (GaN) technology, bipolar-CMOS-DMOS (BCD) technology, etc. Specialized technology may be used to form a variety of specialized technology devices, such as radio frequency devices, mixed signal devices, analog devices, passive devices (e.g., resistors, inductors, capacitors, or photodiodes), micro-electromechanical systems (MEMS) devices, embedded flash memory (eFlash) devices, image sensors, etc.

[0020] like Figure 1 As shown in FIG. 1 , the specialized technology device 100A includes a substrate 101, a device region 103, an interconnect structure 110, a passivation layer 108, and a post-processing interconnect (PPI) 120. In addition, the specialized technology device 100A includes a through-hole 102 (also referred to as a via) extending from a topmost conductive line 107T of the interconnect structure 110 to a conductive bump 104 at the back side of the specialized technology device 100A.

[0021] The substrate 101 may include, for example, bulk silicon, doped or undoped, or an active layer of a semiconductor on insulator (SOI) substrate. Typically, an SOI substrate includes a semiconductor material layer, such as silicon, formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. An insulating layer is provided on a substrate such as a silicon or glass substrate. Alternatively, the substrate 101 may include: another elemental semiconductor, such as germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0022] Electrical components such as transistors, capacitors, resistors, diodes, photodiodes, fuses, etc. are formed in the device region 103 at the front side of the substrate 101 (e.g., at the interface between the substrate 101 and the interconnect structure 110). The interconnect structure 110 is formed over the device region 103 and the substrate 101. The interconnect structure 110 may include a dielectric layer 109 (e.g., an interlayer dielectric (ILD) and / or an intermetallic dielectric (IMD) layer) and conductive features (e.g., wires 107 and vias 105) formed in the dielectric layer 109. The interconnect structure 110 electrically connects the various electrical components in the device region 103 to form functional circuits of the professional technology device 100A. The functions provided by such circuits may include memory structures, processing structures, sensors, amplifiers, power distribution, power management, input / output (I / O) circuits, etc. It will be understood by those skilled in the art that the above examples are provided only for illustrative purposes and are not meant to limit the present application in any way. For a given application, other circuits may be used as appropriate.

[0023] The dielectric layer 109 may be formed of a low-K dielectric material having a dielectric constant value (also referred to as a K value) of, for example, less than about 4.0 or even 2.0. In some embodiments, the dielectric layer 109 may be formed of, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiO using any suitable method such as spin coating, chemical vapor deposition (CVD), and plasma enhanced CVD (PECVD). x C y , spin-on glass, spin-on polymer, silicon-carbon material, their compounds, their composites, their combinations, etc.

[0024] Conductive wires 107 (e.g., 107A and 107B) and vias 105 (e.g., 105A and 105B) are formed in dielectric layer 109 using any suitable method using suitable conductive materials (such as copper, aluminum, tungsten, combinations thereof, etc.). In some embodiments, conductive features (such as conductive wires 107A and vias 105A) in a lower portion (e.g., close to substrate 101) of interconnect structure 110 are formed of a conductive material (e.g., copper) that is different from a conductive material (e.g., aluminum) of conductive features (e.g., conductive wires 107B and vias 105B) in an upper portion (e.g., away from substrate 101) of interconnect structure 110. Conductive wires 107A and 107B may be collectively referred to as conductive wires 107, and vias 105A and 105B may be collectively referred to as vias 105. In other embodiments, all conductive features (e.g., conductive wires 107, vias 105) of interconnect structure 110 are formed of the same material (e.g., aluminum). Aluminum is a cheaper material than copper, and therefore, using aluminum for some or all of the conductive components in the interconnect structure 110 reduces production costs. In some embodiments, despite the wide variety of functions of specialized technology devices and the wide variety of specialized technologies used to form specialized technology devices, the conductive components (e.g., wires 107B and vias 105B) in the upper portion of the interconnect structure 110 are formed of aluminum. In particular, at least the topmost wire 107T (e.g., the wire 107B farthest from the substrate 101) is formed of aluminum. It should be noted that each of the vias 102 is formed to extend from the topmost wire 107T of the interconnect structure 110 to a corresponding conductive bump 104 (also referred to as a connector) at the back side of the substrate 101. By designing the via 102 to contact (e.g., physically contact) the topmost wire 107T of the interconnect structure 110, a unified via design can be used to integrate different types of specialized technology devices in the 3DIC device 200.

[0025] The through hole 102 can be formed by: forming an opening extending from the back side of the substrate 101 to the topmost conductor 107; and then filling the opening with a conductive material such as copper or aluminum. In some embodiments, the use of copper as a material for the through hole 102 provides improved electromigration robustness. The conductive bump 104 can be, for example, a ball grid array (BGA) ball, a microbump (μ bump), a controlled collapse chip connection (C4) bump, a copper pillar, etc., and can be formed by any suitable formation method. In some embodiments, the thickness (e.g., diameter) of the through hole 102 is between about 1 μm and about 50 μm. The spacing between adjacent through holes 102 can be between about 20 μm and about 100 μm.

[0026] Next, input / output (I / O) components and passivation components may be formed above the interconnect structure 110. For example, a contact pad 106 (e.g., an aluminum pad) may be formed above the interconnect structure 110, which may be electrically connected to the device region 103 through various conductive components in the interconnect structure 110. The contact pad 106 may include a conductive material, such as aluminum, copper, etc. In addition, a passivation layer 108 may be formed above the interconnect structure 110 and the contact pad 106. In some embodiments, the passivation layer 108 is formed of a polymer material, such as polyimide. In some embodiments, the passivation layer 108 is formed of an inorganic material, such as silicon oxide, undoped silicate glass, silicon oxynitride, etc. Other suitable passivation materials may also be used. Portions of the passivation layer 108 may cover edge portions of the contact pad 106.

[0027] Next, PPI 120 is formed on passivation layer 108 and electrically coupled to interconnect structure 110, for example, via contact pad 106. In some embodiments, PPI 120 includes dielectric layer 111 and conductive features (e.g., conductive lines 113 and vias 115) formed in dielectric layer 111. Conductive lines 113 and vias 115 may be formed of a suitable conductive material, such as copper. PPI 120 may be formed using the same or similar formation method as interconnect structure 110, so the details are not discussed here. In some embodiments, the thickness (e.g., line width) of conductive lines 113 (e.g., copper lines) of PPI 120 is between about 1 μm and about 30 μm. The number of dielectric layers 111 in PPI 120 may be, for example, between about 1 and about 20. The total thickness (along the length of the dielectric layer) of professional technology device 100A is about 1 μm. Figure 1 The thickness of the PPI 120 may be between about 1 μm and about 30 μm. The PPI 120 and the interconnect structure 110 are disposed at the front side of the professional technology device 100A. The conductive bump 104 is disposed at the back side of the professional technology device 100A.

[0028] exist Figure 1In an example of the PPI 120, in addition to the wires and vias, the PPI 120 includes an electrical component 117 formed in the dielectric layer 111. Examples of the electrical component 117 include capacitors, inductors, resistors, and the like. For example, a metal-insulator-metal (MIM) capacitor can be formed by forming a metal pattern (e.g., a copper pattern) and a high-K dielectric material between metal patterns in the PPI 120. As another example, a coil can be formed by forming a copper pattern in one or more dielectric layers 111. The electrical component 117 can be connected to the electrical component in the device area 103 through the interconnect structure 110 to form a functional circuit of the professional technology device 100A. For example, the professional technology device 100A can be a power management integrated circuit (IC), and the capacitor and / or inductor of the electrical component 117 can be used as a switching capacitor and / or a switching regulator of the power management IC. In some embodiments, the electrical component 117 is omitted in the PPI 120.

[0029] Still reference Figure 1 , a conductive bump 119 (also referred to as a connector) is formed over the PPI 120 and electrically coupled to the PPI 120. The conductive bump 119, together with the conductive bump 104, provides an electrical connection between the professional technology device 100A and another electrical device. In some embodiments, the conductive bump 119 is a solder ball, such as a BGA ball, a micro bump, a C4 bump, etc. The conductive bump 119 may include a Sn-Ag alloy, a Sn-Cu alloy, a Sn-Ag-Cu alloy, etc., and may be a lead-free solder cap or a lead-containing solder cap.

[0030] The various components of the professional technology device 100A can be formed by any suitable method and will not be described in further detail herein. In addition, the general components and configuration of the professional technology device 100A described above are only one exemplary embodiment, and the professional technology device 100A may include any number of the above components and any combination of other components.

[0031] Figure 2 A cross-sectional view of a specialized technology semiconductor device 100B (also referred to as a specialized technology device or specialized technology die) according to another embodiment is shown. The specialized technology device 100B is similar to the specialized technology semiconductor device 100A, but does not have the PPI 120. In the discussion below, the term "specialized technology device 100" may be used to refer to either the specialized technology device 100A or the specialized technology device 100B.

[0032] Figures 3 to 8 1 and 2. A cross-sectional view of a three-dimensional integrated circuit (3DIC) device 200 at various manufacturing stages according to an embodiment is shown. The 3DIC device 200 may also be referred to as a semiconductor package.

[0033] exist Figure 3In the embodiment, a redistribution structure (RDS) 202 is formed on a carrier 201 (also referred to as a carrier substrate 201). The carrier 201 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier 201 may be a wafer, so that a plurality of 3IDC devices 200 may be formed on the carrier 201 at the same time.

[0034] In some embodiments, the RDS 202 (also referred to as the backside RDS 202) includes one or more layers of conductive features, such as conductive lines 203 and vias 205, formed in one or more dielectric layers 207. In some embodiments, the dielectric layer 207 is formed of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In other embodiments, the dielectric layer 207 is formed of: a nitride, such as silicon nitride; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), or boron-doped phosphosilicate glass (BPSG); etc. The one or more dielectric layers 207 can be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, etc., or a combination thereof.

[0035] In some embodiments, the conductive features of the RDS 202 include conductive lines 203 and vias 205 formed of suitable conductive materials such as copper, titanium, tungsten, aluminum, etc. The formation process of the RDS 202 may include: forming a dielectric layer 207; forming an opening in the dielectric layer 207 to expose the conductive features below; forming a seed layer above the dielectric layer 207 and in the opening; forming a patterned photoresist having a design pattern (e.g., an opening) above the seed layer; plating (e.g., electroplating or chemical plating) a conductive material in the design pattern and above the seed layer; and removing the photoresist and the portion of the seed layer on which the conductive material is not formed. The above process may be repeated until a target number of dielectric layers 207 and conductive features are formed in the RDS 202.

[0036] In some embodiments, before forming RDS202, a release layer (not shown) is formed on carrier 201. The release layer can be formed of a polymer-based material, which can be removed from the upper structure to be formed in a subsequent step together with carrier substrate 201. In some embodiments, the release layer is a thermal release material based on epoxy resin, which loses its viscosity when heated, such as light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer can be an ultraviolet (UV) glue that loses its viscosity when exposed to UV light. As an example, the release layer can be dispensed as a liquid and cured, or it can be a laminated film laminated to carrier substrate 201. The top surface of the release layer can be flush and can have a high degree of coplanarity.

[0037] Next, in Figure 4In the embodiment, the professional technology device 100 is attached (eg, bonded) to the upper surface of the RDS 202, and the molding material 209 is formed over the upper surface of the RDS 202 around the professional technology device 100. As an example, the professional technology device 100 may be Figure 1 Professional technology devices 100A or Figure 2 For simplicity, the details of the professional technology device 100 may not be shown in Figure 4 Although some components such as through-hole 102, topmost conductive line 107T and conductive bump 104 are shown, it should be understood that the professional technology device 100 is formed in Figures 4 to 11 Other components not shown, such as Figure 1 or Figure 2 as shown in .

[0038] In some embodiments, the conductive bumps 104 at the back side of the specialized technology device 100 are bonded to the conductive features exposed at the upper surface of the RDS 202. The conductive bumps 104 may be bonded using a solder material, or may be bonded using a hybrid bonding technique in which the specialized technology device 100 is bonded to the RDS 202 using dielectric-to-dielectric bonding and metal-to-metal bonding without using an adhesive material or solder material. Figure 4 As shown in , the through-via 102 of the professional technology device 100 is electrically coupled to the conductive feature of the RDS 202 , for example, through a conductive bump 104 .

[0039] Next, a molding material 209 is formed on the RDS 202 around the professional technology device 100. In some embodiments, the molding material 209 includes epoxy resin, organic polymer, polymer or other material with or without silicon-based or glass filler added. In some embodiments, the molding material 209 includes a liquid molding compound (LMC) that is a gel-type liquid when applied. When applied, the molding material 209 may also include liquid or solid. Optionally, the molding material 209 may include other insulating and / or sealing materials. In some embodiments, the molding material 209 is applied using a wafer-level molding process. The molding material 209 can be molded using, for example, compression molding, transfer molding or other methods.

[0040] Next, in some embodiments, the molding material 209 is cured using a curing process. The curing process may include heating the molding material 209 to a predetermined temperature for a predetermined period of time using an annealing process or other heating process. The curing process may also include an ultraviolet (UV) light exposure process, an infrared (IR) energy exposure process, a combination thereof, or a combination thereof with a heating process. Alternatively, the molding material 209 may be cured using other methods. In some embodiments, a curing process is not included.

[0041] Next, a planarization process, such as chemical mechanical planarization (CMP), is performed to remove excess portions of the molding material 209 and achieve a coplanar upper surface between the specialty technology device 100 and the molding material 209 .

[0042] Next, in Figure 5 In the embodiment, RDS 212 (also referred to as front-side RDS 212) is formed on the front side of the professional technology device 100 and the molding material 209. RDS 212 includes a dielectric layer 217 and conductive features (e.g., wires 213 and vias 215) formed in the dielectric layer 217. RDS 212 can be formed using the same or similar formation method as RDS 202, so the details will not be repeated.

[0043] The conductive component of RDS 212 is electrically coupled to the professional technology device 100. Figure 5 As shown in FIG. 1 , the through hole 102 of the professional technology device 100 is, for example, connected through the topmost conductive line 107T and the conductive bump 119 (see FIG. Figure 1 ) or through the topmost conductor 107T and the contact pad 106 (see Figure 2 ) is electrically coupled to a conductive feature of RDS 212. Thus, via 102 electrically couples RDS 212 with RDS 202.

[0044] Next, in Figure 6 , semiconductor devices 221 and 223 (e.g., semiconductor dies) are attached to the upper surface of RDS 212. For example, conductive connectors 224 of semiconductor devices 221 and 223 are bonded to conductive components of RDS 212, for example, using solder material. Semiconductor devices 221 and 223 are electrically coupled to professional technology device 100 through RDS 212. In addition, semiconductor devices 221 and 223 are electrically coupled to each other through conductive components of RDS 212.

[0045] In some embodiments, semiconductor devices with different functions (eg, 221, 223, 100) are integrated together (eg, Figure 6 ) to form a 3DIC device 200. For example, semiconductor device 221 may be a processor (e.g., a microcontroller, a digital signal processor, etc.), semiconductor device 223 may be a memory device (e.g., a DRAM device) including a memory cell for storing digital information, and professional technology device 100 may be a power management IC (PMIC) device that implements, for example, DC-DC power conversion and supplies regulated power to semiconductor devices 221 and 223. The PMCI device (e.g., 100) may include an inductor and / or a capacitor formed in PPI 120 of the PMIC device (see, e.g., Figure 1117 in FIG. 117). As another example, semiconductor device 223 may be a memory device that includes a memory cell but does not include a control circuit for the memory cell (e.g., for controlling the read / write of the memory cell). The control circuit for the memory cell is implemented in professional technology device 100, and thus, semiconductor device 223 and professional technology device 100 together provide the full functionality of a memory IC device. As yet another example, two professional technology devices including professional technology device 100 (PMIC device) and professional technology device 100A (memory control circuit) are embedded in molding material 209 to form a 3DIC device, such as Fig.10 3DIC device 200A in FIG. 3DIC device 200A. The number of semiconductor devices in 3DIC device 200 and the functions of the semiconductor devices discussed above are non-limiting examples, as will be readily understood by a person of ordinary skill. The number of semiconductor devices in 3DIC device 200 may be any suitable number, and the semiconductor devices in 3DIC device 200 may implement any suitable functions.

[0046] In some embodiments, semiconductor devices 221 and 223 are formed by a more advanced process node than the professional technology device 100. A process node (also referred to as a process technology or a technology node) refers to a technical term for semiconductor manufacturing technology used to manufacture semiconductor devices. A process node is typically characterized by a critical dimension (CD) of the process node. The CD of a process node is also a technical term for the minimum feature size achieved by a process node, which is typically measured as the minimum line width that can be produced by a process node. Therefore, in some embodiments, the CD of a process node can be used interchangeably with the minimum line width of a process node. Currently, advanced process nodes for semiconductor manufacturing include a 7nm node, a 3nm node, and the like. Examples of older process nodes include a 65nm node, a 90nm node, a 110nm node, an 800nm ​​node, a 3μm node, a 10μm node, a 50μm node, and the like.

[0047] Advantages can be achieved by integrating semiconductor devices formed by different process nodes into 3DIC 200. For example, semiconductor devices 221 and 223 can be high-performance devices (e.g., high-performance processors or high-bandwidth high-capacity memory devices) that integrate a large number of (e.g., millions or more) transistors. Using advanced process nodes for semiconductor devices 221 and 223 allows a large number of transistors to be integrated into a small semiconductor die area, thereby improving integration density and reducing production costs for semiconductor devices. Additional advantages may include lower power consumption. Professional technology device 100, due to its function or design / performance requirements, may be very suitable for older process nodes. For example, professional technology device 100 may need to integrate capacitors, and the thicker line width of older process nodes can more effectively achieve large capacitance for capacitors. As another example, professional technology device 100 may have different electrical ratings or performance requirements (e.g., high voltage devices), and those performance requirements can be more easily and cheaper to achieve using older process nodes and / or non-CMOS technology. In some embodiments, semiconductor devices 221 and 223 are formed by CMOS technology, while professional technology device 100 is formed by non-CMOS technology, and the CD of non-CMOS technology is greater than the CD of CMOS technology. The disclosed embodiments (by allowing semiconductor devices formed by different process nodes to be integrated together) allow 3DIC devices with multiple functions to be formed inexpensively.

[0048] It should be noted that the via 102 provides a vertical electrical connection between the front side RDS 212 and the back side RDS 202, which allows power signals (e.g., power supply or electrical ground) and data signals to be easily routed between the front side RDS 212 and the back side RDS 202. Without the via 102, vertical routing of power signals and data signals may be difficult, and due to this difficulty, professional technology devices without the via 102 are usually coupled to a package substrate or a printed circuit board (PCB) at the same vertical level as other semiconductor devices (e.g., side by side). In other words, without the via 102, vertical stacking of professional technology devices with other semiconductor devices (e.g., 221, 223) may be difficult.

[0049] To further illustrate the advantages of the through-hole 102, consider a reference 3DIC device in which a professional technology device without the through-hole 102 is compared with Figure 6A similar configuration is integrated with a larger number (e.g., 4 or more) of semiconductor devices 221 / 223. In the reference 3DIC device, a large number of semiconductor devices 221 / 223 are typically aligned along a single row so that there is sufficient spacing around the semiconductor devices 221 / 223 to form a through hole extending through the molding material 209 to electrically couple the RDS 202 with the RDS 212. In contrast, the professional technology device 100 with through holes 102 provides a vertical electrical connection between the RDS 202 and 212, and allows the semiconductor devices 221 / 223 to be arranged in a matrix form, for example, for a total of four semiconductor devices 221 / 223, arranged in a 2×2 configuration in the top view. This allows for more compact integration of semiconductor devices 221 / 223 (and therefore for smaller areas of the 3DIC device) and greater flexibility in the placement of semiconductor devices 221 / 223 in the 3DIC device.

[0050] In some embodiments, the professional technology device 100 is formed using a first process node, and the semiconductor devices 221 and 223 are formed using a second process node, wherein the CD (or minimum line width) of the first process node is greater than the CD (or minimum line width) of the second process node. In addition, RDS202 and 212 are formed using a third process node, wherein the CD (or minimum line width) of the third process node is greater than the CD of the first process node. Because RDS202 and RDS212 have less stringent requirements for line width due to smaller area limitations, using an older process node (which has a larger CD or a larger minimum line width) allows RDS202 and RDS212 to be formed inexpensively.

[0051] Variations of the disclosed embodiments are possible and are fully intended to be included within the scope of the disclosed embodiments. In the above examples, the professional technology device 100 is formed using a process node older than the semiconductor devices 221 and 223. This is merely a non-limiting example. The professional technology device 100 can be formed using any suitable process node, including advanced process nodes. The semiconductor devices 221 and 223 can be formed by different process nodes that are more advanced (e.g., having a smaller CD) than the process node of the professional technology device 100. The number of professional technology devices and the number of semiconductor devices integrated in the 3DIC device can be any suitable number, as readily understood by a person of ordinary skill.

[0052] Next, in Figure 7In the embodiment of the present invention, a bottom fill material 231 is deposited to fill the gap between the semiconductor devices 221 and 223 and the RDS 212. The bottom fill material 231 may extend along the sidewalls of the semiconductor devices 221 and 223. Examples of the bottom fill material 231 include, but are not limited to, polymers and other suitable non-conductive materials. The bottom fill material 231 may be dispensed in the gap between the semiconductor devices 221 and 223 and the RDS 212 using, for example, a needle or a jet dispenser. A curing process may be performed to cure the bottom fill material 231.

[0053] Next, a molding material 233 is formed on the RDS 212 around the semiconductor devices 221 and 223. The molding material 233 may be the same or similar to the molding material 209 and may be formed using the same or similar formation method. After the molding material 233 is formed, a planarization process such as CMP may be performed to achieve a coplanar upper surface between the molding material 233 and the semiconductor devices 221 and 223.

[0054] Next, in Figure 8 In the embodiment of the present invention, the carrier 201 is removed, for example, by a carrier stripping process. According to some embodiments, the stripping includes projecting light such as laser or UV light onto the release layer so that the release layer decomposes under the heat of the light and the carrier substrate 201 can be removed. The remaining structure is then flipped over and placed on the tape, which holds the remaining structure in place. Next, a conductive bump 204 is formed at the outer surface of the RDS 202 away from the professional technology device 100. The conductive bump 204 is electrically coupled to the conductive part of the RDS 202. The conductive bump 204 can be formed by the same or similar formation method as the conductive bump 104 or 119, so the details are not repeated. In some embodiments, a plurality of 3DIC devices 200 are formed simultaneously on the carrier 201, and therefore, the next step is to implement a cutting process along the scribe area (indicated by the dotted line 235) between adjacent 3DIC devices 200 to form independent (e.g., separated) 3DIC devices 200.

[0055] Fig. 9 A cross-sectional view of a semiconductor package 300 according to an embodiment is shown. The semiconductor package 300 is formed by attaching the 3DIC device 200 to a workpiece 310, which may be, for example, a package substrate or a printed circuit board (PCB). The workpiece 310 may include a substrate 301 (e.g., a dielectric core including one or more dielectric material layers) and conductive components (e.g., wires 303 and vias 305) for routing electrical signals, for example, from a first side of the substrate 301 to an opposite second side of the substrate 301. Fig. 9In the example of , 3DIC device 200 is bonded to a first side of substrate 301, for example, by solder material. Conductive bumps 304 are formed at a second, opposite side of substrate 301. Conductive bumps 304 may be the same or similar to conductive bumps 204, so the details are not repeated. Fig. 9 , a heat sink 321 (which is optional) is attached to the molding material 233 and the semiconductor devices 221 and 223 .

[0056] Fig.10 A cross-sectional view of a semiconductor package 300A according to another embodiment is shown. The semiconductor package 300A is similar to the semiconductor package 300, but has a 3DIC device 200A attached to a workpiece 310. The 3DIC device 200A is similar to the 3DIC device 200, but has two specialized technology devices 100 and 100A embedded in a molding material 209. The specialized technology device 100 has a through-hole 102 that provides a vertical electrical connection, and can be, for example, a PMIC device. The specialized technology device 100A may or may not have a through-hole 102, and can be, for example, a control circuit for a semiconductor device 223 (e.g., a memory device).

[0057] Fig.11 FIG. 2 shows a cross-sectional view of a semiconductor package 300B according to yet another embodiment. The semiconductor package 300B is similar to the semiconductor package 300A, but has a local silicon interconnect (LSI) interposer 400 embedded in the RDS 212 to provide electrical connections between the semiconductor devices 221 and 223. The details of the LSI interposer 400 are shown in FIG. Fig.12 as shown in .

[0058] Fig.12 4 shows a cross-sectional view of an LSI interposer 400. Fig.12As shown in , the LSI interposer 400 includes a substrate 401 (e.g., a glass substrate, a ceramic substrate, a dielectric substrate, a semiconductor substrate (e.g., a bulk silicon substrate), etc.), a dielectric layer 403 (e.g., silicon oxide) above the substrate 401, and an RDS 410 above the dielectric layer 403. The RDS 410 includes one or more dielectric layers 405 (e.g., silicon oxide) and conductive features 407 (e.g., wires and vias) formed in the one or more dielectric layers 405. In some embodiments, the LSI interposer 400 is formed using the same back-end-of-line (BEOL) process as used to form the interconnect structure of the semiconductor device 221 (or 223), and therefore, the critical dimensions (e.g., minimum line width) of the LSI interposer 400 are the same as those of the semiconductor device 221 (or 223) to allow high-density wiring. In other words, the process node of the LSI interposer 400 can be the same as the process node of the semiconductor device 221 (or 223). Because the RDS 212 is formed using an older process node, the critical dimension of the RDS 212 is larger than the critical dimension of the LSI interposer 400 .

[0059] Return to reference Fig.11 The dielectric layer of the RDS 212 may be formed of an organic material (eg, a polymer material such as polyimide). The preformed LSI interposer 400 is embedded in the organic material of the RDS 212 .

[0060] Fig.13 1 is a flow chart of a method 1000 for forming a semiconductor package according to an embodiment. It should be understood that Fig.13 The embodiment methods shown in are merely examples of many possible embodiment methods. Those skilled in the art will recognize many variations, options, and modifications. For example, the following may be added, removed, replaced, rearranged, or repeated: Fig.13 The steps shown in .

[0061] refer to Fig.13 , in box 1010, a first redistribution structure (RDS) is formed over a carrier, wherein the first RDS includes a first dielectric layer and a first conductive component in the first dielectric layer. In box 1020, a first die is attached to an upper surface of the first RDS away from the carrier, wherein the first die is formed using a first process node. In box 1030, a first molding material is formed on an upper surface of the first RDS around the first die. In box 1040, a second RDS is formed over the first molding material and the first die, wherein the second RDS includes a second dielectric layer and a second conductive component in the second dielectric layer. In box 1050, a second die is attached to an upper surface of the second RDS away from the carrier, wherein the second die is formed using a second process node, wherein a first critical dimension (CD) of the first process node is greater than a second CD of the second process node.

[0062] Embodiments of the devices and methods in the current disclosure have many advantages. For example, by forming a through hole 102 to extend from the topmost wire 107T (e.g., aluminum wire) of the interconnect structure 110 to the back side of the specialized technology device, a unified design method can be applied for vertical integration of specialized technology devices in a 3DIC device, regardless of the type or function of the specialized technology device. The disclosed 3DIC device allows devices formed using different processing nodes to be integrated together, thereby reducing production costs, and allows the flexibility of selecting process nodes for different devices integrated in the 3DIC device. The vertical wiring provided by the through hole 102 allows the semiconductor device to be flexibly placed in the 3DIC device, which reduces the footprint of the 3DIC device and increases the integration density.

[0063] According to an embodiment, a package includes: a first redistribution structure (RDS) including one or more dielectric layers and conductive features in the one or more dielectric layers; a first die located above a first side of the first RDS and electrically coupled to the first side of the first RDS, wherein the first die includes: a substrate; a first electrical component located above the substrate; an interconnect structure located above the substrate at a front side of the first die, wherein the interconnect structure is located above the first electrical component and electrically coupled to the first electrical component, wherein the topmost conductor of the interconnect structure away from the substrate includes aluminum; a first conductive bump located at a back side of the first die, wherein the first conductive bump is bonded to a conductive feature of the first RDS; and a via extending from the topmost conductor of the interconnect structure to the first conductive bump. The package also includes: a first molding material located above a first side of the first RDS around the first die; a second RDS located above the first molding material and the first die, wherein the second RDS is electrically coupled to the first die and the via; and a second die located above the second RDS and electrically coupled to the second RDS. In an embodiment, a first critical dimension (CD) of the first die is greater than a second CD of the second die. In an embodiment, the third CD of the first RDS is greater than the first CD of the first die. In an embodiment, the third CD of the first RDS is equal to the fourth CD of the second RDS. In an embodiment, the first die further comprises a second electrical component embedded in an interconnect structure, wherein the interconnect structure is configured to connect the first electrical component and the second electrical component to form a functional circuit of the first die. In an embodiment, the first electrical component comprises a transistor, wherein the second electrical component comprises a capacitor, an inductor, or a resistor. In an embodiment, the package further comprises: an underfill material, located between the second die and the second RDS; and a second molding material, located above the second RDS around the second die. In an embodiment, the package further comprises: a heat sink, attached to a first side of the second molding material away from the second RDS. In an embodiment, the package further comprises: a packaging substrate, wherein a second side of the first RDS opposite to the first side of the first RDS is bonded to the packaging substrate. In an embodiment, the second die is a memory die comprising a memory cell, wherein the first die comprises a control circuit for the memory die.

[0064] According to an embodiment, a package includes a first die. The first die includes: a substrate; an electrical component located at a front side of the substrate; an interconnect structure located at the front side of the substrate and electrically coupled to the electrical component, wherein the uppermost wire of the interconnect structure away from the substrate is an aluminum wire; and a through-hole extending from the uppermost wire of the interconnect structure to the back side of the substrate. The package also includes: a first molding material located around the first die; a first redistribution structure (RDS) located below the first die and the first molding material, wherein the first RDS includes a first dielectric layer and a first conductive component in the first dielectric layer; a second RDS located above the first die and the first molding material, wherein the second RDS includes a second conductive component in the second dielectric layer, wherein the through-hole of the first die is electrically coupled to the first RDS and the second RDS; and a second die located above the second RDS and electrically coupled to the second RDS. In an embodiment, the minimum line width of the first die is greater than the minimum line width of the second die. In an embodiment, the minimum line width of the first RDS is greater than the minimum line width of the first die. In an embodiment, the package further includes: a third die located above the second RDS and electrically coupled to the second RDS; and a local silicon interconnect (LSI) interposer embedded in the second RDS, wherein the LSI interposer includes another substrate and a third RDS above the other substrate, wherein the second die is electrically coupled to the third die through the LSI interposer. In an embodiment, the lowest conductor of the interconnect structure close to the substrate is a copper wire. In an embodiment, the first die further includes a post-processing interconnect (PPI) located above the interconnect structure and electrically coupled to the interconnect structure, wherein the PPI includes: a third dielectric layer located above the interconnect structure; a third conductive component located in the third dielectric layer; and a conductive bump located at a first side of the PPI away from the interconnect structure, wherein the conductive bump is bonded to the second RDS.

[0065] According to an embodiment, a method of forming a package includes: forming a first redistribution structure (RDS) above a carrier, wherein the first RDS includes a first dielectric layer and a first conductive component in the first dielectric layer; attaching a first die to an upper surface of the first RDS away from the carrier, wherein the first die is formed using a first process node; forming a first molding material on an upper surface of the first RDS around the first die; forming a second RDS above the first molding material and the first die, wherein the second RDS includes a second dielectric layer and a second conductive component in the second dielectric layer; and attaching a second die to an upper surface of the second RDS away from the carrier, wherein the second die is formed using a second process node, wherein a first critical dimension (CD) of the first process node is greater than a second CD of the second process node. In an embodiment, the first RDS and the second RDS are formed using a third process node, wherein a third CD of the third process node is greater than the first CD. In an embodiment, a first die is formed to include: a substrate; an electrical component located above the substrate; an interconnect structure located at a front side of the substrate, wherein the interconnect structure is located above the electrical component and electrically coupled to the electrical component, wherein a topmost conductor of the interconnect structure away from the substrate is formed of aluminum; a conductive bump located at a back side of the substrate; and a via extending from the topmost conductor of the interconnect structure to the conductive bump, wherein the via of the first die is electrically coupled to the first RDS and the second RDS. In an embodiment, the method further includes: filling a gap between the second die and the second RDS with an underfill material; and after filling, forming a second molding material over the second RDS around the second die.

[0066] Some embodiments of the present application provide a package, comprising: a first redistribution structure (RDS), comprising one or more dielectric layers and conductive features in the one or more dielectric layers; a first tube core, located above a first side of the first redistribution structure and electrically coupled to the first side of the first redistribution structure, wherein the first tube core comprises: a substrate; a first electrical component, located above the substrate; an interconnect structure, located above the substrate at a front side of the first tube core, wherein the interconnect structure is located above the first electrical component and electrically coupled to the first electrical component, wherein the topmost wire of the interconnect structure away from the substrate comprises aluminum; a first conductive bump, located at a back side of the first tube core, wherein the first conductive bump is bonded to the conductive feature of the first redistribution structure; and a through hole, extending from the topmost wire of the interconnect structure to the first conductive bump; a first molding material, located above the first side of the first redistribution structure around the first tube core; a second redistribution structure, located above the first molding material and the first tube core, wherein the second redistribution structure is electrically coupled to the first tube core and the through hole; and a second tube core, located above the second redistribution structure and electrically coupled to the second redistribution structure.

[0067] In some embodiments, a first critical dimension (CD) of the first die is greater than a second critical dimension of the second die. In some embodiments, a third critical dimension of the first redistribution structure is greater than the first critical dimension of the first die. In some embodiments, the third critical dimension of the first redistribution structure is equal to a fourth critical dimension of the second redistribution structure. In some embodiments, the first die further comprises a second electrical component embedded in the interconnect structure, wherein the interconnect structure is configured to connect the first electrical component and the second electrical component to form a functional circuit of the first die. In some embodiments, the first electrical component comprises a transistor, wherein the second electrical component comprises a capacitor, an inductor, or a resistor. In some embodiments, the package further comprises: an underfill material between the second die and the second redistribution structure; and a second molding material over the second redistribution structure around the second die. In some embodiments, the package further comprises: a heat sink attached to a first side of the second molding material away from the second redistribution structure. In some embodiments, the package further comprises: a packaging substrate, wherein a second side of the first redistribution structure opposite to the first side of the first redistribution structure is bonded to the packaging substrate. In some embodiments, the second die is a memory die comprising a memory cell, wherein the first die comprises a control circuit for the memory die.

[0068] Some other embodiments of the present application provide a package, comprising: a first die, comprising: a substrate; an electrical component located at the front side of the substrate; an interconnect structure located at the front side of the substrate and electrically coupled to the electrical component, wherein the uppermost conductive wire of the interconnect structure away from the substrate is an aluminum wire; and a through-hole extending from the uppermost conductive wire of the interconnect structure to the back side of the substrate; a first molding material located around the first die; a first redistribution structure (RDS) located below the first die and the first molding material, wherein the first redistribution structure includes a first dielectric layer and a first conductive component in the first dielectric layer; a second redistribution structure located above the first die and the first molding material, wherein the second redistribution structure includes a second dielectric layer and a second conductive component in the second dielectric layer, wherein the through-hole of the first die is electrically coupled to the first redistribution structure and the second redistribution structure; and a second die located above the second redistribution structure and electrically coupled to the second redistribution structure.

[0069] In some embodiments, the minimum line width of the first die is greater than the minimum line width of the second die. In some embodiments, the minimum line width of the first redistribution structure is greater than the minimum line width of the first die. In some embodiments, the package further comprises: a third die located above the second redistribution structure and electrically coupled to the second redistribution structure; and a local silicon interconnect (LSI) interposer embedded in the second redistribution structure, wherein the local silicon interconnect interposer comprises another substrate and a third redistribution structure above the other substrate, wherein the second die is electrically coupled to the third die through the local silicon interconnect interposer. In some embodiments, the lowest wire of the interconnect structure close to the substrate is a copper wire. In some embodiments, the first die further comprises a post-processing interconnect (PPI) located above the interconnect structure and electrically coupled to the interconnect structure, wherein the post-processing interconnect comprises: a third dielectric layer located above the interconnect structure; a third conductive component located in the third dielectric layer; and a conductive bump located at a first side of the post-processing interconnect away from the interconnect structure, wherein the conductive bump is bonded to the second redistribution structure.

[0070] Some other embodiments of the present application provide a method for forming a package, the method comprising: forming a first redistribution structure (RDS) above a carrier, wherein the first redistribution structure includes a first dielectric layer and a first conductive component in the first dielectric layer; attaching a first die to an upper surface of the first redistribution structure away from the carrier, wherein the first die is formed using a first process node; forming a first molding material on the upper surface of the first redistribution structure around the first die; forming a second redistribution structure above the first molding material and the first die, wherein the second redistribution structure includes a second dielectric layer and a second conductive component in the second dielectric layer; and attaching a second die to an upper surface of the second redistribution structure away from the carrier, wherein the second die is formed using a second process node, wherein a first critical dimension (CD) of the first process node is greater than a second critical dimension of the second process node.

[0071] In some embodiments, the first redistribution structure and the second redistribution structure are formed using a third process node, wherein a third critical dimension of the third process node is greater than the first critical dimension. In some embodiments, the first die is formed to include: a substrate; an electrical component located above the substrate; an interconnect structure located at a front side of the substrate, wherein the interconnect structure is located above the electrical component and electrically coupled to the electrical component, wherein a topmost conductor of the interconnect structure away from the substrate is formed of aluminum; a conductive bump located at a back side of the substrate; and a through-hole extending from the topmost conductor of the interconnect structure to the conductive bump, wherein the through-hole of the first die is electrically coupled to the first redistribution structure and the second redistribution structure. In some embodiments, the method further includes: filling a gap between the second die and the second redistribution structure with an underfill material; and after the filling, forming a second molding material over the second redistribution structure around the second die.

[0072] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A package comprising: a first redistribution structure comprising one or more dielectric layers and conductive features in the one or more dielectric layers; A first die is located above and electrically coupled to a first side of the first redistribution structure, wherein the first die comprises: substrate; a first electrical component located above the substrate; an interconnect structure over the substrate at a front side of the first die, wherein the interconnect structure is over and electrically coupled to the first electrical component, wherein a topmost conductor of the interconnect structure distal from the substrate comprises aluminum; a first conductive bump located at a back side of the first die, wherein the first conductive bump is bonded to a conductive feature of the first redistribution structure; and a through hole extending from the topmost conductive line of the interconnect structure to the first conductive bump; a first molding material over the first side of the first redistribution structure around the first die; a second redistribution structure over the first molding material and the first die, wherein the second redistribution structure is electrically coupled to the first die and the through via; and A second die is located over the second redistribution structure and electrically coupled to the second redistribution structure.

2. The package according to claim 1, wherein: The first critical dimension of the first die is greater than a second critical dimension of the second die.

3. The package according to claim 2, wherein: A third critical dimension of the first redistribution structure is greater than the first critical dimension of the first die.

4. The package according to claim 3, wherein: The third critical dimension of the first redistribution structure is equal to a fourth critical dimension of the second redistribution structure.

5. The package according to claim 2, wherein: The first die also includes a second electrical component embedded in the interconnect structure, wherein the interconnect structure is configured to connect the first electrical component and the second electrical component to form a functional circuit of the first die.

6. The package according to claim 5, wherein: The first electrical component comprises a transistor, wherein the second electrical component comprises a capacitor, an inductor, or a resistor.

7. The package according to claim 5, further comprising: a bottom filling material between the second die and the second redistribution structure; as well as A second molding material is over the second redistribution structure around the second die.

8. The package according to claim 7, further comprising: A heat sink is attached to a first side of the second molding material away from the second redistribution structure.

9. A package comprising: The first die comprises: substrate; an electrical component located at the front side of the substrate; an interconnect structure located at the front side of the substrate and electrically coupled to the electrical component, wherein an uppermost conductive line of the interconnect structure distal from the substrate is an aluminum line; and a through-hole extending from the uppermost conductive line of the interconnect structure to the back side of the substrate; a first molding material disposed around the first die; a first redistribution structure located below the first die and the first molding material, wherein the first redistribution structure includes a first dielectric layer and a first conductive feature in the first dielectric layer; a second redistribution structure over the first die and the first molding material, wherein the second redistribution structure comprises a second dielectric layer and a second conductive feature in the second dielectric layer, wherein the vias of the first die are electrically coupled to the first redistribution structure and the second redistribution structure; and A second die is located over the second redistribution structure and electrically coupled to the second redistribution structure.

10. A method of forming a package, the method comprising: forming a first redistribution structure over the carrier, wherein the first redistribution structure comprises a first dielectric layer and a first conductive feature in the first dielectric layer; attaching a first die to an upper surface of the first redistribution structure remote from the carrier, wherein the first die is formed using a first process node; forming a first molding material on the upper surface of the first redistribution structure around the first die; forming a second redistribution structure over the first molding material and the first die, wherein the second redistribution structure comprises a second dielectric layer and a second conductive feature in the second dielectric layer; and A second die is attached to an upper surface of the second redistribution structure remote from the carrier, wherein the second die is formed using a second process node, wherein a first critical dimension of the first process node is greater than a second critical dimension of the second process node.

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