Vertical cavity surface emitting laser and method for manufacturing the same

Abstract

The application relates to the technical field of semiconductors, in particular to a vertical cavity surface emitting laser and a preparation method thereof. The laser comprises, from bottom to top, an n-face electrode layer, a substrate layer, a buffer layer, an n-DBR layer, an SiO2 insulating layer located at the outer periphery above the n-DBR layer, an n-lower oxidation limiting structure layer, a lower space layer, a quantum well active region, an upper space layer, a p-upper oxidation limiting structure layer, a p-DBR layer, a contact layer and a p-face electrode layer which are sequentially arranged in the center of the SiO2 insulating layer from bottom to top to form a cylindrical platform. By adopting the symmetrical oxidation limiting structure, more carriers are limited in the oxidation hole, the output power and the electro-optical conversion efficiency can be improved, and the number and distribution of transverse modes can be controlled.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a vertical-cavity surface-emitting laser and its fabrication method, which improves the optoelectronic performance of the vertical-cavity surface-emitting laser through a symmetric oxide confinement structure. Background Technology

[0002] A vertical-cavity surface-emitting laser (VCSEL) is a semiconductor laser that emits light perpendicular to the surface of a device. Due to its unique chip structure, VCSELs offer advantages such as low threshold voltage, low power consumption, single longitudinal mode, easily coupled circular spot to optical fibers, on-chip testing, easy arraying, and low manufacturing cost. They have found wide application in fields such as intelligent sensing, optical interconnects, optical communication, optical storage, and quantum precision measurement.

[0003] VCSELs were first proposed by Japanese scientist Iga in 1977. After more than 30 years of development, VCSELs have long been commercialized on a large scale and have formed device types such as GaAs-based VCSELs, InP-based VCSELs, antimony compound VCSELs, and GaN-based VCSELs. Among them, GaAs-based VCSELs are the most mature and widely used VCSEL products, mainly for two reasons: (1) AlGaAs materials and GaAs substrates have a natural lattice match and a large refractive index difference, making it easy to grow distributed Bragg reflector (DBR) structures with high reflectivity and low defect density; (2) AlGaAs materials with high Al content can form oxidation-confined structures through wet oxidation processes, which has a significant effect on reducing the loss of VCSEL devices and is a key technology for promoting the industrialization of GaAs-based VCSELs.

[0004] Thanks to in-depth and systematic research on AlGaAs materials, the wet oxidation process for GaAs-based VCSELs is now very mature. Therefore, oxide confinement structures have become the most widely used method for current and optical field confinement. The oxide confinement layer in GaAs-based VCSELs is typically placed between the first pair of P-DBRs near the active region. This structure can confine carrier and optical field diffusion, trapping most carriers and photons within the oxide apertures. However, a significant number of carriers and photons still diffuse outside the oxide apertures, failing to form effective stimulated emission. Some researchers have also incorporated dual oxide confinement layers in the P-DBRs to reduce the parasitic capacitance of the VCSEL and improve the modulation bandwidth; however, this structure lacks current confinement on the N-side, resulting in lower output power and electro-optical conversion efficiency. Summary of the Invention

[0005] The technical problems to be solved by the present invention are: (1) GaAs-based VCSELs with p-type single oxide confinement layer structure have no current confinement on the n side, and electron diffusion is more serious; (2) The confinement ability of carriers is weak, which is not conducive to improving the carrier injection efficiency; (3) The confinement effect of the optical field is poor, especially the high-order transverse modes are often outside the oxide holes, which cannot form an effective mode gain and reduce the output power.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: a vertical cavity surface emission laser, comprising an n-face electrode layer, a substrate layer, a buffer layer, and an n-DBR layer arranged sequentially from bottom to top. A SiO2 insulating layer is disposed above the n-DBR layer on its outer periphery. An n-lower oxide confinement structure layer, a lower space layer, a quantum well active region, an upper space layer, a p-upper oxide confinement structure layer, a p-DBR layer, a contact layer, and a p-face electrode layer arranged sequentially from bottom to top in the center of the SiO2 insulating layer.

[0007] The n-low oxidation confinement structure layer includes at least one periodic n-low oxidation confinement structure, wherein the n-low oxidation confinement structure is arranged sequentially from bottom to top with n-Al z1 GaAs high refractive index layer, n-Al 0.98 GaAs oxide confinement layer and n-Al 0.9 GaAs low refractive index layer, n-Al 0.98 A first alumina layer was formed on the outer periphery of the GaAs oxide confinement layer by a wet oxidation process.

[0008] The p-on-oxidation confinement structure layer includes at least one periodic p-on-oxidation confinement structure, and the p-on-oxidation confinement structure includes p-Al atoms arranged sequentially from bottom to top. 0.9 GaAs low refractive index layer, p-Al 0.98 GaAs oxide confinement layer and p-Al z2 GaAs high refractive index layer, p-Al 0.98 A second alumina layer is formed on the outer periphery of the GaAs oxide confinement layer through a wet oxidation process, where z1 and z2 represent the Al composition in the corresponding materials.

[0009] The n-Al 0.98 The thickness of the GaAs oxide confinement layer is 30 nm, and the p-Al 0.98 The thickness of the GaAs oxide confinement layer is 30 nm.

[0010] The n-Al 0.98 The doping concentration of the GaAs oxide confinement layer is 1×10⁻⁶. 18 cm -3 Si-doped; the p-Al 0.98The doping concentration of the GaAs oxide confinement layer is 1×10⁻⁶. 18 cm -3 , doped with C.

[0011] The n-Al z1 GaAs high refractive index layer and n-Al 0.98 An n-AlGaAs transition layer is also provided between the GaAs oxide confinement layers, and its Al composition gradually changes from z1 to 0.9.

[0012] p-Al 0.98 GaAs oxide confinement layer and p-Al z A p-AlGaAs transition layer is also provided between the GaAs high refractive index layers, with its Al composition linearly varying from 0.9 to z2.

[0013] The n-sided electrode layer includes gold and nickel layers arranged sequentially from bottom to top;

[0014] The substrate is an n-GaAs substrate with a thickness of 120 μm and a doping concentration of 2 × 10⁻⁶. 18 cm -3 Si-doped;

[0015] The buffer layer is an n-GaAs buffer layer with a thickness of 150 nm and a doping concentration of 2 × 10⁻⁶. 18 cm -3 Si-doped;

[0016] The lower space layer is an AlGaAs lower space layer with a thickness of 114.1 nm and no doping.

[0017] The upper space layer is an AlGaAs upper space layer 09 with a thickness of 114.1 nm;

[0018] The contact layer is a p-GaAs contact layer with a thickness of 100 nm and a doping concentration of 2 × 10⁻⁶. 19 cm -3 Add C;

[0019] The p-side electrode layer comprises layers of titanium, platinum, and gold arranged sequentially from bottom to top.

[0020] The z1 = z2.

[0021] The p-plane electrode layer is annular, with its center coinciding with the center of the n-lower oxide confinement structure layer, and its inner diameter is larger than that of n-Al. 0.98 GaAs oxide confinement layer and p-Al 0.98 The radius of the GaAs oxide confinement layer.

[0022] The n-DBR layer consists of 43 pairs of n-Al z3 GaAs high refractive index layer and n-Al0.9 The GaAs low-refractive-index layers are periodically overlapped; among them, n-Al z3 The thickness of the GaAs high refractive index layer is λ / 4n. H1 -20nm, z3 satisfies: 1.424 + 1.247z3 > 1240 / (λ-50); n-Al 0.9 The thickness of the GaAs low refractive index layer is λ / 4n. L1 –20nm; λ is the emission wavelength of the VCSEL, n H1 For n-Al z3 The refractive index of the GaAs high-refractive-index layer, n L1 For n-Al 0.9 The refractive index of the GaAs low-refractive-index layer;

[0023] Each layer n-Al z3 Above each GaAs high-refractive-index layer, a 20 nm n-AlGaAs transition layer is formed, in which the Al composition linearly changes from z3 to 0.9; similarly, each n-Al layer... 0.9 Above the GaAs low refractive index layer, a 20nm n-AlGaAs transition layer is set, with the Al composition linearly varying from 0.9 to z3.

[0024] The p-DBR layer consists of 23 pairs of p-Al 0.9 GaAs low refractive index layer and p-Al z4 The high-refractive-index GaAs layers are periodically overlapped; among them, p-Al z4 The thickness of the GaAs high refractive index layer is λ / 4n. H2 -20nm, z4 satisfies: 1.424 + 1.247z4 > 1240 / (λ-50); p-Al 0.9 The thickness of the GaAs low refractive index layer is λ / 4n. L2 –20nm; λ is the emission wavelength of the VCSEL, n H2 For n-Al z4 The refractive index of the GaAs high-refractive-index layer, n L2 For n-Al 0.9 The refractive index of the GaAs low-refractive-index layer;

[0025] Each layer of p-Al z Above each GaAs high-refractive-index layer, a 20nm AlGaAs transition layer is formed, with the Al composition linearly varying from z to 0.9; similarly, each p-Al layer... 0.9 Above the low-refractive-index GaAs layer, a 20nm p-AlGaAs transition layer is formed, with the Al composition linearly varying from 0.9 to z; each p-Al layer... zOn each GaAs high refractive index layer, a 20 nm p-AlGaAs transition layer is formed, with the Al composition linearly changing from z4 to 0.9; the topmost p-Al layer... z A 30nm p-AlGaAs transition layer is set on top of the GaAs high refractive index layer, with the Al composition linearly changing from z4 to 0 and the doping concentration increasing from 3×10⁻⁶. 18 cm -3 Linear gradient to 2×10 19 cm -3 z3 and z4 represent the Al components in the corresponding materials, respectively.

[0026] The aforementioned vertical cavity surface-emitting laser has z3 = z4.

[0027] Furthermore, this invention also provides a method for fabricating a vertical-cavity surface-emitting laser, comprising an epitaxial growth step and a chip fabrication step; the epitaxial growth step employs metal-organic chemical vapor deposition (MOCVD) technology and includes the following steps:

[0028] Step 1: Select an (001) n-type GaAs substrate and place it on a graphite tray inside the MOCVD reaction chamber;

[0029] Step 2: In a hydrogen atmosphere, arsine (AsH3) is introduced, and the temperature of the graphite tray is raised to 680°C under the protection of AsH3. High-temperature baking removes impurities and oxide layers from the substrate surface.

[0030] Step 3: Lower the temperature to 640℃, introduce trimethylgallium (TMGa) and silane (SiH4), control the growth rate of the GaAs buffer layer by adjusting the flow rate of TMGa, control the V / III ratio to 60 by adjusting the flow rate of AsH3, and control the doping concentration by adjusting the flow rate of SiH4 to grow the n-GaAs buffer layer.

[0031] Step 4: Maintain the growth temperature at 640℃ and the V / III ratio at 60, introduce trimethylaluminum (TMAl), and gradually increase its flow rate from 0 to Al. z The required flux for GaAs growth to form an AlGaAs transition layer above the n-GaAs buffer layer;

[0032] Step 5: Maintain the growth temperature at 640℃, the V / III ratio at 60, and the flow rates of TMGa and TMAl unchanged. Adjust the SiH4 flow rate to achieve a doping concentration of 2×10⁻⁶. 18 cm -3 Al in n-DBR growth z3 GaAs high refractive index layer;

[0033] Step 6: Maintain the growth temperature at 640℃, V / III ratio at 60, and linearly and gradually increase the flow rates of TMGa and TMAl to Al. 0.9 The flux required for GaAs growth, forming Al z3 AlGaAs transition layer above GaAs high refractive index layer;

[0034] Step 7: Maintain the growth temperature at 640℃, the V / III ratio at 60, and the flow rates of TMGa and TMAl unchanged. Adjust the SiH4 flow rate to achieve a doping concentration of 2×10⁻⁶. 18 cm -3 Al in n-DBR growth 0.9 GaAs low refractive index layer;

[0035] Step 8: Maintain the growth temperature at 640℃, V / III ratio at 60, and linearly and gradually increase the flow rates of TMGa and TMAl to Al. z3 The flux required for GaAs growth, forming Al 0.9 AlGaAs transition layer above GaAs low refractive index layer;

[0036] Step 9: Repeat steps 5-8 to form 40 pairs of doped pairs with a doping concentration of 2×10⁻⁶. 18 cm -3 n-DBR;

[0037] Step 10: Adjust the SiH4 flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 Repeat steps 5-8 to form 3 pairs of doped products with a doping concentration of 1×10⁻⁶. 18 cm -3 n-DBR;

[0038] Step 11: Using the growth parameters from Step 5, but shortening the growth time, grow n-Al in the n-under-oxidation-restricted structure. z1 GaAs high refractive index layer;

[0039] Step 12: Repeat step 6 to form n-Al z1 AlGaAs transition layer above GaAs high refractive index layer;

[0040] Step 13: Maintain the growth temperature at 640℃, V / III ratio at 60, and switch the flow rates of TMGa and TMAl to Al. 0.98 The required flow rate for GaAs growth was adjusted by controlling the SiH4 flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 n-Al in the n-oxidation-restricted structure O4 0.98 GaAs under-oxidation confinement layer 05;

[0041] Step 14: Maintain the growth temperature at 640℃, V / III ratio at 60, and switch the flow rates of TMGa and TMAl to Al. 0.9 The required flow rate for GaAs growth was adjusted by controlling the SiH4 flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 n-Al in the n-oxidation-restricted structure of growth 0.9 GaAs low refractive index layer;

[0042] Step 15: Maintain the growth temperature at 640℃ and the V / III ratio at 60, cut off the SiH4 supply, and linearly and gradually change the flow rates of TMGa and TMAl to the flow rates required for the growth of the AlGaAs quantum barrier layer, and grow the AlGaAs lower space layer.

[0043] Step 16: Maintain the growth temperature at 640℃, the V / III ratio at 60, and the TMGa and TMAl flow rates unchanged to grow the AlGaAs quantum barrier layer. After the growth is complete, cut off the TMGa and TMAl sources and pause the growth for 5 seconds.

[0044] Step 17: Maintain the growth temperature at 640℃ and the V / III ratio at 60. Introduce TMGa, TMAl, and TMIn sources and adjust the flow rates of TMGa, TMAl, and TMIn sources to achieve a growth rate of 0.2 nm / s for the InGaAlAs quantum well layer. After the quantum well layer is grown, cut off the TMGa, TMAl, and TMIn sources and pause the growth for 5 seconds.

[0045] Step 18: Repeat steps 16-17 multiple times to form the active region of the quantum well;

[0046] Step 19: Repeat step 16 to complete the last AlGaAs quantum barrier layer of the quantum well active region;

[0047] Step 20: Maintain the growth temperature at 640℃ and the V / III ratio at 60. Introduce TMGa and TMAl sources, setting the initial flow rate to the flow rate required for AlGaAs quantum barrier layer growth, and then linearly gradually increasing it to Al. 0.9 The flux required for GaAs growth forms the space layer on top of AlGaAs;

[0048] Step 21: Maintain the growth temperature at 640℃, reduce the V / III ratio to 40, keep the flow rates of TMGa and TMAl unchanged, introduce carbon tetrabromide as the C doping source, and adjust the carbon tetrabromide flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 p-Al in p-oxidation-restricted structures growing 0.9 GaAs low refractive index layer;

[0049] Step 22: Maintain the growth temperature at 640℃, V / III ratio at 40, and switch the flow rates of TMGa and TMAl to Al. 0.98 The required flow rate for GaAs growth is achieved by adjusting the carbon tetrabromide flow rate to maintain a doping concentration of 1×10⁻⁶. 18 cm -3 p-Al in p-oxidation-restricted structures growing 0.98 GaAs oxide confinement layer;

[0050] Step 23: Maintain the growth temperature at 640℃ and the V / III ratio at 40. Switch the initial flow rates of TMGa and TMAl to Al. 0.9 The flux required for GaAs growth is then linearly gradiented to Al. z2 The required flux for GaAs growth, to grow a 20nm AlGaAs transition layer;

[0051] Step 24: Maintain the growth temperature at 640℃, the V / III ratio at 40, and the flow rates of TMGa and TMAl unchanged. Adjust the CBr4 flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 p-Al in p-oxidation-restricted structures growing z2 GaAs high refractive index layer;

[0052] Step 25: Maintain the growth temperature at 640℃, V / III ratio at 40, and linearly and gradually increase the flow rates of TMGa and TMAl to Al. 0.9 The required flux for GaAs growth is used to form a 20nm AlGaAs transition layer;

[0053] Step 26: Maintain the growth temperature at 640℃, the V / III ratio at 40, and the flow rates of TMGa and TMAl unchanged. Adjust the CBr4 flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 p-Al in p-DBR growth 0.9 GaAs low refractive index layer;

[0054] Step 27: Maintain the growth temperature at 640℃, V / III ratio at 40, and linearly and gradually increase the flow rates of TMGa and TMAl to Al. z4 The required flux for GaAs growth is used to form a 20nm AlGaAs transition layer;

[0055] Step 28: Maintain the growth temperature at 640℃, the V / III ratio at 40, and the flow rates of TMGa and TMAl unchanged. Adjust the CBr4 flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 p-Al in p-DBR growth z4 GaAs high refractive index layer;

[0056] Step 29: Repeat steps 25-28 to form 3 pairs of doped pairs with a doping concentration of 1×10⁻⁶. 18 cm -3 p-DBR;

[0057] Step 30: Adjust the CBr4 flow rate to achieve a doping concentration of 3 × 10⁻⁶. 18 cm -3 Repeat steps 25-28 to form 20 pairs of doped pairs with a doping concentration of 3×10⁻⁶. 18 cm -3 The p-DBR was used to complete the growth of p-DBR 09;

[0058] Step 31: The growth temperature is linearly decreased from 640℃ to 580℃, the TMAl flow rate is linearly and gradually reduced to 0, the V / III ratio is linearly and gradually reduced to 30, and the CBr4 flow rate is linearly and gradually reduced to the flow rate required for p+GaAs contact layer doping, forming an AlGaAs transition layer from p-DBR to p+GaAs contact layer. The Al composition is linearly and gradually reduced from z to 0, and the doping concentration is reduced from 3×10⁻⁶. 18 cm -3 Linear gradient to 2×10 19 cm -3 ;

[0059] Step 32: Maintain the growth temperature at 580℃ and the V / III ratio at 30, cut off the flow rate of TMAl, TMGa and CBr4 and keep it constant to grow the p+GaAs contact layer;

[0060] Step 33: Cut off TMGa and CBr4, allow to cool naturally to room temperature, then cut off AsH3 to complete the epitaxial wafer growth;

[0061] The chip manufacturing process includes:

[0062] Step 34: Clean the epitaxial wafer using the standard epitaxial wafer cleaning process;

[0063] Step 35: Use photolithography and development process to form the electrode pattern of the p-side electrode layer, retain the photoresist outside the electrode area of ​​the p-side electrode layer, and remove the photoresist in the electrode area of ​​the p-side electrode layer.

[0064] Step 36: Deposit the metal layer corresponding to the p-side electrode using electron beam evaporation or magnetron sputtering processes;

[0065] Step 37: Use an adhesive peeling process to remove the metal outside the glass ring electrode, leaving the metal in the ring electrode area to form a p-side ring electrode;

[0066] Step 38: Use photolithography and development to form a cylindrical pattern on the wafer surface, leaving the photoresist in the cylindrical area, and remove the photoresist outside the cylindrical area;

[0067] Step 39: Use a dry etching process to etch a cylindrical mesa down to the n-DBR layer, and then remove the photoresist from the cylindrical mesa.

[0068] Step 40: Use chemical polishing to treat the sidewalls of the cylindrical mesa to eliminate etching damage to the sidewalls;

[0069] Step 41: The oxide confinement layer in the n-lower oxide confinement structure layer and the p-upper oxide confinement structure layer is oxidized by a wet oxidation process to form an aluminum oxide layer on the outer periphery of the oxide confinement layer;

[0070] Step 42: Deposit a SiO2 insulating layer using plasma chemical vapor deposition technology. The thickness of the SiO2 insulating layer is greater than the height of the cylindrical platform to protect the sidewalls of the cylindrical platform.

[0071] Step 43: Use photolithography + development process to overlay the cylindrical stage, remove the photoresist on the upper surface of the cylindrical stage, and retain the photoresist outside the cylindrical stage area to protect the SiO2 insulating layer;

[0072] Step 44: Use a wet etching process to remove the SiO2 insulating layer on the upper surface of the cylindrical stage, exposing the p-side annular electrode, and then remove all photoresist.

[0073] Step 45: Use photolithography and development to form the lead wires and pad pattern of the p-side electrode layer;

[0074] Step 46: Deposit the p-plane metal using electron beam evaporation or magnetron sputtering.

[0075] Step 47: Use a stripping process to remove the photoresist and metal from the wafer surface to form p-side electrode leads and pads;

[0076] Step 48: Thin the n-GaAs substrate to 120 μm using a polishing process;

[0077] Step 49: Polish the back side of the n-GaAs substrate using a polishing process;

[0078] Step 50: Deposit metal on the back side of the n-GaAs substrate using electron beam evaporation or magnetron sputtering to form an n-face electrode;

[0079] Step 51: Alloy the n-side electrode and p-side electrode using a high-temperature annealing process to form an ohmic contact with the semiconductor;

[0080] Step 52: Dicing and splitting to form a single-tube or array chip, completing the fabrication of GaAs-based VCSEL chips.

[0081] Compared with the prior art, the present invention has the following advantages:

[0082] First, the vertical-cavity surface-emitting laser of this invention employs a symmetrical oxide confinement structure, which confines more charge carriers within the oxide holes, significantly improving the charge carrier injection efficiency. This results in a marked increase in both the charge carrier concentration and current density within the active region. The increased charge carrier concentration consequently enhances the radiative recombination efficiency, internal quantum efficiency, and slope efficiency, thereby significantly increasing the output power and electro-optical conversion efficiency, as shown in the attached figure. Figure 4 and attached Figure 5 As shown;

[0083] Second, in the vertical cavity surface-emitting laser of the present invention, under the action of the symmetrical oxide confinement structure, the confinement ability of the oxide hole to the optical field is improved, the confinement factor is increased, more higher-order modes are confined in the oxide hole, and photon leakage is less, which is conducive to improving the optical output power.

[0084] Third, in this invention, the symmetric oxide confinement structure can serve as the mode control structure for a vertical-cavity surface-emitting laser. By changing the number of symmetric oxide confinement layers and the size of the oxide holes, the number and distribution of transverse modes can be controlled, thereby increasing the output power, as shown in the attached figure. Figure 6 As shown. Attached Figure Description

[0085] Figure 1 This is a schematic diagram of a 940nm vertical-cavity surface-emitting laser provided in Embodiment 1 of the present invention;

[0086] Figure 2 This is a schematic diagram of the p-side electrode layer in Embodiment 1 of the present invention;

[0087] Figure 3 This is a schematic diagram of a 940nm vertical-cavity surface-emitting laser provided in Embodiment 2 of the present invention;

[0088] Figure 4 This is a comparison of the PIV curves of the vertical cavity surface-emitting lasers of Embodiments 1 and 2 of the present invention and the vertical cavity surface-emitting laser with a single oxide confinement layer structure; wherein the single oxide confinement structure refers to a structure with only p-oxide confinement and no n-oxide confinement, and the p-oxide confinement structure has only one period.

[0089] Figure 5 This is a comparison of the electro-optical conversion efficiency of the vertical cavity surface-emitting lasers of Embodiments 1 and 2 of the present invention and the vertical cavity surface-emitting laser with a single oxide confinement layer structure;

[0090] Figure 6This is a comparison diagram of the mode distribution of the vertical cavity surface-emitting laser (VCSEL) of Embodiment 1 and Embodiment 2 of the present invention and the VCSEL with a single oxide confinement layer structure. (a) corresponds to the VCSEL with a single oxide confinement structure, (b) corresponds to Embodiment 1, and (c) corresponds to Embodiment 2. LP01, LP11, etc. are all transverse modes. Detailed Implementation

[0091] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0092] Example 1

[0093] Embodiment 1 of the present invention provides a 940nm vertical-cavity surface-emitting laser, the structure of which is shown in the attached figure. Figure 1 As shown, the structure includes, from bottom to top, an n-side electrode layer 17, a substrate layer 1, a buffer layer 2, and an n-DBR layer 3. A SiO2 insulating layer 16 is disposed on the outer periphery of the n-DBR layer 3. From bottom to top, the center of the SiO2 insulating layer 16 is provided with an n-lower oxide confinement structure layer forming a cylindrical platform, a lower space layer 7, a quantum well active region 8, an upper space layer 9, a p-upper oxide confinement structure layer, a p-DBR layer 13, a contact layer 14, and a p-side electrode layer 15.

[0094] The n-low oxidation confinement structure layer includes a periodic n-low oxidation confinement structure, wherein n-Al is arranged sequentially from bottom to top in the n-low oxidation confinement structure. z1 GaAs high refractive index layer 4,n-Al 0.98 GaAs oxide confinement layer 5 and n-Al 0.9 GaAs low refractive index layer 6, the n-Al 0.98 A first alumina layer was formed on the outer periphery of the GaAs oxide confinement layer 5 through a wet oxidation process.

[0095] The p-on-oxidation confinement structure layer includes a periodic p-on-oxidation confinement structure, wherein the p-on-oxidation confinement structure includes p-Al atoms arranged sequentially from bottom to top. 0.9 GaAs low refractive index layer 10, p-Al 0.98 GaAs oxide confinement layer 11 and p-Al z2 GaAs high refractive index layer 12, p-Al 0.98A second alumina layer is formed on the outer periphery of the GaAs oxide confinement layer 11 through a wet oxidation process. Here, z1 and z2 represent the Al composition in the corresponding materials, respectively.

[0096] In this embodiment, z1 = z2 = 0.05, ultimately resulting in a 940nm vertical-cavity surface-emitting laser. The n-lower oxide confinement layer and the p-upper oxide confinement layer then form a symmetrical structure.

[0097] Specifically, in this embodiment, the n-face electrode layer 17 includes gold and nickel layers arranged sequentially from bottom to top, and is located below the thinned and polished n-GaAs substrate;

[0098] The substrate layer 1 is an n-GaAs substrate, which has undergone a thinning and polishing process, has a thickness of 120 μm, and a doping concentration of 2 × 10⁻⁶. 18 cm -3 , doped with Si.

[0099] The buffer layer 2 is an n-GaAs buffer layer with a thickness of 150 nm and a doping concentration of 2 × 10⁻⁶. 18 cm -3 , doped with Si.

[0100] Furthermore, an AlGaAs transition layer is disposed above the buffer layer 2, with the Al composition linearly varying from 0 to 0.05 and a doping concentration of 2 × 10⁻⁶. 18 cm -3 , doped with Si.

[0101] The n-DBR layer 3 consists of 43 pairs of n-Al z3 GaAs high refractive index layer and n-Al 0.9 The GaAs low-refractive-index layers are periodically overlapped; among them, n-Al z3 The thickness of the GaAs high refractive index layer is λ / 4n. H1 -20nm, z3 satisfies: 1.424 + 1.247z3 > 1240 / (λ-50); n-Al 0.9 The thickness of the GaAs low refractive index layer is λ / 4n. L1 –20nm; λ is the emission wavelength of the VCSEL, n H1 For n-Al z3 The refractive index of the GaAs high-refractive-index layer, n L1 For n-Al 0.9 The refractive index of the GaAs low-refractive-index layer.

[0102] Furthermore, for each layer n-Al z3 Above each GaAs high-refractive-index layer, a 20 nm n-AlGaAs transition layer is formed, in which the Al composition linearly changes from z3 to 0.9; similarly, each n-Al layer...0.9 Above the low-refractive-index GaAs layer, a 20nm n-AlGaAs transition layer is set, with the Al composition linearly varying from 0.9 to z3.

[0103] Specifically, the n-DBR layer 3 consists of 43 pairs of Al 0.05 GaAs / Al 0.9 GaAs is formed by periodic overlapping, Al 0.05 The GaAs thickness is 44.3 nm, and the Al... 0.9 The GaAs thickness is 56.9 nm, and each Al layer... 0.05 A 20nm AlGaAs transition layer is formed on top of GaAs, with the Al composition of the transition layer linearly varying from 0.05 to 0.9; similarly, each Al layer... 0.9 A 20nm AlGaAs transition layer is disposed on top of GaAs, with the Al composition linearly varying from 0.9 to 0.05; in the n-DBR layer 3, the doping concentration of the three pairs of n-DBRs near the active region is 1×10⁻⁶. 18 cm -3 The remaining 40 pairs of n-DBR have a doping concentration of 2×10⁻⁶. 18 cm -3 , doped with Si.

[0104] The n-Al z1 The GaAs high-refractive-index layer 4 has a thickness of 19.6 nm and a doping concentration of 1 × 10⁻⁶. 18 cm -3 , doped with Si.

[0105] Furthermore, the n-Al z1 Above the GaAs high refractive index layer 4, a 20 nm transition layer is formed, with the Al composition linearly varying from 0.05 to 0.9 and a doping concentration of 1 × 10⁻⁶. 18 cm -3 , doped with Si.

[0106] The n-Al 0.98 The GaAs oxide confinement layer 5 has a thickness of 30 nm and a doping concentration of 1 × 10⁻⁶. 18 cm -3 , doped with Si.

[0107] The n-Al 0.9 The GaAs low-refractive-index layer 6 has a thickness of 76.9 nm and a doping concentration of 1 × 10⁶. 18 cm -3 , doped with Si.

[0108] The lower space layer 7 is an AlGaAs lower space layer with a thickness of 114.1 nm. The Al composition changes linearly from 0.9 to 0.05 and is undoped.

[0109] The multi-quantum well active region 8 consists of 3.5 pairs of In 0.15 GaAs / Al 0.05 GaAs quantum well composition, In 0.15 The GaAs quantum well layer is 8 nm thick, and Al 0.05 The GaAs quantum barrier layer is 8 nm thick, with 4 quantum barrier layers and 3 quantum well layers.

[0110] The upper space layer 9 is an AlGaAs upper space layer with a thickness of 114.1 nm and an Al composition that linearly changes from 0.05 to 0.9.

[0111] p-Al 0.9 The GaAs low-refractive-index layer 10 has a thickness of 76.9 nm and a doping concentration of 1 × 10⁻⁶. 18 cm -3 , doped with C.

[0112] p-Al 0.98 The GaAs oxide confinement layer 11 has a thickness of 30 nm and a doping concentration of 1 × 10⁻⁶. 18 cm -3 , doped with C.

[0113] Furthermore, the p-Al 0.98 A 20 nm AlGaAs transition layer is disposed on top of the GaAs oxide confinement layer 11, with the Al composition linearly varying from 0.9 to 0.05.

[0114] p-Al z2 The GaAs high refractive index layer 12 has a thickness of 19.6 nm and a doping concentration of 1 × 10⁻⁶. 18 cm -3 Add C;

[0115] p-Al z2 A 20 nm AlGaAs transition layer is disposed on top of the GaAs high refractive index layer 12, with the Al composition linearly varying from 0.05 to 0.9 and a doping concentration of 1 × 10⁻⁶. 18 cm -3 Add C;

[0116] The p-DBR layer consists of 23 pairs of p-Al 0.9 GaAs low refractive index layer and p-Al z4 The high-refractive-index GaAs layers are periodically overlapped; among them, p-Al z4 The thickness of the GaAs high refractive index layer is λ / 4n. H2 -20nm, z4 satisfies: 1.424 + 1.247z4 > 1240 / (λ-50); p-Al 0.9 The thickness of the GaAs low refractive index layer is λ / 4n.L2 –20nm; λ is the emission wavelength of the VCSEL, n H2 For n-Al z4 The refractive index of the GaAs high-refractive-index layer, n L2 For n-Al 0.9 The refractive index of the GaAs low-refractive-index layer;

[0117] Each layer of p-Al z4 Above each GaAs high-refractive-index layer, a 20nm AlGaAs transition layer is formed, with the Al composition linearly varying from z4 to 0.9; similarly, each p-Al layer... 0.9 Above the low-refractive-index GaAs layer, a 20nm p-AlGaAs transition layer is set, with the Al composition linearly varying from 0.9 to z4; the topmost p-Al layer... z4 A 30nm p-AlGaAs transition layer is set on top of the GaAs high refractive index layer, with the Al composition linearly changing from z4 to 0 and the doping concentration increasing from 3×10⁻⁶. 18 cm -3 Linear gradient to 2×10 19 cm -3 z3 and z4 represent the Al components in the corresponding materials, respectively.

[0118] Specifically, in this embodiment, z4 = z3 = 0.05. In the p-DBR layer, p-Al 0.9 The GaAs low-refractive-index layer is 56.9 nm thick, p-Al z2 The GaAs high-refractive-index layer 12 has a thickness of 44.3 nm, and the three pairs of p-DBR near the active region have a doping concentration of 1 × 10⁻⁶. 18 cm -3 The doping concentration of its 20p-DBR is 3×10⁻⁶. 18 cm -3 , doped with C.

[0119] The contact layer 14 is a p-GaAs contact layer with a thickness of 100 nm and a doping concentration of 2 × 10⁻⁶. 19 cm -3 Add C;

[0120] The p-side electrode layer comprises titanium, platinum, and gold layers arranged sequentially from bottom to top. In this embodiment, the electrode of the p-side electrode layer is annular, with its center coinciding with the center of the n-lower oxide confinement structure layer, and its inner diameter being larger than that of n-Al. 0.98 GaAs oxide confinement layer and p-Al 0.98 The diameter of the GaAs oxide confinement layer. Specifically, such as... Figure 2 As shown, in this embodiment, the inner diameter of the annular electrode in the p-side electrode layer is 8 μm, and the outer diameter is 35 μm. The diameter of the oxide confinement layer is 4–6 μm.

[0121] In this embodiment, the n-lower oxide confinement structure layer, lower space layer 7, quantum well active region 8, upper space layer 9, p-upper oxide confinement structure layer, p-DBR layer 13, and contact layer 14 above the n-DBR layer 3 form a cylindrical platform with a diameter of 40 μm. The annular electrode of the p-surface electrode layer is located at the center of the upper surface of the cylindrical platform.

[0122] In this embodiment, the thicknesses of the lower spatial layer 7, the quantum well active region 8, and the upper spatial layer 9 satisfy the following:

[0123]

[0124] Among them, h i n represents the actual thickness of each layer. i λ represents the refractive index of each layer, m is a positive integer not greater than 5, and λ is the emission wavelength of the VCSEL.

[0125] In this embodiment, n-Al 0.98 GaAs oxide confinement layer and p-Al 0.98 The outer periphery of the GaAs oxide confinement layer is aluminum oxide, while only the central oxide pore region is Al. 0.98 In GaAs, the centers of the oxide holes, the p-plane annular electrode, and the central axis of the cylindrical frustum coincide.

[0126] Example 2

[0127] like Figure 3 As shown, Embodiment 2 of the present invention provides a 940nm vertical cavity surface emission laser. Similar to Embodiment 1, it includes an n-face electrode layer 17, a substrate layer 1, a buffer layer 2, and an n-DBR layer 3 arranged sequentially from bottom to top. A SiO2 insulating layer 16 is disposed on the outer periphery of the n-DBR layer 3. An n-lower oxide confinement structure layer forming a cylinder, a lower space layer 7, a quantum well active region 8, an upper space layer 9, a p-upper oxide confinement structure layer, a p-DBR layer 13, a contact layer 14, and a p-face electrode layer 15 are arranged sequentially from bottom to top in the center of the SiO2 insulating layer 16.

[0128] Unlike Embodiment 1, in this embodiment, the n-lower oxidation confinement structure layer includes two periods of n-lower oxidation confinement structures, and the p-upper oxidation confinement structure layer includes two periods of p-upper oxidation confinement structures. Therefore, there are two oxidation confinement layers above and below the active region 8, forming two pairs of symmetrical oxidation confinement structures comprising four oxidation confinement layers, whereas Embodiment 1 only has one pair of symmetrical oxidation confinement structures.

[0129] Specifically, n-Al is set in both the first and second pairs of n-DBRs near the active region. 0.98GaAs oxide confinement layer; p-Al is respectively set in the first and second pairs of p-DBRs near the active region. 0.98 The GaAs oxide confinement layer can form two pairs of symmetrical oxide confinement structures with four oxide confinement layers.

[0130] Furthermore, in this invention, the n-low oxidation restriction structure layer may further include two or more n-low oxidation restriction structures, and the p-up oxidation restriction structure layer includes two or more p-up oxidation restriction structures.

[0131] Example 3

[0132] Embodiment 3 of the present invention provides a method for fabricating a vertical-cavity surface-emitting laser as described in Embodiments 1 and 2, including an epitaxial growth step and a chip fabrication step; the epitaxial growth step employs metal-organic chemical vapor deposition (MOCVD) technology and includes the following steps:

[0133] (1) Select (001) n-type GaAs substrate 1 and place it on the graphite tray inside the MOCVD reaction chamber;

[0134] (2) In a hydrogen atmosphere, arsine (AsH3) is introduced, and the temperature of the graphite tray is raised to 680°C under the protection of AsH3. High-temperature baking removes impurities and oxide layers from the substrate surface.

[0135] (3) Lower the temperature to 640℃, introduce trimethylgallium (TMGa) and silane (SiH4), control the growth rate of GaAs buffer layer by adjusting the flow rate of TMGa, control the V / III ratio to 60 by adjusting the flow rate of AsH3, control the doping concentration by adjusting the flow rate of SiH4, and grow n-GaAs buffer layer.

[0136] (4) Maintain the growth temperature at 640℃ and the V / III ratio at 60, introduce trimethylaluminum (TMAl), and gradually increase its flow rate from 0 to Al. 0.05 The required flux for GaAs growth to form an AlGaAs transition layer above the n-GaAs buffer layer;

[0137] (5) Maintain the growth temperature at 640℃, the V / III ratio at 60, and the flow rates of TMGa and TMAl unchanged. Adjust the SiH4 flow rate to achieve a doping concentration of 2×10⁻⁶. 18 cm -3 Al in n-DBR growth 0.05 GaAs high refractive index layer;

[0138] (6) Maintain the growth temperature at 640℃, the V / III ratio at 60, and linearly and gradually change the flow rates of TMGa and TMAl to Al. 0.9The flux required for GaAs growth, forming Al 0.05 AlGaAs transition layer above GaAs high refractive index layer;

[0139] (7) Maintain the growth temperature at 640℃, the V / III ratio at 60, and the flow rates of TMGa and TMAl unchanged. Adjust the flow rate of SiH4 to achieve a doping concentration of 2×10⁻⁶. 18 cm -3 Al in n-DBR growth 0.9 GaAs low refractive index layer;

[0140] (8) Maintain the growth temperature at 640℃, the V / III ratio at 60, and linearly and gradually change the flow rates of TMGa and TMAl to Al. 0.05 The flux required for GaAs growth, forming Al 0.9 AlGaAs transition layer above GaAs low refractive index layer;

[0141] (9) Repeat steps (5) to (8) for 40 cycles to form 40 pairs of doped pairs with a doping concentration of 2×10⁻⁶. 18 cm -3 n-DBR;

[0142] (10) Adjust the SiH4 flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 Repeat steps (5) to (8) for 3 cycles to form 3 pairs of doping concentrations of 1×10 18 cm -3 n-DBR;

[0143] (11) Use the growth parameters in step (5), but shorten the growth time to form n-Al 0.05 GaAs high refractive index layer 04;

[0144] (12) Repeat step (6) to form n-Al 0.05 AlGaAs transition layer above GaAs high refractive index layer;

[0145] (13) Maintain the growth temperature at 640℃, V / III ratio at 60, and switch the flow rates of TMGa and TMAl to Al. 0.98 The required flow rate for GaAs growth was adjusted by controlling the SiH4 flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 , growth of n-Al 0.98 GaAs first oxide confinement layer 5;

[0146] (14) Maintain the growth temperature at 640℃, V / III ratio at 60, and switch the flow rates of TMGa and TMAl to Al. 0.9The required flow rate for GaAs growth was adjusted by controlling the SiH4 flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 , growth of n-Al 0.9 GaAs low refractive index layer 6;

[0147] (15) Maintain the growth temperature at 640℃, V / III ratio at 60, cut off the SiH4 supply, and linearly and gradually change the flow rates of TMGa and TMAl to Al. 0.05 The flux required for GaAs growth, growing AlGaAs lower spatial layer 7;

[0148] (16) Maintaining the growth temperature at 640℃, the V / III ratio at 60, and the constant flow rates of TMGa and TMAl, grow 8 nm Al. 0.05 After GaAs quantum barrier layer growth is complete, the TMGa and TMAl sources are cut off, and growth is paused for 5 seconds.

[0149] (17) Maintain the growth temperature at 640℃ and the V / III ratio at 60. Introduce TMGa and TMIn sources, and adjust the flow rates of TMGa and TMIn sources to make In... 0.15 The growth rate of the GaAs quantum well layer is 0.2 nm / s, and the growth rate of 8 nm In is... 0.15 After the GaAs quantum well layer is grown, the TMGa, TMAl and TMIn sources are cut off, and the growth is paused for 5 seconds.

[0150] (18) Repeat steps (16) and (17) three times to form a 3-cycle In 0.15 GaAs / Al 0.05 GaAs multi-quantum-well active region 8;

[0151] (19) Repeat step (16) to complete the last layer of Al in the active region of the quantum well. 0.05 GaAs quantum barrier layer;

[0152] (20) Maintain the growth temperature at 640℃, V / III ratio at 60, and introduce TMGa and TMAl sources, with the initial flow rate set to Al. 0.05 The flux required for GaAs growth is then linearly gradiented to Al. 0.9 The flux required for GaAs growth forms the upper spatial layer 9 of AlGaAs;

[0153] (21) Maintain the growth temperature at 640℃, reduce the V / III ratio to 40, keep the flow rates of TMGa and TMAl unchanged, introduce carbon tetrabromide (CBr4) as the C doping source, and adjust the CBr4 flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 growth of p-Al 0.9 GaAs low refractive index layer 10;

[0154] (22) Maintain the growth temperature at 640℃, V / III ratio at 40, and switch the flow rates of TMGa and TMAl to Al. 0.98 The required flow rate for GaAs growth is achieved by adjusting the CBr4 flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 30nm p-Al 0.98 GaAs second oxide confinement layer 11;

[0155] (23) Maintain the growth temperature at 640℃, V / III ratio at 40, and switch the initial flow rates of TMGa and TMAl to Al. 0.9 The flux required for GaAs growth is then linearly gradiented to Al. 0.05 The required flux for GaAs growth, to grow a 20nm AlGaAs transition layer;

[0156] (24) Maintain the growth temperature at 640℃, the V / III ratio at 40, and the flow rates of TMGa and TMAl unchanged. Adjust the CBr4 flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 A high-refractive-index layer 12 of p-Al z2GaAs with z2 = 0.05 was grown.

[0157] (25) Maintain the growth temperature at 640℃, V / III ratio at 40, and linearly and gradually increase the flow rates of TMGa and TMAl to Al. 0.9 The required flux for GaAs growth was used to form a 20 nm AlGaAs transition layer, with the Al composition linearly varying from 0.05 to 0.9.

[0158] (26) Maintain the growth temperature at 640℃, the V / III ratio at 40, and the flow rates of TMGa and TMAl unchanged. Adjust the CBr4 flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 p-Al in p-DBR growth 0.9 GaAs low refractive index layer;

[0159] (27) Maintain the growth temperature at 640℃, V / III ratio at 40, and linearly and gradually increase the flow rates of TMGa and TMAl to Al. 0.05 The required flux for GaAs growth was used to form a 20 nm AlGaAs transition layer, with the Al composition linearly varying from 0.9 to 0.05.

[0160] (28) Maintain the growth temperature at 640℃, the V / III ratio at 40, and the flow rates of TMGa and TMAl unchanged. Adjust the CBr4 flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 p-Al in p-DBR growth0.05 GaAs high refractive index layer;

[0161] (29) Repeat steps (25) to (28) for 3 cycles to form 3 pairs of doping concentrations of 1×10 18 cm -3 p-DBR;

[0162] (30) Adjust the CBr4 flow rate to achieve a doping concentration of 3 × 10⁻⁶. 18 cm -3 Repeat steps (25) to (28) for 20 cycles to form 20 pairs of doped pairs with a doping concentration of 3×10⁻⁶. 18 cm -3 p-DBR, completing the growth of p-DBR 13;

[0163] (31) The growth temperature decreased linearly from 640℃ to 580℃, the flow rate of TMAl decreased linearly to 0, the V / III ratio decreased linearly to 30, the CBr4 flow rate decreased linearly to the flow rate required for doping the p+GaAs contact layer, forming an AlGaAs transition layer from p-DBR to the p+GaAs contact layer. The Al composition decreased linearly from 0.05 to 0, and the doping concentration decreased from 3×10 18 cm -3 Linear gradient to 2×10 19 cm -3 ;

[0164] (32) Keep the growth temperature at 580℃ and the V / III ratio at 30, cut off TMAl, keep the flow rates of TMGa and CBr4 constant, and grow p+GaAs contact layer 14.

[0165] (33) Cut off TMGa and CBr4, cool naturally to room temperature, and then cut off AsH3 to complete the epitaxial wafer growth.

[0166] Next is the chip manufacturing process:

[0167] (34) The epitaxial wafer is cleaned using the standard epitaxial wafer cleaning process;

[0168] (35) A photolithography + development process is used to form the pattern of the p-side ring electrode, retaining the photoresist outside the p-side ring electrode area and removing the photoresist in the p-side ring electrode area.

[0169] (36) Deposit p-plane metal using electron beam evaporation or magnetron sputtering processes;

[0170] (37) The metal outside the glass ring electrode is removed by adhesive peeling process, leaving the metal in the ring electrode area to form the p-side ring electrode 15.

[0171] (38) A VCSEL cylindrical mesa pattern is formed on the wafer surface using photolithography and development process, leaving the photoresist in the cylindrical mesa area and removing the photoresist outside the cylindrical mesa.

[0172] (39) A cylindrical mesa was etched using a dry etching process until the n-DBR was reached, exposing the p-Al. 0.98 The sides of the first and second oxide confinement layers of GaAs are then removed, followed by the removal of the photoresist on the cylindrical mesa.

[0173] (40) Chemical polishing process is used to treat the sidewalls of the cylindrical mesa to eliminate the etching damage to the sidewalls;

[0174] (41) The two oxide confinement layers are oxidized by wet oxidation process to form symmetrical oxide pores with a diameter of 6 μm, that is, the diameter of the two oxide confinement layers is 6 μm; specifically, water vapor is carried into the reaction chamber by nitrogen gas, and the oxygen atoms in the water and Al atoms in the two oxide confinement layers AlGaAs form aluminum oxide.

[0175] (42) A SiO2 insulating layer was deposited using plasma chemical vapor deposition (PECVD). The thickness of the insulating layer was slightly greater than the height of the cylindrical mesa to protect the sidewalls of the cylindrical mesa.

[0176] (43) The cylindrical mesa is overlaid using a photolithography + development process to remove the photoresist on the upper surface of the cylindrical mesa, while retaining the photoresist outside the cylindrical mesa area to protect the SiO2 insulating layer.

[0177] (44) The SiO2 insulating layer on the upper surface of the cylindrical mesa is removed by wet etching process to expose the p-side ring electrode, and then all photoresist is removed.

[0178] (45) The lead wires and Pad pattern of the p-side electrode are formed by photolithography and development process;

[0179] (46) Deposit p-plane metal using electron beam evaporation or magnetron sputtering processes;

[0180] (47) The photoresist and metal on the wafer surface are removed by a stripping process to form p-side electrode leads and Pad;

[0181] (48) The n-GaAs substrate was thinned to 120 μm by a grinding process;

[0182] (49) Polishing process is used to polish the back side of the n-GaAs substrate;

[0183] (50) Metal is deposited on the back side of the n-GaAs substrate by electron beam evaporation or magnetron sputtering to form an n-surface electrode layer 17;

[0184] (51) The n-side electrode and the p-side electrode are alloyed by high-temperature annealing process to form an ohmic contact with the semiconductor.

[0185] (52) Dicing and splitting to form a single tube or array chip, thus completing the fabrication of GaAs-based VCSEL chips.

[0186] Furthermore, when it is necessary to fabricate the vertical-cavity surface-emitting laser including two pairs of symmetric oxide-confined structures as in Example 2, only the following process adjustments are required:

[0187] In the epitaxial growth step, an additional n-lower oxide confinement structure and a p-upper oxide confinement structure are grown, so that oxide confinement layers are grown in both pairs of n-type DBRs and p-type DBRs near the active region.

[0188] In the chip manufacturing process, due to the addition of a pair of symmetrical oxide confinement layers, the etching depth needs to be increased by the depth of two pairs of n-type DBRs during the dry etching process to form the cylindrical mesa of VCSEL, so as to ensure that the sides of the two pairs of symmetrical oxide confinement layers are exposed.

[0189] like Figure 4 The figure shows a comparison of the PIV curves of the vertical-cavity surface-emitting lasers of Embodiments 1 and 2 of this invention with those of a vertical-cavity surface-emitting laser with a single oxide confinement layer structure. The single oxide confinement structure refers to a structure with only p-oxide confinement and no n-oxide confinement, and the p-oxide confinement structure has only one period. As can be seen from the figure, the optical power of the vertical-cavity surface-emitting laser of this invention is significantly increased. Figure 5 The figure shows a comparison of the electro-optical conversion efficiency of the vertical cavity surface-emitting lasers of Embodiments 1 and 2 of the present invention and the vertical cavity surface-emitting laser with a single oxide confinement layer structure. As can be seen from the figure, the electro-optical conversion efficiency of the vertical cavity surface-emitting laser of the present invention is also significantly increased. Figure 6 The diagram shows a comparison of the mode distribution of the vertical cavity surface-emitting lasers of Embodiments 1 and 2 of the present invention with that of a vertical cavity surface-emitting laser with a single oxide confinement layer structure. As can be seen from the diagram, by changing the number of oxide confinement layers, the number and distribution of transverse modes can be changed. Therefore, the present invention can also realize mode control of the vertical cavity surface-emitting laser.

[0190] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A vertical-cavity surface-emitting laser, characterized in that, The structure includes, from bottom to top, an n-face electrode layer, a substrate layer, a buffer layer, and an n-DBR layer. A SiO2 insulating layer is disposed on the outer periphery of the n-DBR layer. From bottom to top, an n-lower oxide confinement structure layer, a lower space layer, a quantum well active region, an upper space layer, a p-upper oxide confinement structure layer, a p-DBR layer, a contact layer, and a p-face electrode layer are disposed in the center of the SiO2 insulating layer, forming a cylindrical platform. The n-low oxidation confinement structure layer includes at least one periodic n-low oxidation confinement structure, wherein the n-low oxidation confinement structure is arranged sequentially from bottom to top as n-Al z1 GaAs high refractive index layer, n-Al 0.98 GaAs oxide confinement layer and n-Al 0.9 GaAs low refractive index layer, n-Al 0.98 A first alumina layer was formed on the outer periphery of the GaAs oxide confinement layer by a wet oxidation process. The p-on-oxidation confinement structure layer includes at least one periodic p-on-oxidation confinement structure, and the p-on-oxidation confinement structure includes p-Al atoms arranged sequentially from bottom to top. 0.9 GaAs low refractive index layer, p-Al 0.98 GaAs oxide confinement layer and p-Al z2 GaAs high refractive index layer, p-Al 0.98 A second alumina layer was formed on the outer periphery of the GaAs oxide confinement layer by a wet oxidation process. z1 and z2 represent the Al composition in the corresponding materials, respectively, and z1=z2=0.

05.

2. A vertical-cavity surface-emitting laser according to claim 1, characterized in that, The n-Al 0.98 The thickness of the GaAs oxide confinement layer is 30 nm, and the p-Al 0.98 The thickness of the GaAs oxide confinement layer is 30 nm.

3. A vertical-cavity surface-emitting laser according to claim 1, characterized in that, The n-Al 0.98 The doping concentration of the GaAs oxide confinement layer is 1×10⁻⁶. 18 cm -3 Si-doped; the p-Al 0.98 The doping concentration of the GaAs oxide confinement layer is 1×10⁻⁶. 18 cm -3 , doped with C.

4. A vertical-cavity surface-emitting laser according to claim 1, characterized in that, The n-Al z1 GaAs high refractive index layer and n-Al 0.98 An n-AlGaAs transition layer is also provided between the GaAs oxide confinement layers, and its Al composition gradually changes from z1 to 0.

9. p-Al 0.98 GaAs oxide confinement layer and p-Al z2 A p-AlGaAs transition layer is also provided between the GaAs high refractive index layers, with its Al composition linearly varying from 0.9 to z2.

5. A vertical-cavity surface-emitting laser according to claim 1, characterized in that, The n-sided electrode layer includes gold and nickel layers arranged sequentially from bottom to top; The substrate is an n-GaAs substrate with a thickness of 120 μm and a doping concentration of 2×10⁻⁶. 18 cm -3 Si-doped; The buffer layer is an n-GaAs buffer layer with a thickness of 150 nm and a doping concentration of 2 × 10⁻⁶. 18 cm -3 Si-doped; The lower space layer is an AlGaAs lower space layer with a thickness of 114.1 nm and no doping. The upper space layer is an AlGaAs upper space layer with a thickness of 114.1 nm; The contact layer is a p-GaAs contact layer with a thickness of 100 nm and a doping concentration of 2 × 10⁻⁶. 19 cm -3 Add C; The p-side electrode layer comprises layers of titanium, platinum, and gold arranged sequentially from bottom to top.

6. A vertical-cavity surface-emitting laser according to claim 1, characterized in that, The p-plane electrode layer is annular, with its center coinciding with the center of the n-lower oxide confinement structure layer, and its inner diameter is larger than that of n-Al. 0.98 GaAs oxide confinement layer and p-Al 0.98 The radius of the GaAs oxide confinement layer.

7. A vertical-cavity surface-emitting laser according to claim 1, characterized in that, The n-DBR layer consists of 43 pairs of n-Al z3 GaAs high refractive index layer and n-Al 0.9 The GaAs low-refractive-index layers are periodically overlapped; among them, n-Al z3 The thickness of the GaAs high refractive index layer is λ / 4n. H1 -20 nm, z3 satisfies: 1.424 + 1.247z3 > 1240 / (λ-50); n-Al 0.9 The thickness of the GaAs low refractive index layer is λ / 4n. L1 – 20 nm; λ is the emission wavelength of the VCSEL, n H1 For n-Al z3 The refractive index of the GaAs high-refractive-index layer, n L1 For n- Al 0.9 The refractive index of the GaAs low-refractive-index layer; Each layer n-Al z3 Above each GaAs high-refractive-index layer, a 20 nm n-AlGaAs transition layer is formed, in which the Al composition linearly changes from z3 to 0.9; similarly, each n-Al layer... 0.9 Above the GaAs low refractive index layer, a 20 nm n-AlGaAs transition layer is set, with the Al composition linearly varying from 0.9 to z3. The p-DBR layer consists of 23 pairs of p-Al 0.9 GaAs low refractive index layer and p-Al z4 The high-refractive-index GaAs layers are periodically overlapped; among them, p-Al z4 The thickness of the GaAs high refractive index layer is λ / 4n. H2 -20 nm, z₄ satisfies: 1.424 + 1.247z₄ > 1240 / (λ-50); p-Al 0.9 The thickness of the GaAs low refractive index layer is λ / 4n. L2 – 20 nm; λ is the emission wavelength of the VCSEL, n H2 For n-Al z4 The refractive index of the GaAs high-refractive-index layer, n L2 For n- Al 0.9 The refractive index of the GaAs low-refractive-index layer; Each layer of p-Al z4 Above each GaAs high-refractive-index layer, a 20 nm AlGaAs transition layer is formed, with the Al composition linearly varying from z4 to 0.9; similarly, each p-Al layer... 0.9 Above the low-refractive-index GaAs layer, a 20 nm p-AlGaAs transition layer is set, with the Al composition linearly varying from 0.9 to z4; the topmost p-Al layer... z4 A 30 nm p-AlGaAs transition layer is set on top of the GaAs high refractive index layer, with the Al composition linearly changing from z4 to 0 and the doping concentration increasing from 3 × 10⁻⁶. 18 cm -3 Linear gradient to 2×10 19 cm -3 z3 and z4 represent the Al components in the corresponding materials, respectively.

8. A vertical-cavity surface-emitting laser according to claim 7, characterized in that, z3=z4.

9. A method for fabricating a vertical-cavity surface-emitting laser according to any one of claims 1 to 8, characterized in that, It includes an epitaxial growth step and a chip fabrication step; the epitaxial growth step uses metal-organic chemical vapor deposition technology for epitaxial growth, and includes the following steps: Step 1: Select an (001) n-type GaAs substrate and place it on a graphite tray inside the MOCVD reaction chamber; Step 2: In a hydrogen atmosphere, arsine (AsH3) is introduced, and the temperature of the graphite tray is raised to 680 ℃ under the protection of AsH3. High-temperature baking removes impurities and oxide layers from the substrate surface. Step 3: Lower the temperature to 640 ℃, introduce trimethylgallium (TMGa) and silane (SiH4), control the growth rate of GaAs buffer layer by adjusting the flow rate of TMGa, control the V / III ratio to 60 by adjusting the flow rate of AsH3, and control the doping concentration by adjusting the flow rate of SiH4 to grow n-GaAs buffer layer. Step 4: Maintain the growth temperature at 640 ℃ and the V / III ratio at 60, introduce trimethylaluminum (TMAl), and gradually increase its flow rate from 0 to Al. z3 The required flux for GaAs growth to form an AlGaAs transition layer above the n-GaAs buffer layer; Step 5: Maintain the growth temperature at 640 ℃, the V / III ratio at 60, and the flow rates of TMGa and TMAl unchanged. Adjust the SiH4 flow rate to achieve a doping concentration of 2 × 10⁻⁶. 18 cm -3 Al in n-DBR growth z3 GaAs high refractive index layer; Step 6: Maintain the growth temperature at 640 ℃, V / III ratio at 60, and linearly and gradually increase the flow rates of TMGa and TMAl to Al. 0.9 The flux required for GaAs growth, forming Al z3 AlGaAs transition layer above GaAs high refractive index layer; Step 7: Maintain the growth temperature at 640 ℃, the V / III ratio at 60, and the flow rates of TMGa and TMAl unchanged. Adjust the SiH4 flow rate to achieve a doping concentration of 2 × 10⁻⁶. 18 cm -3 Al in n-DBR growth 0.9 GaAs low refractive index layer; Step 8: Maintain the growth temperature at 640 ℃, V / III ratio at 60, and linearly and gradually increase the flow rates of TMGa and TMAl to Al. z3 The flux required for GaAs growth, forming Al 0.9 AlGaAs transition layer above GaAs low refractive index layer; Step 9: Repeat steps 5-8 to form 40 pairs of doped pairs with a doping concentration of 2×10⁻⁶. 18 cm -3 n-DBR; Step 10: Adjust the SiH4 flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 Repeat steps 5-8 to form 3 pairs of doped pairs with a doping concentration of 1×10⁻⁶. 18 cm -3 n-DBR; Step 11: Using the growth parameters from Step 5, but shortening the growth time, grow n-Al in the n-under-oxidation-restricted structure. z1 GaAs high refractive index layer; Step 12: Repeat step 6 to form n-Al z1 AlGaAs transition layer above GaAs high refractive index layer; Step 13: Maintain the growth temperature at 640 ℃, V / III ratio at 60, and switch the flow rates of TMGa and TMAl to Al. 0.98 The required flow rate for GaAs growth was adjusted by controlling the SiH4 flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 n-Al in the n-oxidation-restricted structure O4 0.98 GaAs under-oxidation confinement layer 05; Step 14: Maintain the growth temperature at 640 ℃, V / III ratio at 60, and switch the flow rates of TMGa and TMAl to Al. 0.9 The required flow rate for GaAs growth was adjusted by controlling the SiH4 flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 n-Al in the n-oxidation-restricted structure of growth 0.9 GaAs low refractive index layer; Step 15: Maintain the growth temperature at 640 ℃ and the V / III ratio at 60, cut off the SiH4 supply, and linearly and gradually change the flow rates of TMGa and TMAl to the flow rates required for the growth of the AlGaAs quantum barrier layer to grow the AlGaAs lower space layer. Step 16: Maintain the growth temperature at 640 ℃, the V / III ratio at 60, and the TMGa and TMAl flow rates unchanged to grow the AlGaAs quantum barrier layer. After the growth is complete, cut off the TMGa and TMAl sources and pause the growth for 5 seconds. Step 17: Maintain the growth temperature at 640 ℃ and the V / III ratio at 60. Introduce TMGa, TMAl and TMIn sources and adjust the flow rates of TMGa, TMAl and TMIn sources to make the growth rate of InGaAlAs quantum well layer 0.2 nm / s. After the quantum well layer is grown, cut off the TMGa, TMAl and TMIn sources and pause the growth for 5s. Step 18: Repeat steps 16-17 multiple times to form the active region of the quantum well; Step 19: Repeat step 16 to complete the last AlGaAs quantum barrier layer of the quantum well active region; Step 20: Maintain the growth temperature at 640 ℃ and the V / III ratio at 60. Introduce TMGa and TMAl sources, setting the initial flow rate to the flow rate required for AlGaAs quantum barrier layer growth, and then linearly gradually increasing it to Al. 0.9 The flux required for GaAs growth forms the space layer on top of AlGaAs; Step 21: Maintain the growth temperature at 640 ℃, reduce the V / III ratio to 40, keep the flow rates of TMGa and TMAl unchanged, introduce carbon tetrabromide as the C doping source, and adjust the carbon tetrabromide flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 p-Al in p-oxidation-restricted structures growing 0.9 GaAs low refractive index layer; Step 22: Maintain the growth temperature at 640 ℃ and the V / III ratio at 40, and switch the flow rates of TMGa and TMAl to Al. 0.98 The required flow rate for GaAs growth is achieved by adjusting the carbon tetrabromide flow rate to maintain a doping concentration of 1×10⁻⁶. 18 cm -3 p-Al in p-oxidation-restricted structures growing 0.98 GaAs oxide confinement layer; Step 23: Maintain the growth temperature at 640 ℃ and the V / III ratio at 40. Switch the initial flow rates of TMGa and TMAl to Al. 0.9 The flux required for GaAs growth is then linearly gradiented to Al. z2 The required flux for GaAs growth, to grow a 20 nm AlGaAs transition layer; Step 24: Maintain the growth temperature at 640 ℃, the V / III ratio at 40, and the flow rates of TMGa and TMAl unchanged. Adjust the CBr4 flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 p-Al in p-oxidation-restricted structures growing z2 GaAs high refractive index layer; Step 25: Maintain the growth temperature at 640 ℃, V / III ratio at 40, and linearly and gradually increase the flow rates of TMGa and TMAl to Al. 0.9 The required flux for GaAs growth is used to form a 20 nm AlGaAs transition layer; Step 26: Maintain the growth temperature at 640 ℃, the V / III ratio at 40, and the flow rates of TMGa and TMAl unchanged. Adjust the CBr4 flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 p-Al in p-DBR growth 0.9 GaAs low refractive index layer; Step 27: Maintain the growth temperature at 640 ℃, V / III ratio at 40, and linearly and gradually increase the flow rates of TMGa and TMAl to Al. z4 The required flux for GaAs growth is used to form a 20 nm AlGaAs transition layer; Step 28: Maintain the growth temperature at 640 ℃, the V / III ratio at 40, and the flow rates of TMGa and TMAl unchanged. Adjust the CBr4 flow rate to achieve a doping concentration of 1×10⁻⁶. 18 cm -3 p-Al in p-DBR growth z4 GaAs high refractive index layer; Step 29: Repeat steps 25-28 to form 3 pairs of doped pairs with a doping concentration of 1×10⁻⁶. 18 cm -3 p-DBR; Step 30: Adjust the CBr4 flow rate to achieve a doping concentration of 3 × 10⁻⁶. 18 cm -3 Repeat steps 25-28 to form 20 pairs of doped pairs with a doping concentration of 3×10⁻⁶. 18 cm -3 The p-DBR was used to complete the growth of p-DBR 09; Step 31: The growth temperature is linearly decreased from 640 ℃ to 580 ℃, the TMAl flow rate is linearly and gradually reduced to 0, the V / III ratio is linearly and gradually reduced to 30, and the CBr4 flow rate is linearly and gradually reduced to the flow rate required for p+GaAs contact layer doping, forming an AlGaAs transition layer from p-DBR to p+GaAs contact layer. The Al composition is linearly and gradually reduced from z4 to 0, and the doping concentration is reduced from 3×10 18 cm -3 Linear gradient to 2×10 19 cm -3 ; Step 32: Maintain the growth temperature at 580 ℃ and the V / III ratio at 30, cut off the flow rates of TMAl, TMGa and CBr4 and grow the p+GaAs contact layer. Step 33: Cut off TMGa and CBr4, allow to cool naturally to room temperature, then cut off AsH3 to complete the epitaxial wafer growth; The chip manufacturing process includes: Step 34: Clean the epitaxial wafer using the standard epitaxial wafer cleaning process; Step 35: Use photolithography and development process to form the electrode pattern of the p-side electrode layer, retain the photoresist outside the electrode area of ​​the p-side electrode layer, and remove the photoresist in the electrode area of ​​the p-side electrode layer. Step 36: Deposit the metal layer corresponding to the p-side electrode using electron beam evaporation or magnetron sputtering processes; Step 37: Use an adhesive peeling process to remove the metal outside the glass ring electrode, leaving the metal in the ring electrode area to form a p-side ring electrode; Step 38: Use photolithography and development to form a cylindrical pattern on the wafer surface, leaving the photoresist in the cylindrical area, and remove the photoresist outside the cylindrical area; Step 39: Use a dry etching process to etch a cylindrical mesa down to the n-DBR layer, and then remove the photoresist from the cylindrical mesa. Step 40: Use chemical polishing to treat the sidewalls of the cylindrical mesa to eliminate etching damage to the sidewalls; Step 41: The oxide confinement layer in the n-lower oxide confinement structure layer and the p-upper oxide confinement structure layer is oxidized by a wet oxidation process to form an aluminum oxide layer on the outer periphery of the oxide confinement layer; Step 42: Deposit a SiO2 insulating layer using plasma chemical vapor deposition technology. The thickness of the SiO2 insulating layer is greater than the height of the cylindrical platform to protect the sidewalls of the cylindrical platform. Step 43: Use photolithography + development process to overlay the cylindrical stage, remove the photoresist on the upper surface of the cylindrical stage, and retain the photoresist outside the cylindrical stage area to protect the SiO2 insulating layer; Step 44: Use a wet etching process to remove the SiO2 insulating layer on the upper surface of the cylindrical stage, exposing the p-side annular electrode, and then remove all photoresist. Step 45: Use photolithography and development to form the lead wires and pad pattern of the p-side electrode layer; Step 46: Deposit the p-plane metal using electron beam evaporation or magnetron sputtering. Step 47: Use a stripping process to remove the photoresist and metal from the wafer surface to form p-side electrode leads and pads; Step 48: Thin the n-GaAs substrate to 120 μm using a polishing process; Step 49: Polish the back side of the n-GaAs substrate using a polishing process; Step 50: Deposit metal on the back side of the n-GaAs substrate using electron beam evaporation or magnetron sputtering to form an n-face electrode; Step 51: Alloy the n-side electrode and p-side electrode using a high-temperature annealing process to form an ohmic contact with the semiconductor; Step 52: Dicing and splitting to form a single-tube or array chip, completing the fabrication of GaAs-based VCSEL chips.

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