Structure of a trench-gate power MOSFET and method for manufacturing a trench-gate power MOSFET

Abstract

The present application discloses a structure of a trench-gate power MOSFET and a manufacturing method thereof. The structure includes: a second epitaxial layer; a strip-shaped P pillar, the length direction of the strip-shaped P pillar being parallel to the projection direction of the crystal orientation with the most obvious channel effect on the surface of the epitaxial material; a trench gate, including a trench, the trench being parallel to the length direction of the strip-shaped P pillar or perpendicular to the length direction of the strip-shaped P pillar, and filling a filler into the trench to manufacture the trench gate. When the length direction of the trench is parallel to the length direction of the strip-shaped P pillar, the trench is located directly above the strip-shaped P pillar and has the same width as the strip-shaped P pillar. When the length direction of the trench is perpendicular to the length direction of the strip-shaped P pillar, the width of the trench is not related to the strip-shaped P pillar; a surface source region. The advantage of the present application is that it can reduce the manufacturing steps and simplify the processing technology.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a structure of a trench gate power MOSFET and a method for manufacturing the trench gate power MOSFET. Background Art

[0002] Silicon carbide (SiC) MOSFET devices are currently widely used in high-voltage power electronic equipment due to their high withstand voltage, low loss, and high efficiency. At present, silicon carbide power devices are mainly positioned in scenarios with power between 1kW and 500kW and operating frequencies between 10kHz and 100MHz, especially in some applications with high requirements for energy efficiency and space size, such as electric vehicle onboard chargers and electric drive systems, charging piles, photovoltaic micro inverters, electric vehicles, etc. The use of silicon carbide MOSFET to replace silicon IGBT is an inevitable trend in the development of electric drive systems. Most of the electric vehicles launched on the market in recent years have adopted electric drive and electronic control systems based on silicon carbide power devices.

[0003] Silicon carbide (SiC) MOSFET devices are mainly divided into planar gate MOSFET device structures and trench gate MOSFET device structures in terms of structure. Among them, the planar gate structure has a simpler processing technology and higher maturity, and is the main structure of the current mass-produced SiCMOSFET devices. However, with the continuous improvement of device performance and cost requirements, the larger cell size and higher JFET area resistance of planar gate SiC MOSFET devices limit their further optimization. In comparison, trench gate SiCMOSFET devices change the flow direction of channel current by introducing a trench structure, eliminating the constraints of the JFET area on performance and cell size, and have greater development potential. The performance of the newly released new generation of trench gate SiC MOSFET devices has shown a significant improvement.

[0004] Furthermore, as SiC device technology and processing technology continue to mature, combining the trench gate structure with the charge balance concept (super junction) to form a trench gate SiC MOSFET with a super junction structure will be the ultimate goal of SiC MOSFET device development. At present, in SiC devices, the mainstream super junction implementation plans include: 1) deep trench etching combined with Al ion implantation on the trench sidewall; 2) deep trench etching combined with P-type epitaxial backfill; 3) high-energy Al ion implantation combined with multiple epitaxial growth, etc. The above solutions all have the problem of increased process difficulty and low mass production. Summary of the invention

[0005] In order to solve the above problems in the prior art, the present application provides a structure of a trench gate power MOSFET, a trench gate power MOSFET chip and a method for manufacturing a trench gate power MOSFET.

[0006] First, the present application provides a structure of a trench-gate power MOSFET, including a substrate, a first epitaxial layer, and a P-body region, and further including:

[0007] A second epitaxial layer, where the P-body region is located at the upper part of the surface layer of the second epitaxial layer;

[0008] A strip-shaped P column, the length direction of the strip-shaped P column is parallel to the projection direction of the crystal orientation with the most obvious channel effect on the surface of the epitaxial material, and the depth of the strip-shaped P column penetrates through the P-body region and the second epitaxial layer to reach the first epitaxial layer;

[0009] A trench gate, including a trench, the trench is parallel to the length direction of the strip-shaped P column or perpendicular to the length direction of the strip-shaped P column, the depth of the trench penetrates through the P-body region to reach the second epitaxial layer, and a filler is filled into the trench to manufacture the trench gate;

[0010] A surface source region, located at the surface layer of the P-body region, and further including a surface N++ region and a surface P++ region, the surface N++ region and the surface P++ region are arranged at intervals, and the length direction thereof is perpendicular to the length direction of the trench.

[0011] In the above structure, the second epitaxial layer is formed on the upper half of the first epitaxial layer by ion implantation, wherein the ion implantation method includes at least one high-energy ion implantation or channel implantation, and the direction of the channel implantation is the direction with the most obvious channel effect of the epitaxial material.

[0012] In the above structure, when the length direction of the trench is parallel to the length direction of the strip-shaped P column, the trench is located directly above the strip-shaped P column, and the width is the same as the width of the strip-shaped P column. A P connector with the same width is further included below the surface P++ region, and one end of the P connector is electrically connected to the surface P++ region, and the other end is electrically connected to the strip-shaped P column.

[0013] In the above structure, when the length direction of the trench is perpendicular to the length direction of the strip-shaped P column, the width of the strip-shaped P column is the same as the width of the surface P++ region, and the surface P++ region is electrically connected to the strip-shaped P column.

[0014] In the above structure, the orthographic projection of the second epitaxial layer on the first epitaxial layer completely covers the first epitaxial layer, or only covers the region predetermined as the active area of the chip.

[0015] In the above structure, the P connector is formed by at least one high-energy implantation.

[0016] In the above structure, a P-type doped bottom protection region of the trench gate is further formed at the bottom of the trench of the trench gate. The bottom protection region of the trench is formed after etching the trench and before filling the trench.

[0017] Secondly, the present application also provides a trench gate power MOSFET chip, which has the structure of the trench gate power MOSFET as described above.

[0018] Finally, the present application also provides a method for manufacturing a trench gate power MOSFET, which is used to manufacture the trench gate power MOSFET chip as described above, and includes the following steps:

[0019] Form a second epitaxial layer, and inject N-type ions into the first epitaxial layer with N-type SiC epitaxial material one or more times by ion implantation, so as to form the uniformly doped second epitaxial layer;

[0020] Form strip-shaped P pillars, inject P-type ions into the second epitaxial layer one or more times, the injection direction is the direction with the most obvious channel effect of the epitaxial material, and the injection depth penetrates the second epitaxial layer to reach the first epitaxial layer, so as to form the strip-shaped P pillars;

[0021] Form a P body region, inject P-type ions into the surface layer of the second epitaxial layer multiple times, so as to form the P body region in the upper part of the second epitaxial layer;

[0022] Source surface injection, inject high-concentration P-type ions and high-concentration N-type ions at intervals above the P body region to form strip-shaped surface N++ regions and surface P++ regions that appear at intervals. The length directions of the surface N++ regions and the surface P++ regions are perpendicular or parallel to the length direction of the strip-shaped P pillars;

[0023] Etch the gate trench, etch the trench in a direction parallel or perpendicular to the length direction of the strip-shaped P pillar, and the etching depth penetrates the surface N++ region, the surface P++ region, and the P body region to reach the second epitaxial layer;

[0024] Fabricate the trench gate, fill the trench with a filler, so as to obtain the trench gate.

[0025] In the above manufacturing method, the ion implantation method includes at least one high-energy ion implantation or channel implantation, and the direction of the channel implantation is the direction with the most obvious channel effect of the epitaxial material.

[0026] In the above manufacturing method, when the length direction of the groove is parallel to the length direction of the strip P column, the groove is located directly above the strip P column and its width is consistent with the width of the strip P column. The surface P++ area also includes a P connector with a width consistent with it below the surface P++ area. One end of the P connector is electrically connected to the surface P++ area, and the other end is electrically connected to the strip P column.

[0027] In the above manufacturing method, when the length direction of the groove is perpendicular to the length direction of the strip P column, the width of the strip P column is consistent with the width of the surface P++ region, and the surface P++ region is electrically connected to the strip P column.

[0028] In the above manufacturing method, the orthographic projection of the second epitaxial layer on the first epitaxial layer completely covers the first epitaxial layer, or only covers the area predetermined as the active area of ​​the chip.

[0029] The above manufacturing method further includes, after etching the gate trench, performing ion implantation on the bottom surface of the trench to form a trench bottom protection area.

[0030] Compared with the prior art, the present application has made improvements in both device structure and manufacturing method. Structurally, the present application proposes that the strip P-pillar structure may not be set at the bottom of the groove parallel to the groove direction, and may even intersect the groove direction at 90°, so that the strip P-pillar design and the groove design are independent of each other. In other words, the width of the strip P-pillar and the width of the groove can be independently designed according to their respective design requirements, which can maximize the potential of the super junction structure and the trench gate structure.

[0031] In terms of method, this application breaks through the existing inherent idea of ​​"injection at the bottom of the groove" and proposes a process method of first injection and then groove etching. This method makes the P-column structure design independent of the groove design and etching process. Furthermore, when ion implantation is performed at the bottom of the groove, the injected ions will inevitably be injected into the sidewalls of the groove. By adopting the process method of first injection and then groove etching, the problem of affecting the doping concentration of the body region and the threshold voltage of the device can be completely solved, thereby optimizing the device design and improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 According to some embodiments of the present application, a schematic diagram of basic materials for making trench gate power SiC MOSFET is shown;

[0033] Figure 2a According to some embodiments of the present application, a schematic structural diagram of a second epitaxial layer for manufacturing a trench gate power SiC MOSFET is shown;

[0034] Figure 2b According to some embodiments of the present application, a schematic structural diagram of another second epitaxial layer for fabricating a trench-gate power SiC MOSFET is shown;

[0035] Figure 3 According to some embodiments of the present application, a schematic structural diagram of a strip-shaped P pillar for fabricating a trench-gate power SiC MOSFET is shown;

[0036] Figure 4 According to some embodiments of the present application, a schematic structural diagram of a P body region for fabricating a trench-gate power SiC MOSFET is shown;

[0037] Figure 5 According to some embodiments of the present application, a schematic structural diagram of a P connection body for fabricating a trench-gate power SiC MOSFET is shown;

[0038] Figure 6 According to some embodiments of the present application, a schematic structural diagram of a surface source region for fabricating a trench-gate power SiC MOSFET is shown;

[0039] Figure 7 According to some embodiments of the present application, a schematic structural diagram of a trench for fabricating a trench-gate power SiC MOSFET is shown;

[0040] Figure 8a According to some embodiments of the present application, a schematic structural diagram of a trench bottom protection region for fabricating a trench-gate power SiC MOSFET is shown;

[0041] Figure 8b According to some embodiments of the present application, shown is Figure 8a a schematic diagram of a cross-section of the shown structure;

[0042] Figure 9 According to some embodiments of the present application, a schematic diagram of inner wall deposition for fabricating a trench-gate power SiC MOSFET is shown;

[0043] Figure 10 According to some embodiments of the present application, a schematic diagram of the change in filling deposition for fabricating a trench-gate power SiC MOSFET is shown;

[0044] Figure 11 According to some other embodiments of the present application, a schematic structural diagram of another trench for fabricating a trench-gate power SiC MOSFET is shown;

[0045] Figure 12 According to some other embodiments of the present application, a schematic structural diagram of another strip-shaped P pillar for fabricating a trench-gate power SiC MOSFET is shown;

[0046] Figure 13 According to still other embodiments of the present application, a schematic structural diagram of a surface source region and a strip-shaped P pillar of a trench-gate power SiC MOSFET is shown;

[0047] Figure 14 According to still other embodiments of the present application, a schematic structural diagram of a trench and a trench bottom protection region of a trench-gate power SiC MOSFET is shown;

[0048] Figure 15 According to some embodiments of the present application, a flowchart of a method for fabricating a trench-gate power SiC MOSFET device is shown. Detailed implementation manners

[0049] Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings do not have to be drawn to scale unless otherwise specified.

[0050] In the description of the present application, it should be understood that the orientation or positional relationships indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application.

[0051] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise specifically defined, the meaning of "a plurality" is two or more.

[0052] In the present application, unless otherwise clearly defined and limited, the terms "mounted", "connected", "coupled", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral body; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0053] As used herein, the term "exemplary" means "serving as an example, instance, or illustration". Any embodiment described herein as "exemplary" is not necessarily to be construed as superior or better than other embodiments.

[0054] As used herein, the term "and / or" is merely a description of an association relationship between associated objects, indicating that three relationships may exist.

[0055] In addition, the term "at least one" as used herein means any one of a plurality or any combination of at least two of a plurality. For example, including at least one of A, B, and C may mean including any one or more elements selected from the set consisting of A, B, and C.

[0056] In addition, to better illustrate the present application, numerous specific details are given in the following detailed description. Those skilled in the art should understand that the present application can be implemented without some specific details. In some instances, methods, means, elements, and circuits well-known to those skilled in the art are not described in detail in order to highlight the gist of the present application.

[0057] First, in combination with Figures 1 - 10 and Figure 15 a method for manufacturing a trench-gate power MOSFET will be described, as well as the structural changes of the trench-gate power MOSFET after each step of manufacturing.

[0058] As Figure 1 shown, the epitaxial material to be processed includes a SiC substrate 1 and a first epitaxial layer 2. The first epitaxial layer 2 is a lightly doped epitaxial layer formed on the SiC substrate 1 through an epitaxial growth process. In this embodiment, the doping type of the first epitaxial layer 2 is N-type ion doping.

[0059] Step S1, forming a second epitaxial layer. In some embodiments, N-type ions, such as phosphorus (P) ions, can be implanted into the N-type SiC epitaxial material having the first epitaxial layer 2 one or more times, so as to form a uniformly doped second epitaxial layer 3 in the upper half of the first epitaxial layer 2. And the thickness of the second epitaxial layer 3 is greater than that of the first epitaxial layer 2. The implantation method can be high-energy ion implantation or channel implantation (or called tunnel implantation). The N-type ion concentration in the second epitaxial layer 3 is greater than the N-type ion concentration in the first epitaxial layer 2. Generally speaking, the second epitaxial layer 3 is as Figure 2a shown, that is, the orthographic projection of the second epitaxial layer 3 on the first epitaxial layer 2 completely covers the first epitaxial layer 2. Another more optimal embodiment is as Figure 2bAs shown, the orthographic projection of the second epitaxial layer 3 on the first epitaxial layer 2 may only cover a part of the chip active region. In some embodiments, the depth of the second epitaxial layer 3 may be much greater than the implantation depth that can be achieved by conventional ion implantation. Therefore, the channel implantation method can be adopted, that is, the implantation direction is the direction in which the channeling effect of the epitaxial material is most obvious. This direction is usually parallel to a specific crystal orientation of the epitaxial material. The depth of the second epitaxial layer formed by this method can be 2-5 microns, and the doping concentration is 3E16~2E17. In a preferred embodiment, after channel implantation, the thickness of the second epitaxial layer 3 is 3-4 microns, and the doping concentration is 6E16~8E16. The thickness of the second epitaxial layer 3 can also be understood as the implantation depth during channel implantation, and its formed effect is to increase the ion concentration in the upper half of the first epitaxial layer 2. Specifically, the doping depth of the second epitaxial layer 3 is determined by the highest energy selected during channel implantation, the doping distribution is a uniform distribution, and the doping concentration is determined by the implantation dose.

[0060] Step S2, forming a strip-shaped P column 6. The length direction of the strip-shaped P column 6 is parallel to the projection direction of the crystal orientation with the most obvious channeling effect on the surface of the second epitaxial layer 3. The strip-shaped P column 6 can be formed by implanting P-type ions into the second epitaxial layer 3 one or more times. The P-type ions can be aluminum (Al) ions or boron (B) ions, and the implantation direction is the direction with the most obvious channeling effect. The depth of the strip-shaped P column 6 can be close to or even exceed the thickness of the second epitaxial layer 3 and penetrate into the first epitaxial layer 2. Figure 3 As shown is an example where the strip-shaped P column 6 penetrates into the first epitaxial layer 2. The depth of the strip-shaped P column 6 formed by this method can be 2-5 microns, and the doping concentration is 5E16~3E17. In a preferred embodiment, after channel implantation, the thickness of the strip-shaped P column 6 is 3-4 microns, and the doping concentration is 1E17~2E17.

[0061] Step S3, forming a P body region. As Figure 4 shown, a layer of P body region 4 is also formed inside the second epitaxial layer 3. The P body region 4 can be realized by an ion implantation process. The P body region 4 is located in the upper middle part of the second epitaxial layer 3. The impurity doped in the P body region 4 is P-type doping, such as aluminum (Al) ions. The specific doping concentration can be about 1E17-5E17, and the implantation depth is 0.2-1.0 micron.

[0062] After step S3, there are two different cell structures. One structure is that the long strip groove is parallel to the strip P pillar 6 and located above the strip P pillar 6, and the groove width is the same as the width of the strip P pillar 6. The other structure is that the long strip groove is perpendicular to the strip P pillar 6, and their widths are independent of each other. For both of these structures, additional implantations at the bottom of the groove are required to suppress the concentration of the electric field strength at the corners of the bottom of the groove. In addition, the P-type source highly doped regions and N-type source highly doped regions that appear at intervals on the epitaxial surface are always perpendicular to the groove direction.

[0063] The following steps S4a - S5a illustrate the first structure, that is, the scheme where the groove is parallel to the P pillar. The schematic diagram of the relevant structural changes can be referred to Figures 5 - 8b .

[0064] Step S4a, source surface implantation. The goal of this step is to implant high-concentration P-type ions and high-concentration N-type ions at intervals on the surface part of the second epitaxial layer 3 above the P body region 4, so as to form Figure 6 the surface N++ region 5a and surface P++ region 5b in the form of strips that appear at intervals and are perpendicular to the strip P pillar 6 as shown. The concentrations of both are at the heavily doped level.

[0065] Specifically, it includes:

[0066] 1) As Figure 5 shown, high-energy ion implantation is performed at the position where the surface P++ region 5b is to be formed to form the P connector 11. The concentration of the P connector 11 is generally significantly higher than the concentration of the P body region 4 and is equivalent to the concentration of the P-type protection region at the bottom of the groove to be fabricated later. And the implantation depth of the P connector 11 is greater than the depth of the groove to be processed later. After the groove etching is completed, the P connector 11 remains electrically connected to the P-type protection region at the bottom of the channel. Here, the relationship between the depth of the P connector 11 and the depth of the groove can be explained in combination with Figure 8b . Figure 8b is Figure 8a the cross-sectional view at the position indicated by the green arrow in. As shown in the figure, the depth of the P connector 11 needs to be greater than the groove 7 and connected to the protection region 8 at the bottom of the groove, so that the strip P pillar 6 can be reliably connected to the ground through the source.

[0067] 2) Then Figure 5 shown, continue to perform ion implantation in the top region of the P connector 11 to form the surface P++ region 5b with a doping concentration of P++ (indicating a higher concentration than the P connector 11), as Figure 6As shown. Further, N-type ions are implanted into the region of the surface source region 5 except for the surface P++ region 5b to form a surface N++ region 5a with a concentration of N++ (indicating that the concentration is equivalent to that of the surface P++ region 5b). Among them, the depth of the surface P++ region 5b can be slightly greater than that of the surface N++ region 5a, that is, the depth of the surface P++ region 5b can penetrate the surface source region 5 and reach the P body region 4.

[0068] After performing the above step S4a, the structure shown in Figure 6 is obtained. On the upper surface of the epitaxial material, blue regions with a concentration of P++ and red regions with a concentration of N++ appear alternately to form a surface N++ region 5a and a surface P++ region 5b. Among them, the implantation depth of the high-concentration N-type ions reaches the P body region 4, and the length directions of the surface N++ region 5a and the surface P++ region 5b are perpendicular to the length direction of the strip-shaped P column 6.

[0069] Step S5a, etching the gate trench. The length direction of the gate trench is perpendicular to the length directions of the surface N++ region 5a and the surface P++ region 5b. The etching depth is to penetrate the surface N++ region 5a, the surface P++ region 5b, and the P body region 4 and reach the second epitaxial layer 3, but shallower than the depth of the P connector 11. That is, on the basis of the structure shown in Figure 6 the length direction of the groove 7 is parallel to the length direction of the strip-shaped P column 6, the groove 7 is located directly above the strip-shaped P column 6, and the width is the same as the width of the strip-shaped P column 6, as shown in Figure 7 shown.

[0070] Further, in this embodiment, P-type ions are implanted again at the bottom of the groove 7 to form a bottom protection region 8 of the groove to relieve the problem of electric field concentration at the corner of the bottom of the trench. Refer to the attached Figure 8a and 8b . The ion concentration of the bottom protection region 8 of the groove is higher than the P-type ion concentration of the strip-shaped P column 6 and is electrically connected to the strip-shaped P column 6.

[0071] After completing the etching of the groove 7, the device structure shown in Figure 8a is obtained. Figure 8a In the structure shown, if a cross-section is intercepted at the position indicated by the green arrow in Figure 8a , a cross-sectional view shown in Figure 8b will be obtained. By comparing Figure 8a and 8b it can be clearly seen that the P connector 11 intersects with the strip-shaped P column 6 in the second epitaxial layer 3.

[0072] Step S6, fabricating a trench gate. As shown in Figures 9 - 10 a layer of inner-wall GOX deposition 9 is deposited on the inner wall of the groove 7 by depositing GOX (Gate Oxide),Figure 9 As shown. Then, the groove 7 is filled with a filler to form a POLY fill deposition 10 that fills the groove 7, and polysilicon back-etching is performed in a local area by photolithography to obtain the trench gate cell structure, as Figure 10 shown.

[0073] So far, the manufacturing method of a trench gate power MOSFET is completed, and subsequent processes such as interlayer dielectric (ILD) deposition and etching, surface metal interconnection, passivation layer deposition and etching, back thinning and laser annealing can be carried out.

[0074] In this embodiment, the method of channel implantation is used to manufacture the second epitaxial layer 3 and the strip-shaped P pillar 6, and a relatively deep implantation depth can be obtained. When the strip-shaped P pillar 6 is arranged directly below the trench, the width of the strip-shaped P pillar 6 is limited by the width of the groove 7. During the manufacturing process, the same mask can be used to manufacture the trench and the P pillar, thereby reducing the steps of mask making and cleaning once.

[0075] In addition, in another embodiment, the groove 7 can also be etched before manufacturing the strip-shaped P pillar 6. The specific steps are as follows:

[0076] Form the second epitaxial layer 3. The specific formation method is the same as that in step S1 and will not be elaborated here;

[0077] Form the P body region 4 and the surface source region 5 (including the surface N++ region 5a and the surface P++ region 5b) by ion implantation. Specifically, steps S3 and S4a can be referred to;

[0078] Form the P connector 11 by high-energy ion implantation. Specifically, step S4a can be referred to;

[0079] Trench etching. The trench is formed by etching. The length direction of the trench is parallel to the projection direction of the crystal orientation with the most obvious channel effect of the epitaxial material on the surface of the epitaxial material, so as to form the groove 7 as Figure 11 shown.

[0080] Perform P-type ion implantation along the crystal orientation with the most obvious channel effect of the epitaxial material at the bottom of the groove 7, so as to form a strip-shaped P pillar 6 below the trench, as Figure 12 shown.

[0081] Through the above method, a structure with the same process steps as Figures 1 - 7 shown can be obtained, and subsequent processing can be continued according to Figures 8a - 10 shown. The difference between these two routes lies in whether to perform trench etching first and then P pillar implantation at the bottom, or to perform P pillar implantation first and then trench etching.

[0082] The following steps S4b - S5b illustrate the second structure, that is, the solution where the trench is perpendicular to the P pillar. Generally speaking, compared with the first structure, in the second structure, the P - type bottom protection area 8 at the bottom of the trench is connected to the surface P++ region 5b through the strip - shaped P pillar 6, so as to be directly electrically connected to the source electrode. Therefore, there is no need to fabricate the P - connector 11. The schematic diagram of the relevant structural changes can be combined with Figures 1 - 4 , Figures 9 - 10 and Figures 13 - 14 for understanding.

[0083] Step S4b, source - surface implantation. High - concentration P - type ions and N - type ions are implanted at intervals on the surface source region 5, so as to form strip - shaped surface N++ regions 5a and surface P++ regions 5b that appear at intervals as shown in Figure 13 . Among them, the implantation region of the P - type ions coincides with the strip - shaped P pillar 6 or is slightly larger than the width of the strip - shaped P pillar 6, that is, the width of the surface P++ region 5b is the same as the width of the strip - shaped P pillar 6.

[0084] Step S5b, etching the gate trench as shown in Figure 14 . Based on the surface N++ region 5a and surface P++ region 5b formed in step S4b, the length direction of the gate trench is perpendicular to the length direction of the surface N++ region 5a and surface P++ region 5b. The etching depth is to penetrate the surface N++ region 5a, surface P++ region 5b and the P - body region 4 to reach the second epitaxial layer 3. In this embodiment, the length direction of the trench 7 is perpendicular to the length direction of the strip - shaped P pillar 6, and the width is not related to the strip - shaped P pillar 6. The trench width and the P - pillar width can be designed independently, which can better exert the performance advantages of this structure.

[0085] Similar to step S5a, P - type ions are implanted again at the bottom of the trench 7, so as to form the bottom protection area 8 of the trench, which is used to suppress the phenomenon of electric - field - intensity concentration at the bottom corner of the trench.

[0086] Step S6, fabricating the trench gate. This step has been described in detail above and will not be elaborated here.

[0087] It should be noted that in the examples and description of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one" does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0088] Although this application has been illustrated and described by reference to certain preferred embodiments thereof, those of ordinary skill in the art should understand that various changes may be made therein in form and detail without departing from the spirit and scope of this application.

Claims

1. A structure of a trench gate power MOSFET, characterized in that: The method comprises a substrate, a first epitaxial layer, a P body region, and further comprises: A second epitaxial layer, wherein the second epitaxial layer is formed on the upper part of the first epitaxial layer by ion implantation, and the orthographic projection of the second epitaxial layer on the first epitaxial layer completely covers the first epitaxial layer, or only covers the area predetermined as the active area of ​​the chip, and the P body region is located in the middle and upper part of the second epitaxial layer; A strip-shaped P column, wherein the length direction of the strip-shaped P column is parallel to the projection direction of the crystal direction with the most obvious channel effect on the surface of the epitaxial material, and the depth of the strip-shaped P column penetrates the P body region and approaches or exceeds the second epitaxial layer; A trench gate, comprising a trench, which is perpendicular to the length direction of the strip-shaped P column, the depth of the trench penetrates the P body region to reach the second epitaxial layer, and a filler is filled into the trench to manufacture the trench gate; a surface source region, located at the surface layer of the P body region, and further comprising a surface N++ region and a surface P++ region, wherein the surface N++ region and the surface P++ region are arranged at intervals, and the length direction thereof is perpendicular to the length direction of the trench, and when the length direction of the trench is perpendicular to the length direction of the strip P column, the width of the strip P column is consistent with the width of the surface P++ region, and the surface P++ region is electrically connected to the strip P column; in, First, P-type ion implantation is performed along the crystal direction where the channel effect of the epitaxial material is most obvious to form the strip-shaped P column, and then gate trench etching is performed to obtain the trench, and then ion implantation is performed again on the bottom surface of the trench to form a trench bottom protection area.

2. The structure of the trench gate power MOSFET according to claim 1, characterized in that: The ion implantation method includes at least one high-energy ion implantation or channel implantation, and the direction of the channel implantation is the direction in which the channel effect of the epitaxial material is most obvious.

3. The structure of the trench gate power MOSFET according to claim 1, characterized in that: Or the groove is parallel to the length direction of the strip P column. In this case, the groove is located directly above the strip P column and its width is consistent with the width of the strip P column. Below the surface P++ area, there is also a P connector with a width consistent with it. One end of the P connector is electrically connected to the surface P++ area, and the other end is electrically connected to the strip P column.

4. The structure of the trench gate power MOSFET according to claim 3, characterized in that: The P linker is formed by at least one high energy implantation.

5. The structure of the trench gate power MOSFET according to claim 1, characterized in that: The groove bottom protection area is formed after the groove is etched and before the groove is filled.

6. A trench gate power MOSFET chip, characterized in that: A trench gate power MOSFET having the structure of any one of claims 1 to 5.

7. A method for manufacturing a trench gate power MOSFET chip, characterized in that: The method for manufacturing the trench gate power MOSFET chip as claimed in claim 6 comprises the following steps: Forming a second epitaxial layer, by implanting N-type ions into the first epitaxial layer having the N-type SiC epitaxial material once or multiple times by an ion implantation method, thereby forming a uniformly doped second epitaxial layer, and the orthographic projection of the second epitaxial layer on the first epitaxial layer completely covers the first epitaxial layer, or only covers the area predetermined as the active area of ​​the chip; Forming a strip-shaped P column, injecting P-type ions into the second epitaxial layer once or multiple times, the injection direction is the direction in which the channel effect of the epitaxial material is most obvious, and the injection depth penetrates the second epitaxial layer to reach the first epitaxial layer, thereby forming the strip-shaped P column; Forming a P body region, injecting P type ions into the surface layer of the second epitaxial layer multiple times, thereby forming the P body region in the upper layer of the second epitaxial layer; Source surface implantation, injecting high-concentration P-type ions and high-concentration N-type ions at intervals above the P body region to form alternately appearing strip-shaped surface N++ regions and surface P++ regions, wherein the length directions of the surface N++ regions and the surface P++ regions are perpendicular or parallel to the length direction of the strip-shaped P columns; Etching a gate trench in a direction perpendicular to the length direction of the strip P column, the etching depth is to penetrate the surface N++ region, the surface P++ region and the P body region to reach the second epitaxial layer, when the length direction of the trench is perpendicular to the length direction of the strip P column, the width of the strip P column is consistent with the width of the surface P++ region, and the surface P++ region is electrically connected to the strip P column; Manufacturing a trench gate, and filling the trench with a filler to obtain the trench gate; In the above steps, First, P-type ion implantation is performed along the crystal direction where the channel effect of the epitaxial material is most obvious to form the strip-shaped P column, and then gate trench etching is performed to obtain the trench, and then ion implantation is performed again on the bottom surface of the trench to form a trench bottom protection area.

8. The manufacturing method according to claim 7, characterized in that: The ion implantation method includes at least one high-energy ion implantation or channel implantation, and the direction of the channel implantation is the direction in which the channel effect of the epitaxial material is most obvious.

9. The manufacturing method according to claim 7, characterized in that: Alternatively, the groove is etched in a direction parallel to the length direction of the strip P column, in which case the groove is located directly above the strip P column and has a width consistent with that of the strip P column, and a P connector having a width consistent with that of the surface P++ region is also included below the surface P++ region, one end of the P connector is electrically connected to the surface P++ region, and the other end is electrically connected to the strip P column.

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