Power-saving circuit and method for serial port data wake-up circuit

Abstract

The invention discloses a power-saving circuit of a serial port data wake-up circuit, and relates to the field of system dormancy, and the power-saving circuit of the serial port data wake-up circuit comprises a synchronizing signal generation module which is used for generating a single pulse with a certain pulse width as a synchronizing pulse signal based on the falling edge of a source signal RX, and outputting the synchronizing pulse signal to a displacement drive generation module; the displacement drive generation module is used for generating a displacement pulse signal when receiving the synchronous pulse signal, so that the data cache displacement module performs primary latching and displacement; compared with the prior art, the wake-up circuit has the advantages that low-power-consumption hardware circuit design (an adder and a phase inverter) is added for power loss, the wake-up circuit has the automatic energy-saving characteristic, when a system has serial port data, the wake-up circuit works normally, when no data exists for a certain time, a clock of the wake-up circuit is closed, the wake-up circuit enters dormant work, and the wake-up circuit does not work normally. And after data exist, restarting to enter a normal working mode.

Description

Technical Field

[0001] The invention relates to the field of system dormancy, in particular to a power saving circuit and method for a serial port data wake-up circuit. Background Art

[0002] In low-power systems, a proprietary wake-up circuit design can automatically wake up a dormant system through serial port data without losing data.

[0003] The wake-up circuit itself requires a clock generation circuit, so it has a certain amount of power consumption, resulting in power loss, which needs to be improved. Summary of the invention

[0004] The object of the present invention is to provide a power saving circuit and method for a serial port data wake-up circuit to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A power saving circuit for a serial port data wake-up circuit, comprising:

[0007] A synchronization signal generation module is used to generate a single pulse with a certain pulse width as a synchronization pulse signal based on the falling edge of the source signal RX, and output it to the displacement drive generation module;

[0008] The displacement drive generation module is used to generate a displacement pulse signal when receiving a synchronization pulse signal, so that the data cache displacement module performs a latch and displacement; at the same time, it starts to reset the count until the next data signal arrives, and then generates a displacement pulse signal again and outputs it to the data cache displacement module;

[0009] The data cache shift module is used to shift under the shift pulse signal, determine the final shift times based on the number of shift registers, end the shift after the shift times reach the final shift times, send a working signal to the CPU and adder, and wake up the CPU;

[0010] The adder is used to receive the synchronization pulse signal, the displacement pulse signal and the working signal. Before the working signal is input, the inverter is used to drive the displacement drive generation module to work continuously. After the working signal is input, the inverter is used to stop driving the displacement pulse signal.

[0011] The output end of the synchronization signal generation module is connected to the first input end of the displacement drive generation module and the first input end of the adder, the output end of the displacement drive generation module is connected to the input end of the data buffer displacement module and the second input end of the adder, the output end of the data buffer displacement module is connected to the third input end of the adder, the output end of the adder is connected to the input end of the inverter, and the output end of the inverter is connected to the second input end of the displacement drive generation module.

[0012] As a further solution of the present invention: the synchronization signal generation module includes a first NOT gate, a first MOS tube, a second MOS tube, a first resistor, and a first capacitor. The input end of the first NOT gate is input with a source signal RX, the output end of the first NOT gate is connected to the G pole of the first MOS tube and the G pole of the second MOS tube, the S pole of the first MOS tube is connected to the power supply voltage VCC, the D pole of the first MOS tube is connected to the D pole of the second MOS tube and one end of the first capacitor, the S pole of the second MOS tube is connected to one end of the first resistor, the first input end of the displacement drive generation module, and the first input end of the adder, the other end of the first resistor is grounded, and the other end of the first capacitor is grounded.

[0013] As a further solution of the present invention: the displacement drive generation module (as a clock generation circuit) includes a second XOR gate, a third NOT gate, a counter, and a clock buffer. The clock signal CLOCK is introduced into the input end of the clock buffer, the output end of the clock buffer is connected to the first input end of the counter, the output end of the counter is connected to the first input end of the second XOR gate, the second input end of the second XOR gate is connected to the output end of the synchronization signal generation module, the output end of the second XOR gate is connected to the input end of the third NOT gate, the input end of the data buffer displacement module, and the second input end of the adder, and the output end of the third NOT gate is connected to the second input end of the counter.

[0014] As a further solution of the present invention: the data buffer shift module includes at least one shift register. When there are multiple shift registers, the shift registers are connected in series.

[0015] A power saving method for a serial port data wake-up circuit is applied to the power saving circuit of the serial port data wake-up circuit as described above, and the power saving method for the serial port data wake-up circuit comprises the following steps:

[0016] Step 1, a synchronization signal generation module generates a synchronization pulse signal based on a source signal RX;

[0017] Step 2, the displacement drive generation module generates a displacement pulse signal based on the synchronization pulse signal;

[0018] Step 3: The data buffer shift module latches and shifts the shift register based on the shift pulse signal. When the data is shifted to the end of the shift register, a working signal is transmitted to the CPU, and the CPU enters the normal working mode to receive the serial port data normally.

[0019] Step 4, the adder receives the synchronization pulse signal, the displacement pulse signal, and the working signal. When the data buffer displacement module does not output the working signal, the CPU is in a dormant state. At this time, the adder does not output a level signal (low level), and outputs a level signal (high level) through the inverter to drive the displacement drive generation module to continue working; when the data buffer displacement module outputs a working signal, the CPU enters a normal working mode, the adder outputs a level signal (high level), and does not output a level signal (low level) through the inverter, driving the displacement drive generation module to stop working and stop outputting the displacement pulse signal.

[0020] As a further solution of the present invention: in step 4, the displacement pulse signal is used as a driving clock of the adder.

[0021] As a further solution of the present invention: in step 4, the synchronization pulse signal is used as a reset signal of the adder.

[0022] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention aims at power loss, adds low-power consumption hardware circuit design (adder, inverter), so that the wake-up circuit itself has automatic energy-saving characteristics, when the system has serial port data, the wake-up circuit works normally, when there is no data for a certain period of time, the wake-up circuit clock is turned off, enters sleep mode, and restarts to enter normal working mode after there is data; the wake-up circuit is composed of a synchronization signal generation module, a displacement drive generation module, and a data cache displacement module, and when the source signal RX wakes up the CPU, the synchronization signal generation module, the displacement drive generation module, and the data cache displacement module are used to delay driving the CPU to perform data communication, and after the delay ends, the CPU has entered the normal working mode, and the serial port data can be received normally, and the circuit design is simple and easy to promote. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 The present invention is a schematic diagram of a power saving circuit of a serial port data wake-up circuit.

[0024] Figure 2 Circuit diagram of the synchronization signal generation module.

[0025] Figure 3 Generate a circuit diagram for the displacement drive module. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0027] See also Figure 1 , a power saving circuit of a serial port data wake-up circuit, comprising:

[0028] The interrupt wake-up module is used to use the source signal RX as the wake-up source and output it to the IO pin that wakes up the CPU;

[0029] A synchronization signal generation module is used to generate a single pulse with a certain pulse width as a synchronization pulse signal based on the falling edge of the source signal RX, and output it to the displacement drive generation module;

[0030] The displacement drive generation module is used to generate a displacement pulse signal when receiving a synchronization pulse signal, so that the data cache displacement module performs a latch and displacement; at the same time, it starts to reset the count until the next data signal arrives, and then generates a displacement pulse signal again and outputs it to the data cache displacement module;

[0031] The data cache shift module is used to shift under the shift pulse signal, determine the final shift times based on the number of shift registers, end the shift after the shift times reach the final shift times, send a working signal to the CPU and adder, and wake up the CPU;

[0032] The adder is used to receive the synchronization pulse signal, the displacement pulse signal and the working signal. Before the working signal is input, the inverter is used to drive the displacement drive generation module to work continuously. After the working signal is input, the inverter is used to stop driving the displacement pulse signal.

[0033] The output end of the interrupt wake-up module is connected to the input end of the synchronization signal generation module, the output end of the synchronization signal generation module is connected to the first input end of the displacement drive generation module and the first input end of the adder, the output end of the displacement drive generation module is connected to the input end of the data buffer displacement module and the second input end of the adder, the output end of the data buffer displacement module is connected to the third input end of the adder, the output end of the adder is connected to the input end of the inverter, and the output end of the inverter is connected to the second input end of the displacement drive generation module.

[0034] In this example: See Figure 2 The synchronization signal generation module includes a first NOT gate, a first MOS tube, a second MOS tube, a first resistor, and a first capacitor. The input end of the first NOT gate is input with a source signal RX, the output end of the first NOT gate is connected with the G pole of the first MOS tube and the G pole of the second MOS tube, the S pole of the first MOS tube is connected with a power supply voltage VCC, the D pole of the first MOS tube is connected with the D pole of the second MOS tube and one end of the first capacitor, the S pole of the second MOS tube is connected with one end of the first resistor, the first input end of the displacement drive generation module, and the first input end of the adder, the other end of the first resistor is grounded, and the other end of the first capacitor is grounded.

[0035] When the source signal RX is a falling edge, it passes through the first NOT gate U1 to be a high level, driving the second MOS tube Q2 to be turned on. At this time, the electric energy stored in the first capacitor C1 provides the second MOS tube Q2 to output a high level. When the source signal RX is a rising edge, it passes through the first NOT gate U1 to be a low level, driving the first MOS tube Q1 to be turned on, charging the first capacitor C1, and so on and so forth, so that the second MOS tube Q2 outputs a single pulse with a certain pulse width as a synchronous pulse signal based on the source signal RX.

[0036] In this example: See Figure 3 The displacement drive generation module includes a second XOR gate, a third NOT gate, a counter, and a clock buffer. The input end of the clock buffer introduces a clock signal CLOCK, the output end of the clock buffer is connected to the first input end of the counter, the output end of the counter is connected to the first input end of the second XOR gate, the second input end of the second XOR gate is connected to the output end of the synchronization signal generation module, the output end of the second XOR gate is connected to the input end of the third NOT gate, the input end of the data buffer displacement module, and the second input end of the adder, and the output end of the third NOT gate is connected to the second input end of the counter.

[0037] The clock signal CLOCK passes through the clock buffer and the counter, and the counter overflow signal is input to the first input terminal of the second XOR gate U2. The synchronization pulse signal is input to the second input terminal of the second XOR gate U2. A high level is output based on the difference in the input levels of the XOR gate, so that a displacement pulse signal is output through the second XOR gate U2. The counter period is determined by the baud rate of the data. In the presence of the synchronization pulse signal, the feedback signal through the third NOT gate U3 controls the accumulated error of the counter.

[0038] In this example: See Figure 1 The data buffer shift module includes at least one shift register. When there are multiple shift registers, the shift registers are connected in series.

[0039] Receive the shift pulse signal to shift once. When the counter starts to reset and counts to the next data signal, it generates a shift pulse again, causing the shift register to latch and shift once. When the data is shifted to the end of the register, the CPU has entered the normal working mode, and the serial port data can be received normally. The number of shift bits is determined by the buffer buffer time.

[0040] In this example: See Figure 1 , a power saving method for a serial port data wake-up circuit, applied to the power saving circuit of the serial port data wake-up circuit as described above, the power saving method for the serial port data wake-up circuit comprises the following steps:

[0041] Step 1, a synchronization signal generation module generates a synchronization pulse signal based on a source signal RX;

[0042] Step 2, the displacement drive generation module generates a displacement pulse signal based on the synchronization pulse signal;

[0043] Step 3: The data buffer shift module latches and shifts the shift register based on the shift pulse signal. When the data is shifted to the end of the shift register, a working signal is transmitted to the CPU, and the CPU enters the normal working mode to receive the serial port data normally.

[0044] Step 4, the adder receives the synchronization pulse signal, the displacement pulse signal, and the working signal. When the data buffer displacement module does not output the working signal, the CPU is in a dormant state. At this time, the adder does not output a level signal (low level), and outputs a level signal (high level) through the inverter to drive the displacement drive generation module to continue working; when the data buffer displacement module outputs a working signal, the CPU enters a normal working mode, the adder outputs a level signal (high level), and does not output a level signal (low level) through the inverter, driving the displacement drive generation module to stop working and stop outputting the displacement pulse signal.

[0045] In this example: See Figure 1 ,In step 4, the displacement pulse signal is used as the driving clock of the adder.

[0046] In this example: See Figure 1 ,In step 4, the synchronization pulse signal serves as the reset signal of the adder.

[0047] After the source signal RX wakes up the CPU, the present invention delays driving the CPU to perform data communication through the synchronization signal generation module, the displacement drive generation module, and the data cache displacement module. After the delay ends, the CPU has entered the normal working mode, and the serial port data is received normally. At this time, the adder outputs a level signal (high level), and the inverter does not output a level signal (low level), driving the displacement drive generation module to stop working and stop outputting the displacement pulse signal, thereby reducing power consumption, and the circuit enters a low power consumption state.

[0048] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0049] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A power saving circuit for a serial port data wake-up circuit, characterized in that: The power saving circuit of the serial port data wake-up circuit includes: A synchronization signal generation module is used to generate a single pulse with a certain pulse width as a synchronization pulse signal based on the falling edge of the source signal RX, and output it to the displacement drive generation module; The displacement drive generation module is used to generate a displacement pulse signal when receiving a synchronization pulse signal, so that the data cache displacement module performs a latch and displacement; at the same time, it starts to reset the count until the next data signal arrives, and then generates a displacement pulse signal again and outputs it to the data cache displacement module; The data cache shift module is used to shift under the shift pulse signal, determine the final shift times based on the number of shift registers, end the shift after the shift times reach the final shift times, send a working signal to the CPU and adder, and wake up the CPU; The adder is used to receive the synchronization pulse signal, the displacement pulse signal and the working signal. Before the working signal is input, the inverter is used to drive the displacement drive generation module to work continuously. After the working signal is input, the inverter is used to stop driving the displacement pulse signal. The output end of the synchronization signal generation module is connected to the first input end of the displacement drive generation module and the first input end of the adder, the output end of the displacement drive generation module is connected to the input end of the data buffer displacement module and the second input end of the adder, the output end of the data buffer displacement module is connected to the third input end of the adder, the output end of the adder is connected to the input end of the inverter, and the output end of the inverter is connected to the second input end of the displacement drive generation module.

2. The power saving circuit of the serial port data wake-up circuit according to claim 1, characterized in that: The synchronization signal generation module includes a first NOT gate, a first MOS tube, a second MOS tube, a first resistor, and a first capacitor. The input end of the first NOT gate inputs a source signal RX, the output end of the first NOT gate is connected to the G pole of the first MOS tube and the G pole of the second MOS tube, the S pole of the first MOS tube is connected to the power supply voltage VCC, the D pole of the first MOS tube is connected to the D pole of the second MOS tube and one end of the first capacitor, the S pole of the second MOS tube is connected to one end of the first resistor, the first input end of the displacement drive generation module, and the first input end of the adder, the other end of the first resistor is grounded, and the other end of the first capacitor is grounded.

3. The power saving circuit of the serial port data wake-up circuit according to claim 1, characterized in that: The displacement drive generation module includes a second XOR gate, a third NOT gate, a counter, and a clock buffer. The input end of the clock buffer introduces a clock signal CLOCK, the output end of the clock buffer is connected to the first input end of the counter, the output end of the counter is connected to the first input end of the second XOR gate, the second input end of the second XOR gate is connected to the output end of the synchronization signal generation module, the output end of the second XOR gate is connected to the input end of the third NOT gate, the input end of the data buffer displacement module, and the second input end of the adder, and the output end of the third NOT gate is connected to the second input end of the counter.

4. The power saving circuit of the serial port data wake-up circuit according to claim 1, characterized in that: The data buffer shift module includes at least one shift register. When there are multiple shift registers, the shift registers are connected in series.

5. A power saving method for a serial port data wake-up circuit, applied to the power saving circuit for the serial port data wake-up circuit as claimed in any one of claims 1 to 4, the power saving method for the serial port data wake-up circuit comprising the following steps: Step 1, a synchronization signal generation module generates a synchronization pulse signal based on a source signal RX; Step 2, the displacement drive generation module generates a displacement pulse signal based on the synchronization pulse signal; Step 3: The data buffer shift module latches and shifts the shift register based on the shift pulse signal. When the data is shifted to the end of the shift register, a working signal is transmitted to the CPU, and the CPU enters the normal working mode to receive the serial port data normally. Step 4, the adder receives the synchronization pulse signal, the displacement pulse signal, and the working signal. When the data buffer displacement module does not output the working signal, the CPU is in a dormant state. At this time, the adder does not output a level signal, and outputs a level signal through the inverter to drive the displacement drive generation module to continue working; when the data buffer displacement module outputs a working signal, the CPU enters a normal working mode, the adder outputs a level signal, and does not output a level signal through the inverter, driving the displacement drive generation module to stop working and stop outputting the displacement pulse signal.

6. The power saving method of the serial port data wake-up circuit according to claim 5, characterized in that: In step 4, the displacement pulse signal is used as the driving clock of the adder.

7. The power saving method of the serial port data wake-up circuit according to claim 5, characterized in that: In step 4, the synchronization pulse signal is used as a reset signal of the adder.

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