Method and device for asynchronously and parallelly executing calculation tasks

Abstract

The invention provides a method and device for asynchronously and parallelly executing calculation tasks, and the method comprises the steps: sequentially carrying out segmented calculation on data of a current data block in a register under the condition that the current data block is determined to be located in the register; after calculation of each segment is completed, detecting whether the next data block is located in the shared memory or not, if yes, sending a carrying instruction to the shared memory, and continuing calculation of the next segment of the current data block; if not, directly entering the next section calculation of the current data block; the carrying instruction is used for writing the next data block into the register from the shared memory; after the segmentation calculation of the data of the current data block is completed, whether the next data block is located in the register or not is checked, if yes, segmentation calculation is continuously carried out on the data of the next data block in sequence, and if not, waiting is continuously carried out until the next data block is located in the register, so that the idling time of an execution unit is shortened, and the calculation efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of processor technology, and in particular to a method and device for asynchronously and parallelly executing computing tasks. Background Art

[0002] In the field of modern artificial intelligence (AI) computing, graphics processing units (GPUs) are widely used due to their powerful parallel processing capabilities. GPUs process complex computing tasks, such as matrix operations, by executing kernel programs. When executing these tasks, the GPU's execution unit (EU) can schedule multiple warps to improve computing efficiency.

[0003] However, existing technologies have efficiency bottlenecks when processing asynchronous concurrent tasks. Specifically, when the execution unit EU executes a task, it often needs to wait for a prerequisite to be met, and the time of meeting this condition is uncertain. If the wait is too early, the entire instruction flow will stagnate, reducing computing efficiency; if the wait is too late, the subsequent actions will be delayed, which also affects efficiency.

[0004] Therefore, how to enable the GPU to handle asynchronous concurrent tasks more efficiently when processing AI computing tasks and reduce the waste of computing resources caused by waiting is a technical problem that needs to be solved. Summary of the invention

[0005] The present invention provides a method and device for asynchronously executing computing tasks in parallel, so as to solve the defect of the prior art that computing resources are wasted due to waiting.

[0006] The present invention provides a method for asynchronously and parallelly executing computing tasks, which is used in an execution unit of a kernel program, and the method comprises: When it is determined that the current data block is located in the register, sequentially performing segmented calculations on the data of the current data block in the register; After each calculation is completed, it is detected whether the next data block is located in the shared memory. If so, a transfer instruction is sent to the shared memory, and the next calculation of the current data block is continued; if not, the next calculation of the current data block is directly entered; wherein the transfer instruction is used to write the next data block from the shared memory to the register; After the segmented calculation of the data of the current data block is completed, check whether the next data block is located in the register. If so, continue to perform segmented calculation on the data of the next data block in sequence. If not, continue to wait until the next data block is located in the register.

[0007] According to the method for asynchronously executing computing tasks in parallel provided by the present invention, detecting whether the next data block is located in the shared memory specifically includes: Detect whether the state of the first synchronization channel corresponding to the next data block is true; When it is determined that the state of the first synchronization channel corresponding to the next data block is true, determining that the next data block is located in the shared memory; wherein the first synchronization channel is used to identify that the corresponding data block is located in the shared memory; When it is determined that the state of the first synchronization channel corresponding to the next data block is false, it is determined that the next data block is not located in the shared memory.

[0008] According to the method for asynchronously and parallelly executing computing tasks provided by the present invention, determining that the current data block is located in a register specifically includes: when it is determined that the state of the second synchronization channel corresponding to the current data block is true, determining that the current data block is located in the register; wherein the second synchronization channel is used to identify that the corresponding data block is located in the register.

[0009] According to the method for asynchronously and parallelly executing computing tasks provided by the present invention, after sending a transfer instruction to the shared memory and before continuing the next calculation of the current data block, the method also includes: changing the state of the first synchronization channel corresponding to the next data block from true to false, and setting the state of the transfer instruction flag bit to true; wherein the transfer instruction flag bit is used to indicate that the corresponding data block is written from the shared memory to the register.

[0010] According to the method for asynchronously executing computing tasks in parallel provided by the present invention, after the segmented computing of the data of the current data block is completed, the method further includes: Check whether the status of the handling instruction flag is true; If so, continue with the step of checking whether the next data block is located in the register; If not, continue to check the first status flag bit corresponding to the next data block until the first status flag bit corresponding to the next data block is true, write the next data block from the shared memory to the register, and check whether the next data block is located in the register.

[0011] According to the method for asynchronously executing computing tasks provided by the present invention, after determining that the next data block is located in the register, before continuing to perform segmented calculations on the data of the next data block in sequence, the method also includes: resetting the state of the transfer instruction flag bit from true to false.

[0012] The present invention also provides a device for asynchronously and parallelly executing computing tasks, which is used in an execution unit of a kernel program, and the device comprises: A first checking module is used to perform segmented calculations on the data of the current data block in the register in sequence when it is determined that the current data block is in the register; The iterative calculation module is used to detect whether the next data block is located in the shared memory after each calculation is completed. If so, send a transfer instruction to the shared memory and continue the next calculation of the current data block; if not, directly enter the next calculation of the current data block; wherein the transfer instruction is used to write the next data block from the shared memory to the register; The second checking module is used to check whether the next data block is located in the register after the segmented calculation of the data of the current data block is completed. If so, continue to perform segmented calculation on the data of the next data block in sequence; if not, continue to wait until the next data block is located in the register.

[0013] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method for asynchronously and parallelly executing computing tasks as described in any one of the above is implemented.

[0014] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements any of the above-described methods for asynchronously and parallelly executing computing tasks.

[0015] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the method for asynchronously and parallelly executing computing tasks as described in any one of the above is implemented.

[0016] The method for asynchronously executing computing tasks provided by the present invention realizes asynchronous parallel execution of data block processing by performing segmented calculation on the current data block in the register and checking whether the next data block is already in the shared memory after each segment calculation. If the next data block is already in the shared memory, the system will immediately send a transfer instruction to move the next data block from the shared memory to the register, and continue to calculate the next segment of the current data block. This method avoids waiting for the data block to be moved from the global memory to the shared memory, reduces the idle time of the execution unit, and improves the computing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is a schematic diagram of the hardware environment provided by an embodiment of the present invention.

[0019] Figure 2 It is a thread diagram for executing computing tasks provided by conventional technology.

[0020] Figure 3 It is a flowchart of a method for asynchronously and concurrently executing computing tasks provided by an embodiment of the present invention.

[0021] Figure 4 It is a thread diagram of asynchronous parallel execution of computing tasks provided by an embodiment of the present invention.

[0022] Figure 5 It is a schematic diagram of the structure of a device for asynchronously and parallelly executing computing tasks provided by an embodiment of the present invention.

[0023] Figure 6 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] First, the terms involved in the embodiments of the present invention are schematically explained.

[0026] Graphics Processing Unit (GPU): is a hardware device specially designed to handle graphics and image-related calculations. It was originally designed to accelerate graphics rendering, but with the development of technology, GPU is also used for various non-graphics computing tasks, especially in situations that require a lot of parallel processing capabilities, such as deep learning and scientific computing.

[0027] Artificial Intelligence (AI): refers to intelligent behavior exhibited by man-made systems, covering a wide range from simple automation tools to intelligent systems capable of performing complex tasks.

[0028] Kernel: In GPU programming, a kernel is a parallel program that runs on the GPU and is executed in parallel by multiple threads. Kernel programs are often used to perform large-scale data processing tasks such as image processing, physics simulation, and training of machine learning models.

[0029] Execution Unit (EU): The execution unit is the part of the GPU that is responsible for executing instructions. It usually contains multiple processing cores and can process instructions from multiple warps at the same time. The design of the execution unit directly affects the performance and efficiency of the GPU.

[0030] Register file (REG): A register is a high-speed storage area located inside the execution unit for fast access and processing of data. A register file is a set of registers. Each thread warp has its own set of registers for storing local variables, temporary data, and instruction pointers.

[0031] Shared memory (SMEM): Shared memory is a fast on-chip memory in the GPU that can be shared by all threads in the same execution unit (EU). Shared memory is used to store temporary data to reduce the number of accesses to global memory, thereby improving data access speed and program execution efficiency.

[0032] Global memory (GMEM): Global memory is the largest memory area in the GPU and is usually shared by all threads. It is the main location where programs store data and instructions. Access to global memory is relatively slow, so optimizing access to global memory is key to improving GPU performance.

[0033] Warp: A collection of threads that are executed simultaneously in a GPU. A warp contains multiple threads that execute the same instructions but may process different data. Warp is the basic unit of GPU parallel processing. By executing multiple warps simultaneously, the GPU can efficiently process a large number of parallel tasks.

[0034] First synchronization channel (sc1): The first synchronization channel is a status flag or signal that is used to identify whether the next data block is already in the shared memory (SMEM).

[0035] Second synchronization channel (sc2): The second synchronization channel is another status flag or signal used to identify whether the current data block is already in the register (REG).

[0036] See also Figure 1, a schematic illustration of the hardware environment used in the embodiments of the present invention is given.

[0037] Figure 1 In the diagram, the execution unit EU is the instruction execution unit of the graphics processor GPU, the register REG, the shared memory SMEM and the global memory GMEM are all places where data is stored; Warp is the instruction execution thread in the execution unit EU, and each EU can schedule multiple thread bundles warp to execute concurrently.

[0038] When processing a certain data block, it is necessary to first read the data block from the global memory to the shared memory, then read it from the shared memory to the register, and finally process the data block in the register.

[0039] The producer is responsible for generating or providing data, while the consumer is responsible for using or processing data. The producer and consumer threads are executed independently on their own concurrent warps.

[0040] The producer thread reads data blocks A0, A1, A2, ... from the global memory GMEM to the shared memory SMEM in sequence; the consumer thread reads data blocks A0, A1, A2, ... to the register REG in the same sequence for subsequent calculations.

[0041] In conventional technology, there are two waiting instructions in this process that may cause the EU to idle: one is to wait for the data block An to be moved from the global memory GMEM to the shared memory SMEM ("wait(sc1)", instruction #3, i.e. step 203), and the other is to wait for the data block An to be moved from the shared memory SMEM to the register REG ("wait(sc2)", instruction #5, i.e. step 205). These two waiting instructions, because they are in the loop body, may significantly reduce the computing efficiency.

[0042] See also Figure 2 , for the thread consumer, the execution process includes: 201. Execute the movement of data block A(i+1) from global memory to shared memory.

[0043] In this step, the producer thread (Producer) is responsible for reading the data block A(i+1) from the global memory GMEM to the shared memory SMEM. In order to improve efficiency, the embodiment of the present invention may optimize this process through asynchronous operation, allowing the EU to process other tasks while waiting for data to be moved. After the move is completed, the state of the first synchronization channel sc1 is set to true.

[0044] 202. Calculation of data block Ai in register.

[0045] For step 202, there is no need to wait for the data block A(i+1) to be moved. In step 202, the consumer thread (Consumer) can start calculating the data block Ai in the register REG while the data block A(i+1) is being moved. The calculation may be a matrix operation, a logical operation, or other types of data processing.

[0046] 203. Wait for data block A(i+1) to be in the shared memory.

[0047] Specifically, it is necessary to wait for the state of the first synchronization channel sc1 to be true. If it is true, it is determined that the data block A(i+1) is located in the shared memory.

[0048] 204. Move data block A(i+1) from the shared memory to the register.

[0049] 205. Wait for data block A(i+1) to be in the register.

[0050] Specifically, it is necessary to wait for the state of the second synchronization channel sc2 to be true. If it is true, it is determined that the data block A(i+1) is located in the register.

[0051] 206. Accumulate i and continue to execute the next loop.

[0052] For step 203 and step 205, the two waiting instructions may cause the EU to idle, thereby affecting the computing efficiency.

[0053] It can be seen from the above embodiments that Figure 2 The example consists of 3 asynchronous tasks: Task 1: Wait for the data block A(i+1) to be moved from the global memory GMEM to the shared memory SMEM (instruction #1, i.e., step 201); Task 2: Calculation of data block Ai in register (instruction #2, i.e. step 202); Task 3: Move data block A(i+1) from shared memory SMEM to register REG (instruction #4, i.e. step 204).

[0054] Task 1 and Task 2 overlap in time and run in parallel. However, due to the time uncertainty of Task 1, it may be completed in the middle of Task 2. In this way, Task 2 can only be executed alone in the remaining time; and Task 3 can only be executed alone after Task 2 is completed.

[0055] In the embodiment of the present invention, the implementation principle is to convert the above Figure 2Task 2 (calculation of data blocks) is split into multiple segments. After each segment of calculation, the completion status of Task 1 is checked. If completed, Task 3 is started, so that Task 3 and Task 2 can run in parallel and the waiting time is reduced.

[0056] Specifically, see Figure 3 , Figure 3 This is one of the flow charts of the method for asynchronously and concurrently executing computing tasks provided by an embodiment of the present invention, which is used in an execution unit of a kernel program. The method includes: Step 301: When it is determined that the current data block is in a register, segment calculation is performed on the data of the current data block in the register in sequence.

[0057] Specifically, the second state flag of the current data block is checked. When it is determined that the state of the second synchronization channel sc2 corresponding to the current data block is true, it is determined that the current data block is located in the register; wherein the second synchronization channel sc2 is used to identify that the corresponding data block is located in the register.

[0058] By checking the status of the next data block after each calculation, the system can start data movement or calculation immediately instead of waiting in the loop body. This reduces the idle time of the execution unit waiting for data movement to complete.

[0059] Step 302: After each calculation is completed, check whether the next data block is located in the shared memory. If so, send a transfer instruction to the shared memory and continue the next calculation of the current data block; if not, directly enter the next calculation of the current data block; wherein the transfer instruction is used to write the next data block from the shared memory to the register.

[0060] The current data block is split into multiple segments for calculation, and after each segment is calculated, it is checked whether the next data block is in the shared memory. If so, the task of moving the next data block from the shared memory to the register is immediately executed, so that the calculation task of the current data block and the task of moving the next data block to the register are executed asynchronously and in parallel, thereby reducing waiting time.

[0061] Specifically, detecting whether the next data block is located in the shared memory specifically includes: detecting whether the state of the first synchronization channel sc1 corresponding to the next data block is true; if it is determined that the state of the first synchronization channel sc1 corresponding to the next data block is true, determining that the next data block is located in the shared memory; wherein the first synchronization channel sc1 is used to identify that the corresponding data block is located in the shared memory. If it is determined that the state of the first synchronization channel sc1 corresponding to the next data block is false, determining that the next data block is not located in the shared memory.

[0062] Step 303: After the segmented calculation of the data of the current data block is completed, check whether the next data block is located in the register. If so, continue to perform segmented calculation on the data of the next data block in sequence. If not, continue to wait until the next data block is located in the register.

[0063] In step 303, the system checks whether the next data block is already in the register. If the data block is not in the register yet, the system will continue to wait until the data block arrives. In order to improve the efficiency of the waiting process, the system may use an interrupt or polling mechanism to manage the waiting state. In addition, the system may implement priority scheduling to ensure that more important data blocks can be processed faster. After the data block arrives in the register, the execution unit will immediately start the segmented calculation and continue to execute the calculation task.

[0064] The method for asynchronously executing computing tasks provided by an embodiment of the present invention implements asynchronous parallel execution of data block processing by performing segmented calculations on the current data block in the register and checking whether the next data block is already in the shared memory after each segment of calculation. If the next data block is already in the shared memory, the system will immediately send a move instruction to move the next data block from the shared memory to the register, and continue to calculate the next segment of the current data block. This method avoids waiting for the data block to be moved from the global memory to the shared memory, reduces the idle time of the execution unit, and improves computing efficiency.

[0065] Furthermore, after sending the transfer instruction to the shared memory and before continuing the next calculation of the current data block, the method also includes: changing the state of the first synchronization channel corresponding to the next data block from true to false, and setting the state of the transfer instruction flag bit to true; wherein the transfer instruction flag bit is used to indicate that the corresponding data block is written from the shared memory to the register.

[0066] It should be noted here that in this case, the next data block is already in the shared memory, and the step of writing the next data block from the shared memory to the register has been executed. In this process, the state of the first synchronization channel corresponding to the next data block is changed from true to false. Then, after the next calculation is completed, when checking whether the next data block is in the shared memory, it will be detected that the state of the first synchronization channel corresponding to the next data block is false, and the next calculation of the current data block will be directly entered without repeatedly sending the transfer instruction to the shared memory.

[0067] Correspondingly, after the segmentation calculation of the data of the current data block is completed, the method also includes: checking whether the state of the transfer instruction mark bit is true; if so, continuing to execute the step of checking whether the next data block is located in the register; if not, continuing to check the first state mark bit corresponding to the next data block, until the first state mark bit corresponding to the next data block is true, writing the next data block from the shared memory to the register, and checking whether the next data block is located in the register.

[0068] After the segmentation calculation of the data of the current data block is completed, the state of the transfer instruction flag is checked to see if it is true, so as to avoid the situation where the next data block is still not in the shared memory after the segmentation calculation of the data of the current data block is completed. In this case, the consumer thread of the execution unit can only stop and wait, and continuously check the first state flag sc1 corresponding to the next data block until the first state flag corresponding to the next data block is true, write the next data block from the shared memory to the register, and then wait for the second state flag corresponding to the next data block to be true, and then determine that the next data block is in the register.

[0069] In addition, after determining that the next data block is located in the register, the state of the transfer instruction mark bit is reset from true to false, and then the data of the next data block is continuously segmented and calculated in sequence.

[0070] To facilitate understanding of the solution of this embodiment, see Figure 4 , Figure 4 The process flow chart of the production thread (producer) and the consumption thread (consumer) is shown.

[0071] For the production thread (producer), the data blocks A0, A1, A2... are read from the global memory GMEM to the shared memory SMEM in sequence.

[0072] For the consumer thread, the execution flow is as follows: 401. Waiting for data block A(i+1) to be moved from global memory to shared memory.

[0073] 402. Calculate the first segment A(i_0) of the data block Ai in the register.

[0074] 403 . Detect whether the state of the first synchronization channel sc1 corresponding to the data block A(i+1) is true. If so, execute step 404 ; if not, execute step 405 .

[0075] 404. Execute proc0.

[0076] Among them, Proc0 includes: 4041. Write data block A(i+1) from the shared memory SMEM to the register REG.

[0077] It should be noted that the process of writing data block A(i+1) is a continuous process, which can be executed in parallel with the calculation process of data block Ai. After the writing is completed, the state of the first synchronization channel sc1 corresponding to data block A(i+1) is true.

[0078] 4042. Change the state of the first synchronization channel sc1 corresponding to the data block A(i+1) from true to false.

[0079] By changing the state of the first synchronization channel sc1 corresponding to the data block A(i+1) from true to false, after the next segment A(i_x) of the data block Ai is calculated, proc0 is no longer executed, but step 405 is directly executed.

[0080] 4043. Set the status of the transport instruction flag to true, and then return to the step of the main program.

[0081] 405. Calculate the next segment A(i_x) of the data block Ai in the register, and then repeat steps 403 to 404 until all segments of the data block Ai are calculated.

[0082] 406. Check whether the status of the transport instruction flag is false. If so, execute step 407; if not, execute step 410.

[0083] 407. Wait for data block A(i+1) to be in the shared memory.

[0084] Specifically, if the state of the first synchronization channel sc1 corresponding to the data block A(i+1) is detected to be true, it is determined that the data block A(i+1) is located in the shared memory.

[0085] 408. Move data block A(i+1) from the shared memory to the register.

[0086] 409. Wait for data block A(i+1) to be in the register.

[0087] Specifically, if the state of the second synchronization channel sc1 corresponding to the detection data block A(i+1) is changed to true, it is determined that the data block A(i+1) is located in the register.

[0088] 410. Reset the status of the transport instruction flag from true to false.

[0089] Through steps 401-410 in the embodiment of the present invention, the move instruction of the data block A(i+1) from the shared memory SMEM to the register REG (i.e., task 3) can be sent in advance, so as to realize the concurrent execution of the calculation of the data block Ai in the register (i.e., task 2) and task 3. In the most ideal case, the waiting time of task 3 can be completely eliminated. In actual operation, the execution efficiency of the program is improved by more than 10%.

[0090] The device for asynchronously and parallelly executing computing tasks provided by the present invention is described below. The device for asynchronously and parallelly executing computing tasks described below and the method for asynchronously and parallelly executing computing tasks described above can be referred to each other.

[0091] The embodiment of the present invention provides a device for asynchronously executing computing tasks in parallel, which is used in the execution unit of the kernel program. Figure 5 , the device comprises: A first checking module 501 is used to perform segmented calculations on the data of the current data block in the register in sequence when it is determined that the current data block is in the register; The iterative calculation module 502 is used to detect whether the next data block is located in the shared memory after each calculation is completed. If so, send a transfer instruction to the shared memory and continue the next calculation of the current data block; if not, directly enter the next calculation of the current data block; wherein the transfer instruction is used to write the next data block from the shared memory to the register; The second checking module 503 is used to check whether the next data block is located in the register after the segmented calculation of the data of the current data block is completed. If so, continue to perform segmented calculation on the data of the next data block in sequence; if not, continue to wait until the next data block is located in the register.

[0092] Optionally, the first checking module 501 is specifically used to: when it is determined that the state of the second synchronization channel corresponding to the current data block is true, determine that the current data block is located in the register; wherein the second synchronization channel is used to identify that the corresponding data block is located in the register.

[0093] Optionally, the iterative calculation module 502 is specifically configured to: Detect whether the state of the first synchronization channel corresponding to the next data block is true; When it is determined that the state of the first synchronization channel corresponding to the next data block is true, determining that the next data block is located in the shared memory; wherein the first synchronization channel is used to identify that the corresponding data block is located in the shared memory; When it is determined that the state of the first synchronization channel corresponding to the next data block is false, it is determined that the next data block is not located in the shared memory.

[0094] Optionally, the iterative calculation module 502 is specifically configured to: After sending the transfer instruction to the shared memory, the state of the first synchronization channel corresponding to the next data block is changed from true to false, and the state of the transfer instruction flag is set to true; wherein the transfer instruction flag is used to indicate that the corresponding data block is written from the shared memory to the register.

[0095] Optionally, the second checking module 503 is specifically configured to: Check whether the status of the handling instruction flag is true; If so, continue with the step of checking whether the next data block is located in the register; If not, continue to check the first status flag bit corresponding to the next data block until the first status flag bit corresponding to the next data block is true, write the next data block from the shared memory to the register, and check whether the next data block is located in the register.

[0096] Optionally, the second checking module 503 is specifically configured to: after determining that the next data block is located in the register, reset the state of the transport instruction flag bit from true to false.

[0097] Figure 6 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 6As shown, the electronic device may include: a processor (processor) 610 , a communication interface (Communications Interface) 620 , a memory (memory) 630 and a communication bus 640 , wherein the processor 610 , the communication interface 620 , and the memory 630 communicate with each other through the communication bus 640 . The processor 610 can call the logic instructions in the memory 630 to execute a method for asynchronously and parallelly executing computing tasks, which method includes: when it is determined that the current data block is located in the register, the data of the current data block in the register are calculated in sequence by segments; after each segment calculation is completed, it is detected whether the next data block is located in the shared memory, if so, a transfer instruction is sent to the shared memory, and the next segment calculation of the current data block is continued; if not, directly enter the next segment calculation of the current data block; wherein the transfer instruction is used to write the next data block from the shared memory to the register; after the segment calculation of the data of the current data block is completed, check whether the next data block is located in the register, if so, continue to perform segment calculation on the data of the next data block in sequence, if not, continue to wait until the next data block is located in the register.

[0098] In addition, the logic instructions in the above-mentioned memory 630 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0099] On the other hand, the present invention also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the method for asynchronously and parallelly executing computing tasks provided by the above methods, the method including: when it is determined that the current data block is located in a register, performing segmented calculations on the data of the current data block in the register in sequence; after each segment calculation is completed, detecting whether the next data block is located in a shared memory, if so, sending a transfer instruction to the shared memory, and continuing to calculate the next segment of the current data block; if not, directly entering the next segment calculation of the current data block; wherein the transfer instruction is used to write the next data block from the shared memory to the register; after the segmented calculation of the data of the current data block is completed, checking whether the next data block is located in the register, if so, continuing to perform segmented calculations on the data of the next data block in sequence, if not, continuing to wait until the next data block is located in the register.

[0100] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a method for asynchronously and parallelly executing computing tasks provided by the above-mentioned methods, the method comprising: when it is determined that the current data block is located in a register, performing segmented calculations on the data of the current data block in the register in sequence; after each segment of calculation is completed, detecting whether the next data block is located in a shared memory, if so, sending a transfer instruction to the shared memory, and continuing to calculate the next segment of the current data block; if not, directly entering the next segment of calculation of the current data block; wherein the transfer instruction is used to write the next data block from the shared memory to the register; after the segmented calculation of the data of the current data block is completed, checking whether the next data block is located in the register, if so, continuing to perform segmented calculations on the data of the next data block in sequence, if not, continuing to wait until the next data block is located in the register.

[0101] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0102] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for asynchronously executing computing tasks in parallel, characterized in that: In an execution unit of a kernel program, the method comprises: When it is determined that the current data block is located in the register, sequentially performing segmented calculations on the data of the current data block in the register; After each calculation is completed, it is detected whether the next data block is located in the shared memory. If so, a transfer instruction is sent to the shared memory, and the next calculation of the current data block is continued; if not, the next calculation of the current data block is directly entered; wherein the transfer instruction is used to write the next data block from the shared memory to the register; After the segmented calculation of the data of the current data block is completed, check whether the next data block is located in the register. If so, continue to perform segmented calculation on the data of the next data block in sequence. If not, continue to wait until the next data block is located in the register.

2. The method for asynchronously executing computing tasks in parallel according to claim 1, characterized in that: Check whether the next data block is in the shared memory, including: Detect whether the state of the first synchronization channel corresponding to the next data block is true; When it is determined that the state of the first synchronization channel corresponding to the next data block is true, determining that the next data block is located in the shared memory; wherein the first synchronization channel is used to identify that the corresponding data block is located in the shared memory; When it is determined that the state of the first synchronization channel corresponding to the next data block is false, it is determined that the next data block is not located in the shared memory.

3. The method for asynchronously executing computing tasks in parallel according to claim 1, characterized in that: Determine that the current data block is in the register, including: When it is determined that the state of the second synchronization channel corresponding to the current data block is true, it is determined that the current data block is located in the register; wherein the second synchronization channel is used to identify that the corresponding data block is located in the register.

4. The method for asynchronously executing computing tasks in parallel according to claim 2, characterized in that: After sending the transfer instruction to the shared memory and before continuing to calculate the next segment of the current data block, the method further includes: The state of the first synchronization channel corresponding to the next data block is changed from true to false, and the state of the transfer instruction flag is set to true; wherein the transfer instruction flag is used to indicate that the corresponding data block is written from the shared memory to the register.

5. The method for asynchronously executing computing tasks in parallel according to claim 4, characterized in that: After the segmentation calculation of the data of the current data block is completed, the method further includes: Check whether the status of the handling instruction flag is true; If so, continue with the step of checking whether the next data block is located in the register; If not, continue to check the first status flag bit corresponding to the next data block until the first status flag bit corresponding to the next data block is true, write the next data block from the shared memory to the register, and check whether the next data block is located in the register.

6. The method for asynchronously executing computing tasks in parallel according to claim 4, characterized in that: After determining that the next data block is located in the register, before continuing to sequentially perform segmented calculations on the data of the next data block, the method further includes: The state of the transport instruction flag is reset from true to false.

7. A device for asynchronously executing computing tasks in parallel, characterized in that: In an execution unit for a kernel program, the device comprises: A first checking module is used to perform segmented calculations on the data of the current data block in the register in sequence when it is determined that the current data block is in the register; The iterative calculation module is used to detect whether the next data block is located in the shared memory after each calculation is completed. If so, send a transfer instruction to the shared memory and continue the next calculation of the current data block; if not, directly enter the next calculation of the current data block; wherein the transfer instruction is used to write the next data block from the shared memory to the register; The second checking module is used to check whether the next data block is located in the register after the segmented calculation of the data of the current data block is completed. If so, continue to perform segmented calculation on the data of the next data block in sequence; if not, continue to wait until the next data block is located in the register.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the method for asynchronously and parallelly executing computing tasks as described in any one of claims 1 to 6 is implemented.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for asynchronously and parallelly executing computing tasks as claimed in any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the method for asynchronously and parallelly executing computing tasks as claimed in any one of claims 1 to 6 is implemented.

Images