Chip testing method and testing device

Abstract

The invention provides a test method and a test device for a chip, relates to the technical field of chips, and solves the problems of insufficient protection or excessive protection and the like of protection measures adopted by the chip. According to the specific scheme, based on the number of logic units of each functional module of the chip and the single-particle features of the logic units, the single-particle function interruption occurrence frequency of each functional module is obtained; and based on the logic relationship among the plurality of function modules and the single-particle function interruption occurrence frequency of each function module, obtaining the single-particle function interruption occurrence frequency of the chip. Wherein the logic unit uses at least one protection measure, and the single particle feature is a corresponding relation between linear energy transfer of a single particle incident to the logic unit and a cross section.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a chip testing method and testing device. Background Art

[0002] At present, the satellite-ground integrated interconnection network is an integrated fusion of multiple heterogeneous networks such as non-terrestrial networks (NTN) subnets (such as high-orbit satellite networks and medium- and low-orbit satellite networks) and ground subnets. It is one of the possible solutions for realizing the 6th generation (6G) three-dimensional communication. In the satellite-ground integrated solution, there are many high-energy particles such as protons, alpha particles and heavy ions in the orbital environment where the satellite-borne communication equipment operates. When high-energy particles pass through semiconductor devices, various single event effects (SEE) such as single event upset (SEU), single event transient (SET) and single event latchup (SEL) may be generated. Single event effects may cause abnormal working state of the chip, thereby generating a single event functional interrupt (SEFI) of the chip (or circuit). Therefore, it is necessary to adopt certain protection measures to ensure the reliability of the on-orbit chip in space. How to avoid insufficient or excessive protection caused by the adopted protection measures has become an urgent problem to be solved. Summary of the invention

[0003] The present application provides a chip testing method and a testing device, which improve the problem of insufficient protection or excessive protection of the protection measures adopted by the chip.

[0004] In order to achieve the above-mentioned purpose, this application adopts the following technical solution.

[0005] In a first aspect, the present application provides a chip testing method, the method comprising: based on the number of logic units of each functional module of the chip and the single particle characteristics of the logic unit, obtaining the number of single particle functional interruption occurrences of each functional module, the logic unit uses at least one protection measure, and the single particle characteristic is the correspondence between the linear energy transfer and the cross section of the single particle incident on the logic unit. Based on the logical relationship between multiple functional modules and the number of single particle functional interruption occurrences of each functional module, the number of single particle functional interruption occurrences of the chip is obtained.

[0006] Therefore, in the chip testing method provided by the present application, the method divides the chip into functional modules, and the number of single-particle functional interruptions of each functional module in the chip can be calculated by the number of logic units of each functional module of the chip and the single-particle characteristics of the logic units, and the influence of the architecture (i.e., logical relationship) between multiple functional modules on the chip is considered, and the number of single-particle functional interruptions of the chip can be obtained. Since the chip testing method of the present application calculates the number of single-particle functional interruptions based on the logic units of the chip, it can be applied to a variety of chips with different processes and different architectures, and the method can calculate the number of single-particle functional interruptions of the chip during the research and development stage of the chip, thereby timely adjusting the chip protection measures to avoid problems such as insufficient protection or excessive protection in the protection measures adopted by the chip, and the reliability of the on-orbit chip can be improved.

[0007] In a possible design, the method further includes: if the number of single-particle functional interruptions of the chip is greater than the target threshold, adjusting the protection measures of the functional modules and / or adjusting the logical relationship between multiple functional modules, and repeatedly executing the step of calculating the number of single-particle functional interruptions of the chip until the number of single-particle functional interruptions of the chip is less than or equal to the target threshold. Therefore, in the research and development stage of the chip, by calculating the number of single-particle functional interruptions of the chip, the protection measures are adjusted and the protection effect is predicted, so as to avoid insufficient or excessive protection caused by the protection measures adopted by the chip, and improve the reliability of the on-orbit chip.

[0008] In a possible design, based on the number of logic units of each functional module of the chip and the single-particle characteristics of the logic units, the number of single-particle functional interruption occurrences of each functional module is obtained, including: based on the number of logic units of each functional module of the chip and the single-particle characteristics of the logic units, the number of first single-particle functional interruption occurrences of each functional module is obtained. Based on the number of first single-particle functional interruption occurrences of each functional module and the weight corresponding to each functional module, the number of single-particle functional interruption occurrences of each functional module is obtained.

[0009] In a possible design, the method further includes: obtaining the weight of the first logic unit in the logic unit of each functional module based on the failure mode and effect analysis method. Thus, by introducing the weight of the first logic unit in the logic unit and eliminating the single-particle functional interruption caused by other abnormalities, the accuracy of the number of single-particle functional interruptions of the computing chip can be improved.

[0010] In one possible design, based on the number of logic units of each functional module of the chip and the single-particle characteristics of the logic units, the number of occurrences of the first single-particle functional interruption of each functional module is obtained, including: inputting the number of logic units of each functional module, the single-particle characteristics of the logic units and the target orbit information of the chip into a space radiation environment model to obtain the number of occurrences of the first single-particle functional interruption of each functional module.

[0011] In a possible design, the multiple functional modules include a first functional module and a second functional module, and the number of single-particle functional interruptions of the chip is obtained based on the logical relationship between the multiple functional modules and the number of single-particle functional interruptions of each functional module, including: if the logical relationship between the first functional module and the second functional module is an AND relationship, then the number of single-particle functional interruptions of the first functional module and the number of single-particle functional interruptions of the second functional module are added. If the logical relationship between the first functional module and the second functional module is an OR relationship, then the number of single-particle functional interruptions of the first functional module and the number of single-particle functional interruptions of the second functional module are multiplied. Therefore, the test method provided by the present application introduces the influence of the chip architecture (i.e., the logical relationship) on the working state of the chip, which can improve the accuracy of predicting the number of single-particle functional interruptions.

[0012] In a possible design, different functional modules correspond to different protection measures.

[0013] In a second aspect, the present application provides a chip testing device, the testing device comprising an acquisition module and a calculation module. The acquisition module is used to obtain the number of single-particle functional interruption occurrences of each functional module based on the number of logic units of each functional module of the chip and the single-particle characteristics of the logic unit, the logic unit uses at least one protection measure, and the single-particle characteristic is the correspondence between the linear energy transfer and the cross section of the single particle incident on the logic unit. The calculation module is used to obtain the number of single-particle functional interruption occurrences of the chip based on the logical relationship between multiple functional modules and the number of single-particle functional interruption occurrences of each functional module.

[0014] In one possible design, the test device further includes: a judgment module. The judgment module is used to adjust the protection measures of the functional modules and / or adjust the logical relationship between multiple functional modules if the number of single-particle functional interruptions of the chip is greater than the target threshold, and repeatedly execute the calculation step of the number of single-particle functional interruptions of the chip until the number of single-particle functional interruptions of the chip is less than or equal to the target threshold.

[0015] In a possible design, the acquisition module is specifically used to obtain the number of occurrences of the first single-particle functional interruption of each functional module based on the number of logic units of each functional module of the chip and the single-particle characteristics of the logic units, and to obtain the number of occurrences of the single-particle functional interruption of each functional module based on the number of occurrences of the first single-particle functional interruption of each functional module and the weight corresponding to each functional module.

[0016] In a possible design, the acquisition module is further used to acquire the weight of the first logic unit in the logic units of each functional module based on a failure mode and effect analysis method.

[0017] In one possible design, the acquisition module is specifically used to input the number of logic units of each functional module, the single particle characteristics of the logic units and the target orbit information of the chip into the space radiation environment model to obtain the number of occurrences of the first single particle functional interruption of each functional module.

[0018] In a possible design, the plurality of functional modules include a first functional module and a second functional module. The calculation module is specifically configured to add the number of single particle functional interruption occurrences of the first functional module and the number of single particle functional interruption occurrences of the second functional module if the logical relationship between the first functional module and the second functional module is an AND relationship. If the logical relationship between the first functional module and the second functional module is an OR relationship, the number of single particle functional interruption occurrences of the first functional module and the number of single particle functional interruption occurrences of the second functional module are multiplied.

[0019] In a possible design, different functional modules correspond to different protection measures.

[0020] The beneficial effects of the second aspect can refer to the description of the first aspect.

[0021] In a third aspect, the present application provides a computer-readable storage medium, including computer instructions. When the computer instructions are executed on an electronic device, the electronic device executes the chip testing method in the above-mentioned first aspect and any possible implementation manner.

[0022] In a fourth aspect, the present application provides a computer program product, which, when executed on a computer or a processor, enables the computer or the processor to execute the chip testing method in the first aspect and any possible implementation manner.

[0023] It can be understood that any of the chip testing devices, computer-readable storage media or computer program products provided above can be applied to the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods and will not be repeated here.

[0024] These and other aspects of the present application will become more apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A curve diagram of integrated fluence rate-linear energy transfer of charged particles on a target orbit provided in an embodiment of the present application;

[0026] Figure 2 A cross-sectional-linear energy transfer curve diagram provided in an embodiment of the present application;

[0027] Figure 3 A flowchart of a method for calculating the number of occurrences of abnormal events of a chip provided in an embodiment of the present application;

[0028] Figure 4 A flowchart of another method for calculating the number of occurrences of abnormal events of a chip provided in an embodiment of the present application;

[0029] Figure 5 A flowchart of another method for calculating the number of occurrences of abnormal events of a chip provided in an embodiment of the present application;

[0030] Figure 6 A flowchart of a chip testing method provided in an embodiment of the present application;

[0031] Figure 7 A flowchart of another chip testing method provided in an embodiment of the present application;

[0032] Figure 8 A flowchart of another chip testing method provided in an embodiment of the present application;

[0033] Fig. 9 A schematic diagram of the composition of a testing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] For ease of understanding, some examples of concepts related to the embodiments of the present application are provided for reference, as shown below:

[0035] Single event upset refers to a single particle hitting an integrated circuit, causing the circuit locked logic state to change from 1 to 0 or from 0 to 1. Single event upsets include soft upsets and hard errors (single event hard error, SEHE). Among them, soft upsets are not destructive. Most single event upsets are soft upsets, and the logic unit can be rewritten or reset. Hard errors refer to permanent damage to the semiconductor device medium caused by single particle impacts, which is an irreversible state.

[0036] Single-event transient refers to a transient current pulse generated when a charged particle hits a combinatorial logic block. If the combinatorial logic block runs fast enough and introduces a transient current pulse during propagation, the transient current pulse may be considered a valid signal, and thus the transient current pulse may be saved as real data.

[0037] Single event latch-up refers to a potentially or permanently destructive state in an integrated circuit caused by a single event strike, which triggers a parasitic thyristor structure equivalent to a silicon-controlled rectifier, creating a low-impedance, high-current channel.

[0038] Space radiation environment models, such as the cosmic ray effects on micro-electronics code (CREME96) model published in 1996 or the space radiation model.

[0039] Linear energy transfer (LET) refers to the energy deposited by a charged particle (such as an ion) per unit length along the incident direction. It is usually used to measure the ability of a charged particle to generate charge when passing through a semiconductor material. Among them, linear energy transfer depends on the mass of the incident charged particle, the energy of the incident charged particle, and the material density of the incident semiconductor material. The unit of linear energy transfer is the energy lost per unit length of the path (million electron volts (MeV) / centimeter (cm)), and the unit after normalization for material density is (MeV*cm 2 / milligram (mg)).

[0040] Fluence is the number of charged particles incident on a unit area, expressed in charged particles per square centimeter (charged particles / cm 2 Correspondingly, the flux rate represents the number of charged particles incident on a unit area per unit time, and the unit is the number of charged particles per square centimeter per second (charged particles / cm 2 *seconds. Charged particles of different energies in the space environment (such as heavy ions and protons) have corresponding fluence and fluence rate, which can be obtained through the space radiation environment model. Figure 1 The integral fluence rate-linear energy transfer curve (flux-LET curve) of charged particles on the target orbit is shown. Figure 1 The horizontal axis is the linear energy transfer, and the vertical axis is the integrated fluence rate.

[0041] The cross section (σ) represents the number of observable abnormal events caused by a unit fluence of charged particles. It is generally used to measure the sensitivity of a circuit to a charged particle impact of a certain energy. The abnormal event can be a single particle upset, a single particle functional interruption, or an uncorrectable bit error. The abnormal event can also be called a single particle event. The mathematical expression of the cross section can be: Where N is the number of abnormal events caused by charged particles, and fluence is the number of charged particles incident on a unit area. The unit of fluence is the number of charged particles / cm 2 , then the unit of σ is cm 2 .

[0042] Cross-section-linear energy transfer curve (σ~LET curve), different charged particles have different linear energy transfer values, and specific linear energy transfer values ​​correspond to their respective cross-sections. Therefore, by using a variety of charged particles with different linear energy transfers to conduct accelerated irradiation experiments on the chip, a cross-section-linear energy transfer curve can be obtained, such as Figure 2 In addition, Figure 2 The saturation cross section and the linear energy transfer threshold are also shown in FIG. 1 , wherein the saturation cross section is the cross section when the cross section no longer increases with increasing the linear energy transfer value of the incident charged particles, and the linear energy transfer threshold is the minimum linear energy transfer value that can produce the number of observable abnormal events. In an example, the linear energy transfer corresponding to the 1% saturation cross section can be defined as the linear energy transfer threshold.

[0043] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0044] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this embodiment, unless otherwise specified, "plurality" means two or more.

[0045] The σ~LET curve of the charged particles in the target track and the integral flux~LET curve can be integrated to obtain the number of occurrences of abnormal events represented by the σ~LET curve, thereby evaluating whether the protection measures of the chip are appropriate.

[0046] In one example, if Figure 3 As shown, Figure 3 A flowchart of a method for calculating the number of occurrences of abnormal events of a chip provided in an embodiment of the present application. The method multiplies the saturation cross section of the chip by the integrated injection rate to obtain the number of occurrences of abnormal events of the chip in the target track. Figure 3 The σ~LET curve and the equivalent σ~LET curve are shown in Figure 3 The integrated flux-LET curve when the target orbit is a low earth orbit (LEO) and the integrated flux-LET curve when the target orbit is a geostationary earth orbit (GEO) are shown in the figure. The specific steps in the method may include: (1) obtaining the saturation cross section and linear energy transfer threshold of the chip through an accelerator irradiation experiment. (2) inputting the target orbit information into the space radiation environment model, obtaining the fluence rate of charged particles in the target orbit through the space radiation environment model, and obtaining the integrated fluence rate of some charged particles whose linear energy transfer values ​​among all charged particles are greater than the linear energy transfer threshold. (3) multiplying the saturation cross section of the chip and the integrated fluence rate of some charged particles to obtain the number of abnormal events of the chip.

[0047] However, the number of abnormal events of the chip calculated by this method cannot be generalized or generalized, that is, accelerated irradiation experiments need to be performed for each chip, which increases the testing cost. In addition, this method can only obtain test results after the chip is designed, and it is impossible to adjust the protection measures and predict the protection effect during the chip development stage.

[0048] In another example, Figure 4 As shown, Figure 4A flowchart of another method for calculating the number of occurrences of abnormal events of a chip provided in an embodiment of the present application. The method predicts the number of occurrences of abnormal events of a chip based on the single particle characteristics of a logic unit (such as a memory bitcell and a register unit (flip flop, FF), etc.) and the number of logic units of the chip, wherein the logic unit can also be referred to as a basic logic resource. The specific steps in the method may include: (1) obtaining the σ~LET curve of the logic unit through an accelerator irradiation experiment to obtain a saturation cross section and a linear energy transfer threshold. (2) determining the relevant information of the chip, the relevant information may include the orbital information of the spacecraft where the chip is located (such as solar activity, etc.) and the spacecraft itself where the chip is located (such as the shielding condition of the spacecraft). (3) inputting the saturation cross section, the linear energy transfer threshold, the number of logic units and the relevant information of the chip into the space radiation environment model, the number of abnormal events of the chip in the target orbit can be obtained.

[0049] However, this method does not consider the impact of the chip architecture, application and working scenarios on the chip functional abnormality. It believes that the abnormality of all logic units will cause the chip to have a single-particle functional interruption. The number of abnormal events of the chip obtained is too large, and the accurate number of abnormal events of the chip cannot be obtained.

[0050] Therefore, another method for calculating the number of occurrences of abnormal events of a chip is proposed, such as Figure 5 As shown, Figure 5A flowchart of another method for calculating the number of occurrences of abnormal events of a chip provided in an embodiment of the present application. The method proposes that not all flips of logic units will lead to single-particle functional interruptions, and introduces the concept of sensitive resources for correcting the final prediction results, wherein the proportion of sensitive resources can be obtained by analyzing the configuration random access memory (CRAM) of a field programmable gate array (FPGA) by a specific development tool. The specific steps in the method may include: (1) obtaining the σ~LET curve of the logic unit through an accelerator irradiation experiment to obtain a saturation cross section and a linear energy transfer threshold. (2) determining the relevant information of the chip, the relevant information may include the orbital information of the spacecraft where the chip is located (such as solar activity, etc.) and the spacecraft itself where the chip is located (such as the shielding of the spacecraft). (3) inputting the saturation cross section, the linear energy transfer threshold, the number of logic units and the relevant information of the chip into the space radiation environment model, the number of abnormal events of the chip in the target orbit can be obtained. (4) multiplying the number of occurrences of the abnormal event by the proportion of sensitive resources to obtain the final number of abnormal events of the chip in the target orbit.

[0051] However, this method cannot realize the sensitive resource ratio analysis of application specific integrated circuit (ASIC), and cannot be applied to the calculation of the number of abnormal events of ASIC chips. In addition, this method can only obtain test results after the chip is designed, and cannot select protection measures and predict protection effects during the chip development stage.

[0052] Therefore, the embodiment of the present application provides a chip testing method, which divides the chip into functional modules. The number of single-particle functional interruptions of each functional module in the chip can be predicted by the number of logic units in each functional module of the chip and the single-particle characteristics of the logic units, and the number of single-particle functional interruptions of the chip can be obtained by considering the influence of the architecture (i.e., logical relationship) between multiple functional modules on the chip. Since the chip testing method of the embodiment of the present application calculates the number of single-particle functional interruptions based on the logic units of the chip, it can be applied to a variety of chips with different processes and different architectures, and the method can calculate the number of single-particle functional interruptions of the chip during the research and development stage of the chip, thereby timely adjusting the chip protection measures to avoid problems such as insufficient protection or excessive protection in the protection measures adopted by the chip, and the reliability of the on-orbit chip can be improved.

[0053] In the above scenario, the chip testing method and device of the present application can be applied to different systems or devices, such as an execution device. The execution device can be a terminal, such as a mobile phone, a tablet computer, a laptop computer, an augmented reality (AR) device, a virtual reality (VR) device, a vehicle terminal, etc., and can also be a server, etc. The chip testing method provided in the present application can be applied to the scenario of calculating the number of occurrences of single-particle functional interruptions involved in the execution device.

[0054] In some embodiments, the chip test device proposed in the present application can be a chip, for example, the chip is a system-on-a-chip (SoC). The SoC includes a processor, a memory, and an input / output (I / O) interface, etc. The processor can be a single-core processor or a multi-core processor. After the processor loads the data and application in the memory, it processes the data, for example, calculating the number of single-particle functional interruptions of the chip in the present application.

[0055] It can be understood that the chip proposed in this application can be used in a space environment, and thus, the chip proposed in this application can also be called an on-orbit chip.

[0056] Applied to the above-mentioned device or equipment, the chip testing method provided in the embodiment of the present application is introduced below.

[0057] The present application embodiment provides a chip testing method, such as Figure 6 As shown, Figure 6 A flow chart of a chip testing method provided in an embodiment of the present application. The method includes the following process.

[0058] S601 . Based on the number of logic units of each functional module of the chip and the single-particle characteristics of the logic units, obtain the number of occurrences of single-particle functional interruptions of each functional module.

[0059] Among them, the logic unit uses at least one protection measure, and the single particle characteristic is the corresponding relationship between the linear energy transfer and the cross section of the single particle incident on the logic unit, that is, the σ~LET curve.

[0060] Exemplarily, a logic unit is the smallest unit for implementing user logic in an FPGA. In one classification method, a logic unit may be a storage unit, a register unit, or a clock tree, etc. In another classification method, a logic unit may include a sequential logic unit and a combinational logic unit. In one example, a sequential logic unit may be a latch, a trigger, and a register, etc., and a combinational logic unit may be a data selector, a data comparator, an adder, and an encoder, etc.

[0061] Exemplarily, the protection measures can also be called reinforcement measures, wherein the protection measures can be triple modular redundancy (TMR), error correction code (ECC) plus interleaving, and time redundancy, etc. Among them, triple modular redundancy is to use three identical modules to perform the same operation respectively, and take the majority of the same output as the correct output of the voting system, usually three out of two, that is, as long as two identical errors do not occur at the same time in the three modules, the error of the faulty module can be masked to ensure the correct output of the system. Error correction code is a code that can be discovered or corrected by the receiving end after an error occurs during the transmission process. Error correction code plus interleaving can disperse burst errors and improve the error correction capability. Time redundancy is a fault-tolerant idea that uses the continuous characteristics of time to repeatedly execute the system process where the error occurs to eliminate the error when an occasional error occurs in the system. Among them, the protection measures taken for the functional module can be determined according to the important procedures of the functional module. For example, for more important functional modules, protection measures such as triple modular redundancy can be used, and for unimportant functional modules, protection measures such as error correction code plus interleaving can be used.

[0062] Among them, different functional modules can correspond to different protection measures.

[0063] In one example, the functional modules can be divided based on different protection measures of the chip. Specifically, the circuit using protection measures such as triple modular redundancy can be divided into functional module A, the circuit using protection measures such as error correction code plus interleaving can be divided into functional module B, and the circuit using protection measures such as time redundancy can be divided into functional module C. In addition, the circuit using protection measures such as triple modular redundancy and error correction code plus interleaving can be divided into functional module D, or the circuit using protection measures such as triple modular redundancy, error correction code plus interleaving, and time redundancy can be divided into functional module E.

[0064] In another example, the functional modules can also be divided based on the functional components of the chip. Taking the chip as a central processing unit (CPU) as an example, the CPU can include functional module A, functional module B and functional module C, wherein functional module A can be a cache, functional module B can be an addressing unit, and functional module C can be an execution unit, etc. In addition, taking the chip as a memory as an example, the memory can include functional module A, functional module B and functional module C, wherein functional module A can be a decoder, functional module B can be a control logic circuit, and functional module C can be a storage array, etc.

[0065] It is understandable that the embodiments of the present application do not impose specific restrictions on the division of functional modules, and the functional modules of the chip can also be divided based on other methods.

[0066] Exemplarily, in order to solve the generalization problem of ASIC chips and reduce the testing cost, and avoid repeated accelerated irradiation experiments on different chips, a method for predicting the number of single-particle functional interruptions can be used. The principle of its prediction can be: for functional modules using the same protection measures, the number of single-particle functional interruptions is positively correlated with the number of logic units. Specifically, taking functional module A as an example, functional module A uses protection measures such as triple-module redundancy. Assuming that functional module A includes 100 logic units, an accelerated irradiation experiment is performed on functional module A to obtain the single-particle characteristics of functional module A. Based on the single-particle characteristics of functional module A, the number of single-particle functional interruptions of functional module A can be obtained. If functional module X also uses protection measures such as triple-module redundancy, and functional module X includes 1000 logic units, it can be predicted that the number of single-particle functional interruptions of functional module X is 10a. Therefore, the present application can predict and evaluate the number of single-particle functional interruptions of various types of ASIC chips with different architectures under a specific process platform based on the single-particle characteristics of logic units under the process platform.

[0067] Therefore, the present application can obtain the number of single-particle functional interruptions of each functional module of the chip through the single-particle characteristics of the number of logic units corresponding to each different protection measure and the number of logic units of each functional module.

[0068] Optionally, S601 may include: obtaining the number of occurrences of the first single-particle functional interruption of each functional module based on the number of logic units of each functional module of the chip and the single-particle characteristics of the logic units. Obtaining the number of occurrences of the single-particle functional interruption of each functional module based on the number of occurrences of the first single-particle functional interruption of each functional module and the weight corresponding to each functional module.

[0069] In a possible example, if the chip is divided into functional modules based on protection measures, assuming that the chip includes functional module A, functional module B and functional module C, wherein the number of occurrences of the first single particle functional interruption of functional module A is a1, the number of occurrences of the first single particle functional interruption of functional module B is b1, and the number of occurrences of the first single particle functional interruption of functional module C is c1. In addition, the weight of functional module A obtained based on the FMEA method or the FTA method is a2, the weight of functional module B is b2, and the weight of functional module C is c2, then the number of occurrences of the single particle functional interruption of functional module A is a1*a2, the number of occurrences of the single particle functional interruption of functional module B is b1*b2, and the number of occurrences of the single particle functional interruption of functional module C is c1*c2.

[0070] In another possible example, if the chip is divided into functional modules based on functional components, it is assumed that the chip includes functional module A, wherein functional module A includes functional components A1, A2 and A3 that use three protection measures respectively. Among them, the weight of functional component A1 in functional module A is a1, the weight of functional component A2 in functional module A is a2, and the weight of functional component A3 in functional module A is a3. In addition, based on the FMEA method or the FTA method, the weight corresponding to functional component A1 is a4, the weight corresponding to functional component A2 is a5, and the weight corresponding to functional component A3 is a6, then the weight of functional module A is a1*a4+a2*a5+a3*a6. After calculating the number of occurrences of the first single-particle functional interruption of functional module A, the number of occurrences of the first single-particle functional interruption of functional module A is multiplied by the weight of functional module A, that is, the number of occurrences of the single-particle functional interruption of functional module A can be obtained.

[0071] Therefore, by introducing the weight of the first logic unit in the logic unit, the accuracy of calculating the number of occurrences of single-particle functional interruptions of the chip can be improved.

[0072] Optionally, S601 may further include: inputting the number of logic units of each functional module, the single particle characteristics of the logic unit and the target orbit information of the chip into the space radiation environment model to obtain the number of occurrences of the first single particle functional interruption of each functional module.

[0073] Exemplarily, the single particle characteristics of the logic unit are σ~LET curves of different protection measures and different numbers of logic units. The target orbit information of the chip may include orbit information of a geostationary orbit or a low orbit. Specifically, the orbit information may include perigee, apogee, inclination, argument of perigee, and solar activity status during the mission cycle.

[0074] S602 : Obtain the number of single-particle functional interruption occurrences of the chip based on the logical relationship between the multiple functional modules and the number of single-particle functional interruption occurrences of each functional module.

[0075] Exemplarily, the logical relationship between multiple functional modules is also the architecture of the chip, wherein the logical relationship between multiple functional modules can be an AND relationship or an OR relationship. If the logical relationship between multiple functional modules is an AND relationship, that is, when the functions of the multiple functional modules are normal, the function of the chip is normal. If the logical relationship between multiple functional modules is an OR relationship, that is, when the function of any one of the multiple different functional modules is normal, the function of the chip is normal.

[0076] The plurality of functional modules may include a first functional module and a second functional module. If the logical relationship between the first functional module and the second functional module is an AND relationship, the number of single particle functional interruption occurrences of the first functional module and the number of single particle functional interruption occurrences of the second functional module are added. If the logical relationship between the first functional module and the second functional module is an OR relationship, the number of single particle functional interruption occurrences of the first functional module and the number of single particle functional interruption occurrences of the second functional module are multiplied.

[0077] Exemplarily, taking a chip including a first functional module, a second functional module and a third functional module as an example, if the logical relationship between the first functional module and the second functional module is an AND relationship, after determining the number of single particle functional interruption occurrences of the first functional module and the number of single particle functional interruption occurrences of the second functional module, the number of single particle functional interruption occurrences of the first functional module and the number of single particle functional interruption occurrences of the second functional module are added. If the relationship between the third functional module and the first functional module and the second functional module is also an AND relationship, the number of single particle functional interruption occurrences of the first functional module and the number of single particle functional interruption occurrences of the second functional module are added, and then the number of single particle functional interruption occurrences of the third functional module are added, and finally the number of single particle functional interruption occurrences of the chip is obtained.

[0078] In another possible implementation, taking the chip including the first functional module, the second functional module and the third functional module as an example, if the logical relationship between the first functional module and the second functional module is an OR relationship, after determining the number of single particle functional interruption occurrences of the first functional module and the number of single particle functional interruption occurrences of the second functional module, the number of single particle functional interruption occurrences of the first functional module and the number of single particle functional interruption occurrences of the second functional module are multiplied. If the relationship between the third functional module and the first functional module and the second functional module is also an OR relationship, the number of single particle functional interruption occurrences of the first functional module and the number of single particle functional interruption occurrences of the second functional module are multiplied, and then the number of single particle functional interruption occurrences of the third functional module are multiplied, and finally the number of single particle functional interruption occurrences of the chip is obtained.

[0079] In another possible implementation, taking the chip including the first functional module, the second functional module and the third functional module as an example, if the logical relationship between the first functional module and the second functional module is an OR relationship, after determining the number of single particle functional interruption occurrences of the first functional module and the number of single particle functional interruption occurrences of the second functional module, the number of single particle functional interruption occurrences of the first functional module and the number of single particle functional interruption occurrences of the second functional module are multiplied. If the relationship between the third functional module and the first functional module and the second functional module is an AND relationship, the number of single particle functional interruption occurrences of the first functional module and the number of single particle functional interruption occurrences of the second functional module are multiplied and then added to the number of single particle functional interruption occurrences of the third functional module. By analogy, the logical relationships of all functional modules are traversed to finally obtain the number of single particle functional interruption occurrences of the chip.

[0080] Optionally, the chip testing method provided in the embodiment of the present application also includes: if the number of single-particle functional interruptions of the chip is greater than the target threshold, adjusting the protection measures of the functional module and / or adjusting the logical relationship between multiple functional modules, and repeating the calculation step of the number of single-particle functional interruptions of the chip until the number of single-particle functional interruptions of the chip is less than or equal to the target threshold.

[0081] For example, the target threshold may be related to the design requirements of the chip. If the number of single-particle functional interruptions of the chip is greater than the target threshold, it can be considered that the chip does not meet the design requirements at this time, and the logical relationship and protection measures of the functional modules of the chip can be optimized and iterated, and then the number of single-particle functional interruptions of the chip can be recalculated until the chip meets the design requirements.

[0082] Specifically, Figure 7 As shown, Figure 7 A flowchart of another chip testing method provided in an embodiment of the present application. The process may include:

[0083] S701, obtaining input information. The input information may include the σ~LET curve of the logic unit of the current chip, that is, the σ~LET curve of different protection measures and different numbers of logic units. The input information may also include target orbit information, which may include perigee, apogee, inclination, argument of perigee, and solar activity status during the mission cycle.

[0084] S702, calculating the number of single-particle functional interruption occurrences of the chip. That is, firstly calculating the number of single-particle functional interruption occurrences of each functional module, and then obtaining a new number of single-particle functional interruption occurrences of the chip based on the new logical relationship between the multiple functional modules and the number of single-particle functional interruption occurrences of each functional module.

[0085] S703: Determine whether the number of new single-particle functional interruption occurrences of the chip is less than or equal to the target threshold. If the number of new single-particle functional interruption occurrences of the chip is greater than the target threshold, execute S704. If the number of new single-particle functional interruption occurrences of the chip is less than or equal to the target threshold, execute S705.

[0086] S704, adjusting the protection measures of the functional modules and the logical relationship of the multiple functional modules. That is, for the functional modules, the protection measures with lower fault tolerance can be adjusted to protection measures with stronger fault tolerance. In a specific example, the protection measures of the functional modules can be replaced from time redundancy to triple module redundancy. In addition, the logical relationship between two functional modules can be adjusted from an OR relationship to an AND relationship, or the logical relationship between two functional modules can be adjusted from an AND relationship to an OR relationship.

[0087] S705, end, that is, the iterative process of chip testing ends.

[0088] Therefore, the chip testing method provided in the embodiment of the present application can calculate the number of single-particle functional interruptions of the chip during the chip research and development stage to adjust protection measures and predict protection effects, thereby avoiding insufficient or excessive protection caused by the protection measures adopted by the chip and improving the reliability of the on-orbit chip.

[0089] Optionally, the chip testing method provided in the embodiment of the present application may further include: obtaining the weight of the first logic unit in the logic units of each functional module based on a failure mode and effects analysis (FMEA) method.

[0090] Exemplarily, a first logic unit in the logic units may be a logic unit that is easily flipped when hit by a single particle, and the first logic unit may also be referred to as a sensitive resource.

[0091] Exemplarily, the failure mode and effect analysis method is to analyze the sub-circuits, parts and various processes of the chip in the chip design stage, find out all potential failure modes, and analyze the possible consequences of the failure modes, so as to take necessary measures in advance to improve the quality and reliability of the product. Therefore, the failure mode and effect analysis method can obtain the weight of the first logic unit in the logic unit of each functional module in the concept stage of the chip.

[0092] In addition, the weight of the first logic unit in the logic units of each functional module can also be obtained based on a fault tree analysis (FTA) method. The fault tree analysis method identifies all possible causes based on a single potential failure mode, thereby analyzing chip errors.

[0093] like Figure 8 As shown, Figure 8 A flowchart of another chip testing method provided in an embodiment of the present application. The method may include S1 to S8, wherein S1: based on different protection measures, the functional modules are divided, and the chip may include functional module A, functional module B, functional module C, ..., functional module X, functional module A corresponds to input information A, functional module B corresponds to input information B, functional module C corresponds to input information C, and functional module X corresponds to input information X. S2: Obtain σ~LET curves for different protection measures and different numbers of logical units. S3: Obtain target orbit information. S4: Obtain the number of logical units, and input the σ~LET curve, target orbit information, and the number of logical units into the space radiation environment model. S5: Obtain the number of first single-particle functional interruptions of each functional module of the chip. S6: Obtain weights. S7: Multiply the number of first single-particle functional interruptions of each functional module of the chip by the weight to obtain the number of single-particle functional interruptions of each functional module of the chip. S8: Determine the number of single event functional interruption occurrences of the chip based on the logical relationship between the multiple functional modules and the number of single event functional interruption occurrences of each functional module (eg, SEFI_A, SEFI_B, SEFI_C, . . . , SEFI_X).

[0094] It is understandable that in order to implement the above functions, the electronic device includes hardware and / or software modules corresponding to the execution of each function. In combination with the algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to be beyond the scope of the present application.

[0095] In this embodiment, the electronic device can be divided into functional modules according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0096] In the case of dividing each functional module into corresponding functional modules, Fig. 9 A possible schematic diagram of the composition of the testing device 900 involved in the above embodiment is shown. Fig. 9 As shown, the testing device 900 may include: an acquisition module 901 and a calculation module 902 .

[0097] The acquisition module 901 may be used to support the test device 900 to execute the above step S601 and / or other processes of the solution described herein.

[0098] The computing module 902 may be used to support the testing device 900 in executing the above step S602 and / or other processes of the technology described herein.

[0099] It should be noted that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0100] The testing device 900 provided in this embodiment is used to execute the testing method of the above chip, and thus can achieve the same effect as the above implementation method.

[0101] In the case of using an integrated unit, the test device 900 may include a processing module, a storage module and a communication module. Among them, the processing module can be used to control and manage the actions of the test device 900, for example, it can be used to support the test device 900 to execute the steps executed by the above-mentioned acquisition module 901 and calculation module 902. The storage module can be used to support the test device 900 to store program codes and data, etc. The communication module can be used to support the communication between the test device 900 and other devices, such as communication with wireless access devices.

[0102] Among them, the processing module can be a processor or a controller. It can implement or execute various exemplary logic boxes, modules and circuits described in conjunction with the disclosure of this application. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of digital signal processing (DSP) and a microprocessor, etc. The storage module can be a memory. The communication module can specifically be a device that interacts with other electronic devices, such as a radio frequency circuit, a Bluetooth chip, a Wi-Fi chip, etc.

[0103] The embodiment of the present application also provides an electronic device, including one or more processors and one or more memories. The one or more memories are coupled to the one or more processors, and the one or more memories are used to store computer program codes, and the computer program codes include computer instructions. When the one or more processors execute the computer instructions, the electronic device executes the above-mentioned related method steps to implement the chip testing method in the above-mentioned embodiment.

[0104] An embodiment of the present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on an electronic device, the electronic device executes the above-mentioned related method steps to implement the chip testing method in the above-mentioned embodiment.

[0105] An embodiment of the present application further provides a computer program product. When the computer program product is run on a computer, the computer is caused to execute the above-mentioned related steps to implement the chip testing method executed by the electronic device in the above-mentioned embodiment.

[0106] In addition, an embodiment of the present application also provides a device, which may specifically be a chip, component or module, and the device may include a connected processor and a memory; wherein the memory is used to store computer execution instructions, and when the device is running, the processor may execute the computer execution instructions stored in the memory so that the chip executes the chip testing method executed by the electronic device in the above-mentioned method embodiments.

[0107] Among them, the electronic device, computer-readable storage medium, computer program product or chip provided in this embodiment are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above and will not be repeated here.

[0108] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0109] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0110] The units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0111] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0112] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0113] The above contents are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip testing method, characterized in that: The method comprises: Based on the number of logic units of each functional module of the chip and the single particle characteristics of the logic units, the number of single particle function interruption occurrences of each functional module is obtained, the logic unit uses at least one protection measure, and the single particle characteristics are the corresponding relationship between the linear energy transfer and the cross section of the single particle incident on the logic unit; The number of occurrences of the single event functional interruption of the chip is obtained based on the logical relationship between the multiple functional modules and the number of occurrences of the single event functional interruption of each functional module.

2. The method according to claim 1, characterized in that The method further comprises: If the number of occurrences of the single-particle functional interruption of the chip is greater than a target threshold, the protection measures of the functional modules in the chip and / or the logical relationship between the multiple functional modules are adjusted, and the step of calculating the number of occurrences of the single-particle functional interruption of the chip is repeatedly executed until the number of occurrences of the single-particle functional interruption of the chip is less than or equal to the target threshold.

3. The method according to claim 1, characterized in that The step of obtaining the number of logic units of each functional module of the chip and the single-particle characteristics of the logic units to obtain the number of single-particle functional interruption occurrences of each functional module includes: Based on the number of logic units of each functional module of the chip and the single-particle characteristics of the logic units, obtaining the number of occurrences of the first single-particle functional interruption of each functional module; Based on the first single event functional interruption occurrence number of each functional module and the weight corresponding to each functional module, the single event functional interruption occurrence number of each functional module is obtained.

4. The method according to claim 3, characterized in that The method further comprises: The weight of the first logic unit in the logic units of each functional module is obtained based on a failure mode and effect analysis method.

5. The method according to claim 3 or 4, characterized in that: The obtaining, based on the number of logic units of each functional module of the chip and the single-particle characteristics of the logic units, the number of occurrences of the first single-particle functional interruption of each functional module comprises: The number of logic units of each functional module, the single particle characteristics of the logic units and the target orbit information of the chip are input into a space radiation environment model to obtain the number of occurrences of the first single particle function interruption of each functional module.

6. The method according to claim 1, characterized in that The multiple functional modules include a first functional module and a second functional module, and obtaining the number of single-particle functional interruption occurrences of the chip based on the logical relationship between the multiple functional modules and the number of single-particle functional interruption occurrences of each functional module includes: If the logical relationship between the first functional module and the second functional module is an AND relationship, then the number of occurrences of the single-particle functional interruption of the first functional module and the number of occurrences of the single-particle functional interruption of the second functional module are added; If the logical relationship between the first functional module and the second functional module is an OR relationship, the number of occurrences of the single event functional interruption of the first functional module and the number of occurrences of the single event functional interruption of the second functional module are multiplied.

7. The method according to any one of claims 1 to 6, characterized in that: Different functional modules correspond to different protection measures.

8. A chip testing device, characterized in that: The testing device comprises: an acquisition module, configured to obtain the number of occurrences of single-particle functional interruptions of each functional module of the chip based on the number of logic units of each functional module of the chip and the single-particle characteristics of the logic units, wherein the logic units use at least one protection measure, and the single-particle characteristics are the corresponding relationship between the linear energy transfer and the cross section of the single particle incident on the logic unit; The calculation module is used to obtain the number of occurrences of the single-particle functional interruption of the chip based on the logical relationship between the multiple functional modules and the number of occurrences of the single-particle functional interruption of each functional module.

9. The testing device according to claim 8, characterized in that: The testing device also includes: A judgment module is used for adjusting the protection measures of the functional modules and / or adjusting the logical relationship between the multiple functional modules if the number of occurrences of the single-particle functional interruption of the chip is greater than a target threshold, and repeatedly executing the step of calculating the number of occurrences of the single-particle functional interruption of the chip until the number of occurrences of the single-particle functional interruption of the chip is less than or equal to the target threshold.

10. The testing device according to claim 8, characterized in that: The acquisition module is specifically configured to obtain the number of occurrences of the first single-particle functional interruption of each functional module based on the number of logic units of each functional module of the chip and the single-particle characteristics of the logic units; Based on the first single event functional interruption occurrence number of each functional module and the weight corresponding to each functional module, the single event functional interruption occurrence number of each functional module is obtained.

11. The testing device according to claim 10, characterized in that: The acquisition module is further used to acquire the weight of the first logic unit in the logic units of each functional module based on a failure mode and effect analysis method.

12. The testing device according to claim 10 or 11, characterized in that: The acquisition module is specifically used to input the number of logic units of each functional module, the single particle characteristics of the logic unit and the target orbit information of the chip into the space radiation environment model to obtain the number of occurrences of the first single particle function interruption of each functional module.

13. The testing device according to claim 8, characterized in that: The multiple functional modules include a first functional module and a second functional module, and the calculation module is specifically configured to add the number of single particle functional interruption occurrences of the first functional module and the number of single particle functional interruption occurrences of the second functional module if the logical relationship between the first functional module and the second functional module is an AND relationship; If the logical relationship between the first functional module and the second functional module is an OR relationship, the number of occurrences of the single event functional interruption of the first functional module and the number of occurrences of the single event functional interruption of the second functional module are multiplied.

14. The testing device according to any one of claims 8 to 13, characterized in that: Different functional modules correspond to different protection measures.

15. A computer-readable storage medium, characterized in that: The method comprises computer instructions, which, when executed on an electronic device, cause the electronic device to execute the method according to any one of claims 1 to 7.

16. A computer program product, characterized in that When the computer program product runs on a computer or a processor, the computer or the processor is caused to execute the method according to any one of claims 1 to 7.

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