Mechanical grinding method for incomplete wafer
The wafer lobes are repaired through metal bonding, and mechanically grinding is performed after forming a complete wafer, which solves the problems of uneven grinding and poor cutting effects caused by the lobes, and achieves better thinning and cutting performance.
Patent Information
- Application Number
- CN202411915425.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-24
- Publication Date
- 2025-04-18
AI Technical Summary
During wafer transportation, wafer lobes are caused by external impact stress, which leads to displaced impact, dropping and edge stress concentration during mechanical grinding and thinning, causing the sheet collapse, and the inability to effectively grind.
The wafer lobes are repaired by metal bonding. By providing the lobe wafer and the fake wafer, the wafer fragments are selected and the fake wafers that can be spliced out from the fake wafer are cut out, and the seed layer is formed and connected through the electroplating process to form a complete wafer and then mechanically grind it.
It improves the mechanical grinding thinning effect and cutting effect of incomplete wafers, ensures uniformity of thickness distribution, and reduces the influence of viscous impurities during cutting, and improves the cutting effect.
Smart Images
Figure CN119852165A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit manufacturing technology, and more specifically, to a mechanical polishing method for incomplete wafers. Background Technology
[0002] During transportation, wafers are often cracked due to external impact stress, breaking a complete wafer into several irregularly shaped and incomplete fragments. Before the wafer is diced into individual chips, it needs to undergo wafer thinning to meet the chip thickness requirements. This is typically done by mechanical grinding on the back side of the wafer. To ensure uniform thickness after thinning, the entire wafer needs to be ground. Because the fragments are broken into several pieces, the thinning equipment cannot hold them in place. This increases the risk of wafer displacement, impact, or falling during the thinning process. Furthermore, the irregular outlines of the fragments can cause stress concentration at the edges during mechanical grinding, leading to secondary cracking and making further grinding impossible.
[0003] Current technologies often use adhesive bonding to fix broken wafer fragments back into a complete wafer before mechanical grinding. However, during mechanical grinding, adhesive-bonded wafers can produce sticky impurities that affect the uniformity of thinning. Furthermore, wafers thinned by mechanical grinding still need to be cut into individual chips, and the adhesive used in bonding can adhere to the cutting edge, weakening the cutting ability, reducing the cutting width, and lowering the cutting effect. Summary of the Invention
[0004] The purpose of this invention is to propose a mechanical grinding method for incomplete wafers, which uses metal bonding to repair wafer cleavage, resulting in better flatness of the stitched wafer, thereby improving the mechanical grinding and thinning effect and cutting effect of incomplete wafers.
[0005] To achieve the above objectives, this invention proposes a mechanical polishing method for incomplete wafers, comprising:
[0006] Provide a sharded wafer and a dummy wafer with the same size and thickness as the sharded wafer, wherein the front side of the sharded wafer is an effective circuit layer;
[0007] Select wafer fragments from the diced wafers, and cut out dummy wafers from the dummy wafers based on the selected wafer fragments so that they can be spliced together with the wafer fragments to form a complete wafer;
[0008] Seed layers are formed on the cracked cross-section of the wafer fragment, the spliced cross-section of the dummy wafer, the back side of the wafer fragment, and the back side of the dummy wafer.
[0009] The cracked cross-section of the wafer fragment is aligned with the splicing cross-section of the dummy wafer, and an electroplating process is used to form an electroplating layer on the seed layer to support and connect the wafer fragment and the dummy wafer, so that the wafer fragment and the dummy wafer are spliced together into a complete wafer.
[0010] After the film is applied to the front side of the complete wafer, the back side of the complete wafer is mechanically ground to reduce the wafer thickness.
[0011] Optionally, wafer fragments are selected from the diced wafer, and based on the selected wafer fragments, dummy wafer dies that can be spliced with the wafer fragments to form a complete wafer are cut from the dummy wafer, including:
[0012] Select the wafer fragment with the largest area from the diced wafers as a template;
[0013] Place the selected wafer fragment face up on the dummy wafer, and align the arc edge of the wafer fragment with the edge of the dummy wafer;
[0014] The dummy wafer is cut along the broken edge of the wafer fragment to cut out a dummy wafer slab that can be spliced with the wafer fragment to form a whole wafer.
[0015] Optionally, a seed layer is formed at the crack cross-section of the wafer fragment, the splicing cross-section of the dummy wafer, the back side of the wafer fragment, and the back side of the dummy wafer, including:
[0016] A photoresist layer is formed on the front side of the wafer fragment and the dummy wafer.
[0017] The wafer fragment and the dummy wafer are placed together in the PVD process chamber with their back sides facing up.
[0018] A first metal layer is sputtered on the cracked cross-section of the wafer fragment, the spliced cross-section of the dummy wafer, the back side of the wafer fragment, and the back side of the dummy wafer, and a second metal layer is sputtered on the first metal layer, wherein the first metal layer and the second metal layer form the seed layer.
[0019] Remove the photoresist layer on the front side of the wafer fragment and the dummy wafer.
[0020] Optionally, when sputtering the first metal layer and the second metal layer to form a seed layer, the closest distance on the projection plane between the edge of the fracture region of the wafer fragment and the edge of the splicing region of the dummy wafer is not less than 2 mm.
[0021] Optionally, when the back side of the wafer fragment has a convex corner structure at the edge of the fracture region, a first metal layer is formed on the crack cross surface of the wafer fragment and the back side of the wafer fragment using a secondary sputtering process, and a second metal layer is formed on the first metal layer using a secondary sputtering process, so that the seed layer on the wafer fragment reaches the target thickness.
[0022] Optionally, when the back side of the dummy wafer has a convex corner structure at the edge of the splicing area, a second splicing process is used to form a first metal layer on the splicing section surface of the dummy wafer and the back side of the dummy wafer, and a second metal layer is formed on the first metal layer using a second splicing process, so that the seed layer on the dummy wafer reaches the target thickness.
[0023] Optionally, the material of the first metal layer is Ti; the material of the second metal layer is Cu.
[0024] Optionally, the thickness of the first metal layer is 12–255 nm; the thickness of the second metal layer is 25–870 μm.
[0025] Optionally, the cracked cross-section of the wafer fragment is aligned with the spliced cross-section of the dummy wafer, and an electroplating process is used to form an electroplated layer on the seed layer to support and connect the wafer fragment and the dummy wafer, including:
[0026] The wafer fragment and the dummy wafer are placed in an electroplating fixture, with the front side of the wafer fragment and the front side of the dummy wafer on the same plane, and the cracked cross-section of the wafer fragment and the spliced cross-section of the dummy wafer are spliced together.
[0027] An electroplating layer is formed on the seed layer of the cracked cross-section of the wafer fragment and the splicing cross-section of the dummy wafer, the back side of the wafer fragment, and the back side of the dummy wafer through an electroplating process. The electroplating layer fills the gap between the cracked cross-section of the wafer fragment and the splicing cross-section of the dummy wafer, and covers the back side of the wafer fragment and the back side of the dummy wafer.
[0028] Optionally, the material of the electroplated layer is Cu; the thickness of the electroplated layer is 23 to 2300 μm.
[0029] The beneficial effects of this invention are as follows:
[0030] The method of this invention first cuts out dummy wafers from selected wafer fragments from a dummy wafer, which can be spliced with the wafer fragments to form a complete wafer. Then, a seed layer is formed on the cracked cross-section of the wafer fragment, the splicing cross-section of the dummy wafer, the back side of the wafer fragment, and the back side of the dummy wafer. Next, an electroplating process is used to form an electroplated layer on the seed layer on the wafer fragment and the dummy wafer, which supports and connects the wafer fragment and the dummy wafer, allowing them to be spliced into a complete wafer. Finally, after applying a film to the front side of the complete wafer, the back side of the wafer is mechanically ground to thin it. This method utilizes metal bonding to repair the wafer. Compared to existing adhesive bonding methods, the circular wafers produced by this invention offer better flatness after stitching. Furthermore, during mechanical grinding, no sticky impurities are generated that affect the uniformity of thinning, resulting in thinned wafers with a more uniform thickness distribution. In addition, the wafers thinned by mechanical grinding still need to be cut into individual chips. The adhesive used in existing technologies tends to adhere to the cutting edge, weakening the cutting ability, reducing the cutting width, and lowering the cutting effect. However, the seed layer and electroplating layer materials used in the metal bonding of this invention are consistent with the metal (Cu) in the original wafer dicing channel, which can reduce the differences between the cutting objects and achieve better cutting results.
[0031] The system of the present invention has other features and advantages that will be apparent from or will be set forth in detail in the accompanying drawings and following detailed description, which together serve to explain the particular principles of the invention. Attached Figure Description
[0032] The above and other objects, features and advantages of the present invention will become more apparent from the accompanying drawings, in which like reference numerals generally denote like parts.
[0033] Figure 1 This is a schematic diagram of the morphology of a split wafer in one embodiment of the present invention.
[0034] Figure 2 This is a schematic diagram of the splicing of a dummy wafer and a split wafer in one embodiment of the present invention.
[0035] Figure 3 This is a cross-sectional view of the area where wafer fragments and dummy wafers are spliced together in one embodiment of the present invention.
[0036] Figure 4 This is a schematic diagram of the seed layer fabricated in the splicing area of wafer fragments and dummy wafers in one embodiment of the present invention.
[0037] Figure 5This is a schematic diagram illustrating the electroplating layer fabricated in the splicing area of wafer fragments and dummy wafers in one embodiment of the present invention.
[0038] Figure 6 This is a schematic diagram of the edge repair morphology of a wafer fragment after electroplating in one embodiment of the present invention. Detailed Implementation
[0039] The invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
[0040] Example
[0041] This embodiment provides a mechanical polishing method for incomplete wafers, the steps of which are as follows: Figure 1 As shown, it specifically includes:
[0042] S1: Provide a diced wafer 100 and a dummy wafer with the same size and thickness as the diced wafer 100, the front side of the diced wafer 100 being an effective circuit layer 104;
[0043] The cleaved wafer 100 provided in this step is a wafer that has been fractured due to external impact stress or other reasons. The type of wafer is not limited; it can be a wafer made of different materials such as silicon wafer, lithium niobate wafer, lithium tantalate wafer, silicon carbide wafer, gallium arsenide wafer, gallium nitride wafer, or thin-film wafer (SOI, POI, etc.). This embodiment uses the processing of a fractured single-crystal silicon wafer as an example for explanation. Because a single-crystal silicon wafer has a uniform orientation, the morphology of the fragments after cleaving is generally as follows: Figure 2 The through-crack 102 shown is unilinear, the front side of the cleaved wafer is the effective circuit layer 104, and the multiple wafer fragments 101 are irregular in shape and cannot be directly mechanically polished.
[0044] The dummy wafer provided in this step is a dummy wafer without circuit patterns. The thickness and size of the dummy wafer are the same as those of the diced wafer 100, and it is used to make dummy wafer 201.
[0045] S2: Select wafer fragment 101 from the diced wafer 100, and based on the selected wafer fragment 101, cut out a dummy wafer 201 from the dummy wafer that can be spliced with the wafer fragment 101 to form a complete wafer.
[0046] This step specifically includes:
[0047] Select the largest wafer fragment 101 from the diced wafer 100 as a template;
[0048] Place the selected wafer fragment 101 face up on the dummy wafer, and align the arc edge of the wafer fragment 101 with the edge of the dummy wafer.
[0049] A dummy wafer is cut along the broken edge of wafer fragment 101 to cut out a dummy wafer 201 that can be spliced with wafer fragment 101 to form a whole wafer.
[0050] Specifically, such as Figure 3 As shown, this step utilizes a dummy wafer of the same thickness as wafer fragment 101 as a template. The largest piece of the original wafer fragment 101 is used as a template, with its front side (effective circuit layer 104) facing upwards on the dummy wafer. The arc edge of the wafer fragment 101 is aligned with the edge of the dummy wafer. Then, the dummy wafer is cut along the broken edge of the wafer fragment 101 to create a dummy wafer template 201 that can be assembled with the wafer fragment 101 to form a complete piece. The preferred cutting method is an electroplated diamond wire saw. During the cutting process, the front side of the wafer fragment 101 needs to be protected with a protective film.
[0051] S3: A seed layer is formed on the cracked cross-section 103 of the wafer fragment 101, the splicing cross-section 202 of the dummy wafer 201, the back side 105 of the wafer fragment, and the back side 203 of the dummy wafer 201.
[0052] This step specifically includes:
[0053] First, a photoresist layer is formed on the front side (effective circuit layer 104) of the wafer fragment and the front side 204 of the dummy wafer; optionally, the thickness of the photoresist layer is 1 to 190 μm, preferably 4 to 81 μm.
[0054] Then, the wafer fragment 101 and the dummy wafer 201 are placed together with their back sides facing up into the PVD process chamber; in this embodiment, the splicing area between the wafer fragment 101 and the dummy wafer 201 is as follows: Figure 4 As shown. In the specific implementation process, in order to obtain a seed layer of the target thickness in the crack splicing area, a certain gap is required between the crack cross-section 103 of the wafer fragment 101 and the splicing cross-section 202 of the dummy wafer 201 during the splicing operation, so that the spliced metal atoms can be deposited on the crack cross-section 103 of the wafer fragment 101 and the splicing cross-section 202 of the dummy wafer 201. Therefore, when placing the wafer fragment 101 and the dummy wafer 201 together with their back sides facing up into the PVD process chamber, it is necessary to ensure that the closest distance on the projection plane between the edge of the fracture area of the wafer fragment 101 and the edge of the splicing area of the dummy wafer 201 is not less than 2 mm.
[0055] Subsequently, a first metal layer 301 is sputtered onto the cracked cross-section 103 of the wafer fragment 101, the spliced cross-section 202 of the dummy wafer 201, the back surface 105 of the wafer fragment, and the back surface 203 of the dummy wafer 201. In this embodiment, the material of the first metal layer 301 is preferably Ti, and the thickness of the first metal layer 301 is preferably 12-255 nm. Figure 5 As shown, a Ti thin film with a thickness of 12-255 nm is sputtered on the cracked section 103 of the wafer fragment 101, the spliced section 202 of the dummy wafer 201, the back side 105 of the wafer fragment, and the back side 203 of the dummy wafer 201 using a magnetron sputtering process.
[0056] Then, continue to refer to Figure 5 A second metal layer 302 is sputtered onto the first metal layer 301, forming a seed layer. In this embodiment, the material of the second metal layer 302 is preferably Cu, and the thickness of the second metal layer 302 is preferably 25–870 μm. After forming the first metal layer 301, a Cu thin film with a thickness of 25–870 μm is sputtered onto the Ti thin film using a PVD device. These two metal thin films serve as seed layers for electroplating.
[0057] Finally, the photoresist layer on the front side of wafer fragment 101 and dummy wafer 201 is removed.
[0058] Furthermore, in the above-mentioned steps of sputtering the first metal layer 301 and the second metal layer 302, when the back side 105 of the wafer fragment has a convex corner structure at the edge of the fracture region, it is preferable to use a secondary sputtering process to form the first metal layer 301 on the crack cross surface 103 of the wafer fragment 101 and the back side 105 of the wafer fragment 101, and to use a secondary sputtering process to form the second metal layer 302 on the first metal layer 301, so that the seed layer on the wafer fragment 101 reaches the target thickness.
[0059] And / or, when the back surface 203 of the dummy wafer has a convex corner structure at the edge of the splicing area, it is preferable to use a secondary splicing process to form a first metal layer 301 on the splicing section surface of the dummy wafer 201 and the back surface 203 of the dummy wafer 201, and to use a secondary splicing process to form a second metal layer 302 on the first metal layer 301, so that the seed layer on the dummy wafer 201 reaches the target thickness.
[0060] Specifically, such as Figure 4 and Figure 5As shown, in this embodiment, the dummy wafer 201 has a convex corner structure 205 formed between its splicing section 202 and the back surface (the angle between the splicing section 202 and the back surface in the direction perpendicular to the wafer surface is less than 90 degrees). This convex corner structure 205 is not conducive to sputtering a metal film of sufficient thickness on the splicing section 202 of the dummy wafer 201. Therefore, a second sputtering is required, that is, after sputtering a Ti film once, the dummy wafer 201 is sputtered a Ti film a second time. The thickness of the Ti film sputtered a second time is set to be the same as that of the first sputtering. The Ti film sputtered twice forms a first metal layer 301 that meets the thickness requirement. Then, on the first metal layer 301, a Cu film is sputtered once, and then a Cu film is sputtered a second time. The thickness of the Cu film sputtered a second time is set to be the same as that of the first sputtering. The Ti film sputtered twice forms a second metal layer 302 that meets the thickness requirement. Similarly, when a convex corner structure appears on the back side of wafer fragment 101, a second sputtering process is required, and the requirements for the second sputtering are the same as described above. After the second sputtering, the photoresist layer covering the back surface of wafer fragment 101 is removed by photoresist stripping.
[0061] S4: The cracked cross-section 103 of the wafer fragment 101 is aligned with the splicing cross-section 202 of the dummy wafer 201. An electroplating layer 303 is formed on the seed layer to support and connect the wafer fragment 101 and the dummy wafer 201, so that the wafer fragment 101 and the dummy wafer 201 are spliced together into a complete wafer.
[0062] This step specifically includes:
[0063] Place wafer fragment 101 and dummy wafer 201 in an electroplating fixture, so that the front side of wafer fragment 101 and the front side of dummy wafer 201 are on the same plane, and splice the cracked cross section 103 of wafer fragment 101 and the spliced cross section 202 of dummy wafer 201 together.
[0064] An electroplating layer 303 is formed on the seed layer of the cracked cross-section 103 of the wafer fragment 101 and the splicing cross-section 202 of the dummy wafer 201, the back surface 105 of the wafer fragment, and the back surface 203 of the dummy wafer 201 through an electroplating process. The electroplating layer 303 fills the gap between the cracked cross-section 103 of the wafer fragment 101 and the splicing cross-section 202 of the dummy wafer 201, and covers the back surface 105 of the wafer fragment and the back surface 203 of the dummy wafer 201.
[0065] In this embodiment, the material of the electroplated layer 303 is preferably Cu; the thickness of the electroplated layer 303 is preferably 23 to 2300 μm.
[0066] In this step, wafer fragment 101 and dummy wafer 201 are placed in an electroplating fixture and electroplated with a layer of Cu. The edge repair morphology of the electroplated wafer fragment 101 is as follows. Figure 6As shown, the electroplated layer 303 fills the gap between the cracked cross-section 103 of the wafer fragment 101 and the spliced cross-section 202 of the dummy wafer 201, and covers the back surface 105 of the wafer fragment and the back surface 203 of the dummy wafer 201. The electroplated layer 303 serves as a supporting connection structure, restoring the wafer to its intact state.
[0067] S5: After applying a film to the front side of the complete wafer, mechanically grind the back side of the complete wafer to reduce the wafer thickness.
[0068] Specifically, the complete wafer obtained through metal stitching in step S4 is then subjected to subsequent processes such as film lamination and mechanical grinding for thinning, in a conventional manner.
[0069] Compared to existing adhesive bonding methods, this invention utilizes metal bonding to repair wafer dicing, resulting in better flatness of the stitched wafer. Furthermore, during mechanical grinding, it avoids generating sticky impurities that could affect the uniformity of thinning, ultimately yielding a thinned wafer with a more uniform thickness distribution. Simultaneously, the metal bonding method of this invention uses the same metal type (Cu) as the original wafer dicing track, reducing differences between the cutting objects and thus achieving better cutting results.
[0070] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.
Claims
1. A method for mechanical grinding of an incomplete wafer, characterized in that: include: Providing a split wafer and a dummy wafer having the same size and thickness as the split wafer, wherein the front side of the split wafer is an effective circuit layer; Selecting wafer fragments from the split wafer, and cutting pseudo wafer companion wafers from the pseudo wafer based on the selected wafer fragments, which can be spliced with the wafer fragments to form a complete wafer; forming a seed layer on the crack section of the wafer fragment, the spliced section of the pseudo wafer companion, the back side of the wafer fragment and the back side of the pseudo wafer companion; The crack section of the wafer fragment is aligned with the splicing section of the pseudo wafer companion, and an electroplating layer supporting and connecting the wafer fragment and the pseudo wafer companion is formed on the seed layer through an electroplating process, so that the wafer fragment and the pseudo wafer companion are spliced into a complete wafer; After the front side of the complete wafer is filmed, the back side of the complete wafer is mechanically ground to reduce the thickness of the wafer.
2. The mechanical grinding method for an incomplete wafer according to claim 1, characterized in that: Selecting wafer fragments from the split wafer, and cutting a pseudo wafer companion wafer from the pseudo wafer based on the selected wafer fragments, which can be spliced with the wafer fragments to form a complete wafer, comprising: Selecting the wafer fragment with the largest area from the split wafer as a template; Placing the selected wafer fragment with its front side facing upward on the pseudo wafer, and aligning the arc edge of the wafer fragment with the edge of the pseudo wafer; The pseudo wafer is cut along the broken edge of the wafer fragment to cut out a pseudo wafer companion piece that can be spliced with the wafer fragment to form a whole wafer.
3. The mechanical grinding method of an incomplete wafer according to claim 1, characterized in that: Forming a seed layer on the crack section of the wafer fragment, the splicing section of the pseudo wafer companion, the back side of the wafer fragment and the back side of the pseudo wafer companion, comprising: forming a photoresist layer on the front sides of the wafer fragments and the pseudo wafer companion; Put the wafer fragments and the pseudo wafer companion piece into the PVD process chamber with the back side facing upward; Sputtering a first metal layer on the crack section of the wafer fragment, the spliced section of the pseudo wafer companion, the back side of the wafer fragment and the back side of the pseudo wafer companion, and sputtering a second metal layer on the first metal layer, the first metal layer and the second metal layer forming the seed layer; The wafer fragments and the photoresist layer on the front side of the pseudo wafer companion piece are removed.
4. The mechanical grinding method for an incomplete wafer according to claim 3, characterized in that: When the first metal layer and the second metal layer are sputtered to form a seed layer, the closest distance between the edge of the fractured region of the wafer fragment and the edge of the spliced region of the pseudo wafer companion piece on the projection plane is not less than 2 mm.
5. The mechanical grinding method for an incomplete wafer according to claim 3, characterized in that: When the back side of the wafer fragment has a convex corner structure at the edge of the fracture area, a secondary sputtering process is used to form a first metal layer on the crack section of the wafer fragment and the back side of the wafer fragment, and a secondary sputtering process is used to form a second metal layer on the first metal layer, so that the seed layer on the wafer fragment reaches the target thickness.
6. The mechanical grinding method for an incomplete wafer according to claim 3, characterized in that: When the back side of the pseudo wafer companion has a convex corner structure at the edge of the splicing area, a secondary sputtering process is used to form a first metal layer on the splicing section surface of the pseudo wafer companion and the back side of the pseudo wafer companion, and a secondary sputtering process is used to form a second metal layer on the first metal layer, so that the seed layer on the pseudo wafer companion reaches the target thickness.
7. The mechanical grinding method for an incomplete wafer according to any one of claims 3 to 6, characterized in that: The material of the first metal layer is Ti; the material of the second metal layer is Cu.
8. The mechanical grinding method for an incomplete wafer according to any one of claims 3 to 6, characterized in that: The thickness of the first metal layer is 12-255 nm; the thickness of the second metal layer is 25-870 μm.
9. The mechanical grinding method for an incomplete wafer according to claim 1, characterized in that: The crack section of the wafer fragment is aligned with the splicing section of the pseudo wafer companion, and an electroplating layer supporting and connecting the wafer fragment and the pseudo wafer companion is formed on the seed layer through an electroplating process, including: Placing the wafer fragments and the pseudo wafer companion piece on an electroplating jig so that the front surface of the wafer fragments and the front surface of the pseudo wafer companion piece are located in the same plane, and the crack section of the wafer fragment and the splicing section of the pseudo wafer companion piece are spliced together relatively; An electroplating layer is formed on the seed layer of the crack section of the wafer fragment, the splicing section of the pseudo wafer companion, the back side of the wafer fragment and the back side of the pseudo wafer companion through an electroplating process. The electroplating layer fills the gap between the crack section of the wafer fragment and the splicing section of the pseudo wafer companion, and covers the back side of the wafer fragment and the back side of the pseudo wafer companion.
10. The mechanical grinding method for an incomplete wafer according to claim 1 or 9, characterized in that: The material of the electroplating layer is Cu; the thickness of the electroplating layer is 23-2300 μm.