Method and system for filling gaps

Abstract

Methods and systems for filling gaps are disclosed. An exemplary method includes providing a substrate in a reaction chamber. The substrate includes at least one gap. The method further includes depositing a layer into the gap. The layer has a first volume. Finally, the method further includes converting the layer into a converted layer. The conversion layer has a second volume. The second volume is greater than the first volume. The methods and systems are useful, for example, in the field of integrated circuit fabrication.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor processing methods and systems, and to the field of integrated circuit fabrication. In particular, methods and systems suitable for filling gaps are disclosed. Background Art

[0002] The reduction in size of semiconductor devices (such as logic devices and memory devices) has led to significant increases in the speed and density of integrated circuits. However, conventional device scaling techniques face significant challenges at future technology nodes.

[0003] For example, one challenge is finding suitable methods to fill gaps, such as recesses, trenches, vias, etc., with materials without forming any gaps or voids.

[0004] Any discussion set forth in this section, including discussion of problems and solutions, has been included in the present disclosure merely to provide context for the present disclosure. Such discussion should not be construed as an admission that any or all information was known at the time the present invention was made, or constitutes prior art. Summary of the invention

[0005] This summary is provided to introduce some concepts in a simplified form. These concepts are further described in detail in the detailed description of the example embodiments disclosed below. This summary is not intended to identify the key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0006] Various embodiments of the present disclosure relate to methods of filling gaps, structures and devices formed using such methods, and apparatus for performing such methods and / or for forming such structures and / or devices. These layers can be used in various applications. For example, they can be used in the field of integrated circuit manufacturing.

[0007] Thus, a method for filling a gap is described herein. The method includes providing a substrate in a reaction chamber. The substrate includes at least one gap. The method also includes depositing a layer into the gap. The layer has a first volume. Finally, the method also includes converting the layer into a conversion layer in the gap. The conversion layer has a second volume. The second volume is greater than the first volume.

[0008] A system is further described herein. The system includes a reaction chamber. The system also includes a first precursor gas source. The first precursor gas source includes a first precursor. The system also includes a second precursor gas source. The second precursor gas source includes a second precursor. The system also includes a controller. The controller is configured to control the flow of gas into the reaction chamber to form a conversion layer in the gap of the substrate by the method described herein.

[0009] These and other embodiments will become apparent to those skilled in the art from the following detailed description of certain embodiments with reference to the accompanying figures.The present invention is not limited to any particular embodiment disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A more complete understanding of embodiments of the present disclosure may be obtained by referring to the detailed description and claims when considered in conjunction with the following illustrative drawings.

[0011] Figure 1 An embodiment of the method disclosed herein is shown.

[0012] Figure 2 An embodiment of the method disclosed herein is shown.

[0013] Figure 3 a) to c) in FIG. 1 illustrate the operation of an embodiment of the method described herein.

[0014] Figure 4 Another embodiment of the system described herein is shown in a stylized manner.

[0015] Figure 5 A stylized representation of a substrate including a gap is shown.

[0016] It should be understood that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the size of some elements in the drawings may be exaggerated relative to other elements to help improve the understanding of the illustrated embodiments of the present disclosure. DETAILED DESCRIPTION

[0017] Although certain embodiments and examples are disclosed below, it will be appreciated by those skilled in the art that the present invention extends beyond the specifically disclosed embodiments and / or uses of the present invention and their obvious modifications and equivalents. Therefore, it is intended that the scope of the disclosed invention should not be limited by the specifically disclosed embodiments described below.

[0018] In the present disclosure, "gas" may include materials that are gaseous at normal temperature and pressure (NTP), evaporated solids and / or evaporated liquids, and may be composed of a single gas or a gas mixture depending on the circumstances. Gases other than process gases, i.e., gases that are not introduced through gas distribution components, other gas distribution devices, etc., may be used, for example, to seal reaction spaces, and may include sealing gases, such as rare gases. In some cases, the term "precursor" may refer to a compound that participates in a chemical reaction that produces another compound, particularly a compound that constitutes a membrane matrix or a main skeleton of a membrane. The term "reactant" may be used interchangeably with the term precursor.

[0019] As used herein, the term "substrate" may refer to any one or more underlying materials that may be used to form or on which a device, circuit, or film may be formed. The substrate may include a bulk material, such as silicon (e.g., single crystal silicon), other Group IV materials, such as germanium, or other semiconductor materials, such as Group II-VI or Group III-V semiconductor materials, and may include one or more layers overlying or underlying the bulk material. In addition, the substrate may include various features, such as depressions, protrusions, etc., formed in or on at least a portion of the substrate layer. For example, the substrate may include at least one of a bulk semiconductor material and a layer of insulating or dielectric material overlying at least a portion of the bulk semiconductor material.

[0020] As used herein, the terms "film" and / or "layer" may refer to any continuous or discontinuous structure and material, such as a material deposited by the methods disclosed herein. For example, the film and / or layer may include a two-dimensional material, a three-dimensional material, nanoparticles, a partial or complete molecular layer or a partial or complete atomic layer or atom and / or molecular clusters. The film or layer may be composed in part or in whole of a plurality of dispersed atoms on a substrate surface and / or embedded in a substrate and / or embedded in a device manufactured on the substrate. The film or layer may include a material or layer having pinholes and / or islands. The film or layer may be at least partially continuous. The film or layer may be patterned, for example, subdivided, and may be included in a plurality of semiconductor devices.

[0021] As used herein, a "structure" may be or include a substrate as described herein. A structure may include one or more layers covering a substrate, such as one or more layers formed according to the methods described herein. A device portion may be or include a structure.

[0022] The term "deposition process" as used herein may refer to the introduction of precursors (and / or reactants) into a reaction chamber to deposit a layer on a substrate. A "cyclic deposition process" is an example of a "deposition process". The methods described herein may include depositing a layer by a cyclic deposition process. The term "cyclic deposition process" or "cyclic deposition process" may refer to the sequential introduction of precursors (and / or reactants) into a reaction chamber to deposit a layer on a substrate, and includes processing techniques such as atomic layer deposition (ALD), cyclic chemical vapor deposition (cyclic CVD), and a hybrid cyclic deposition process including an ALD component and a CVD component.

[0023] The methods described herein may include depositing a layer by an atomic layer deposition process. The term "atomic layer deposition" may refer to a vapor deposition process in which a deposition cycle (typically multiple consecutive deposition cycles) is performed in a process chamber. The term atomic layer deposition as used herein is also meant to include processes designated by related terms, such as chemical vapor atomic layer deposition, atomic layer epitaxy (ALE), molecular beam epitaxy (MBE), gas source MBE, organometallic MBE, and chemical beam epitaxy when performed with alternating pulses of precursor / reactive gas and purge gas (e.g., inert carrier gas).

[0024] Typically, for an ALD process, during each cycle, a precursor is introduced into a reaction chamber and is chemically adsorbed onto a deposition surface (e.g., a substrate surface that may include previously deposited material from a previous ALD cycle or other material), thereby forming a monolayer or sub-monolayer of material that does not readily react with additional precursors (i.e., a self-limiting reaction). Thereafter, a reactant (e.g., another precursor or a reactive gas) may subsequently be introduced into the process chamber for converting the chemically adsorbed precursor into a desired material on the deposition surface. The reactant is capable of further reacting with the precursor. During one or more cycles, such as during each step of each cycle, a purge step may be utilized to remove any excess precursor from the process chamber and / or to remove any excess reactant and / or reaction byproducts from the reaction chamber.

[0025] As used herein, the term "purge" may refer to the process of providing an inert or substantially inert gas to a reaction chamber between two gas pulses that react with each other. For example, a purge may be provided between a precursor pulse and a reactant pulse, such as using a rare gas, so as to avoid or at least minimize gas phase interactions between the precursor and the reactant. It should be understood that the purge may be performed in time or space, or both. For example, in the case of a time purge, the purge step may be used, for example, in a time sequence of providing a first precursor to the reaction chamber, providing a purge gas to the reaction chamber, and providing a second precursor to the reaction chamber, wherein the substrate on which the layer is deposited does not move. For example, in the case of a space purge, the purge step may take the form of moving the substrate from a first position where the first precursor is continuously supplied to a second position where the second precursor is continuously supplied through a purge gas curtain.

[0026] As used herein, "precursor" includes a gas or a material that can be turned into a gaseous state, which material can be represented by a chemical formula including elements that can be introduced during the deposition process described herein.

[0027] The term "reactant" may refer to a gas or material that can become a gaseous state and react with a precursor.

[0028] In addition, in the present disclosure, any two numbers of a variable may constitute a feasible range for the variable, and any range indicated may include or exclude endpoints. In addition, any variable value indicated may refer to an exact value or an approximate value, and include equivalents, and may refer to an average value, a median value, a representative value, a majority value, etc. In addition, in the present disclosure, the terms "including", "consisting of" and "having" independently refer to "generally or broadly including", "comprising", "essentially consisting of" or "consisting of" in some embodiments.

[0029] In this disclosure, any defined meaning does not necessarily exclude the ordinary and customary meaning in some embodiments.

[0030] A method for filling a gap is described herein. The method includes providing a substrate including a gap to a reaction chamber. A single crystal silicon wafer may be a suitable substrate. Other substrates may be suitable, such as a single crystal germanium wafer, a gallium arsenide wafer, quartz, sapphire, glass, steel, aluminum, a silicon-on-insulator substrate, plastic, etc.

[0031] The method also includes depositing a layer into the gap. The layer has a first volume. Finally, the method also includes converting the layer into a conversion layer. The conversion layer has a second volume. The second volume is greater than the first volume.

[0032] The presently disclosed method describes a dilation-based gap filling process that allows for gap filling without gaps or voids.

[0033] In some embodiments, the method further comprises performing a plasma trimming step prior to converting the layer into a conversion layer. In the plasma trimming step, a hydrogen plasma is formed into the reaction chamber which trims the upper edge of the layer to form a V-shape. This enables the conversion element to reach all the way to the bottom of the gap, thereby completely converting the layer into a conversion layer. The V-shape also prevents pinching off, which means that the gap will close at the top, leaving a void in the middle and bottom of the gap. The pinching off effect can also complicate the transfer of the conversion element to all parts of the layer in the gap. In some embodiments, the plasma trimming time is the same for each super cycle. In some embodiments, the plasma trimming time decreases in each super cycle.

[0034] In some embodiments, the method further comprises depositing a liner layer prior to depositing the liner layer into the gap. The liner acts as a protective liner to prevent damage to the underlying substrate. Another task of the liner is that since it has partially filled the gap, less layer needs to be deposited in the gap, thereby converting the layer into a conversion layer. Therefore, it may increase yield. In some embodiments, the liner comprises silicon oxide. In some embodiments, the liner is a conformal atomic layer deposition liner. In some embodiments, the liner is an inhibited atomic layer deposition liner. Inhibited ALD liners allow for a tapered deposition shape, which can reduce pinch-off effects.

[0035] In some embodiments, the converting step is performed by oxidation treatment. In some embodiments, the oxidation treatment comprises treatment selected from at least one of ozone, hydrogen peroxide, oxygen plasma, oxygen free radicals, vacuum ultraviolet oxygen, and steam.

[0036] In some embodiments, the converting step is performed by a nitridation process. In some embodiments, the nitridation process comprises a process selected from at least one of ammonia, ammonia plasma, hydrazine, hydrazine plasma, nitrogen / hydrogen plasma, nitrogen plasma, or nitrogen radicals.

[0037] In some embodiments, the liner layer includes at least one material selected from silicon oxide, silicon, silicon carbide, and silicon nitride.

[0038] In some embodiments, the layer includes silicon or silicon nitride.

[0039] In some embodiments, the conversion layer includes silicon oxide.

[0040] In some embodiments, the second precursor includes a silane group. In some embodiments, the silane group is selected from tetrasilane, neopentasilane, silane, disilane, trisilane, diiodosilane, cyclohexasilane, and cyclopentasilane.

[0041] In some embodiments, plasma trimming is performed using a plasma gas including hydrogen, argon, helium, or a mixture thereof.

[0042] In some embodiments, the liner includes silicon oxide.

[0043] Materials formed according to the present method may be advantageously used in the field of integrated circuit manufacturing.

[0044] Exemplary gaps include recesses, contact holes, vias, trenches, etc. In some embodiments, the width of the gap is at least 5 nm to at most 500 nm, or at least 10 nm to at most 250 nm, or at least 20 nm to at most 200 nm, or at least 50 nm to at most 150 nm, or at least 100 nm to at most 150 nm.

[0045] In some embodiments, the depth of the gap is at least 10 nm to at most 10000 nm, or at least 20 nm to at most 5000 nm, or at least 40 nm to at most 2500 nm, or at least 80 nm to at most 1000 nm, or at least 100 nm to at most 500 nm, or at least 150 nm to at most 400 nm, or at least 200 nm to at most 300 nm.

[0046] The layers described herein may be suitably deposited using a deposition technique that produces a conformal layer, such as atomic layer deposition (ALD) or another cyclic deposition process. Alternatively, the layers described herein may be deposited using a deposition technique that produces a non-conformal layer, i.e., a non-uniform layer, such as a layer having a higher thickness on the flat surface of the substrate than inside a gap or trench; or a layer having a higher thickness inside a gap or trench than on the flat surface of the substrate. Examples of techniques that can produce non-conformal layers are chemical vapor deposition and plasma enhanced chemical vapor deposition.

[0047] The deposited layers described herein may include performing a cyclic deposition process. The cyclic deposition process may include cyclic CVD, ALD, or a hybrid cyclic CVD / ALD process or a plasma enhanced ALD / CVD process. For example, in some embodiments, the growth rate of a particular ALD process may be lower than that of a CVD process. One method of increasing the growth rate may be to operate at a deposition temperature higher than the deposition temperature typically used in the ALD process, resulting in certain parts of the chemical vapor deposition process, i.e., at least one of the non-self-limiting surface and gas phase reactions, but still utilizing the sequential introduction of reactants. Such a process may be referred to as cyclic CVD. In some embodiments, the cyclic CVD process may include introducing two or more precursors or reactants into a reaction chamber, wherein there may be an overlap time between the two or more precursors or reactants in the reaction chamber, resulting in an ALD component of the deposition and a CVD component of the deposition. This is referred to as a hybrid process. According to a further example, the cyclic deposition process may include a continuous flow of a reactant or precursor and periodic pulses of a second reactant or precursor entering the reaction chamber.

[0048] In some embodiments, the liner layer and the layer are conformally deposited on the substrate. In other words, the liner layer and / or the layer may have a constant thickness on the substrate surface, including in gaps, recesses, etc., for example within an error range of 50%, 20%, 10%, 5%, 2%, 1%, 0.5%, or 0.1%.

[0049] In some embodiments, the lining layer and / or the layer is deposited by a deposition method that produces a higher growth rate at the distal surface of the gap than at the proximal surface of the gap. In some embodiments, the growth rate at the distal surface of the gap is at least 200% to at most 500% higher than the growth rate at the proximal surface, or at least 100% to at most 200%, or at least 50% to at most 100%, or at least 20% to at most 50%, or at least 10% to at most 20%, or at least 5% to at most 10%, or at least 2% to at most 5%, or at least 1% to at most 2%.

[0050] In some embodiments, when the substrate is exposed to the active species, the substrate is maintained at a temperature of at least -25°C to at most 400°C, or at least 0°C to at most 200°C, or at least 25°C to at most 150°C, or at least 50°C to at most 100°C.

[0051] In some embodiments, the liner layer is deposited at a substrate temperature of less than 800° C., or at least 50° C. to at most 500° C., or at least 100° C. to at most 300° C. In some embodiments, the liner layer is deposited at a temperature of at least -25° C. to at most 300° C., or at least 0° C. to at most 250° C., or at least 25° C. to at most 200° C., or at least 50° C. to at most 150° C., or at least 75° C. to at most 125° C.

[0052] In some embodiments, the layer is deposited at a substrate temperature of less than 800°C, or at least -25°C to at most 800°C, or at least 0°C to at most 700°C, or at least 25°C to at most 600°C, or at least 50°C to at most 400°C, or at least 75°C to at most 200°C, or at least 100°C to at most 150°C.

[0053] In some embodiments, the presently described methods are performed at a pressure of less than 760 Torr, or at least 0.2 Torr to at most 760 Torr, at least 1 Torr to at most 100 Torr, or at least 1 Torr to at most 10 Torr. In some embodiments, the layer is deposited at a pressure of at most 10.0 Torr, or at most 5.0 Torr, or at most 3.0 Torr, or at most 2.0 Torr, or at most 1.0 Torr, or at most 0.1 Torr, or at most 10 -2 Torr pressure, or up to 10 -3 Torr pressure, or up to 10 -4 Torr pressure, or up to 10 -5 Torr, or a pressure of at least 0.1 Torr to at most 10 Torr, or a pressure of at least 0.2 Torr to at most 5 Torr, or a pressure of at least 0.5 Torr to at most 2.0 Torr.

[0054] In some embodiments, the first precursor is pulsed into the reaction chamber for a duration of at least 0.1 seconds to at most 1000 seconds, or at least 0.2 seconds to at most 500 seconds, or at least 0.5 seconds to at most 200 seconds, or at least 1.0 seconds to at most 100 seconds, or at least 2 seconds to at most 50 seconds, or at least 5 seconds to at most 20 seconds.

[0055] In some embodiments, the methods described herein include multiple super cycles. For example, the methods described herein may include at least 2 to at most 5, or at least 5 to at most 10, or at least 10 to at most 20, or at least 20 to at most 50, or at least 50 to at most 100 super cycles. The super cycles include depositing a layer into the gap; performing an optional plasma trim; and converting the layer into a conversion layer.

[0056] The total number of supercycles included in the methods described herein depends, among other things, on the desired total layer thickness. In some embodiments, the method comprises at least 1 supercycle to at most 100 supercycles, or at least 2 supercycles to at most 80 supercycles, or at least 3 supercycles to at most 70 supercycles, or at least 4 supercycles to at most 60 supercycles, or at least 5 supercycles to at most 50 supercycles, or at least 10 supercycles to at most 40 supercycles, or at least 20 supercycles to at most 30 supercycles. In some embodiments, the method comprises at most 100 super cycles, or at most 90 super cycles, or at most 80 super cycles, or at most 70 super cycles, or at most 60 super cycles, or at most 50 super cycles, or at most 40 super cycles, or at most 30 super cycles, or at most 20 super cycles, or at most 10 super cycles, or at most 5 super cycles, or at most 4 super cycles, or at most 3 super cycles, or at most 2 super cycles, or a single super cycle.

[0057] A system is also described herein, the system comprising a reaction chamber, a first precursor gas source, a second precursor gas source, and a controller. The first precursor gas source comprises a first precursor, and the second precursor gas source comprises a second precursor. The controller is configured to control the flow of gas into the reaction chamber to form a layer on a substrate by the method described herein.

[0058] Optionally, the system further comprises one or more plasma gas sources. The plasma gas sources are arranged to provide plasma for plasma trimming.

[0059] According to another embodiment of the present disclosure, the method and / or structure described herein can be used to form a device or a portion thereof. The device may include a substrate, one or more insulating layers, one or more metal layers, and one or more semiconductor layers. The device also includes a gap filled according to the method disclosed herein.

[0060] Also described is a field effect transistor comprising a gate contact comprising a layer formed according to the methods described herein.

[0061] Also described is a metal contact comprising a layer deposited by the method described herein.

[0062] Also provided herein is a metal-insulator-metal (MIM) capacitor comprising a metal electrode comprising a layer formed by the method described herein.

[0063] The illustrations presented herein are not meant to be actual views of any particular material, structure, or device, but are merely idealized representations used to describe embodiments of the present disclosure.

[0064] The specific embodiments shown and described are illustrations of the present invention and are not intended to limit the scope of these aspects and embodiments in any way. In fact, for the sake of brevity, the traditional manufacturing, connection, preparation and other functional aspects of the system may not be described in detail. In addition, the connecting lines shown in the various figures are intended to represent exemplary functional relationships and / or physical connections between the various elements. Many alternative or additional functional relationships or physical connections may exist in actual systems, and / or may not exist in some embodiments.

[0065] It should be understood that the configuration and / or method described herein are exemplary in nature, and these specific embodiments or examples should not be considered restrictive, because many variations are possible. The specific routine or method described herein can represent one or more of any number of processing strategies. Therefore, the various actions shown can be performed in the order shown, in other orders, or omitted in some cases.

[0066] The subject matter of the present disclosure includes all novel and nonobvious combinations and subcombinations of the various processes, systems and configurations, and other features, functions, acts and / or properties disclosed herein, and any and all equivalents thereof.

[0067] Figure 1 A schematic diagram of an embodiment of the method described herein is shown. The method can be used to fill a gap, for example, to form an electrode, an insulator, or a dielectric layer in a semiconductor device. However, unless otherwise stated, the method described herein is not limited to these applications. The method includes a step 111 of positioning a substrate on a substrate support. The substrate support is located in a reaction chamber. Suitable substrate supports include bases, pedestals, etc. Optionally, the method also includes providing a first precursor in a gas phase into the reaction chamber to deposit a liner layer into the gap 112. Optionally, the reaction chamber is then purged. Purging can be accomplished by exposing the substrate to a purge gas, which can be accomplished by, for example, providing a purge gas to the reaction chamber. Exemplary purge gases include rare gases. Exemplary rare gases include He, Ne, Ar, Xe, and Kr. Alternatively, purging can include conveying the substrate through a purge gas curtain. During purging, excess chemicals and reaction byproducts (if any) can be removed from the substrate surface or the reaction chamber before the substrate proceeds to the next step, for example, by purging the reaction space or by moving the substrate.

[0068] In some embodiments, the first precursor comprises a silicon precursor. In some embodiments, the liner layer comprises at least one material selected from silicon oxide, silicon, silicon carbide, and silicon nitride.

[0069] The method then includes providing a second precursor in a gas phase into the reaction chamber to deposit a layer into the gap 113. Optionally, the reaction chamber is then purged. In some embodiments, the layer includes silicon or silicon nitride or silicon carbide. The layer has a first volume. The volume of the layer is defined by: the thickness of the layer deposited in the gap; the length of the layer deposited in the gap, in other words, the depth of the gap; and the width of the layer deposited in the gap, in other words, the width of the gap. In some embodiments, the second precursor includes a silane group. In some embodiments, the silane group is selected from trisilane, diiodosilane, cyclohexasilane, tetrasilane, neopentasilane, silane, disilane and cyclopentasilane.

[0070] Next, the layer is converted into a conversion layer 114. The conversion layer has a second volume. The second volume is greater than the first volume. In other words, during the conversion step, the first volume of the layer expands to the second volume. In some embodiments, the conversion step is performed by an oxidation process. Any suitable oxidation process can be used. In some embodiments, the oxidation process includes a process selected from at least one of ozone, hydrogen peroxide, oxygen plasma, oxygen free radicals, ozone, water, vacuum ultraviolet ozone, vacuum ultraviolet oxygen, or steam. In some embodiments, the conversion step is performed by a nitridation process. Any suitable nitridation process can be used. In some embodiments, the nitridation process includes a process selected from at least one of ammonia, ammonia plasma, hydrazine, hydrazine plasma, nitrogen / hydrogen plasma, nitrogen plasma, or nitrogen free radicals.

[0071] In some embodiments, the conversion layer comprises silicon oxide. In some embodiments, the conversion layer comprises silicon nitride. In some embodiments, the layer is silicon and the conversion layer is silicon oxide. In some embodiments, the layer is silicon nitride and the conversion layer is silicon oxide. In some embodiments, the layer is silicon carbide and the conversion layer is silicon oxide. In yet other embodiments, the layer is silicon and the conversion layer is silicon nitride.

[0072] Thus, the gap is filled, preferably without gaps. Optionally, the step 113 of providing the second precursor and the step 114 of the conversion layer are repeated 115 one or more times. When the gap has been filled sufficiently without gaps, the method ends 116.

[0073] Figure 2 A further embodiment of the method described here is schematically shown. Figure 2 The method is similar to Figure 1 The method as it also comprises positioning a substrate on a substrate support 211 , providing a first precursor 212 , providing a second precursor 213 and converting the layer 217 .

[0074] Figure 2 Methods and Figure 1 The method of is different in that it also includes a step of plasma trimming 214. Plasma trimming is a step of trimming the edge of the gap with the help of plasma. The edge forms a V shape. The purpose of plasma trimming is to prevent pinching off by removing some of the deposited film from the upper end of the gap. In other words, plasma trimming avoids closing of the upper end of the gap and leaving a void within the gap. In some embodiments, trimming is performed with hydrogen plasma. In other words, hydrogen is supplied into the reaction chamber and the substrate is exposed to direct plasma. In some embodiments, the plasma trimming time is the same for each super cycle. In some embodiments, the plasma trimming time is reduced in each super cycle. In some embodiments, plasma trimming is performed at a lower temperature than the deposition step 213. In some embodiments, plasma trimming is performed at a temperature of about 100°C.

[0075] In some embodiments, the plasma trimming step 214 is performed in a different reaction chamber than the step 213 of providing the second precursor. Figure 2 The method comprises a plurality of super cycles 216, wherein the steps of providing a second precursor 213, plasma trimming 214 and conversion layer 217 are repeated one or more times. After a predetermined amount of conversion material has been formed on the substrate, Figure 2 The method ends at 217.

[0076] Figure 3 The operation of the method described herein is shown. In particular, Figure 3 A substrate 310 including at least one gap 320 is shown. Figure 3 FIG. 3 a ) shows a liner layer 320 conformally deposited on a substrate 310 . Figure 3 b) in FIG. 3 shows the same substrate 310 , with a layer 350 deposited on the substrate. The layer has a first volume. In the gap 320 , a gap 360 is visible. Figure 3 c) in FIG. 3 shows a layer that is converted into a conversion layer 330. The conversion layer has a second volume that is greater than the first volume, which means that the layer expands to fill the gaps 360 in the gap 320.

[0077] Figure 4 A deposition assembly 400 according to the present disclosure is shown in schematic form. The deposition assembly 400 can be used to perform the methods described herein and / or form the structures or devices described herein or portions thereof.

[0078] In the illustrated example, the deposition assembly 400 includes one or more reaction chambers 402, a precursor injector system 401, a first precursor container 404, a second precursor container 406, an exhaust source 410, and a controller 412. The deposition assembly 400 may include one or more additional gas sources (not shown), such as an inert gas source, a carrier gas source, and / or a purge gas source.

[0079] Reaction chamber 402 may include any suitable reaction chamber, such as an ALD or CVD reaction chamber as described herein.

[0080] The first precursor container 404 may include a container and one or more precursors described herein, either alone or mixed with one or more carrier gases (e.g., inert gases). The second precursor container 406 may include a container and a second precursor described herein, either alone or mixed with one or more carrier gases. Although two source containers 404, 406 are shown, the deposition assembly 400 may include any suitable number of source containers. The source containers 404, 406 may be coupled to the reaction chamber 402 via lines 414, 416, which may each include a flow controller, a valve, a heater, etc. In some embodiments, the first precursor in the first precursor container 404 and the second precursor in the second precursor container 406 may be heated. In some embodiments, the containers are heated so that the precursors or reactants reach a temperature, for example, between about 30°C and about 200°C, depending on the nature of the chemical substance in question.

[0081] Exhaust source 410 may include one or more vacuum pumps.

[0082] Controller 412 includes electronic circuits and software to selectively operate valves, manifolds, heaters, pumps, and other components included in deposition assembly 400. Such circuits and components are used to introduce precursors, reactants, and purge gases from corresponding sources. Controller 412 can control the timing of gas pulse sequences, the temperature of substrates and / or reaction chamber 402, the pressure in reaction chamber 402, and various other operations to provide proper operation of deposition assembly 400. Controller 412 can include control software to control the flow of precursors, reactants, and purge gases into and out of reaction chamber 402 by electrically or pneumatically controlling valves. Controller 412 can include modules that perform specific tasks, such as software or hardware components. Modules can be configured to reside on an addressable storage medium of a control system and configured to perform one or more processes.

[0083] Other configurations of the deposition assembly 400 are also possible, including different numbers and types of precursor and reactant sources. In addition, it should be understood that many arrangements of valves, conduits, precursor sources, and auxiliary reactant sources can be used to achieve the goal of selectively and in a coordinated manner supplying gases to the reaction chamber 402. In addition, as a schematic representation of the deposition assembly, many components have been omitted for simplicity of illustration, and these components may include, for example, various valves, manifolds, purifiers, heaters, containers, vents, and / or bypasses.

[0084] During operation of the deposition assembly 400, a substrate, such as a semiconductor wafer (not shown), is transferred from, for example, a substrate handling system to the reaction chamber 402. Once the substrate is transferred to the reaction chamber 402, one or more gases, such as precursors, reactants, carrier gases, and / or purge gases, are introduced into the reaction chamber 402 from a gas source.

[0085] Figure 5 A schematic diagram of a substrate 500 including a gap 510 is shown. The gap 510 includes a sidewall 511 and a distal end 512. The substrate also includes a proximal surface 520. In some embodiments, the sidewall 511 and the distal end 512 include the same material. In some embodiments, at least one of the sidewall 511 and the distal end includes a dielectric, such as a silicon-containing dielectric, such as silicon oxide, silicon nitride, silicon carbide, and mixtures thereof. In some embodiments, at least one of the sidewall 511 and the distal end 512 includes a metal, such as a transition metal, a post-transition metal, and a rare earth metal. In some embodiments, the metal includes Cu, Co, W, Ru, Mo, Al, or alloys thereof.

[0086] In some embodiments, the sidewall 511 and the distal end 512 have the same or substantially the same composition. In some embodiments, the sidewall 511 and the distal end 512 have different compositions. In some embodiments, the sidewall and the distal end 512 comprise a dielectric. In some embodiments, the sidewall 511 and the distal end 512 comprise a metal. In some embodiments, the sidewall 511 comprises a metal and the distal end 512 comprises a dielectric. In some embodiments, the sidewall 511 comprises a dielectric and the distal end comprises a metal.

[0087] In some embodiments, the proximal surface 520 has the same composition as the sidewall 511. In some embodiments, the proximal surface 520 has a different composition than the sidewall 511. In some embodiments, the proximal surface 520 has a different composition than the distal end 512. In some embodiments, the proximal surface 520 has the same composition as the distal end 512.

[0088] In some embodiments, the proximal surface 520, the sidewall 511, and the distal end 512 comprise the same material. In some embodiments, the proximal surface 520, the sidewall 511, and the distal end 512 comprise a dielectric. In some embodiments, the proximal surface 520, the sidewall 511, and the distal end 512 comprise a metal. In some embodiments, the proximal surface 520, the sidewall 511, and the distal end 512 comprise a semiconductor.

Claims

1. A method for filling a gap, comprising: providing a substrate in a reaction chamber, wherein the substrate comprises at least one gap; depositing a layer into the gap, wherein the layer has a first volume; as well as converting the layer into a conversion layer in the gap, wherein the conversion layer has a second volume, The second volume is greater than the first volume. 2 . The method of claim 1 , further comprising plasma trimming before converting the layer into a conversion layer. 3 . The method of claim 1 , further comprising depositing a liner layer prior to depositing the layer into the gap.

4. The method according to claim 1, wherein: The conversion step is performed by an oxidation treatment or a nitridation treatment.

5. The method according to claim 4, wherein: The oxidation treatment includes at least one treatment selected from ozone, hydrogen peroxide, oxygen plasma, oxygen free radicals, vacuum ultraviolet oxygen or steam.

6. The method according to claim 4, wherein: The nitridation treatment includes at least one treatment selected from ammonia, ammonia plasma, hydrazine, hydrazine plasma, nitrogen / hydrogen plasma, nitrogen plasma or nitrogen radicals.

7. The method according to claim 3, wherein: The liner layer includes at least one material selected from silicon oxide, silicon, silicon carbide, and silicon nitride.

8. The method according to claim 1, wherein: The layer comprises silicon, silicon carbide or silicon nitride.

9. The method according to claim 1, wherein: The conversion layer includes silicon oxide or silicon nitride.

10. The method according to claim 1, wherein: The layer is deposited using a first precursor.

11. The method according to claim 10, wherein: The first precursor includes silane groups.

12. The method according to claim 11, wherein: The silane is selected from tetrasilane, neopentasilane, silane, disilane, trisilane, diiodosilane, cyclohexasilane and cyclopentasilane.

13. The method according to claim 2, wherein: The plasma trimming is performed using a plasma gas including hydrogen, argon, helium, or a mixture thereof.

14. A system comprising: Reaction chamber; a first precursor gas source comprising a first precursor; a second precursor gas source comprising a second precursor; as well as A controller, wherein the controller is configured to control the flow of gas into the reaction chamber to form a conversion layer in the gap on the substrate by the method according to claim 1.

Images