Monitor structure for measuring impedance of device
By manufacturing the monitor structure in the scribe channel of the semiconductor wafer and using impedance measurement at different bias voltages, the problem of insufficient accuracy of the device impedance measurement in the prior art is solved, more accurate impedance measurement is achieved, and the quality of the semiconductor manufacturing process is improved.
Patent Information
- Application Number
- CN202411399615.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-16
- Filing Date
- 2024-10-09
- Publication Date
- 2025-04-18
AI Technical Summary
The existing semiconductor device impedance measurement technology has the problem of insufficient accuracy, especially during the preparation of the die, it is difficult to accurately measure the impedance of the transistor.
A system and method are designed to calculate device impedance by manufacturing first and second monitor structures in scribe channels of semiconductor wafers using these structures to measure impedance at different bias voltages. The monitor structure includes a source region, a drain region and a gate region. By measuring the impedance between these regions, the impedance of the transistor on the die can be more accurately reflected.
Through this method, the device impedance of the semiconductor wafer can be measured more accurately, reducing measurement errors and improving measurement accuracy, thereby helping to improve the quality of the semiconductor manufacturing process.
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Figure CN119852286A_ABST
Abstract
Description
Technical Field
[0001] This description relates to systems and methods for impedance measurement, and more particularly to monitor structures for measuring device impedance. Background Art
[0002] Die preparation is part of the semiconductor device manufacturing process, where the wafer is prepared for integrated circuit (IC) packaging and testing. The process of die preparation generally includes wafer dicing. Prior to wafer dicing, the wafer is mounted on a strip (e.g., dicing tape). The wafer dicing process is used to separate the individual dies from the semiconductor wafer while being mounted to the dicing tape. The dicing process may involve scribing and breaking, mechanical dicing, or laser cutting. Once the wafer has been diced, the die will remain on the dicing tape until the die is extracted by a die handling device such as a die bonder or die sorter later in the packaging process. Summary of the invention
[0003] In the described example, the semiconductor wafer may include a first monitor structure located adjacent to the die in a scribe street, the first monitor structure including a first source region, a first drain region, and a first gate region. From a top plan view, the first gate region may include a first elongated finger extending longitudinally between the first source region and the first drain region. The semiconductor wafer may include a second monitor structure located adjacent to the die in a scribe street, the second monitor structure including one or more second source regions, one or more second drain regions, and a plurality of second gate regions. From a top plan view, each of the second gate regions may include a second elongated finger extending longitudinally between the one or more second source regions and the one or more second drain regions over a corresponding region of the die.
[0004] In the described example, the system may include a sensor and a processor. The sensor may be configured to measure a first impedance between a first terminal and a second terminal of a test device, wherein in response to applying a first bias voltage across a third terminal and a second terminal of a first monitor structure, the first impedance represents the impedance of a first monitor structure in a scribe line of a semiconductor wafer. The sensor may be configured to measure a second impedance between a first terminal and a second terminal of a test device, wherein in response to applying a first bias voltage across a third terminal and a second terminal of a second monitor structure, the second impedance represents the impedance of a second monitor structure in a scribe line of a semiconductor wafer. The sensor may be configured to measure a third impedance between a first terminal and a second terminal of a test device, wherein in response to applying a second bias voltage across a third terminal and a second terminal of a first monitor structure, the third impedance represents the impedance of a first monitor structure. The sensor may be configured to measure a fourth impedance between a first terminal and a second terminal of a test device, wherein in response to applying a second bias voltage across a third terminal and a second terminal of a second monitor structure, the fourth impedance represents the impedance of a second monitor structure. The processor may be configured to calculate a device impedance based on the first impedance, the second impedance, the third impedance, and the fourth impedance. The device impedance represents the impedance of a transistor on a bare die adjacent to a scribe line of a semiconductor wafer.
[0005] In the described example, the method may include: measuring a first impedance between a first terminal and a second terminal of a first monitor structure in a scribe line of a semiconductor wafer in response to applying a first bias voltage across a third terminal and a second terminal of the first monitor structure; measuring a second impedance between a first terminal and a second terminal of a second monitor structure in a scribe line of the semiconductor wafer in response to applying a first bias voltage across the third terminal and the second terminal of the second monitor structure; measuring a third impedance between the first terminal and the second terminal of the first monitor structure in response to applying a second bias voltage across the third terminal and the second terminal of the first monitor structure; measuring a fourth impedance between the first terminal and the second terminal of the second monitor structure in response to applying a second bias voltage across the third terminal and the second terminal of the second monitor structure; and calculating a device impedance based on the first impedance, the second impedance, the third impedance, and the fourth impedance. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figure 1 is a diagram of an example semiconductor wafer.
[0007] Figure 2 is a block diagram of an example of a test system for testing semiconductor wafers.
[0008] Figure 3 A top plan view of an example laterally diffused metal oxide semiconductor (LDMOS) transistor is shown.
[0009] Figure 4To show Figure 3 A cross-sectional view of an example LDMOS transistor.
[0010] Figure 5 A block diagram of another example of a test system for devices on a semiconductor wafer.
[0011] Figure 6 is a flow chart illustrating an example method for calculating device impedance.
[0012] Figure 7 Graph showing device impedance for different types of monitor structures. DETAILED DESCRIPTION
[0013] This description is directed to systems, methods, and devices designed to provide more accurate measurements of device impedance using monitor structures.
[0014] For example, a more accurate impedance measurement of the device impedance of the die can be provided by fabricating the first monitor structure and the second monitor structure adjacent to the die in the scribe lane. The first monitor structure and the second monitor structure can be transistor structures, such as metal oxide semiconductor field effect transistors (MOSFETs) (e.g., laterally diffused MOS (LDMOS) transistors). For example, the first monitor structure and the second monitor structure are configured to have the same on-resistance between their respective source and drain regions as corresponding transistors on the die. The test system can be configured to measure the impedance of the first monitor structure (e.g., R DS and measuring the R of the first monitor structure at a second bias voltage. DS The test system can also be configured to measure the R of the second monitor structure at the first bias voltage. DS , and measure the R of the second monitor structure at a second bias voltage DS Based on the foregoing measurements, metal and / or contact routing related parasitic resistances may be determined and extracted from the measurements to provide a more accurate impedance measurement for the device impedance.
[0015] Figure 1 FIG. 1 is a diagram of an example semiconductor wafer 100. Figure 1 As seen in FIG. 1 , semiconductor wafer 100 may include a plurality of dies 104 separated from one another by scribe lanes 110 extending across semiconductor wafer 100. Generally, a wafer dicing process is used to separate individual dies 104 from semiconductor wafer 100. The dicing process may involve breaking, mechanical dicing, or laser cutting along scribe lanes 110. Monitor structures may be fabricated within scribe lanes 110, as described herein (see, e.g., Figure 2 These monitor structures can be utilized during the test phase (e.g., wafer test) to determine a more accurate R by extracting metal and / or contact routing related parasitic resistances from the device impedance.DS (e.g., impedance measurement).
[0016] Figure 2 For semiconductor wafers (such as Figure 1 A block diagram of an example of a test system 250 for measuring device impedance of a device on a semiconductor wafer 100). Figure 2 In an example of , the test system includes a test fixture (e.g., one or more probes) coupled to corresponding terminals (e.g., pads) on the surface of a given scribe line 110. As discussed herein, the scribe lines 110 on the semiconductor wafer 100 can be manufactured to include different monitor structures, such as the first monitor structure 220, the second monitor structure 230, the third monitor structure 240, etc. Figure 2 As shown in the example of , different monitor structures (e.g., a first monitor structure 220, a second monitor structure 230, a third monitor structure 240, etc.) can be formed adjacent to a given die in a scribe lane 110. These monitor structures 220, 230, 240 can be instances of respective transistors of adjacent dies, and thereby enable more accurate impedance measurements of the device impedance of the die. Each monitor structure 220, 230, 240 includes a terminal coupled to a respective pad formed of a conductive material (e.g., a metal such as copper, aluminum, or gold) in the scribe lane 110 and configured to be contacted by a respective probe tip of the test system 250. For example, pads 222, 224, and 226 are coupled to terminals of the monitor structure 220. Pads 232, 234, and 236 are coupled to terminals of the monitor structure 230, and pads 242, 244, and 246 are coupled to respective terminals of the monitor structure 240.
[0017] As another example, Figure 3 Shown are top plan views of example monitor structures 220 and 230 that may be fabricated in a scribe street 110 of a semiconductor wafer 100 at a location adjacent to a given die 104 , as described herein. Figure 4 Show Figure 3 A cross-sectional view of example monitor structures 220 and 230 is shown. Figure 3 and 4 In the example of FIG. 1 , monitor structures 220 and 230 implement LDMOS transistors. Figures 3 to 4 As shown, the first monitor structure 220 may thus include a first source region 304, a first drain region 306, and a first gate region 302 formed over a substrate 402. The second monitor structure 230 may include one or more second source regions 314, one or more second drain regions 316, and a plurality of second gate regions 312 formed over a substrate 412 (in some example scenarios, substrates 402 and 412 may be the same substrate).
[0018] exist Figure 3 and 4 In the example of , the monitor structure 220 is implemented as a single finger configuration LDMOS, where the first gate region 302 may include a first elongated finger extending longitudinally between the first source region 304 and the first drain region 306 as viewed from a top plan view (e.g., a single finger configuration). The monitor structure 230 is implemented as a multi-finger configuration LDMOS, where each of the second gate regions 312 may include a respective second elongated finger (e.g., a multi-finger configuration). Figure 3 , each second elongated finger 312 extends longitudinally over a corresponding doped region of the substrate between a corresponding source region 314 and a drain region 316. The multi-finger configuration of the second monitor structure 230 may be more representative of an actual MOSFET on a die because a MOSFET on a die may have a similar multi-finger configuration. For example, the fingers of the single-finger and multi-finger gate regions 302 and 312 may be formed to include polysilicon.
[0019] As described herein, each of the monitor structures 220 and 230 may be formed in the scribe lane 110 as another example of a corresponding transistor formed on the die 104, which may also be an LDMOS transistor. Thus, the first monitor structure 220 or the second monitor structure 230 may be configured to have the same on-resistance between the corresponding source and drain regions as the corresponding transistor on the die.
[0020] Return to Figure 2 , it should be appreciated that any number of monitor structures may be included in scribe lane 110 adjacent to one or more dies, and each of the monitor structures may have the same or different configuration (e.g., single finger, multiple fingers) relative to other monitor structures in scribe lane 110. As described herein, first monitor structure 220 has a single finger configuration, and second monitor structure 230 has a multiple finger configuration. Third monitor structure 240 (when implemented) may have a single finger configuration, a multiple finger configuration, or another configuration depending on the transistors on the die that provide the corresponding monitor structure. In one example, third monitor structure 240 may include one or more third source regions, one or more third drain regions, and a plurality of third gate regions similar to second monitor structure 230. Thus, from a top plan view, each of the third gate regions may include a third elongated finger extending longitudinally between the one or more third source regions and the one or more third drain regions over a respective region of the die.
[0021] According to one example, the device impedance for the devices of the semiconductor wafer 100 may be calculated according to the following formula:
[0022]
[0023] The above formula is based on LDMOS Si R DS Depends on V GS bias (e.g., gate-to-source bias voltage), while metal and / or contact routing related parasitic resistance is independent of V GS bias. Therefore, by applying more than one V GS The total R is measured under bias voltage DS , array R DS and R DS (metal parasitics) can be extracted and calculated separately. The test system can therefore be configured to more accurately calculate R DS - On value.
[0024] Figure 5 FIG. 5 is a block diagram of another example of a test system 500 for measuring device impedance of a corresponding device of a semiconductor wafer. The test system may be used to implement Figure 2 Therefore, Figure 5 The description can also refer to Figure 2 The test system 500 may include one or more sensors 510, a processor 520, and a probe card 530. For example, the probe card 530 may be an interface between the test system 500 and a test head. The probe card 530 may include a plurality of probe tips configured to electrically contact pads (e.g., pads 222, 224, 226, 232, 234, 236, 242, 244, 246) of the monitor structures 220, 230, 240. One or more of the probe tips may be configured to apply a bias voltage across two terminals (e.g., across gate and source terminals) of the respective monitor structures 220, 230, 240. The sensor 510 may be configured to measure an impedance across a pair of terminals (e.g., drain and source terminals) of each monitor structure 220, 230, 240 in response to the applied bias voltage. The probe tip of the probe card 530 may be coupled to the sensor 510, which may be configured to measure a plurality of impedance values at different bias voltages. The processor 520 may be configured to calculate R according to equation (1) based on the impedance measurement. DS (Metallic parasitism).
[0025] For example, the sensor 510 is configured to measure a first impedance between a first terminal and a second terminal (e.g., drain and source terminals) of the first monitor structure 220 in response to applying a first bias voltage across a third terminal and a second terminal (e.g., gate and source terminals) of the first monitor structure 220. The sensor 510 may be configured to measure a second impedance between a first terminal and a second terminal (e.g., drain and source terminals) of the second monitor structure 230 in response to applying a first bias voltage across a third terminal and a second terminal (e.g., gate and source terminals) of the second monitor structure 230. Additionally, the sensor 510 may be configured to measure a third impedance between the first terminal and the second terminal (e.g., drain and source terminals) of the first monitor structure 220 in response to applying a second bias voltage across the third terminal and the second terminal (e.g., gate and source terminals) of the first monitor structure 220. The sensor 510 may be further configured to measure a fourth impedance between the first terminal and the second terminal (e.g., the drain and source terminals) of the second monitor structure 230 in response to applying a second bias voltage across the third terminal and the second terminal (e.g., the gate and source terminals) of the second monitor structure 230. As described herein, the first bias voltage may be different from the second bias voltage. For example, the processor 520 may be configured to calculate a device impedance (e.g., R) of one or both of the monitor structures 220 and 230 based on the first impedance measurement, the second impedance measurement, the third impedance measurement, and the fourth impedance measurement, such as using equations (1) and (2). DS -on-resistance). In addition, the device impedance value may represent the impedance of one or more corresponding transistors on the die 104 of the semiconductor wafer 100 adjacent to the scribe street 110.
[0026] The first impedance, the second impedance, the third impedance, and the fourth impedance may be measured from the first monitor structure 220, the second monitor structure 230, and the third monitor structure 240 in the scribe line 110. The processor 520 may be configured to calculate the parasitic impedance (e.g., R ) of the first monitor structure 220, the second monitor structure 230, and the third monitor structure 240 based on the first impedance, the second impedance, the third impedance, and the fourth impedance. DS (metal parasitics)). Processor 520 may be configured to determine the device impedance (eg, R) based on the parasitic impedances determined for first monitor structure 220, second monitor structure 230, and third monitor structure 240 (eg, using Equation 2). DS阵列 ).
[0027] Additionally, processor 520 may be configured to assign scores to die 104 based on device impedance. For example, a die having a device impedance below a first threshold may be assigned a first score, and a die having a device impedance below a second threshold may be assigned a second score. DSThe value may be scored higher. Therefore, devices or dies with device impedances (associated with higher or more favorable performance) may be assigned different scores than dies with device impedances (associated with less favorable performance). The processor 520 may be configured to separate the dies 104 from the semiconductor wafer 100 based on the device impedances. For example, after the dies 104 are sliced, the dies 104 associated with device impedances below a first threshold may be separated from the dies associated with device impedances below a second threshold. The processor 520 may be configured to bin the dies 104 based on the assigned scores. In this way, the processor 520 may bin high-performance dies from low-performance dies.
[0028] Figure 6 6 is a flow chart illustrating an example method 600 for calculating device impedance. Figure 2 and / or 5) the method may be used to determine impedance. Thus, Figure 6 The description also refers to Figures 1 to 5 In the described example, method 600 may include measuring 602 a first impedance between a first terminal and a second terminal of a first monitor structure in a scribe lane of a semiconductor wafer in response to applying a first bias voltage across a third terminal and a second terminal of the first monitor structure. For example, the measurement at 602 may be implemented by sensor 510 of probe card 530. Method 600 may include measuring 604 a second impedance between a first terminal and a second terminal of a second monitor structure in a scribe lane of a semiconductor wafer in response to applying a first bias voltage across a third terminal and a second terminal of the second monitor structure. For example, the measurement at 604 may be implemented by sensor 510 of probe card 530. Method 600 may include measuring 606 a third impedance between a first terminal and a second terminal of the first monitor structure in response to applying a second bias voltage across a third terminal and a second terminal of the first monitor structure. For example, the measurement at 606 may be implemented by sensor 510 of probe card 530. The method 600 may include measuring 608 a fourth impedance between the first terminal and the second terminal of the second monitor structure in response to applying a second bias voltage across the third terminal and the second terminal of the second monitor structure. For example, the measurement at 608 may be implemented by the sensor 510 of the probe card 530. The method 600 may include calculating 610 a device impedance based on the first impedance, the second impedance, the third impedance, and the fourth impedance. For example, the calculation at 610 may be implemented by the processor 520.
[0029] Figure 7700 is a graphical representation of device impedance (e.g., y-axis) for different types of monitor structures in sample devices of an example batch (e.g., x-axis). For example, four groups of devices of different voltage ratings are shown, where each group is tested under a first test scenario 702, 704, 706, 708, where only a single finger type monitor structure is utilized to calculate device impedance, and a second test scenario where both single finger and multi-finger type monitor structures are utilized to calculate device impedance. Figure 7 As seen, the second test scenarios 712, 714, 716, 718 for four groups of devices with different voltage ratings (where both single and multi-finger type monitor structures are utilized in the impedance calculations) produce lower device impedances once the metal and / or contact routing related parasitic resistances are extracted from the overall device impedance, compared to the first test scenarios 702, 704, 706, 708 where only a single finger type monitor structure is utilized, thereby providing a more accurate impedance measurement for the device impedance of the die. In other words, the device impedance of the first rated voltage device is artificially higher when measured using the first test scenario 702 than when measured using the second test scenario 712, the device impedance of the second rated voltage device is artificially higher when measured using the first test scenario 704 than when measured using the second test scenario 714, the device impedance of the third rated voltage device is artificially higher when measured using the first test scenario 706 than when measured using the second test scenario 716, and the device impedance of the fourth rated voltage device is artificially higher when measured using the first test scenario 708 than when measured using the second test scenario 718.
[0030] In this description, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.
[0031] In this specification, a device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigured) by a user after manufacturing to perform the function and / or other additional or alternative functions. Configuration may be performed by firmware and / or software programming of the device, by the construction and / or layout of hardware components and interconnections of the device, or a combination thereof. In addition, a circuit or device described herein as including specific components may actually be configured to be coupled to those components to form the described circuit system or device. For example, a structure described herein as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors and / or inductors), and / or one or more sources (such as voltage sources and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package) and may be configured to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacturing or after manufacturing, for example, by an end user and / or a third party.
[0032] The phrase “based on” means “based, at least in part, on.” Thus, if X is based on Y, then X may be a function of Y and any number of other factors.
[0033] Modifications may be made in the described embodiments, and other embodiments are possible, within the scope of the claims.
Claims
1. A semiconductor wafer, comprising: a first monitor structure located adjacent the die in a scribe street and comprising a first source region, a first drain region, and a first gate region, wherein the first gate region includes a first elongated finger extending longitudinally between the first source region and the first drain region as viewed in top plan view; as well as a second monitor structure located adjacent to the die in the scribe line and comprising one or more second source regions, one or more second drain regions and a plurality of second gate regions, wherein each of the second gate regions includes, as viewed from the top plan view, a second elongated finger extending longitudinally between the one or more second source regions and the one or more second drain regions over a corresponding region of the die.
2. The semiconductor wafer according to claim 1, comprising: a third monitor structure located adjacent to the die in the scribe line and comprising one or more third source regions, one or more third drain regions and a plurality of third gate regions, wherein each of the third gate regions includes a third elongated finger extending longitudinally between the one or more third source regions and the one or more third drain regions over a corresponding region of the die when viewed from the top plan view.
3. The semiconductor wafer of claim 1, wherein the second monitor structure is configured to represent a corresponding transistor on the die. 4 . The semiconductor wafer of claim 3 , wherein the respective transistors on the die of the semiconductor wafer are laterally diffused metal oxide semiconductors (LDMOS). 5 . The semiconductor wafer of claim 3 , wherein the first monitor structure or the second monitor structure is configured to have the same on-resistance between corresponding source and drain regions as the corresponding transistor on the die.
6. The semiconductor wafer of claim 1 including an arrangement of conductive pads and traces in the scribe streets and exposed on a surface of the semiconductor wafer, wherein the pads are coupled to respective gate, source, and drain regions.
7. A system comprising: A sensor configured to measure: a first impedance between a first terminal and a second terminal of a test device, wherein the first impedance represents an impedance of the first monitor structure in a scribe street of a semiconductor wafer in response to applying a first bias voltage across a third terminal of the first monitor structure and the second terminal; a second impedance between the first terminal and the second terminal of the test device, wherein the second impedance represents an impedance of the second monitor structure in the scribe street of the semiconductor wafer in response to applying the first bias voltage across a third terminal of the second monitor structure and the second terminal; a third impedance between the first terminal and the second terminal of the test device, wherein the third impedance represents an impedance of the first monitor structure in response to applying a second bias voltage across the third terminal and the second terminal of the first monitor structure; a fourth impedance between the first terminal and the second terminal of the test device, wherein the fourth impedance represents an impedance of the second monitor structure in response to applying the second bias voltage across the third terminal and the second terminal of the second monitor structure; as well as A processor is configured to calculate a device impedance based on the first impedance, the second impedance, the third impedance, and the fourth impedance, wherein the device impedance represents an impedance of a transistor on a die of a semiconductor wafer adjacent to the scribe street.
8. The system of claim 7, wherein the transistor on the die is a laterally diffused metal oxide semiconductor (LDMOS) transistor and the device impedance represents an on-resistance of the LDMOS transistor.
9. The system of claim 7, wherein the processor is configured to calculate a parasitic impedance of the first monitor structure or the second monitor structure based on the first impedance, the second impedance, the third impedance, and the fourth impedance, and wherein the device impedance is determined based on the parasitic impedance of the first monitor structure or the second monitor structure.
10. The system of claim 7, wherein the processor is configured to assign scores to the dies based on the device impedance.
11. The system of claim 7, wherein the first impedance, the second impedance, the third impedance, and the fourth impedance are measured from a first monitor structure and a second monitor structure adjacent to the die in the scribe line, and wherein the first monitor structure and the second monitor structure each include a conductive pad and a trace.
12. The system of claim 11, wherein the first monitor structure comprises a first source region, a first drain region, and a first gate region, wherein the first gate region comprises a first elongated finger extending longitudinally between the first source region and the first drain region as viewed from a top plan view.
13. The system of claim 12, wherein the second monitor structure comprises one or more second source regions, one or more second drain regions, and a plurality of second gate regions, wherein each of the second gate regions comprises, as viewed from the top plan view, a second elongated finger extending longitudinally between the one or more second source regions and the one or more second drain regions over a corresponding region of the die.
14. The system of claim 13, wherein: measuring the first impedance, the second impedance, the third impedance, and the fourth impedance from the first monitor structure, the second monitor structure, and the third monitor structure adjacent to the die in the scribe line, and The third monitor structure includes one or more third source regions, one or more third drain regions and multiple third gate regions, wherein each of the third gate regions includes a third elongated finger extending longitudinally between the one or more third source regions and the one or more third drain regions above a corresponding region of the die when viewed from the top plan view.
15. A method comprising: measuring a first impedance between a first terminal and a second terminal of a first monitor structure in a scribe street of a semiconductor wafer in response to applying a first bias voltage across a third terminal and a second terminal of the first monitor structure; measuring a second impedance between a first terminal and the second terminal of the second monitor structure in the scribe line of the semiconductor wafer in response to applying the first bias voltage across a third terminal and a second terminal of the second monitor structure; measuring a third impedance between the first terminal and the second terminal of the first monitor structure in response to applying a second bias voltage across the third terminal and the second terminal of the first monitor structure; measuring a fourth impedance between the first terminal and the second terminal of the second monitor structure in response to applying the second bias voltage across the third terminal and the second terminal of the second monitor structure; as well as A device impedance is calculated based on the first impedance, the second impedance, the third impedance, and the fourth impedance.
16. The method of claim 15, wherein the device impedance represents an impedance of a transistor on a die of the semiconductor wafer adjacent to the scribe line.
17. The method of claim 16, wherein the transistor on the die is a laterally diffused metal oxide semiconductor (LDMOS), and the device impedance represents an on-resistance of the LDMOS transistor.
18. The method according to claim 16, comprising: assigning scores to the dies based on the device impedance; separating the die from the semiconductor wafer; as well as The dies are binned based on the scores.
19. The method of claim 15, comprising calculating a parasitic impedance of the first monitor structure or the second monitor structure based on the first impedance, the second impedance, the third impedance, and the fourth impedance, wherein the device impedance is determined based on the parasitic impedance of the first monitor structure or the second monitor structure.
20. The method of claim 15, wherein the first bias voltage is different from the second bias voltage.