A gallium nitride transistor and gallium arsenide vcsel hetero three-dimensional integrated device structure and fabrication method

Abstract

The present invention discloses a gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure and a manufacturing method, belonging to the field of semiconductor technology. The device structure comprises, from bottom to top, an underlying metal, an N-side reflector, a VCSEL light-emitting area, a P-side reflector, a VCSEL bonding metal, a gallium nitride device bonding metal, a gallium nitride substrate layer, a gallium nitride epitaxial layer, a metal through-hole, a gallium nitride transistor electrode source, a gallium nitride transistor electrode gate, and a gallium nitride transistor electrode drain. The device achieves three-dimensional heterogeneous vertical integration based on metal bonding, thereby obtaining a gallium nitride device and gallium arsenide VCSEL three-dimensional integrated material structure and device structure, and a feasible manufacturing method is proposed.

Description

TECHNICAL FIELD

[0001] The application relates to a gallium nitride transistor and gallium arsenide VCSEL hetero three-dimensional integrated device structure and a manufacturing method thereof, and belongs to the technical field of semiconductors. BACKGROUND

[0002] The gallium arsenide VCSEL (Vertical-Cavity Surface-Emitting Laser) is a new generation of semiconductor laser, which forms a resonant cavity in the vertical direction of the substrate, and emits laser light in the vertical direction. The semiconductor laser has the characteristics of small temperature drift, low threshold, easy coupling with an optical fiber, low power consumption, and better dynamic single-mode performance, and is widely used in optical communication, optical storage, optical interconnection and other fields, and is suitable for various application scenarios such as vehicle-mounted laser radar, face recognition and 3D sensing.

[0003] In recent years, with the rapid development of 5G networks, the Internet and AR / VR technologies, we have entered an information age centered on big data and interconnection of all things.

[0004] Therefore, the demand for information transmission speed and communication capacity is increasing.

[0005] Optical interconnection technology with optical fibers as transmission links is becoming more and more mature and is rapidly occupying a large market share.

[0006] Gallium nitride, as the third generation of semiconductors, has excellent characteristics such as wide band gap, high electron mobility and high electron saturation velocity, and has wide application potential in the next generation of radio frequency devices, power electrical devices and other fields.

[0007] Gallium nitride-based devices have the characteristics of high breakdown voltage, high efficiency, high switching frequency and short switching time, while gallium arsenide-based devices have advantages in realizing red light, infrared LED, laser and other aspects.

[0008] Therefore, if high-density micro-nano hetero integration of gallium nitride driving and gallium arsenide light-emitting chips can be realized, it is of great significance for developing more functional, smaller and higher performance optoelectronic device systems such as high-end displays, laser radars and optical communication modules.

[0009] However, there are still many problems in material compatibility, process compatibility and other aspects.

[0010] Therefore, in view of the above problems, a gallium nitride transistor and gallium arsenide VCSEL hetero three-dimensional integrated device structure and a manufacturing method thereof are needed to improve the above problems. SUMMARY

[0011] The main purpose of the present application is to provide a gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure and manufacturing method.

[0012] The purpose of the present application can be achieved by adopting the following technical solutions:

[0013] A gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure and manufacturing method, the device structure comprises from bottom to top: gallium arsenide VCSEL N electrode metal, gallium arsenide VCSEL N pole reflector, gallium arsenide VCSEL light emitting area, gallium arsenide VCSEL P pole reflector, gallium arsenide VCSEL P electrode metal, gallium arsenide VCSEL bonding metal, gallium nitride device bonding metal, gallium nitride device back and via metal, gallium nitride substrate layer, gallium nitride epitaxial layer, metal via, gallium nitride transistor electrode source, gallium nitride transistor electrode gate and gallium nitride transistor electrode drain.

[0014] The gallium arsenide VCSEL N electrode metal, the gallium arsenide VCSEL N pole reflector, the gallium arsenide VCSEL light emitting area, the gallium arsenide VCSEL P pole reflector, the gallium arsenide VCSEL P electrode metal and the gallium arsenide VCSEL bonding metal form a gallium arsenide VCSEL device, the gallium arsenide VCSEL light emitting area realizes photon lasing, and a light beam is emitted from the back surface.

[0015] The gallium nitride device bonding metal, the gallium nitride device back and via metal, the gallium nitride substrate layer, the gallium nitride epitaxial layer, the metal via, the gallium nitride transistor electrode source, the gallium nitride transistor electrode gate and the gallium nitride transistor electrode drain form a gallium nitride transistor, the gallium nitride epitaxial layer is a III-V nitride material, which can be one or a combination of GaN, AlN and InN; a conductive channel is formed in the gallium nitride epitaxial layer and is regulated by the gallium nitride transistor electrode gate, and during operation, current flows from the gallium nitride transistor electrode drain to the gallium nitride transistor electrode source.

[0016] The gallium nitride transistor and the gallium arsenide VCSEL are three-dimensionally and vertically integrated by metal bonding, current flows from the gallium nitride transistor electrode drain to the gallium arsenide VCSEL P pole reflector through the gallium nitride transistor electrode source, the gallium nitride device back and via metal, the gallium nitride device bonding metal, the gallium arsenide VCSEL P electrode metal and the gallium arsenide VCSEL bonding metal, hole provided by the gallium arsenide VCSEL light emitting area and electron provided by the gallium arsenide VCSEL N electrode metal are combined to emit light, and the gallium nitride transistor electrode gate regulates the light emission of the gallium arsenide VCSEL.

[0017] The structure can utilize the characteristics of high breakdown voltage, high efficiency, high switching frequency and short switching time of gallium nitride transistor to provide driving for gallium arsenide VCSEL. The integrated scheme makes the gallium nitride transistor and the gallium arsenide VCSEL have a small spatial interval, reduces the chip volume and weight, and improves the integration of the chip; reduces the loss of long-distance package signal transmission and the influence of parasitic parameters such as inductance under high frequency, and improves the high-frequency performance of the system; reduces the package shell and package lead in the traditional scheme, and reduces the cost of the whole system.

[0018] Preferably, the gallium nitride substrate can be without the gallium nitride device, and the back of the gallium nitride device and the through-hole metal are in direct contact with the gallium nitride epitaxial layer.

[0019] Preferably, the material of the gallium nitride substrate can be one of silicon carbide, silicon, and sapphire substrate, and the thickness is 100-1500 μm; the material of the gallium nitride device epitaxial layer is a group III nitride semiconductor material, which is one or a plurality of compounds formed by gallium nitride, aluminum nitride, and indium nitride. The gallium nitride device epitaxial layer comprises a nitride nucleation layer, a nitride transition layer, a nitride buffer layer, a nitride channel layer, and a nitride barrier layer. The material of the nitride nucleation layer is aluminum nitride, and the thickness is 50-300 nm; the material of the nitride transition layer is gradually changing aluminum gallium nitride or aluminum nitride / aluminum gallium nitride superlattice, and the thickness is 500-1000 nm; the material of the nitride buffer layer is gallium nitride, and the thickness is 100-1000 nm; the material of the nitride channel layer is gallium nitride, or indium gallium nitride, or aluminum gallium nitride, and the thickness is 50-500 nm; the material of the nitride barrier layer is aluminum gallium nitride or indium aluminum nitride, and the thickness is 5-30 nm. A two-dimensional electron gas is formed between the nitride channel layer and the nitride barrier layer, which serves as a conductive channel of the gallium nitride radio frequency device.

[0020] Preferably, the material of the gallium nitride transistor electrode gate is Ni, Ti, TiN, or TaN in the lowermost layer, and Al, Au, Ti, Ta, Pt, TiN, TaN, W, or Cu in one or more of the second layer or layers above.

[0021] The material of the gallium nitride transistor electrode source is Ti, Al, or Ta, Al, or Mo, Al from bottom to top in the lowermost two layers, and one or more of Ti, Al, Ni, Au, Mo, Pt, and W in other layers.

[0022] The material of the gallium nitride transistor electrode drain is Ti, Al, or Ta, Al, or Mo, Al from bottom to top in the lowermost two layers, and one or more of Ti, Al, Ni, Au, Mo, Pt, and W in other layers.

[0023] The back surface and via metal of the gallium nitride device is Ti, Cu, or Au, or W.

[0024] The preferred material of the N electrode metal of the gallium arsenide VCSEL contacts the N-type arsenide material is Ni, or Mo, and the other materials are Ge, Au, and Ni in one or several combinations.

[0025] The preferred material of the P electrode metal of the gallium arsenide VCSEL contacts the P-type arsenide material is Ti, and the other materials are Pt, Au, and Zn in one or several combinations.

[0026] The preferred material of the bonding metal of the gallium arsenide VCSEL and the bonding metal of the gallium nitride device is Ti, Ni, Au, Cu, or one or several combinations thereof.

[0027] The preferred N-pole mirror and P-pole mirror of the gallium arsenide VCSEL are distributed Bragg reflectors (DBR), and the material is one or several periodic material structures of AlAs / GaAs, AlGaAs / GaAs, AlGaAs / InGaP, and AlAs.

[0028] The preferred VCSEL light-emitting region includes an active region and an electrical confinement layer, and the active region is composed of quantum wells.

[0029] The preferred gallium nitride transistor and gallium arsenide VCSEL hetero three-dimensional integrated device structure and manufacturing method includes the following steps:

[0030] Step S1: Select a gallium arsenide epitaxial wafer to prepare a gallium arsenide VCSEL.

[0031] Step S2: Select a gallium nitride epitaxial wafer to prepare a gallium nitride transistor, including substrate thinning, metal via preparation, and gallium nitride device back surface and via metal preparation.

[0032] Step S3: Deposit gallium arsenide VCSEL bonding metal and gallium nitride device bonding metal on the gallium arsenide VCSEL P electrode metal and the gallium nitride device back surface and via metal, respectively.

[0033] Step S4: The gallium nitride transistor and the gallium arsenide VCSEL are metal-bonded through the gallium arsenide VCSEL bonding metal and the gallium nitride device bonding metal.

[0034] The beneficial technical effects of the present application are:

[0035] The present application provides a gallium nitride transistor and gallium arsenide VCSEL hetero three-dimensional integrated device structure and manufacturing method,

[0036] 1. GaN transistors utilize the high breakdown voltage, high efficiency, high switching frequency, and short switching time to drive GaAs VCSELs, meeting the high laser modulation rate requirements of some applications such as LiDAR.

[0037] 2. The proposed integration scheme enables smaller spacing between GaN transistors and GaAs VCSELs, reducing chip size and weight, and improving chip integration.

[0038] 3. Reduces the loss of long-distance package image transmission signals at high frequencies and the influence of parasitic parameters such as inductance, thereby improving the high-frequency performance of the system;

[0039] 4. It reduces the package tube and package leads in the traditional solution, reducing the cost of the entire system. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 1 is a schematic structural diagram (cross-sectional view) of a device comprising a gallium nitride device and a gallium arsenide VCSEL heterogeneously vertically integrated according to embodiment 1 of the present invention;

[0041] Figure 2 A schematic flow chart of a method for manufacturing a device comprising heterogeneous vertical integration of a gallium nitride device and a gallium arsenide VCSEL is provided in an embodiment of the present invention.

[0042] In the figure: 2. GaAs VCSEL N-pole reflector; 3. GaAs VCSEL light-emitting area; 4. GaAs VCSEL P-pole reflector; 5. GaAs VCSEL bonding metal; 6. GaN device bonding metal; 7. GaN substrate layer; 8. GaN epitaxial layer; 10. Metal via; 11. GaAs VCSEL N-electrode metal; 12. GaAs VCSEL N-electrode metal; 41. GaAs VCSEL P-electrode metal; 9. GaN device back and via metal; 91. GaN transistor electrode source; 92. GaN transistor electrode gate; 93. GaN transistor electrode drain. DETAILED DESCRIPTION

[0043] In order to make the technical solution of the present invention more clear and specific to those skilled in the art, the present invention is further described in detail below with reference to embodiments and drawings, but the embodiments of the present invention are not limited thereto.

[0044] like Figure 1 - Figure 2As shown, the gallium nitride transistor and gallium arsenide VCSEL hetero three-dimensional integrated device structure and manufacturing method provided by the embodiment includes, from bottom to top, gallium arsenide VCSEL N electrode metal 11, 12, gallium arsenide VCSEL N pole mirror 2, gallium arsenide VCSEL light emitting area 3, gallium arsenide VCSEL P pole mirror 4, gallium arsenide VCSEL P electrode metal 41, gallium arsenide VCSEL bonding metal 5, gallium nitride device bonding metal 6, gallium nitride device back and via metal 9, gallium nitride substrate layer 7, gallium nitride epitaxial layer 8, metal via 10, gallium nitride transistor electrode source 91, gallium nitride transistor electrode gate 92, and gallium nitride transistor electrode drain 93.

[0045] The gallium arsenide VCSEL N electrode metal 11, 12, the gallium arsenide VCSEL N pole mirror 2, the gallium arsenide VCSEL light emitting area 3, the gallium arsenide VCSEL P pole mirror 4, the gallium arsenide VCSEL P electrode metal 41, and the gallium arsenide VCSEL bonding metal 5 form a gallium arsenide VCSEL device, and the gallium arsenide VCSEL light emitting area realizes photon lasing, and a light beam is emitted from the back surface.

[0046] The gallium nitride device bonding metal 6, the gallium nitride device back and via metal 9, the gallium nitride substrate layer 7, the gallium nitride epitaxial layer 8, the metal via 10, the gallium nitride transistor electrode source 91, the gallium nitride transistor electrode gate 92, and the gallium nitride transistor electrode drain 93 form a gallium nitride transistor, and the gallium nitride epitaxial layer 8 is a III-V nitride material, which can be one or a combination of GaN, AlN, and InN.

[0047] A conductive channel is formed in the gallium nitride epitaxial layer 8 and is regulated by the gallium nitride transistor electrode gate 92, and during operation, current flows from the gallium nitride transistor electrode drain 93 to the gallium nitride transistor electrode source 91.

[0048] The gallium nitride transistor and the gallium arsenide VCSEL are three-dimensionally and vertically integrated by metal bonding, current flows from the gallium nitride transistor electrode drain 93 to the gallium arsenide VCSEL P pole mirror 4 through the gallium nitride transistor electrode source 91, the gallium nitride device back and via metal 9, the gallium nitride device bonding metal 6, the gallium arsenide VCSEL P electrode metal 41, and the gallium arsenide VCSEL bonding metal 5, holes are provided for the gallium arsenide VCSEL light emitting area 3, and light is emitted by recombination of the holes and electrons provided by the gallium arsenide VCSEL N electrode metal 11, 12, and the gallium arsenide VCSEL N pole mirror 2, thereby realizing regulation of the gallium arsenide VCSEL light emitting area 3 by the gallium nitride transistor electrode gate 92.

[0049] The structure can utilize the characteristics of high breakdown voltage, high efficiency, high switching frequency and short switching time of gallium nitride transistor to provide driving for gallium arsenide VCSEL. The integrated scheme makes gallium nitride transistor and gallium arsenide VCSEL have a small spatial interval, reduces the chip volume and weight, and improves the integration of the chip. The scheme reduces the loss of long-distance package signal transmission and the influence of parasitic parameters such as inductance under high frequency, improves the high-frequency performance of the system, and reduces the package shell and package lead in the traditional scheme, thereby reducing the cost of the whole system.

[0050] The gallium nitride substrate 7 can be directly contacted with the back surface of the gallium nitride device and the through-hole metal 9 and the gallium nitride epitaxial layer 8.

[0051] The material of the gallium nitride substrate 7 can be one of silicon carbide, silicon, and sapphire substrate, and the thickness is 100-1500 μm. The material of the gallium nitride device epitaxial layer 8 is a group III nitride semiconductor material, which is a compound formed by one or more of gallium nitride, aluminum nitride, and indium nitride. The gallium nitride device epitaxial layer 3 comprises a nitride nucleation layer, a nitride transition layer, a nitride buffer layer, a nitride channel layer, and a nitride barrier layer. The material of the nitride nucleation layer is aluminum nitride, and the thickness is 50-300 nm. The material of the nitride transition layer is gradually changing aluminum gallium nitride or aluminum nitride / aluminum gallium nitride superlattice, and the thickness is 500-1000 nm. The material of the nitride buffer layer is gallium nitride, and the thickness is 100-1000 nm. The material of the nitride channel layer is gallium nitride, or indium gallium nitride, or aluminum gallium nitride, and the thickness is 50-500 nm. The material of the nitride barrier layer is aluminum gallium nitride or indium aluminum nitride, and the thickness is 5-30 nm. A two-dimensional electron gas is formed between the nitride channel layer and the nitride barrier layer, which serves as a conductive channel of the gallium nitride radio frequency device.

[0052] The material of the gallium nitride transistor electrode gate 92 is Ni, Ti, TiN, or TaN in the lowermost layer, and Al, Au, Ti, Ta, Pt, TiN, TaN, W, or Cu in the second layer or the layers above the second layer.

[0053] The material of the gallium nitride transistor electrode source 91 is Ti, Al, or Ta, Al, or Mo, Al in the lowermost two layers from bottom to top, and one or more of Ti, Al, Ni, Au, Mo, Pt, and W in the other layers.

[0054] The material of the gallium nitride transistor electrode drain 93 is Ti, Al, or Ta, Al, or Mo, Al in the lowermost two layers from bottom to top, and one or more of Ti, Al, Ni, Au, Mo, Pt, and W in the other layers.

[0055] The backside and via metal 9 of the gallium nitride device is Ti, Cu, or Au, or W.

[0056] The material of the gallium arsenide VCSEL N electrode metal 1112 contacting the N-type arsenide material is Ni, or Mo, and the other materials are one or several combinations of Ge, Au, and Ni.

[0057] The material of the gallium arsenide VCSEL P electrode metal 41 contacting the P-type arsenide material is Ti, and the other materials are one or several combinations of Pt, Au, and Zn.

[0058] The material of the gallium arsenide VCSEL bonding metal 5 and the gallium nitride device bonding metal 6 is one or several combinations of Ti, Ni, Au, Cu, etc.

[0059] The gallium arsenide VCSEL N-pole mirror 2 and the gallium arsenide VCSEL P-pole mirror 4 adopt a distributed Bragg reflector (DBR), and the material is one or several periodic material structures of AlAs / GaAs, AlGaAs / GaAs, AlGaAs / InGaP, AlAs.

[0060] The VCSEL light-emitting region 3 includes an active region and an electrical confinement layer; the active region comprises a quantum well group.

[0061] As shown in Figure 1 - Figure 2 The working process of the gallium nitride transistor and the gallium arsenide VCSEL hetero three-dimensional integrated device structure and the manufacturing method provided by the embodiment is as follows:

[0062] Step S1: Select a gallium arsenide epitaxial wafer to prepare a gallium arsenide VCSEL;

[0063] Step S2: Select a gallium nitride epitaxial wafer to prepare a gallium nitride transistor, including substrate thinning, metal via 10 preparation, and gallium nitride device backside and via metal 9 preparation; Step S3: Deposit gallium arsenide VCSEL bonding metal 5 and gallium nitride device bonding metal 6 on the gallium arsenide VCSEL P electrode metal 41 and the gallium nitride device backside and via metal 9, respectively.

[0064] Step S4: The gallium nitride transistor and the gallium arsenide VCSEL are metal-bonded through the gallium arsenide VCSEL bonding metal 5 and the gallium nitride device bonding metal.

[0065] Embodiment

[0066] As shown in Figure 1 - Figure 2As shown, the selected gallium arsenide epitaxial wafer is used for gallium arsenide VCSEL preparation, the selected gallium nitride epitaxial wafer is used for gallium nitride transistor preparation, including substrate thinning, metal via 10 preparation, and gallium nitride device back surface and via metal 9 preparation, gallium arsenide VCSEL bonding metal 5 and gallium nitride device bonding metal 6 are respectively deposited on the gallium arsenide VCSEL P electrode metal 41 and the gallium nitride device back surface and via metal 9, and the gallium nitride transistor and the gallium arsenide VCSEL are metal bonded through the gallium arsenide VCSEL bonding metal 5 and the gallium nitride device bonding metal 6;

[0067] The gallium nitride transistor has the characteristics of high breakdown voltage, high efficiency, high switching frequency and short switching time, and is used for driving the gallium arsenide VCSEL, so as to meet the requirement of high modulation rate of laser for some application scenarios such as laser radar;

[0068] The integrated scheme makes the gallium nitride transistor and the gallium arsenide VCSEL have a small spatial distance, reduces the chip volume and weight, and improves the integration degree of the chip;

[0069] The loss of long-distance packaged image transmission signals under high frequency and the influence of parasitic parameters such as inductance are reduced, and the high-frequency performance of the system is improved.

[0070] The packaging shell and the packaging lead in the traditional scheme are reduced, and the cost of the whole system is reduced.

[0071] The above is only a further embodiment of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can make equivalent replacement or change according to the technical scheme and concept of the present application within the scope disclosed by the present application, which belongs to the protection scope of the present application.

Claims

1. A three-dimensional heterogeneous integrated device structure of a gallium nitride transistor and a gallium arsenide VCSEL, characterized by: The device structure includes, from bottom to top, GaAs VCSEL N-electrode metal (11) (12), GaAs VCSEL N-pole reflector (2), GaAs VCSEL light-emitting region (3), GaAs VCSEL P-pole reflector (4), GaAs VCSEL P-electrode metal (41), GaAs VCSEL bonding metal (5), GaN device bonding metal (6), GaN device back and through-hole metal (9), GaN substrate layer (7), GaN epitaxial layer (8), metal through-hole (10), GaN transistor electrode source (91), GaN transistor electrode gate (92), and GaN transistor electrode drain (93); GaAs VCSEL N-electrode metal (11), (12) GaAs VCSEL N-pole reflector (2), GaAs VCSEL light-emitting region (3), GaAs VCSEL P-pole reflector (4), GaAs VCSEL P-electrode metal (41), and GaAs VCSEL bonding metal (5) constitute a GaAs VCSEL device. The GaAs VCSEL light-emitting region realizes photon lasing, and the light beam is emitted from the back side. The gallium nitride device bonding metal (6), the gallium nitride device back and through-hole metal (9), the gallium nitride substrate layer (7), the gallium nitride epitaxial layer (8), the metal through-hole (10), the gallium nitride transistor electrode source (91), the gallium nitride transistor electrode gate (92) and the gallium nitride transistor electrode drain (93) constitute a gallium nitride transistor. The gallium nitride epitaxial layer (8) is a group III nitride material and can be one or a combination of several of GaN, AlN and InN. A conductive channel is formed in the gallium nitride epitaxial layer (8) and is regulated by the gallium nitride transistor electrode gate (92). When working, current flows from the gallium nitride transistor electrode drain (93) to the gallium nitride transistor electrode source (91). GaN transistor and GaAs VCSEL; three-dimensional vertical integration is achieved by metal bonding, with current flowing from the GaN transistor electrode drain (93), through the GaN transistor electrode source (91), the GaN device back and through-hole metal (9), the GaN device bonding metal (6), the GaAs VCSEL P-electrode metal (41), and the GaAs VCSEL bonding metal (5) to the GaAs VCSEL P-pole reflector (4), providing holes to the GaAs VCSEL light-emitting area (3) and electrons provided by the GaAs VCSEL N-electrode metal (11) (12) for combined luminescence, thereby achieving regulation of the GaAs VCSEL light-emitting by the GaN transistor electrode gate (92).

2. The gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure according to claim 1, characterized in that: The gallium nitride substrate layer (7) may be absent, and the back surface of the gallium nitride device is in direct contact with the through-hole metal (9) and the gallium nitride epitaxial layer (8).

3. The gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure according to claim 2, characterized in that: The material of the gallium nitride substrate layer (7) can be one of silicon carbide, silicon, and sapphire substrate, with a thickness of 100-1500 μm; the material of the gallium nitride epitaxial layer (8) is a group III nitride semiconductor material, which is a compound formed by one or more of gallium nitride, aluminum nitride, and indium nitride. The gallium nitride epitaxial layer (8) comprises a nitride nucleation layer, a nitride transition layer, a nitride buffer layer, a nitride channel layer, and a nitride barrier layer. The material of the nitride nucleation layer is aluminum nitride, with a thickness of 50-300 nm; the material of the nitride transition layer is graded aluminum gallium nitride, or aluminum nitride / aluminum gallium nitride superlattice, with a thickness of 500-1000 nm; the material of the nitride buffer layer is gallium nitride, with a thickness of 100-1000 nm; the material of the nitride channel layer is gallium nitride, or indium gallium nitride, or aluminum gallium nitride, with a thickness of 50-500 nm. nm; the material of the nitride barrier layer is aluminum gallium nitride or indium aluminum nitride, with a thickness of 5-30 nm, and a two-dimensional electron gas is formed between the nitride channel layer and the nitride barrier layer, serving as a conductive channel for the gallium nitride radio frequency device.

4. The gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure according to claim 3, characterized in that: The bottom layer of the material of the gallium nitride transistor electrode gate (92) is Ni, or Ti, or TiN, or TaN, and the second layer or the second layer above the second layer is one or more of Al, Au, Ti, Ta, Pt, TiN, TaN, W, and Cu; The bottom two layers of the material of the gallium nitride transistor electrode source (91) are Ti, Al, or Ta, Al, or Mo, Al from bottom to top; the metals of other layers include one or more of Ti, Al, Ni, Au, Mo, Pt, and W; The back surface and through-hole metal (9) of the gallium nitride device are Ti, Cu, Au or W.

5. The gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure according to claim 4, characterized in that: The GaAs VCSEL N-electrode metal (11) (12) material contacts the N-type arsenide material with a layer of Ni or Mo, and the other layers of materials are one or a combination of Ge, Au, and Ni; The GaAs VCSEL P-electrode metal (41) material contacts a P-type arsenide material with a layer of Ti, and the other layers of material are one or a combination of Pt, Au, and Zn; The materials of the gallium arsenide VCSEL bonding metal (5) and the gallium nitride device bonding metal (6) are one or a combination of Ti, Ni, Au, and Cu.

6. The gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure according to claim 5, characterized in that: The gallium arsenide VCSEL N-pole reflector (2) and the gallium arsenide VCSEL P-pole reflector (4) adopt a distributed Bragg reflector (DBR), the material of which is one or several periodic material structures of multiple pairs of AlAs / GaAs, AlGaAs / GaAs, AlGaAs / InGaP, and AlAs.

7. The gallium nitride transistor and gallium arsenide VCSEL heterogeneous three-dimensional integrated device structure according to claim 6, characterized in that: The VCSEL light-emitting region (3) includes an active region and an electrical confinement layer; The active region comprises a quantum well.

8. A method for fabricating a three-dimensional heterogeneous integrated device of a gallium nitride transistor and a gallium arsenide VCSEL, based on the three-dimensional heterogeneous integrated device structure of a gallium nitride transistor and a gallium arsenide VCSEL according to any one of claims 1 to 7, characterized in that: The following steps are also included: Step S1: Selecting a GaAs epitaxial wafer to prepare a GaAs VCSEL; Step S2: selecting a gallium nitride epitaxial wafer and preparing a gallium nitride transistor, including substrate thinning, preparation of metal through-holes (10), and preparation of the back side and through-hole metal (9) of the gallium nitride device; Step S3: depositing a GaAs VCSEL bonding metal (5) and a GaN device bonding metal (6) on the GaAs VCSEL P electrode metal (41) and on the back surface of the GaN device and the through-hole metal (9), respectively; Step S4: The GaN transistor and the GaAs VCSEL are metal-bonded via the GaAs VCSEL bonding metal (5) and the GaN device bonding metal.

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