LLC topology secondary side synchronous rectification control circuit

Abstract

The invention belongs to the technical field of power electronics, and particularly discloses an LLC topology secondary side synchronous rectification control circuit. The circuit comprises an LLC primary side driving circuit, an LLC secondary side synchronous rectification circuit and a secondary side synchronous rectification control circuit, the secondary side synchronous rectification control circuit is connected with the LLC secondary side synchronous rectification circuit; and the secondary side synchronous rectification control circuit is constructed based on a differential sampling circuit, and is used for sampling the rectification voltage of a target secondary side winding in the LLC secondary side synchronous rectification circuit when the LLC primary side driving circuit operates, and controlling the on-off of an MOS (Metal Oxide Semiconductor) tube in the LLC secondary side synchronous rectification circuit based on the rectification voltage. According to the LLC switching power supply, the problem of duty ratio loss in a traditional synchronous rectification circuit can be effectively avoided, and the efficiency of the LLC switching power supply is greatly improved.

Description

Technical Field

[0001] The present application belongs to the field of power electronics technology, and more specifically, relates to an LLC topology secondary-side synchronous rectification control circuit. Background Art

[0002] As the efficiency requirements of LLC switching power supplies become higher and higher, synchronous rectification technology based on MOS tubes is widely used due to its huge advantage in loss compared to diode rectification, especially in similar low-voltage and high-current output situations, the advantages of this synchronous rectification technology are more obvious.

[0003] In the actual application of MOS tube synchronous rectification circuit, the MOS tube opening logic is generally performed by detecting the voltage of the drain terminal relative to the source terminal (hereinafter referred to as VDS voltage). However, in the synchronous rectification circuit, due to the influence of the MOS tube stray inductance in the circuit and the equivalent inductance of the detection loop, it is easy to produce a situation where the voltage phase at both ends of the MOS tube leads the current, so that when the VDS voltage has a shutdown signal, the MOS tube still has a large current, causing the MOS tube to be shut down in advance, thereby causing part of the voltage square wave provided by the primary side in the LLC circuit to not be effectively utilized, resulting in energy loss, and ultimately leading to the occurrence of duty cycle loss.

[0004] Therefore, how to solve the duty cycle loss problem of the existing synchronous rectification circuit and improve the efficiency of LLC switching power supply has become a technical problem that needs to be solved urgently in the industry. Summary of the invention

[0005] In view of the defects of the prior art, the purpose of the present application is to solve the problem of duty cycle loss in the existing synchronous rectification circuit and improve the efficiency of the LLC switching power supply.

[0006] To achieve the above objectives, the present application provides an LLC topology secondary side synchronous rectification control circuit, comprising:

[0007] LLC primary side driving circuit, LLC secondary side synchronous rectification circuit and secondary side synchronous rectification control circuit;

[0008] The secondary side synchronous rectification control circuit is connected to the LLC secondary side synchronous rectification circuit;

[0009] The secondary synchronous rectification control circuit is constructed based on a differential sampling circuit, and is used to sample the rectified voltage of the target secondary winding in the LLC secondary synchronous rectification circuit when the LLC primary driving circuit is running, and control the on and off of the MOS tube in the LLC secondary synchronous rectification circuit based on the rectified voltage.

[0010] Optionally, the secondary-side synchronous rectification control circuit includes a first drive circuit, a second drive circuit, a voltage divider circuit, a differential sampling circuit, a Schmitt trigger and a comparison trigger circuit connected in sequence;

[0011] The first output terminal of the comparison trigger circuit is connected to the first driving circuit, and the second output terminal of the comparison trigger circuit is connected to the second driving circuit;

[0012] The voltage divider circuit is connected in parallel to the two ends of the target secondary winding, and is used to divide the rectified voltage at the two ends of the target secondary winding;

[0013] The differential sampling circuit is used to collect the target divided voltage on the voltage divider circuit for differential amplification and bias processing;

[0014] The Schmitt trigger is used to perform signal anti-interference processing on the voltage output by the differential sampling circuit to prevent the comparison trigger circuit from being falsely triggered;

[0015] The comparison trigger circuit is used to compare the voltage output by the Schmitt trigger with a preset reference voltage, and drive the MOS tube to be turned on and off through the first drive circuit and the second drive circuit based on the comparison result.

[0016] Optionally, the LLC secondary synchronous rectification circuit includes: the secondary winding S1, the secondary winding S2, the MOS transistor Q3, the MOS transistor Q4, the capacitor C5, the capacitor C6 and the load resistor R load ; The target secondary winding is the secondary winding S1;

[0017] The same-name end of the secondary winding S1, one end of the voltage divider circuit and the drain of the MOS transistor Q3 are connected together, and the gate of the MOS transistor Q3 is connected to the first driving circuit;

[0018] The source of the MOS transistor Q3, the source of the MOS transistor Q4, one end of the capacitor C5, one end of the capacitor C6 and the load resistor R load One end is connected together;

[0019] The opposite-name end of the secondary winding S1, the same-name end of the secondary winding S2, the other end of the voltage divider circuit, the other end of the capacitor C5, the other end of the capacitor C6 and the load resistor R load The other end of the

[0020] The opposite-name end of the secondary winding S2 is connected to the drain of the MOS transistor Q4 , and the gate of the MOS transistor Q4 is connected to the second driving circuit.

[0021] Optionally, the first driving circuit includes a push-pull driving amplifier circuit U6, a voltage source V7, a resistor R14 and a resistor R15; the input end of the push-pull driving amplifier circuit U6 serves as the input end of the first driving circuit;

[0022] The positive power supply terminal of the push-pull drive amplifier circuit U6 is connected to the positive terminal of the voltage source V7, the negative power supply terminal of the push-pull drive amplifier circuit U6, the negative terminal of the voltage source V7 and one end of the resistor R15 are connected in common, the output end of the push-pull drive amplifier circuit U6 is connected to one end of the resistor R14, and the other end of the resistor R14 and the other end of the resistor R15 are connected in common to the gate of the MOS tube Q3;

[0023] The second driving circuit includes a push-pull driving amplifier circuit U7, a voltage source V8, a resistor R16 and a resistor R17; the input end of the push-pull driving amplifier circuit U7 serves as the input end of the second driving circuit;

[0024] The positive power supply terminal of the push-pull drive amplifier circuit U7 is connected to the positive terminal of the voltage source V8, the negative power supply terminal of the push-pull drive amplifier circuit U7, the negative terminal of the voltage source V8 and one end of the resistor R17 are connected in common, the output end of the push-pull drive amplifier circuit U7 is connected to one end of the resistor R16, and the other end of the resistor R16 and the other end of the resistor R17 are connected in common to the gate of the MOS tube Q4.

[0025] Optionally, the voltage divider circuit includes a resistor R5, a resistor R6 and a resistor R7 connected in sequence; one end of the resistor R5 is connected to the same-name end of the target secondary winding, the other end of the resistor R5 is connected to one end of the resistor R7 through the resistor R6, and the other end of the resistor R7 is connected to the opposite-name end of the target secondary winding.

[0026] Optionally, the differential sampling circuit includes a resistor R8, a resistor R9, a resistor R10, a resistor R11, a voltage source V5, a bias voltage source V4 and an operational amplifier U3;

[0027] One end of the resistor R8 is connected to one end of the resistor R6, one end of the resistor R9 is connected to the other end of the resistor R6, the other end of the resistor R8 and one end of the resistor R10 are connected to the positive input end of the operational amplifier U3, and the other end of the resistor R10 is connected to the bias voltage source V4;

[0028] The other end of the resistor R9 and one end of the resistor R11 are connected to the negative input end of the operational amplifier U3, and the other end of the resistor R11 and the output end of the operational amplifier U3 are connected to the input end of the Schmitt trigger;

[0029] The voltage source V5 is connected to the positive power supply terminal of the operational amplifier U3, and the negative power supply terminal of the operational amplifier U3 is grounded.

[0030] Optionally, the comparison trigger circuit includes a resistor R12, a resistor R13, a voltage source V6 for outputting the preset reference voltage, and a comparator U5;

[0031] One end of the resistor R12 is connected to the output end of the Schmitt trigger, the other end of the resistor R12 and one end of the resistor R13 are connected to the positive input end of the comparator U5, and the negative input end of the comparator U5 is connected to the voltage source V6;

[0032] The other end of the resistor R13, the positive output end of the comparator U5 and the input end of the first driving circuit are connected in common, and the negative output end of the comparator U5 is connected to the input end of the second driving circuit.

[0033] Optionally, the LLC primary drive circuit includes a voltage source V1, a capacitor C1, a third drive circuit, a fourth drive circuit, a MOS transistor Q1, a capacitor C2, a MOS transistor Q2, a capacitor C3, a resonant circuit and a primary winding P1;

[0034] One end of the voltage source V1, one end of the capacitor C1, the drain of the MOS transistor Q1, and one end of the capacitor C2 are connected together, and the other end of the voltage source V1, the other end of the capacitor C1, the second output end of the fourth drive circuit, the source of the MOS transistor Q2, and the second input end of the resonant circuit are connected to the ground;

[0035] The first output end of the third driving circuit is connected to the gate of the MOS transistor Q1; the second output end of the third driving circuit, the source of the MOS transistor Q1, the drain of the MOS transistor Q2, and the first input end of the resonant circuit are connected in common; the first output end of the fourth driving circuit is connected to the gate of the MOS transistor Q2;

[0036] The first output end of the resonant circuit is connected to the same-name end of the primary winding P1, and the second output end of the resonant circuit is connected to the opposite-name end of the primary winding P1.

[0037] Optionally, the third driving circuit includes a push-pull driving amplifier circuit U1, a voltage source V2, a resistor R1 and a resistor R2; the input end of the push-pull driving amplifier circuit U1 serves as the input end of the third driving circuit;

[0038] The positive power supply terminal of the push-pull driving amplifier circuit U1 is connected to the positive terminal of the voltage source V2, the negative power supply terminal of the push-pull driving amplifier circuit U1, the negative terminal of the voltage source V2 and one end of the resistor R2 are connected in common, and one end of R2 serves as the second output terminal of the third driving circuit; the output terminal of the push-pull driving amplifier circuit U1 is connected to one end of the resistor R1; the other end of the resistor R1 is connected to the other end of the resistor R2, and the other end of the resistor R2 serves as the first output terminal of the third driving circuit;

[0039] The fourth driving circuit includes a push-pull driving amplifier circuit U2, a voltage source V3, a resistor R3 and a resistor R4; the input end of the push-pull driving amplifier circuit U2 serves as the input end of the fourth driving circuit;

[0040] The positive power supply terminal of the push-pull drive amplifier circuit U2 is connected to the positive terminal of the voltage source V3; the negative power supply terminal of the push-pull drive amplifier circuit U2, the negative terminal of the voltage source V3 and one end of the resistor R4 are connected in common, and one end of R4 serves as the first output terminal of the fourth drive circuit; the output terminal of the push-pull drive amplifier circuit U2 is connected to one end of the resistor R3; the other end of the resistor R3 and the other end of the resistor R4 are connected, and the other end of the resistor R4 serves as the second output terminal of the fourth drive circuit.

[0041] Optionally, the resonant circuit includes an inductor L1, an inductor L2 and a capacitor C4;

[0042] One end of the inductor L1 serves as a first input end of the resonant circuit, the other end of the inductor L1 is connected to one end of the inductor L2, and the other end of the inductor L1 serves as a first output end of the resonant circuit;

[0043] One end of the capacitor C4 serves as the second input end of the resonant circuit, the other end of the capacitor C4 is connected to the other end of the inductor L2, and the other end of the inductor L2 serves as the second output end of the resonant circuit.

[0044] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the prior art:

[0045] The present application provides an LLC topology secondary synchronous rectification control circuit, which controls the on and off of the synchronous rectification MOS tube by changing the traditional method based on detecting the VDS voltage of the synchronous rectification MOS tube to the method of sampling the rectification voltage of the secondary winding of the power transformer, and uses a differential sampling circuit to sample the rectification voltage of the secondary winding, and compares and processes the rectification voltage of the secondary winding with the sampled preset reference voltage. The working state of the secondary winding is directly fed back through the comparison result, so that the MOS tube is turned on in time when the secondary winding power circuit needs to be rectified to reduce the loss, and the MOS tube is turned off in time when the winding power circuit voltage is reversed to prevent the transformer from short-circuiting, and there is no situation where the MOS tube is turned off in advance, which can effectively avoid the duty cycle loss problem in the traditional synchronous rectification circuit and greatly improve the efficiency of the LLC switching power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is one of the structural schematic diagrams of the LLC topology secondary side synchronous rectification control circuit provided in the embodiment of the present application;

[0047] Figure 2 It is one of the structural schematic diagrams of the secondary side synchronous rectification control circuit provided in the embodiment of the present application;

[0048] Figure 3 This is the second structural schematic diagram of the LLC topology secondary side synchronous rectification control circuit provided in the embodiment of the present application;

[0049] Figure 4 This is the second structural schematic diagram of the secondary side synchronous rectification control circuit provided in the embodiment of the present application. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0051] The terms "first" and "second" in the specification and claims herein are used to distinguish different objects rather than to describe a specific order of the objects. For example, the first drive circuit and the second drive circuit are used to distinguish drive circuits with different functions rather than to describe a specific order of the drive circuits.

[0052] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0053] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0054] Figure 1 is one of the structural schematic diagrams of the LLC topology secondary side synchronous rectification control circuit provided in the embodiment of the present application, such as Figure 1 As shown, the circuit includes:

[0055] LLC primary side driving circuit 1, LLC secondary side synchronous rectification circuit 2 and secondary side synchronous rectification control circuit 3;

[0056] The secondary side synchronous rectification control circuit 3 is connected to the LLC secondary side synchronous rectification circuit 2;

[0057] The secondary synchronous rectification control circuit 3 is constructed based on a differential sampling circuit, and is used to sample the rectified voltage of the target secondary winding in the LLC secondary synchronous rectification circuit 2 when the LLC primary driving circuit 1 is running, and control the on and off of the MOS tube in the LLC secondary synchronous rectification circuit 2 based on the rectified voltage.

[0058] Specifically, in an embodiment of the present application, the secondary winding in the LLC secondary synchronous rectification circuit 2 is usually divided into two groups of secondary windings, and the target secondary winding can be any one of the groups of secondary windings as long as the driving logic of the subsequent MOS switch tube meets the requirements.

[0059] In an embodiment of the present application, the secondary synchronous rectification control circuit 3 is constructed based on a differential sampling circuit, and can perform differential sampling on the voltage across the target secondary winding of the transformer in the LLC switching power supply, and then perform voltage division, interference suppression and other processing on the sampled winding end voltage, and then compare it with the pre-set turn-on reference voltage. If it is determined that the sampled winding voltage is higher than the set reference voltage, a high level is given to drive the MOS tube in the LLC secondary synchronous rectification circuit 2 to turn on. If the sampled winding voltage is lower than the set reference voltage, a low level is immediately output to turn off the MOS tube in the LLC secondary synchronous rectification circuit 2.

[0060] More specifically, by inputting two complementary 50% duty cycle square wave drive control signals into the drive signal input port of the LLC primary drive circuit 1 to drive the internal MOS tube, a 50% duty cycle square wave signal is generated on the primary winding of the transformer, and this signal will generate a square wave signal with the same polarity at the same end and a voltage that is consistent with the turns ratio of the primary and secondary windings of the transformer on the target secondary winding in the LLC secondary synchronous rectification circuit 2.

[0061] Furthermore, the target secondary winding voltage of the LLC transformer is differentially sampled by the secondary synchronous rectification control circuit 3, and the sampled winding terminal voltage is compared with the preset turn-on reference voltage. Based on the reference voltage and the transformer secondary winding rectification voltage, the winding working state can be directly fed back by using the final comparison result, so as to form a feedback control signal to control the on and off of the MOS tube in the LLC secondary synchronous rectification circuit 2, so that the MOS tube can be turned on in time when the winding power circuit needs to be rectified, and after the winding power circuit voltage is reversed, the MOS tube can be turned off in time to prevent the transformer from short-circuiting, so as to always keep the square wave signal with a consistent turn ratio of the secondary winding output, so as to achieve the purpose of stable output and reduced power consumption.

[0062] The LLC topology secondary synchronous rectification control circuit of the embodiment of the present application controls the on and off of the synchronous rectification MOS tube by changing the traditional method based on detecting the VDS voltage of the synchronous rectification MOS tube to the method of sampling the rectification voltage of the secondary winding of the power transformer, and samples the rectification voltage of the secondary winding by a differential sampling circuit, and compares and processes the rectification voltage of the secondary winding with the sampled preset reference voltage. The working state of the secondary winding is directly fed back through the comparison result, so that the MOS tube is turned on in time when the secondary winding power circuit needs to be rectified to reduce the loss, and the MOS tube is turned off in time when the winding power circuit voltage is reversed to prevent the transformer from short-circuiting. There will be no situation where the MOS tube is turned off in advance, which can effectively avoid the duty cycle loss problem in the traditional synchronous rectification circuit and greatly improve the efficiency of the LLC switching power supply.

[0063] Figure 2 is one of the structural diagrams of the secondary side synchronous rectification control circuit provided in the embodiment of the present application, such as Figure 2 As shown, in the embodiment of the present application, the secondary synchronous rectification control circuit 3 includes a first drive circuit 31, a second drive circuit 32, a voltage divider circuit 33, a differential sampling circuit 34, a Schmitt trigger U4 and a comparison trigger circuit 35 connected in sequence;

[0064] The first output terminal of the comparison trigger circuit 35 is connected to the first driving circuit 31, and the second output terminal of the comparison trigger circuit 36 ​​is connected to the second driving circuit 32;

[0065] The voltage divider circuit 33 is connected in parallel to both ends of the target secondary winding, and is used to divide the rectified voltage at both ends of the target secondary winding;

[0066] The differential sampling circuit 34 is used to collect the target divided voltage on the voltage divider circuit for differential amplification and bias processing;

[0067] The Schmitt trigger U4 is used to perform signal anti-interference processing on the voltage output by the differential sampling circuit to prevent the comparison trigger circuit from generating false triggering;

[0068] The comparison trigger circuit 35 is used to compare the voltage output by the Schmitt trigger 35 with a preset reference voltage, and drive the MOS tube to be turned on and off through the first drive circuit 31 and the second drive circuit 32 based on the comparison result.

[0069] Specifically, in the embodiment of the present application, the secondary synchronous rectification control circuit 3 is composed of a first driving circuit 31, a second driving circuit 32, a voltage divider circuit 33, a differential sampling circuit 34, a Schmitt trigger U4 and a comparison trigger circuit 35 connected in sequence. Among them, the voltage divider circuit 33 is connected in parallel to the two ends of the target secondary winding in the LLC secondary synchronous rectification circuit 2, and is used to divide the rectified voltage at the two ends of the target secondary winding, reduce the voltage amplitude, and facilitate the differential sampling circuit 34 to sample the voltage signal.

[0070] In an embodiment of the present application, the voltage divider circuit 33 can adopt a structure of multiple series resistors, and obtain a target voltage divider by sampling from both ends of one of the resistors through a differential sampling circuit 34, and differentially amplify and bias the target voltage divider. Further, the Schmitt trigger U4 can perform anti-interference processing such as waveform shaping, transformation, comparison, and amplitude detection on the voltage output by the differential sampling circuit to prevent the subsequent comparison trigger circuit 35 from being falsely triggered due to winding level oscillation caused by parasitic parameters during the dead time. The comparison trigger circuit 35 further compares the voltage output by the Schmitt trigger 35 with a preset reference voltage, and controls the first drive circuit 31 and the second drive circuit 32 to drive the on and off of the MOS tube in the LLC secondary synchronous rectification circuit 2 based on the comparison result.

[0071] The preset reference voltage is a reference voltage pre-set in the input comparison trigger circuit 35 , which can be specifically determined according to the output voltage of the LLC secondary synchronous rectification circuit 2 , the voltage division coefficient of the target voltage and the amplification coefficient of the differential sampling circuit 34 .

[0072] The circuit of the embodiment of the present application utilizes a voltage divider circuit, a differential sampling circuit, a Schmitt trigger, a comparison trigger circuit and a drive circuit to construct a secondary side synchronous rectification control circuit. By performing rectification voltage voltage division sampling on the secondary side winding voltage and comparing it with a preset reference voltage, the effect of dynamically controlling the on and off of the synchronous rectification MOS tube based on the change of the secondary side sampling voltage is achieved, which can effectively avoid the duty cycle loss problem caused by the traditional method of detecting the VDS voltage of the MOS tube.

[0073] Figure 3 FIG. 2 is a second structural diagram of the LLC topology secondary side synchronous rectification control circuit provided in an embodiment of the present application. Figure 3As shown, in the embodiment of the present application, the LLC primary drive circuit 1 includes a voltage source V1, a capacitor C1, a third drive circuit 11, a fourth drive circuit 12, a MOS transistor Q1, a capacitor C2, a MOS transistor Q2, a capacitor C3, a resonant circuit 13 and a primary winding P1;

[0074] One end of the voltage source V1, one end of the capacitor C1, the drain of the MOS transistor Q1, and one end of the capacitor C2 are connected together, and the other end of the voltage source V1, the other end of the capacitor C1, the second output end of the fourth drive circuit, the source of the MOS transistor Q2, and the second input end of the resonant circuit are connected to the ground;

[0075] The first output end of the third driving circuit is connected to the gate of the MOS transistor Q1; the second output end of the third driving circuit, the source of the MOS transistor Q1, the drain of the MOS transistor Q2, and the first input end of the resonant circuit are connected in common; the first output end of the fourth driving circuit is connected to the gate of the MOS transistor Q2;

[0076] The first output end of the resonance circuit is connected to the same-name end of the primary winding P1, and the second output end of the resonance circuit is connected to the opposite-name end of the primary winding P1.

[0077] Specifically, in the embodiment of the present application, the LLC primary drive circuit 1 is provided with a power supply voltage by a voltage source V1, and a capacitor C1 is connected in parallel to both ends of the voltage source V1 to play the role of voltage stabilization and filtering. The two MOS transistors Q1 and Q2 form an upper and lower half-bridge circuit, which are connected in parallel to the voltage source V1 and the capacitor C1, and the center point of the two MOS transistors in series is connected to the first input end of the resonant circuit 13.

[0078] Continue to refer to Figure 3 In the embodiment of the present application, the resonant circuit includes an inductor L1, an inductor L2 and a capacitor C4; one end of the inductor L1 serves as a first input end of the resonant circuit, the other end of the inductor L1 is connected to one end of the inductor L2, and the other end of the inductor L1 serves as a first output end of the resonant circuit;

[0079] One end of the capacitor C4 serves as the second input end of the resonant circuit, the other end of the capacitor C4 is connected to the other end of the inductor L2, and the other end of the inductor L2 serves as the second output end of the resonant circuit.

[0080] Specifically, in an embodiment of the present application, the inductor L1 serves as the first input end of the resonant circuit and is connected to the center point of the two MOS tubes in series. The other end of the inductor L1 serves as the first output end of the resonant circuit and is connected to the same-name end of the primary winding P1 of the transformer TX1. One end of the capacitor C4 serves as the second input end of the resonant circuit and is connected to the negative end of V1. The other end of the capacitor C4 is connected to the opposite-name end of the primary winding P1. L2 is the equivalent excitation inductance of the transformer TX1 and is connected in parallel to the two ends of the primary winding P1.

[0081] Furthermore, in the embodiment of the present application, the working principle of the LLC primary drive circuit 1 is as follows:

[0082] By inputting two complementary 50% duty cycle square wave drive control signals at the primary push-pull drive input ports SW_Q1 and SW_Q2 to drive two MOS tubes, namely MOS tube Q1 and MOS tube Q2, a 50% duty cycle square wave signal is formed at the center point of the two MOS tubes in series to the ground. The signal is applied to the resonant inductor L1, the resonant capacitor C4 and the primary winding P1 of the transformer TX1, and a 50% duty cycle square wave signal is generated on the primary winding P1 of the transformer TX1. The signal will generate a square wave signal with the same polarity at the same end on the target secondary winding of the transformer TX1, and the voltage is the same as the turn ratio of the primary and secondary windings of the transformer.

[0083] For example, when the MOS tube Q1 is turned on and the MOS tube Q2 is turned off, a square wave voltage signal with a voltage amplitude of V1, positive at the top and negative at the bottom is generated at the primary winding P1 end, and the target secondary winding will also generate a voltage with a voltage amplitude proportional to the turns ratio of the original secondary winding, and its direction is also positive at the top and negative at the bottom. At this time, the rectifying MOS tube in the LLC secondary synchronous rectification circuit 2 is switched according to the control signal of the secondary synchronous rectification control circuit 3, so as to achieve the purpose of stabilizing the output while reducing the power consumption.

[0084] The circuit of the embodiment of the present application uses a voltage source V1, a capacitor C1, a drive circuit, a half-bridge circuit, a resonant circuit and a primary winding P1 to build an LLC primary drive circuit, ensuring that the LLC primary drive circuit stably and efficiently converts the input DC voltage into a high-frequency AC voltage, and supplies it to the secondary load after rectification.

[0085] Continue to refer to Figure 3 In the embodiment of the present application, the third driving circuit 11 includes a push-pull driving amplifier circuit U1, a voltage source V2, a resistor R1 and a resistor R2; the input end of the push-pull driving amplifier circuit U1 serves as the input end of the third driving circuit;

[0086] The positive power supply terminal of the push-pull driving amplifier circuit U1 is connected to the positive terminal of the voltage source V2, the negative power supply terminal of the push-pull driving amplifier circuit U1, the negative terminal of the voltage source V2 and one end of the resistor R2 are connected in common, and one end of R2 serves as the second output terminal of the third driving circuit; the output terminal of the push-pull driving amplifier circuit U1 is connected to one end of the resistor R1; the other end of the resistor R1 is connected to the other end of the resistor R2, and the other end of the resistor R2 serves as the first output terminal of the third driving circuit;

[0087] The fourth driving circuit 12 includes a push-pull driving amplifier circuit U2, a voltage source V3, a resistor R3 and a resistor R4; the input end of the push-pull driving amplifier circuit U2 serves as the input end of the fourth driving circuit;

[0088] The positive power supply terminal of the push-pull drive amplifier circuit U2 is connected to the positive terminal of the voltage source V3; the negative power supply terminal of the push-pull drive amplifier circuit U2, the negative terminal of the voltage source V3 and one end of the resistor R4 are connected in common, and one end of R4 serves as the first output terminal of the fourth drive circuit; the output terminal of the push-pull drive amplifier circuit U2 is connected to one end of the resistor R3; the other end of the resistor R3 and the other end of the resistor R4 are connected, and the other end of the resistor R4 serves as the second output terminal of the fourth drive circuit.

[0089] Specifically, in the embodiment of the present application, in the third driving circuit 11, the input end of the push-pull driving amplifier circuit U1 is connected to the external driving signal of the MOS tube Q1, the positive power supply end and the negative power supply end of the push-pull driving amplifier circuit U1 are connected in parallel with the voltage source V2, the output end of the push-pull driving amplifier circuit U1 is connected in series with R1 and then output to the gate of the MOS tube Q1, one end of R2 serves as the second output end of the third driving circuit, and is connected in common with the source of the MOS tube Q1 and the drain of the MOS tube Q2, and the other end of the resistor R2 serves as the first output end of the third driving circuit and is connected to the gate of the MOS tube Q1.

[0090] The voltage source V2 provides the working voltage for the push-pull drive amplifier circuit U1, and the push-pull drive amplifier circuit U1 is used to amplify the power of the pulse signal output by the internal current sampling adjustment circuit with time delay compensation into a control signal to enhance the driving capability of the MOS tube Q1.

[0091] Similarly, the fourth driving circuit 12 includes a push-pull driving amplifier circuit U2, a voltage source V3, a resistor R3 and a resistor R4. Its driving function for the MOS tube Q2 can be realized by referring to the embodiment description of the third driving circuit 11, which is not elaborated in this application.

[0092] The circuit of the embodiment of the present application utilizes a push-pull drive amplifier circuit, a voltage source, and two resistors to construct a drive circuit for MOS tubes Q1 and Q2. By alternately turning on and off the two MOS tubes, the circuit can maintain high efficiency when outputting high and low levels, and has low power consumption and a simple circuit structure.

[0093] Continue to refer to Figure 3 The LLC secondary synchronous rectification circuit 2 includes: a secondary winding S1, a secondary winding S2, a MOS tube Q3, a MOS tube Q4, a capacitor C5, a capacitor C6 and a load resistor R load ; The target secondary winding is the secondary winding S1;

[0094] The same-name end of the secondary winding S1, one end of the voltage divider circuit and the drain of the MOS transistor Q3 are connected together, and the gate of the MOS transistor Q3 is connected to the first driving circuit;

[0095] The source of MOS tube Q3, the source of MOS tube Q4, one end of capacitor C5, one end of capacitor C6 and load resistor R load One end is connected together;

[0096] The opposite end of the secondary winding S1, the same end of the secondary winding S2, the other end of the voltage divider circuit, the other end of the capacitor C5, the other end of the capacitor C6 and the load resistor R load The other end of the

[0097] The opposite-name end of the secondary winding S2 is connected to the drain of the MOS transistor Q4, and the gate of the MOS transistor Q4 is connected to the second driving circuit.

[0098] Specifically, in the embodiment of the present application, the LLC secondary synchronous rectification circuit 2 includes a secondary winding S1, a secondary winding S2, a MOS transistor Q3 and a MOS transistor Q4 for controlling synchronous rectification, and output capacitors C5 and C6 and a load resistor R load , and the target secondary winding can be set to the secondary winding S1. The same-name end of the secondary winding S1 in the transformer TX1 is connected to the drain of the MOS tube Q3, the source of the MOS tube Q3 is connected to the output ground, the opposite-name end of the secondary winding S1 is connected in series with the same-name end of the secondary winding S2, the series connection point leads to a center tap, connected to the positive end of the output Vout, the opposite-name end of the secondary winding S2 is connected to the drain of the MOS tube Q4, the source of the MOS tube Q4 is connected to the output ground, and the capacitor C5, the capacitor C6 and the load resistor Rload are respectively connected in parallel between the positive end of the output Vout and the output ground. Among them, the gate of the MOS tube Q3 is connected to the first drive circuit through the port SW_Q3, and the gate of the MOS tube Q4 is connected to the first drive circuit through the port SW_Q4.

[0099] Usually, the secondary winding S1 and the secondary winding S2 are two windings with the same number of turns. Since the secondary windings S1 and S2 are connected in series, and the middle tap is the output Vout, the induced voltage at the other end of the secondary windings S1 and S2 relative to the middle tap Vout must be a complementary output. Among them, both capacitors C5 and C6 can be polarized capacitors.

[0100] For example, when the primary winding P1 is positive at the top and negative at the bottom, the other end of the secondary winding S1 relative to the output Vout is at a high level, and the secondary winding S2 is at a low level. At this time, the secondary current is output from the same-name end of the S2 winding Vout to the capacitor C5 and the capacitor C6, charging the capacitor and supplying power to the load resistor Rload. Then it flows back to the other end of the secondary winding S2 through the source and drain of the MOS tube Q4 through the output ground. At this time, if the signal input to the input port SW_Q4 is at a high level, it will drive the MOS tube Q4 to turn on, and the loss on the MOS tube is only Rdson*Iout. 2, where Rdson represents the on-resistance between the drain and source of the MOS tube, and Iout is the output current.

[0101] At the same time, the same-name terminal of the secondary winding S1 is positive. At this time, the MOS tube Q3 must remain in the off state, otherwise if the MOS tube Q3 is turned on, the secondary side of the transformer will be short-circuited. Therefore, it can be seen from the above that correctly controlling the drive signal of the MOS tube can achieve the expected reduction of power consumption. At the same time, the drive logic of the synchronous rectification MOS tube is determined by the terminal voltage state of the secondary windings S1 and S2. Therefore, by collecting the terminal voltage of the secondary winding S1 or the secondary winding S2, the drive logic of the synchronous rectification MOS tube can be well determined.

[0102] The circuit of the embodiment of the present application utilizes two sets of secondary windings, two MOS tubes, two capacitors and a load resistor to construct an LLC secondary synchronous rectification circuit. By utilizing the small on-resistance of the rectification MOS tube, the circuit loss during the rectification process can be significantly reduced and the rectification efficiency can be improved. At the same time, the good dynamic response characteristics of the LLC circuit are utilized to further improve the stability and response speed of the entire rectification circuit.

[0103] Figure 4 2 is a schematic diagram of the structure of the secondary synchronous rectification control circuit provided in the embodiment of the present application. Figure 4 As shown, in the embodiment of the present application, the first driving circuit 31 includes a push-pull driving amplifier circuit U6, a voltage source V7, a resistor R14 and a resistor R15; the input end of the push-pull driving amplifier circuit U6 serves as the input end of the first driving circuit;

[0104] The positive power supply terminal of the push-pull driving amplifier circuit U6 is connected to the positive terminal of the voltage source V7, the negative power supply terminal of the push-pull driving amplifier circuit U6, the negative terminal of the voltage source V7 and one end of the resistor R15 are connected in common, the output terminal of the push-pull driving amplifier circuit U6 is connected to one end of the resistor R14, and the other end of the resistor R14 and the other end of the resistor R15 are connected in common to the gate of the MOS tube Q3;

[0105] The second driving circuit 32 includes a push-pull driving amplifier circuit U7, a voltage source V8, a resistor R16 and a resistor R17; the input end of the push-pull driving amplifier circuit U7 serves as the input end of the second driving circuit;

[0106] The positive power supply terminal of the push-pull drive amplifier circuit U7 is connected to the positive terminal of the voltage source V8, the negative power supply terminal of the push-pull drive amplifier circuit U7, the negative terminal of the voltage source V8 and one end of the resistor R17 are connected in common, the output end of the push-pull drive amplifier circuit U7 is connected to one end of the resistor R16, and the other end of the resistor R16 and the other end of the resistor R17 are connected in common to the gate of the MOS tube Q4.

[0107] Similarly, in the embodiment of the present application, the first drive circuit 31 includes a push-pull drive amplifier circuit U6, a voltage source V7, a resistor R14 and a resistor R15, and its drive function for the MOS tube Q3 can also be realized by referring to the description of the embodiment of the third drive circuit 11 mentioned above; at the same time, the second drive circuit 32 includes a push-pull drive amplifier circuit U7, a voltage source V8, a resistor R16 and a resistor R17, and its drive function for the MOS tube Q4 can also be realized by referring to the description of the embodiment of the third drive circuit 11 mentioned above, and the present application will not elaborate on it here.

[0108] The circuit of the embodiment of the present application utilizes a push-pull drive amplifier circuit, a voltage source, and two resistors to construct a drive circuit for MOS tubes Q3 and Q4, so that the circuit can maintain high efficiency when outputting high and low levels, and has low power consumption and a simple circuit structure.

[0109] Continue to refer to Figure 4 As an optional embodiment, the voltage divider circuit 33 includes a resistor R5, a resistor R6 and a resistor R7 connected in sequence; one end of the resistor R5 is connected to the same-name end of the target secondary winding, the other end of the resistor R5 is connected to one end of the resistor R7 through the resistor R6, and the other end of the resistor R7 is connected to the opposite-name end of the target secondary winding.

[0110] As an optional embodiment, the differential sampling circuit 34 includes a resistor R8, a resistor R9, a resistor R10, a resistor R11, a voltage source V5, a bias voltage source V4 and an operational amplifier U3;

[0111] One end of the resistor R8 is connected to one end of the resistor R6, one end of the resistor R9 is connected to the other end of the resistor R6, the other end of the resistor R8 and one end of the resistor R10 are connected to the positive input terminal of the operational amplifier U3, and the other end of the resistor R10 is connected to the bias voltage source V4;

[0112] The other end of the resistor R9 and one end of the resistor R11 are connected in common with the negative input end of the operational amplifier U3, and the other end of the resistor R11 and the output end of the operational amplifier U3 are connected in common with the input end of the Schmitt trigger;

[0113] The voltage source V5 is connected to the positive power supply terminal of the operational amplifier U3, and the negative power supply terminal of the operational amplifier U3 is grounded.

[0114] As an optional embodiment, the comparison trigger circuit 35 includes a resistor R12, a resistor R13, a voltage source V6 for outputting a preset reference voltage, and a comparator U5;

[0115] One end of the resistor R12 is connected to the output end of the Schmitt trigger, the other end of the resistor R12 and one end of the resistor R13 are connected to the positive input end of the comparator U5, and the negative input end of the comparator U5 is connected to the voltage source V6;

[0116] The other end of the resistor R13, the positive output end of the comparator U5 and the input end of the first driving circuit are connected in common, and the negative output end of the comparator U5 is connected to the input end of the second driving circuit.

[0117] Specifically, in an embodiment of the present application, the secondary side synchronous rectification control circuit 3 specifically includes a terminal voltage divider circuit 33 composed of resistors R5, R6, and R7, a differential sampling circuit 34 composed of resistors R8, R9, R10, R11 and a bias voltage source V4, a Schmitt trigger U4, a comparison trigger circuit composed of R12, R13, a voltage source V6 and a comparator U5, and a first drive circuit and a second drive circuit composed of a push-pull drive amplifier circuit U6, a push-pull drive amplifier circuit U7 and its peripheral circuits.

[0118] In an embodiment of the present application, S+ and S- are the two ends of the secondary winding S1, wherein S+ is the opposite end of the secondary winding S1, and S- is the same end of the secondary winding S1. The three resistors R5, R6, and R7 are connected in series, the upper end of the resistor R5 is connected to the port S+, and the lower end of the resistor R7 is connected to the port S-; one end of the resistor R9 is connected to the upper end of the resistor R6, and the other end is connected to the negative input terminal of the operational amplifier U3; one end of the resistor R8 is connected to the upper end of the resistor R7, and the other end is connected to the positive input terminal of the operational amplifier U3.

[0119] The lower end of the bias voltage source V4 is grounded, and the upper end is connected in series with resistor R10 and then connected to the positive input terminal of the operational amplifier U3; the resistor R11 is connected between the output terminal and the negative input terminal of the operational amplifier U3; the output terminal of the operational amplifier U3 is connected to the input terminal of the Schmitt trigger U4, and the output terminal of the Schmitt trigger U4 is connected in series with resistor R12 and then connected to the positive input terminal of the comparator U5; the lower end of the voltage source V6 is grounded, and the upper end is connected to the negative input terminal of the comparator U5; R13 is connected between the positive input terminal and the positive output terminal of the comparator U5.

[0120] The positive output end of the comparator U5 is connected to the input end of the push-pull drive amplifier circuit U6. The positive power supply end and the negative power supply end of the push-pull drive amplifier circuit U6 are connected in parallel to the two ends of the voltage source V7. The output end of the push-pull drive amplifier circuit U6 is connected to the gate of the MOS tube Q3 after being connected in series with the resistor R14. The resistor R15 is also connected between the gate of the MOS tube Q3 and the negative end of the voltage source V7.

[0121] The inverting output terminal of the comparator U5 is connected to the input terminal of the push-pull drive amplifier circuit U7. The positive power supply terminal and the negative power supply terminal of the push-pull drive amplifier circuit U7 are connected in parallel to the two ends of the voltage source V8. The output terminal of the push-pull drive amplifier circuit U7 is connected to the gate of the MOS tube Q4 after being connected in series with the resistor R16. The resistor R17 is between the gate of the MOS tube Q4 and the negative terminal of the voltage source V8.

[0122] In the embodiments of the present application, the corresponding working principle can be described as follows:

[0123] When the power supply is working, the voltage across the secondary winding S1 should be a square wave signal with a duty cycle of 50%, with 0 level as the center point, and equal positive and negative voltages. When the port S+ is at a high level relative to the port S-, the secondary rectifier current loop should be from S+ to the output Vout, passing through the load resistor R load Then it returns to port S- through MOS tube Q3, that is, the same-name terminal of secondary winding S1. At this time, secondary winding S2 is in reverse bias cut-off state. On the contrary, the secondary rectifier current loop is S+ to output Vout, passing through load resistor R loa d and then returns to the opposite end of the secondary winding S2 through the MOS tube Q4. At this time, the secondary winding S1 is in a reverse biased cut-off state.

[0124] Since the driving signals of the MOS tubes Q1 and Q2 in the LLC primary driving circuit 1 are complementary 50% duty cycle square wave signals, it is obvious that after ignoring the dead time, the two secondary windings S1 and S2 of the secondary rectifier circuit and the MOS tubes Q3 and Q4 should be in a complementary 50% duty cycle working state. Therefore, as long as at a certain moment, the secondary winding S1 or S2 presents a positive voltage relative to the S+ terminal, the winding forms an output current output state. Correspondingly, the MOS tube connected in series with the winding should be in an open state at this time, and the other MOS tube must be in a complementary closed state. Therefore, it is only necessary to detect the level state of any one of the secondary windings S1 and S2 in real time, and the driving logic state of the two synchronous rectifier MOS tubes at this time can be determined according to the winding level state.

[0125] For example, when it is detected that the voltage of the port S+ at both ends of the secondary winding S1 is positive relative to the port S-, the driving signal logic is that the MOS tube Q3 is turned on and the MOS tube Q4 is turned off. On the contrary, the MOS tube Q3 is turned off and the MOS tube Q4 is turned on.

[0126] More specifically, by detecting the voltage state of S+ and S- at both ends of the secondary winding S1, the driving logic of the MOS tube is changed according to the voltage state. The voltage divider circuit 33 divides the voltage at both ends of the secondary winding S1 to reduce the voltage amplitude and inputs it into the post-stage differential sampling circuit 34. The differential sampling circuit 34 differentially amplifies the target voltage sampled at both ends of the resistor R6, and superimposes a V4 DC bias. The function of the DC bias is to superimpose a DC level while the differential operational amplifier samples the winding end voltage, so that the original positive and negative levels of the winding are converted into a positive level square wave signal with a midpoint level of V4; the function of the Schmitt trigger U4 is to prevent the subsequent comparison trigger circuit 35 from being falsely triggered due to the winding level oscillation caused by parasitic parameters during the dead time. The comparison trigger circuit 35 compares the voltage after differential amplification and biasing and then anti-interference through the Schmitt trigger with the reference voltage provided by V6.

[0127] Among them, the reference voltage provided by V6 can usually be set to the output voltage Vout divided by the voltage division coefficient of the voltage division circuit 33 and the amplification coefficient of the differential sampling circuit 34, and then multiplied by 0.7. Therefore, when the S+ port of the secondary winding S1 is at a high level relative to the S- port, the output level of the operational amplifier U3 is higher than the reference voltage provided by the voltage source V6. At this time, the positive output end of the comparator U5 outputs a high level, which is output to the subsequent push-pull drive amplifier circuit U6 to drive the MOS tube Q3 to turn on. Among them, the resistors R13 and R12 form a hysteresis comparison circuit, which is conducive to preventing the comparison trigger circuit 35 from being triggered incorrectly due to the interference level. At the same time, the reverse output end of the comparator U5 outputs a low level to the subsequent push-pull drive amplifier circuit U7, so that the MOS tube Q4 remains in the off state.

[0128] When the voltage at the positive input terminal of the comparator U5 is lower than the reference voltage provided by the voltage source V6, a low level will be generated at the positive output terminal of the comparator U5 to the subsequent push-pull drive amplifier circuit U6, while the reverse output terminal will output a high level to the subsequent push-pull drive amplifier circuit U7. Correspondingly, the MOS tube Q3 is turned off and the MOS tube Q4 remains on. In this way, the on-off logic of the rectifier MOS tube is judged by the level state of the secondary winding, thereby realizing the normal operation of the synchronous rectification circuit. At the same time, the traditional working method of collecting the VDS voltage to judge the MOS tube drive logic is abandoned, thereby completely avoiding the duty cycle loss problem caused by the traditional method, and effectively improving the efficiency of the LLC switching power supply.

[0129] It should be understood that expressions such as "including" and "may include" that may be used in the present application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In the present application, terms such as "including" and / or "having" may be interpreted as indicating specific characteristics, numbers, operations, constituent elements, components, or combinations thereof, but may not be interpreted as excluding the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0130] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An LLC topology secondary side synchronous rectification control circuit, characterized in that: include: LLC primary side driving circuit, LLC secondary side synchronous rectification circuit and secondary side synchronous rectification control circuit; The secondary side synchronous rectification control circuit is connected to the LLC secondary side synchronous rectification circuit; The secondary synchronous rectification control circuit is constructed based on a differential sampling circuit, and is used to sample the rectified voltage of the target secondary winding in the LLC secondary synchronous rectification circuit when the LLC primary driving circuit is running, and control the on and off of the MOS tube in the LLC secondary synchronous rectification circuit based on the rectified voltage.

2. The LLC topology secondary side synchronous rectification control circuit according to claim 1, characterized in that: The secondary side synchronous rectification control circuit comprises a first driving circuit, a second driving circuit, a voltage dividing circuit, a differential sampling circuit, a Schmitt trigger and a comparison trigger circuit which are connected in sequence; The first output terminal of the comparison trigger circuit is connected to the first driving circuit, and the second output terminal of the comparison trigger circuit is connected to the second driving circuit; The voltage divider circuit is connected in parallel to the two ends of the target secondary winding, and is used to divide the rectified voltage at the two ends of the target secondary winding; The differential sampling circuit is used to collect the target divided voltage on the voltage divider circuit for differential amplification and bias processing; The Schmitt trigger is used to perform signal anti-interference processing on the voltage output by the differential sampling circuit to prevent the comparison trigger circuit from being falsely triggered; The comparison trigger circuit is used to compare the voltage output by the Schmitt trigger with a preset reference voltage, and drive the MOS tube to be turned on and off through the first drive circuit and the second drive circuit based on the comparison result.

3. The LLC topology secondary side synchronous rectification control circuit according to claim 2, characterized in that: The LLC secondary synchronous rectification circuit includes: a secondary winding S1, a secondary winding S2, a MOS transistor Q3, a MOS transistor Q4, a capacitor C5, a capacitor C6 and a load resistor R load ; The target secondary winding is the secondary winding S1; The same-name end of the secondary winding S1, one end of the voltage divider circuit and the drain of the MOS transistor Q3 are connected together, and the gate of the MOS transistor Q3 is connected to the first driving circuit; The source of the MOS transistor Q3, the source of the MOS transistor Q4, one end of the capacitor C5, one end of the capacitor C6 and the load resistor R load One end is connected together; The opposite-name end of the secondary winding S1, the same-name end of the secondary winding S2, the other end of the voltage divider circuit, the other end of the capacitor C5, the other end of the capacitor C6 and the load resistor R load The other end of the The opposite-name end of the secondary winding S2 is connected to the drain of the MOS transistor Q4 , and the gate of the MOS transistor Q4 is connected to the second driving circuit.

4. The LLC topology secondary side synchronous rectification control circuit according to claim 3, characterized in that: The first driving circuit includes a push-pull driving amplifier circuit U6, a voltage source V7, a resistor R14 and a resistor R15; the input end of the push-pull driving amplifier circuit U6 serves as the input end of the first driving circuit; The positive power supply terminal of the push-pull drive amplifier circuit U6 is connected to the positive terminal of the voltage source V7, the negative power supply terminal of the push-pull drive amplifier circuit U6, the negative terminal of the voltage source V7 and one end of the resistor R15 are connected in common, the output end of the push-pull drive amplifier circuit U6 is connected to one end of the resistor R14, and the other end of the resistor R14 and the other end of the resistor R15 are connected in common to the gate of the MOS tube Q3; The second driving circuit includes a push-pull driving amplifier circuit U7, a voltage source V8, a resistor R16 and a resistor R17; the input end of the push-pull driving amplifier circuit U7 serves as the input end of the second driving circuit; The positive power supply terminal of the push-pull drive amplifier circuit U7 is connected to the positive terminal of the voltage source V8, the negative power supply terminal of the push-pull drive amplifier circuit U7, the negative terminal of the voltage source V8 and one end of the resistor R17 are connected in common, the output end of the push-pull drive amplifier circuit U7 is connected to one end of the resistor R16, and the other end of the resistor R16 and the other end of the resistor R17 are connected in common to the gate of the MOS tube Q4.

5. The LLC topology secondary side synchronous rectification control circuit according to claim 2, characterized in that: The voltage divider circuit includes a resistor R5, a resistor R6 and a resistor R7 connected in sequence; one end of the resistor R5 is connected to the same-name end of the target secondary winding, the other end of the resistor R5 is connected to one end of the resistor R7 through the resistor R6, and the other end of the resistor R7 is connected to the opposite-name end of the target secondary winding.

6. The LLC topology secondary side synchronous rectification control circuit according to claim 5, characterized in that: The differential sampling circuit includes a resistor R8, a resistor R9, a resistor R10, a resistor R11, a voltage source V5, a bias voltage source V4 and an operational amplifier U3; One end of the resistor R8 is connected to one end of the resistor R6, one end of the resistor R9 is connected to the other end of the resistor R6, the other end of the resistor R8 and one end of the resistor R10 are connected to the positive input end of the operational amplifier U3, and the other end of the resistor R10 is connected to the bias voltage source V4; The other end of the resistor R9 and one end of the resistor R11 are connected to the negative input end of the operational amplifier U3, and the other end of the resistor R11 and the output end of the operational amplifier U3 are connected to the input end of the Schmitt trigger; The voltage source V5 is connected to the positive power supply terminal of the operational amplifier U3, and the negative power supply terminal of the operational amplifier U3 is grounded.

7. The LLC topology secondary side synchronous rectification control circuit according to claim 3, characterized in that: The comparison trigger circuit includes a resistor R12, a resistor R13, a voltage source V6 for outputting the preset reference voltage, and a comparator U5; One end of the resistor R12 is connected to the output end of the Schmitt trigger, the other end of the resistor R12 and one end of the resistor R13 are connected to the positive input end of the comparator U5, and the negative input end of the comparator U5 is connected to the voltage source V6; The other end of the resistor R13, the positive output end of the comparator U5 and the input end of the first driving circuit are connected in common, and the negative output end of the comparator U5 is connected to the input end of the second driving circuit.

8. The LLC topology secondary side synchronous rectification control circuit according to any one of claims 1 to 7, characterized in that: The LLC primary drive circuit includes a voltage source V1, a capacitor C1, a third drive circuit, a fourth drive circuit, a MOS transistor Q1, a capacitor C2, a MOS transistor Q2, a capacitor C3, a resonant circuit and a primary winding P1; One end of the voltage source V1, one end of the capacitor C1, the drain of the MOS transistor Q1, and one end of the capacitor C2 are connected together, and the other end of the voltage source V1, the other end of the capacitor C1, the second output end of the fourth drive circuit, the source of the MOS transistor Q2, and the second input end of the resonant circuit are connected to the ground; The first output end of the third driving circuit is connected to the gate of the MOS transistor Q1; the second output end of the third driving circuit, the source of the MOS transistor Q1, the drain of the MOS transistor Q2, and the first input end of the resonant circuit are connected in common; the first output end of the fourth driving circuit is connected to the gate of the MOS transistor Q2; The first output end of the resonant circuit is connected to the same-name end of the primary winding P1, and the second output end of the resonant circuit is connected to the opposite-name end of the primary winding P1.

9. The LLC topology secondary side synchronous rectification control circuit according to claim 8, characterized in that: The third driving circuit includes a push-pull driving amplifier circuit U1, a voltage source V2, a resistor R1 and a resistor R2; the input end of the push-pull driving amplifier circuit U1 serves as the input end of the third driving circuit; The positive power supply terminal of the push-pull driving amplifier circuit U1 is connected to the positive terminal of the voltage source V2, the negative power supply terminal of the push-pull driving amplifier circuit U1, the negative terminal of the voltage source V2 and one end of the resistor R2 are connected in common, and one end of R2 serves as the second output terminal of the third driving circuit; the output terminal of the push-pull driving amplifier circuit U1 is connected to one end of the resistor R1; the other end of the resistor R1 is connected to the other end of the resistor R2, and the other end of the resistor R2 serves as the first output terminal of the third driving circuit; The fourth driving circuit includes a push-pull driving amplifier circuit U2, a voltage source V3, a resistor R3 and a resistor R4; the input end of the push-pull driving amplifier circuit U2 serves as the input end of the fourth driving circuit; The positive power supply terminal of the push-pull drive amplifier circuit U2 is connected to the positive terminal of the voltage source V3; the negative power supply terminal of the push-pull drive amplifier circuit U2, the negative terminal of the voltage source V3 and one end of the resistor R4 are connected in common, and one end of R4 serves as the first output terminal of the fourth drive circuit; the output terminal of the push-pull drive amplifier circuit U2 is connected to one end of the resistor R3; the other end of the resistor R3 and the other end of the resistor R4 are connected, and the other end of the resistor R4 serves as the second output terminal of the fourth drive circuit.

10. The LLC topology secondary side synchronous rectification control circuit according to claim 8, characterized in that: The resonant circuit includes an inductor L1, an inductor L2 and a capacitor C4; One end of the inductor L1 serves as a first input end of the resonant circuit, the other end of the inductor L1 is connected to one end of the inductor L2, and the other end of the inductor L1 serves as a first output end of the resonant circuit; One end of the capacitor C4 serves as the second input end of the resonant circuit, the other end of the capacitor C4 is connected to the other end of the inductor L2, and the other end of the inductor L2 serves as the second output end of the resonant circuit.

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