Noise elimination circuit suitable for high-voltage driving integrated circuit

Abstract

The invention relates to the technical field of driving circuits, in particular to a noise elimination circuit suitable for a high-voltage driving integrated circuit, which comprises a pulse unit, a level shift unit, a voltage-to-current unit and a current-to-voltage unit, the pulse unit is used for driving the level shift unit to generate a first pulse voltage and a second pulse voltage; the voltage-to-current unit is used for receiving the first pulse voltage and the second pulse voltage and converting the first pulse voltage and the second pulse voltage into first pulse current and second pulse current respectively; the current-to-voltage unit is used for receiving the first pulse current and the second pulse current and respectively converting the first pulse current and the second pulse current into a first driving voltage and a second driving voltage to drive the RS trigger; the problems of low efficiency and serious time delay of filtering dVs / dt noise and other types of noise at present are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of drive circuits, in particular to a noise elimination circuit suitable for high-voltage drive integrated circuits. Background Art

[0002] High-voltage driver integrated circuits (HVIC or high-side driver circuits) are usually used to drive semiconductor power components (such as MOS tubes, IGBTs, etc.) connected in half-bridges, and are integrated into intelligent power modules (IPMs, Intelligent Power Modules), making intelligent power modules suitable for frequency converters and various inverter power supplies for driving motors. They are ideal power electronic devices in the fields of variable frequency speed regulation, metallurgical machinery, electric traction, servo drive, and variable frequency home appliances. The input end of the HVIC receives control signals from microcomputers, etc., and the output is used to drive the high-side power devices and low-side power devices in the half-bridge circuit.

[0003] During the operation of the HVIC, only one of the SET level signal and the RESET level signal of the pulse circuit is a high level signal, and the other is a low level signal. The high level will continuously shift between the SET level signal and the RESET level signal, thereby controlling the two MOS tubes to be turned on or off respectively, thereby driving the RS trigger to generate the output signal of the HVIC; however, during the process of the MOS tube switching from on to off (i.e., high level to low level), if the other MOS tube cannot be turned on in time, the high-side floating ground signal VS (i.e., VS pin) in the HVIC will suddenly change, generating very high dVs / dt noise, and due to the existence of the parasitic capacitance of the MOS tube, noise current (I=C*dVs / dt) is generated on both sides of the pulse circuit SET and RESET at the same time, causing the two MOS tubes to appear low level at the same time, thereby causing the RS trigger to be triggered incorrectly and the HVIC to fail.

[0004] At present, the commonly used methods for filtering out dVs / dt noise are: first, using a filter to filter out the noise, but this increases the delay of the circuit; second, the pulse circuit SET and RESET are interlocked to avoid low or high levels at the same time, but the circuit is complex and the interlock duration is uncertain, which greatly affects the working efficiency of HVIC. Therefore, there is an urgent need for a noise elimination circuit suitable for high-voltage drive integrated circuits that can efficiently filter out dVs / dt noise and take into account filtering out other types of noise. Summary of the invention

[0005] In view of the above defects, the purpose of the present invention is to provide a noise elimination circuit suitable for high-voltage driver integrated circuits, which solves the current problems of low efficiency and severe delay in filtering out dVs / dt noise and other types of noise.

[0006] To achieve this object, the present invention adopts the following technical solutions:

[0007] A noise elimination circuit suitable for a high-voltage driving integrated circuit comprises a pulse unit, a level shift unit, a voltage-to-current unit and a current-to-voltage unit; a SET terminal and a RESET terminal of the pulse unit are electrically connected to a first input terminal and a second input terminal of the level shift unit, respectively; a first output terminal and a second output terminal of the level shift unit are electrically connected to a first input terminal and a second input terminal of the voltage-to-current unit, respectively; a first output terminal and a second output terminal of the voltage-to-current unit are electrically connected to a first input terminal and a second input terminal of the current-to-voltage unit, respectively; a first output terminal and a second output terminal of the current-to-voltage unit are electrically connected to an R terminal and an S terminal of an RS trigger, respectively;

[0008] The pulse unit is used to drive the level shift unit to generate a first pulse voltage and a second pulse voltage;

[0009] The voltage-to-current unit is used to receive the first pulse voltage and the second pulse voltage, and convert them into a first pulse current and a second pulse current respectively;

[0010] The current-to-voltage unit is used to receive the first pulse current and the second pulse current, and convert them into a first driving voltage and a second driving voltage respectively to drive the RS trigger.

[0011] Furthermore, the voltage-to-current unit has a current subtraction function, which is used to cancel out the noise current generated by the first pulse voltage and the noise current generated by the second pulse voltage when noise is generated;

[0012] The generation time of the first driving voltage is negatively correlated with the magnitude of the first pulse current, and the generation time of the second driving voltage is negatively correlated with the magnitude of the second pulse current.

[0013] Further, the voltage-to-current unit includes MOS transistor PM1, MOS transistor PM2, MOS transistor PM3, MOS transistor PM4, MOS transistor NM1, MOS transistor NM2, MOS transistor NM3 and MOS transistor NM4; the gate of the MOS transistor PM1 is used as the first input end of the voltage-to-current unit, the gate of the MOS transistor PM3 is used as the second input end of the voltage-to-current unit, the drain of the MOS transistor PM2 is used as the first output end of the voltage-to-current unit, and the drain of the MOS transistor PM3 is used as the second output end of the voltage-to-current unit;

[0014] The gate of the MOS transistor PM1 is electrically connected to the gate of the MOS transistor PM2, the gate of the MOS transistor PM3 is electrically connected to the gate of the MOS transistor PM4, the source of the MOS transistor PM1, the source of the MOS transistor PM2, the source of the MOS transistor PM3 and the source of the MOS transistor PM4 are all connected to the power supply VCCA terminal, the drain of the MOS transistor PM1 is electrically connected to the drain of the MOS transistor NM1, the drain of the MOS transistor PM4 is electrically connected to the drain of the MOS transistor NM4, the drain of the MOS transistor PM2, the gate of the MOS transistor NM4 and the drain of the MOS transistor NM3 are all electrically connected to the gate of the MOS transistor NM3, the drain of the MOS transistor PM3, the gate of the MOS transistor NM1 and the drain of the MOS transistor NM2 are all electrically connected to the gate of the MOS transistor NM2, and the source of the MOS transistor NM1, the source of the MOS transistor NM2, the source of the MOS transistor NM3 and the source of the MOS transistor NM4 are all connected to the power supply VS terminal.

[0015] Further, the current-to-voltage unit includes a first voltage generation control circuit, a second voltage generation control circuit, a resistor R4, a resistor R5, a MOS tube NM5 and a MOS tube NM6; the input end of the first voltage generation control circuit is used as the first input end of the current-to-voltage unit, the input end of the second voltage generation control circuit is used as the second input end of the current-to-voltage unit, the drain of the MOS tube NM5 is used as the first output end of the current-to-voltage unit, and the drain of the MOS tube NM6 is used as the second output end of the current-to-voltage unit;

[0016] The output end of the first voltage generation control circuit is electrically connected to the gate of the MOS tube NM5, one end of the resistor R4 is electrically connected to the drain of the MOS tube NM5, the output end of the second voltage generation control circuit is electrically connected to the gate of the MOS tube NM6, one end of the resistor R5 is electrically connected to the drain of the MOS tube NM6, the other end of the resistor R4 and the other end of the resistor R5 are both connected to the power supply VCCA terminal, the ground terminal of the first voltage generation control circuit, the ground terminal of the second voltage generation control circuit, the source of the MOS tube NM5 and the source of the MOS tube NM6 are all connected to the power supply VS terminal;

[0017] The first voltage generation control circuit is used to receive the first pulse current and generate a first drive signal; the generation time of the first drive signal is negatively correlated with the magnitude of the first pulse current; when the MOS tube NM5 receives the first drive signal, it generates the first drive voltage;

[0018] The second voltage generation control circuit is used to receive the second pulse current and generate a second drive signal; the generation time of the second drive signal is negatively correlated with the magnitude of the second pulse current; when the MOS tube NM6 receives the second drive signal, it generates the second drive voltage.

[0019] Further, the level shift unit includes a resistor R1, a resistor R6, an LDMOS tube Q1 and an LDMOS tube Q2; the gate of the LDMOS tube Q1 is used as the SET terminal of the level shift unit, the gate of the LDMOS tube Q2 is used as the RESET terminal of the level shift unit, the drain of the LDMOS tube Q1 is used as the first output terminal of the level shift unit, and the drain of the LDMOS tube Q2 is used as the second output terminal of the level shift unit;

[0020] The drain of the LDMOS tube Q1 is electrically connected to one end of the resistor R1, the drain of the LDMOS tube Q2 is electrically connected to one end of the resistor R6, the other end of the resistor R1 and the other end of the resistor R6 are both connected to the power supply VCCA terminal, and the source of the LDMOS tube Q1 and the source of the LDMOS tube Q2 are both connected to the power supply VS terminal.

[0021] Further, the first voltage generation control circuit includes a resistor R3 and a capacitor C1; one end of the resistor R3 is used as an input end of the first voltage generation control circuit, the other end of the resistor R3 is used as an output end of the first voltage generation control circuit, and one end of the capacitor C1 is used as a ground end of the first voltage generation control circuit;

[0022] The other end of the resistor R3 is electrically connected to the other end of the capacitor C1.

[0023] Further, the second voltage generation control circuit includes a resistor R2 and a capacitor C2; one end of the resistor R2 is used as an input end of the second voltage generation control circuit, the other end of the resistor R2 is used as an output end of the second voltage generation control circuit, and one end of the capacitor C2 is used as a ground end of the second voltage generation control circuit;

[0024] The other end of the resistor R2 is electrically connected to the other end of the capacitor C2.

[0025] Furthermore, the resistance values ​​of the resistor R2 and the resistor R3 are 1-5KΩ, and the capacitance values ​​of the capacitor C1 and the capacitor C2 are 0.2-1μF.

[0026] The technical solution provided by the present invention may include the following beneficial effects: if the level shift unit generates dVs / dt noise or other noise when driven by the pulse unit, the pulse voltage generated by the level shift unit can be converted into current and then converted back into voltage, and the noise energy is consumed by the conversion process. Then, the voltage is re-established to be shaped and filtered, and an accurate driving voltage is obtained to drive the RS trigger, thereby avoiding false triggering of the RS trigger and causing failure of the HVIC. This makes the noise elimination circuit not only suitable for filtering out dVs / dt noise, but other noises can also be filtered out through the conversion-reconstruction mechanism, with a wider range of applications, a simple circuit, and a short delay time. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 The circuit schematic diagram of a noise elimination circuit applicable to a high-voltage driving integrated circuit according to one embodiment of the present invention.

[0028] Among them: pulse unit 1, level shift unit 2, voltage-to-current unit 3, current-to-voltage unit 4, RS trigger 5, MOS tube PM1, MOS tube PM2, MOS tube PM3, MOS tube PM4, MOS tube NM1, MOS tube NM2, MOS tube NM3, MOS tube NM4, first voltage generation control circuit 41, second voltage generation control circuit 42, resistor R4, resistor R5, MOS tube NM5, MOS tube NM6, resistor R1, resistor R6, LDMOS tube Q1, LDMOS tube Q2, resistor R3, capacitor C1, resistor R2, capacitor C2. DETAILED DESCRIPTION

[0029] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0030] In the description of the embodiments of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0031] In the description of the embodiments of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

[0032] Combine the following Figure 1 , describes a noise elimination circuit suitable for a high-voltage driving integrated circuit according to an embodiment of the present invention.

[0033] A noise elimination circuit suitable for a high-voltage driving integrated circuit comprises a pulse unit 1, a level shift unit 2, a voltage-to-current unit 3 and a current-to-voltage unit 4; a SET terminal and a RESET terminal of the pulse unit 1 are electrically connected to a first input terminal and a second input terminal of the level shift unit 2, respectively; a first output terminal and a second output terminal of the level shift unit 2 are electrically connected to a first input terminal and a second input terminal of the voltage-to-current unit 3, respectively; a first output terminal and a second output terminal of the voltage-to-current unit 3 are electrically connected to a first input terminal and a second input terminal of a current-to-voltage unit 4, respectively; a first output terminal and a second output terminal of the current-to-voltage unit 4 are electrically connected to an R terminal and an S terminal of an RS trigger 5, respectively;

[0034] The pulse unit 1 is used to drive the level shift unit 2 to generate a first pulse voltage and a second pulse voltage;

[0035] The voltage-to-current unit 3 is used to receive the first pulse voltage and the second pulse voltage, and convert them into the first pulse current and the second pulse current respectively;

[0036] The current-to-voltage unit 4 is used to receive the first pulse current and the second pulse current, and convert them into the first driving voltage and the second driving voltage respectively to drive the RS trigger 5 .

[0037] The present invention proposes a preferred embodiment of a noise elimination circuit suitable for a high voltage driver integrated circuit, such as Figure 1As shown, when the level shift unit 2 generates dVs / dt noise or other noise under the drive of the pulse unit 1, the pulse voltage generated by the level shift unit 2 (i.e., the first pulse voltage and the second pulse voltage, respectively SET and RESET in the figure) can be converted into a current and then converted back into a voltage, and the noise energy is consumed by the conversion process. Then, the voltage is reshaped and filtered by re-establishing the voltage to obtain an accurate driving voltage (i.e., the first driving voltage and the second driving voltage, respectively R and S in the figure) to drive the RS trigger 5, so as to avoid false triggering of the RS trigger and cause failure of the HVIC, so that the noise elimination circuit is not only suitable for filtering out dVs / dt noise, but other noises can also be filtered out through the conversion-reconstruction mechanism, with a wider range of applications, a simple circuit and a short delay time.

[0038] Furthermore, the voltage-to-current unit 3 has a current subtraction function, which is used to cancel out the noise current generated by the first pulse voltage and the noise current generated by the second pulse voltage when noise is generated;

[0039] The generation time of the first driving voltage is negatively correlated with the magnitude of the first pulse current, and the generation time of the second driving voltage is negatively correlated with the magnitude of the second pulse current.

[0040] In this embodiment, in order to ensure that if there is dVs / dt noise at the power supply VS end during the process of converting the pulse voltage into current, it can be effectively reduced, a current subtraction function is provided in the voltage-to-current unit 3. When noise is generated, the noise current generated by the first pulse voltage and the noise current generated by the second pulse voltage cancel each other out, thereby achieving noise filtering (mainly common-mode noise caused by dVs / dt noise). It should be noted that when there is dVs / dt noise, the first pulse voltage and the second pulse voltage will contain a transient voltage drop caused by the dVs / dt noise, so that noise current appears in the process of converting voltage into current.

[0041] The current-to-voltage unit 4 is mainly used to filter out differential-mode noise caused by dVs / dt noise (for example, the voltage-to-current unit 3 may cause incomplete noise current cancellation due to process differences in the components, resulting in residual differential-mode noise) and other types of noise; based on the fact that residual noise may cause fluctuations in the first pulse current or the second pulse current, the current-to-voltage unit 4, in order to ensure that the first drive voltage and the second drive voltage can still be generated normally and drive the RS trigger 5, makes the generation time of the first drive voltage (or the second drive voltage) negatively correlated with the size of the first pulse current (or the second pulse current), so that the fluctuation of the first pulse current or the second pulse current only affects the drive signal generation time, and does not affect the normal drive logic, thereby using different drive signal generation times to filter out residual noise, and the adaptive noise range is wide. For example, if there is a certain noise that severely reduces the first pulse current (or the second pulse current), the drive signal generation time is long, or even the drive is turned off, thereby reliably eliminating the differential-mode noise caused by dVs / dt noise, and can also automatically adapt the protection measures for the subsequent drive circuit according to the type of noise and its noise severity.

[0042] Further, the voltage-to-current unit 3 includes MOS transistors PM1, PM2, PM3, PM4, NM1, NM2, NM3 and NM4; the gate of MOS transistor PM1 is used as the first input terminal of the voltage-to-current unit 3, the gate of MOS transistor PM3 is used as the second input terminal of the voltage-to-current unit 3, the drain of MOS transistor PM2 is used as the first output terminal of the voltage-to-current unit 3, and the drain of MOS transistor PM3 is used as the second output terminal of the voltage-to-current unit 3;

[0043] The gate of the MOS transistor PM1 is electrically connected to the gate of the MOS transistor PM2, the gate of the MOS transistor PM3 is electrically connected to the gate of the MOS transistor PM4, the source of the MOS transistor PM1, the source of the MOS transistor PM2, the source of the MOS transistor PM3 and the source of the MOS transistor PM4 are all connected to the power supply VCCA terminal, the drain of the MOS transistor PM1 is electrically connected to the drain of the MOS transistor NM1, the drain of the MOS transistor PM4 is electrically connected to the drain of the MOS transistor NM4, the drain of the MOS transistor PM2, the gate of the MOS transistor NM4 and the drain of the MOS transistor NM3 are all electrically connected to the gate of the MOS transistor NM3, the drain of the MOS transistor PM3, the gate of the MOS transistor NM1 and the drain of the MOS transistor NM2 are all electrically connected to the gate of the MOS transistor NM2, and the source of the MOS transistor NM1, the source of the MOS transistor NM2, the source of the MOS transistor NM3 and the source of the MOS transistor NM4 are all connected to the power supply VS terminal.

[0044] In this embodiment, the voltage-to-current conversion unit 3 with a current subtraction function is formed by MOS transistors PM1, PM2, PM3, PM4, NM1, NM2, NM3 and NM4; wherein the voltage-to-current conversion of the voltage-to-current conversion unit 3 is performed by turning on the MOS transistors according to the first pulse voltage and the second pulse voltage. Figure 1 The first pulse current and the second pulse current are generated at point A and point B respectively.

[0045] The dVs / dt noise or other types of noise filtering mechanism of the voltage-to-current unit 3 is: taking point A as an example, when a transient voltage drop is introduced due to noise, the voltage drop on the SET side will turn on the MOS transistor PM1, and introduce a noise current I1 under the action of the current mirror composed of the MOS transistors NM1 and NM2; the voltage drop on the RESET side will turn on the MOS transistor PM3, generating a noise current I3; the noise currents I1 and I3 are offset against each other, that is, the current subtraction function, when noise is generated, the noise current (I1) generated by the first pulse voltage and the noise current (I2) generated by the second pulse voltage offset each other, thereby filtering the noise.

[0046] Further, the current-to-voltage unit 4 includes a first voltage generation control circuit 41, a second voltage generation control circuit 42, a resistor R4, a resistor R5, a MOS tube NM5 and a MOS tube NM6; the input end of the first voltage generation control circuit 41 is used as the first input end of the current-to-voltage unit 4, the input end of the second voltage generation control circuit 42 is used as the second input end of the current-to-voltage unit 4, the drain of the MOS tube NM5 is used as the first output end of the current-to-voltage unit 4, and the drain of the MOS tube NM6 is used as the second output end of the current-to-voltage unit 4;

[0047] The output end of the first voltage generation control circuit 41 is electrically connected to the gate of the MOS transistor NM5, one end of the resistor R4 is electrically connected to the drain of the MOS transistor NM5, the output end of the second voltage generation control circuit 42 is electrically connected to the gate of the MOS transistor NM6, one end of the resistor R5 is electrically connected to the drain of the MOS transistor NM6, the other end of the resistor R4 and the other end of the resistor R5 are both connected to the power supply VCCA terminal, the ground terminal of the first voltage generation control circuit 41, the ground terminal of the second voltage generation control circuit 42, the source of the MOS transistor NM5 and the source of the MOS transistor NM6 are all connected to the power supply VS terminal;

[0048] The first voltage generation control circuit 41 is used to receive the first pulse current and generate a first drive signal; the generation time of the first drive signal is negatively correlated with the magnitude of the first pulse current; when the MOS tube NM5 receives the first drive signal, it generates a first drive voltage;

[0049] The second voltage generation control circuit 42 is used to receive the second pulse current and generate a second drive signal; the generation time of the second drive signal is negatively correlated with the magnitude of the second pulse current; when the MOS tube NM6 receives the second drive signal, it generates a second drive voltage.

[0050] In this embodiment, the current-to-voltage unit 4 converts current into voltage by MOS tube NM5 and MOS tube NM6, that is, when the MOS tube is turned on, the first drive voltage (or the second drive voltage) is at a high level, and when the MOS tube is turned off, the first drive voltage (or the second drive voltage) is at a low level; the generation time of the first drive voltage (or the second drive voltage) is controlled by the first voltage generation control circuit 41 (or the second voltage generation control circuit 42).

[0051] Further, the level shift unit 2 includes a resistor R1, a resistor R6, an LDMOS transistor Q1 and an LDMOS transistor Q2; the gate of the LDMOS transistor Q1 is used as the SET terminal of the level shift unit 2, the gate of the LDMOS transistor Q2 is used as the RESET terminal of the level shift unit 2, the drain of the LDMOS transistor Q1 is used as the first output terminal of the level shift unit 2, and the drain of the LDMOS transistor Q2 is used as the second output terminal of the level shift unit 2;

[0052] The drain of the LDMOS tube Q1 is electrically connected to one end of the resistor R1, the drain of the LDMOS tube Q2 is electrically connected to one end of the resistor R6, the other end of the resistor R1 and the other end of the resistor R6 are both connected to the power supply VCCA terminal, and the source of the LDMOS tube Q1 and the source of the LDMOS tube Q2 are both connected to the power supply VS terminal.

[0053] In this embodiment, the level shift unit 2 shifts the high level by turning on or off the LDMOS tube Q1 and the LDMOS tube Q2. When there is dVs / dt noise, due to the parasitic capacitance of the LDMOS tube, the dVs / dt noise will generate a transient voltage drop on the resistor R1 and the resistor R6, thereby generating noise current (such as I1 and I3); therefore, the switch tube preferably uses an LDMOS tube, which has low distortion, high efficiency and smaller parasitic capacitance than ordinary MOS tubes, and is less affected by dVs / dt noise, or even not affected by dVs / dt noise.

[0054] Further, the first voltage generation control circuit 41 includes a resistor R3 and a capacitor C1; one end of the resistor R3 is used as an input end of the first voltage generation control circuit 41, the other end of the resistor R3 is used as an output end of the first voltage generation control circuit 41, and one end of the capacitor C1 is used as a ground end of the first voltage generation control circuit 41;

[0055] The other end of the resistor R3 is electrically connected to the other end of the capacitor C1.

[0056] In this embodiment, the first voltage generation control circuit 41 is preferably an RC charge-discharge circuit to achieve a negative correlation between the generation time of the first drive signal and the magnitude of the first pulse current. The charging time can be determined according to the magnitude of the first pulse current. More importantly, the input terminal of the RC charge-discharge circuit is connected to Figure 1 At point B, when the MOS transistor PM1 or the MOS transistor PM2 is turned on, the potential at point B is approximately half of the power supply voltage (power supply VCCA terminal), which does not affect the on or off state of the MOS transistor NM5, thereby not affecting the normal driving logic. Therefore, the first driving voltage is not affected by the noise current of the voltage-to-current unit 3.

[0057] Further, the second voltage generation control circuit 42 includes a resistor R2 and a capacitor C2; one end of the resistor R2 is used as an input end of the second voltage generation control circuit 42, the other end of the resistor R2 is used as an output end of the second voltage generation control circuit 42, and one end of the capacitor C2 is used as a ground end of the second voltage generation control circuit 42;

[0058] The other end of the resistor R2 is electrically connected to the other end of the capacitor C2.

[0059] In this embodiment, the second voltage generation control circuit 42 is similar to the first voltage generation control circuit 41 .

[0060] Furthermore, the resistance values ​​of the resistor R2 and the resistor R3 are 1-5KΩ, and the capacitance values ​​of the capacitor C1 and the capacitor C2 are 0.2-1μF.

[0061] In this embodiment, because the charging process of the RC circuit can be described by the time constant τ=R*C, where R is the resistance value and C is the capacitance value. The charging process of the capacitor is completed within several time constants, and the specific time is generally 3τ to 5τ. At this time, the capacitor voltage reaches between 95% and 99% of the stable value. For example, when R=1KΩ and C=1μF, τ=1ms, which means that the capacitor voltage reaches 95% to 99% of the stable value within about 3ms to 5ms, so that the MOS tube NM5 or MOS tube NM6 is turned on; so in order to shorten the turn-on time of the MOS tube and improve the working efficiency of the noise elimination circuit, the charging time of the RC circuit needs to be shortened as much as possible; based on this, considering that too large a resistance will affect the power injection capacity, and too large a resistance will pull down the voltage, the resistance is preferably 1-5KΩ, and the capacitance is preferably 0.2-1μF, ensuring that the time constant τ is about 1ms, so that it can be ensured that no matter whether the first pulse current and the second pulse current are large or small, the charging time of the RC circuit can be shortened as much as possible to adapt to various noise conditions.

[0062] Other structures and operations of a noise elimination circuit suitable for a high-voltage driving integrated circuit according to an embodiment of the present invention are known to those skilled in the art and will not be described in detail here.

[0063] In the description of this specification, the description with reference to the terms "embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0064] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A noise elimination circuit suitable for a high voltage driver integrated circuit, characterized in that: It comprises a pulse unit, a level shift unit, a voltage-to-current unit and a current-to-voltage unit; the SET terminal and the RESET terminal of the pulse unit are electrically connected to the first input terminal and the second input terminal of the level shift unit, respectively; the first output terminal and the second output terminal of the level shift unit are electrically connected to the first input terminal and the second input terminal of the voltage-to-current unit, respectively; the first output terminal and the second output terminal of the voltage-to-current unit are electrically connected to the first input terminal and the second input terminal of the current-to-voltage unit, respectively; the first output terminal and the second output terminal of the current-to-voltage unit are electrically connected to the R terminal and the S terminal of the RS trigger, respectively; The pulse unit is used to drive the level shift unit to generate a first pulse voltage and a second pulse voltage; The voltage-to-current unit is used to receive the first pulse voltage and the second pulse voltage, and convert them into a first pulse current and a second pulse current respectively; The current-to-voltage unit is used to receive the first pulse current and the second pulse current, and convert them into a first driving voltage and a second driving voltage respectively to drive the RS trigger.

2. A noise elimination circuit suitable for a high voltage driver integrated circuit according to claim 1, characterized in that: The voltage-to-current unit has a current subtraction function, which is used to cancel out the noise current generated by the first pulse voltage and the noise current generated by the second pulse voltage when noise is generated; The generation time of the first driving voltage is negatively correlated with the magnitude of the first pulse current, and the generation time of the second driving voltage is negatively correlated with the magnitude of the second pulse current.

3. A noise elimination circuit suitable for a high voltage driver integrated circuit according to claim 2, characterized in that: The voltage-to-current unit comprises MOS transistors PM1, PM2, PM3, PM4, NM1, NM2, NM3 and NM4; the gate of the MOS transistor PM1 is used as the first input terminal of the voltage-to-current unit, the gate of the MOS transistor PM3 is used as the second input terminal of the voltage-to-current unit, the drain of the MOS transistor PM2 is used as the first output terminal of the voltage-to-current unit, and the drain of the MOS transistor PM3 is used as the second output terminal of the voltage-to-current unit; The gate of the MOS transistor PM1 is electrically connected to the gate of the MOS transistor PM2, the gate of the MOS transistor PM3 is electrically connected to the gate of the MOS transistor PM4, the source of the MOS transistor PM1, the source of the MOS transistor PM2, the source of the MOS transistor PM3 and the source of the MOS transistor PM4 are all connected to the power supply VCCA terminal, the drain of the MOS transistor PM1 is electrically connected to the drain of the MOS transistor NM1, the drain of the MOS transistor PM4 is electrically connected to the drain of the MOS transistor NM4, the drain of the MOS transistor PM2, the gate of the MOS transistor NM4 and the drain of the MOS transistor NM3 are all electrically connected to the gate of the MOS transistor NM3, the drain of the MOS transistor PM3, the gate of the MOS transistor NM1 and the drain of the MOS transistor NM2 are all electrically connected to the gate of the MOS transistor NM2, and the source of the MOS transistor NM1, the source of the MOS transistor NM2, the source of the MOS transistor NM3 and the source of the MOS transistor NM4 are all connected to the power supply VS terminal.

4. The noise elimination circuit suitable for a high voltage driving integrated circuit according to claim 2, characterized in that: The current-to-voltage unit includes a first voltage generation control circuit, a second voltage generation control circuit, a resistor R4, a resistor R5, a MOS tube NM5 and a MOS tube NM6; the input end of the first voltage generation control circuit is used as the first input end of the current-to-voltage unit, the input end of the second voltage generation control circuit is used as the second input end of the current-to-voltage unit, the drain of the MOS tube NM5 is used as the first output end of the current-to-voltage unit, and the drain of the MOS tube NM6 is used as the second output end of the current-to-voltage unit; The output end of the first voltage generation control circuit is electrically connected to the gate of the MOS tube NM5, one end of the resistor R4 is electrically connected to the drain of the MOS tube NM5, the output end of the second voltage generation control circuit is electrically connected to the gate of the MOS tube NM6, one end of the resistor R5 is electrically connected to the drain of the MOS tube NM6, the other end of the resistor R4 and the other end of the resistor R5 are both connected to the power supply VCCA terminal, the ground terminal of the first voltage generation control circuit, the ground terminal of the second voltage generation control circuit, the source of the MOS tube NM5 and the source of the MOS tube NM6 are all connected to the power supply VS terminal; The first voltage generation control circuit is used to receive the first pulse current and generate a first driving signal; The generation time of the first driving signal is negatively correlated with the magnitude of the first pulse current; when the MOS transistor NM5 receives the first driving signal, it generates the first driving voltage; The second voltage generation control circuit is used to receive the second pulse current and generate a second drive signal; The generation time of the second driving signal is negatively correlated with the magnitude of the second pulse current; when the MOS tube NM6 receives the second driving signal, it generates the second driving voltage.

5. The noise elimination circuit suitable for a high voltage driving integrated circuit according to claim 2, characterized in that: The level shift unit includes a resistor R1, a resistor R6, an LDMOS transistor Q1 and an LDMOS transistor Q2; the gate of the LDMOS transistor Q1 is used as the SET terminal of the level shift unit, the gate of the LDMOS transistor Q2 is used as the RESET terminal of the level shift unit, the drain of the LDMOS transistor Q1 is used as the first output terminal of the level shift unit, and the drain of the LDMOS transistor Q2 is used as the second output terminal of the level shift unit; The drain of the LDMOS tube Q1 is electrically connected to one end of the resistor R1, the drain of the LDMOS tube Q2 is electrically connected to one end of the resistor R6, the other end of the resistor R1 and the other end of the resistor R6 are both connected to the power supply VCCA terminal, and the source of the LDMOS tube Q1 and the source of the LDMOS tube Q2 are both connected to the power supply VS terminal.

6. A noise elimination circuit suitable for a high voltage driver integrated circuit according to claim 4, characterized in that: The first voltage generation control circuit includes a resistor R3 and a capacitor C1; one end of the resistor R3 is used as an input end of the first voltage generation control circuit, the other end of the resistor R3 is used as an output end of the first voltage generation control circuit, and one end of the capacitor C1 is used as a ground end of the first voltage generation control circuit; The other end of the resistor R3 is electrically connected to the other end of the capacitor C1.

7. A noise elimination circuit suitable for a high voltage driving integrated circuit according to claim 6, characterized in that: The second voltage generation control circuit includes a resistor R2 and a capacitor C2; one end of the resistor R2 is used as an input end of the second voltage generation control circuit, the other end of the resistor R2 is used as an output end of the second voltage generation control circuit, and one end of the capacitor C2 is used as a ground end of the second voltage generation control circuit; The other end of the resistor R2 is electrically connected to the other end of the capacitor C2.

8. The noise elimination circuit suitable for a high voltage driving integrated circuit according to claim 7, characterized in that: The resistance values ​​of the resistor R2 and the resistor R3 are 1-5KΩ, and the capacitance values ​​of the capacitor C1 and the capacitor C2 are 0.2-1μF.

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