Digital measurement system channel error automatic calibration method, storage medium and system

Abstract

The invention discloses a digital measurement system channel error automatic calibration method, a storage medium and a system, and aims to automatically calibrate zero drift and multiplying power change errors from the angle of reducing DMS analog measurement channel tool errors. The method comprises the following steps of: firstly, connecting an input end of the DMS with a digital-to-analog converter (DAC), a circuit ground and a reference source Vref respectively, then measuring corresponding output voltages Dos, Dx and Dref of the DMS, and finally obtaining a calibration voltage Ui after error elimination by utilizing a formula # imgabs0 #. The calibration circuit required by the invention is simple in structure, low in cost, suitable for different types of DMS equipment, free of synchronism requirements on a measurement system, low in operation difficulty, capable of calibrating relative errors and absolute errors, high in automation degree, and capable of improving the measurement precision of the DMS on the premise of considering the measurement time; and the working reliability and stability of the measuring equipment are improved.

Description

Technical Field

[0001] The invention belongs to the field of automatic testing, and relates to a channel error measurement and calibration method in digital measurement, in particular to a digital measurement system channel error automatic calibration method, storage medium and system. Background Art

[0002] Reducing the systematic error of a digital measurement system (DMS) is one of the main ways to improve the accuracy of a measurement device. Whether it is for a single component (resistor, capacitor, switch, amplifier, comparator, etc.) or for the entire digital measurement device, the systematic error can be reduced. There are two main commonly used calibration methods:

[0003] (1) Standard source method

[0004] First, according to the measurement range and accuracy requirements of the measurement system, select a standard source with a known accurate value, such as a standard voltage source, a standard current source, etc.; then connect the standard source to the channel to be calibrated of the automatic measurement system; then use the automatic measurement system to measure the standard source and record the measured value; finally, compare the measured value with the accurate value of the standard source to calculate the channel error.

[0005] This method has the following disadvantages:

[0006] a) The standard source itself may have certain errors, which may affect the accuracy of the calibration results;

[0007] b) Different standard sources may be suitable for different measurement ranges and accuracy requirements. It is necessary to select the appropriate standard source according to the specific situation, which increases the cost and complexity;

[0008] c) Finally, for some complex measurement systems, multiple standard sources may be required for calibration, which is a rather cumbersome operation.

[0009] (2) Comparative method

[0010] First, select a reference measurement system with high accuracy and stable performance; then measure the same signal simultaneously with the automatic measurement system to be calibrated and the reference measurement system; finally, compare the measurement results of the two measurement systems and calculate the error of the channel to be calibrated.

[0011] This method has the following disadvantages:

[0012] a) The accuracy and stability of the reference measurement system must be high, otherwise the calibration results will be affected;

[0013] b) Simultaneous measurement requires the synchronization of two measurement systems, which increases the difficulty of operation;

[0014] c) The comparison method can only calibrate relative errors, and its effect on calibrating absolute errors is limited.

[0015] In order to accurately, automatically and efficiently determine the magnitude of the measurement channel error and introduce the correction value into the corresponding circuit, a new method for automatically calibrating the channel error of the digital measurement system is needed. Summary of the invention

[0016] In order to solve the deficiencies of the above-mentioned prior art, the inventors have proposed a digital measurement system (DMS) channel error automatic calibration method, storage medium and system after a new design. From the perspective of reducing the tool error of the DMS analog measurement channel, the present invention designs an automatic calibration and control method for zero drift and magnification change, which improves the measurement accuracy of the DMS while taking into account the measurement time, and improves the reliability and stability of the measuring equipment.

[0017] Specifically, the present invention is achieved as follows:

[0018] A method for automatically calibrating a channel error of a digital measurement system comprises a digital measurement system, wherein the digital measurement system comprises an analog-to-digital converter ADC, a digital-to-analog converter DAC, a power operational amplifier OP1, a common operational amplifier OP2, an instrumentation amplifier IA, a single-pole four-throw relay PD0, a single-pole double-throw relay PD1, a single-pole double-throw relay PD2, a plurality of precision sampling resistors Rx and a load DUT, wherein the single-pole four-throw relay PD0 is used to realize switching of different ranges by switching to different precision sampling resistors Rx; and the digital measurement system realizes switching between a voltage-applied current measurement FVMI mode and a current-applied voltage measurement FIMV mode by controlling the on-off of the single-pole double-throw relay PD1 and the single-pole double-throw relay PD2.

[0019] The method provides a channel error measurement circuit in the digital measurement system, wherein the channel error measurement circuit includes a single-pole relay S1, a single-pole relay S2, a single-pole relay S3 and a reference source Vref; the single-pole relay S1 is used to control whether the input end of the digital measurement system is connected to the analog output end of a digital-to-analog converter DAC, the single-pole relay S2 is used to control whether the input end of the digital measurement system is connected to a circuit ground, the single-pole relay S3 is used to control whether the input end of the digital measurement system is connected to the reference source Vref, and the reference source Vref is used to provide a high-precision reference voltage;

[0020] The method comprises the following steps:

[0021] (1) The controller controls the single-pole relay S1 to be turned on, and the single-pole relay S2 and the single-pole relay S3 to be turned off, so that the input end of the digital measurement system is connected to the analog output end of the digital-to-analog converter DAC. At this time, the output voltage is set to D os ;

[0022] (2) The controller controls the single-pole relay S2 to conduct, disconnects the single-pole relay S1, disconnects the single-pole relay S3, and connects the input end of the digital measurement system to the circuit ground. At this time, the output voltage is set to D x ;

[0023] (3) The controller controls the single-pole relay S3 to conduct, disconnects the single-pole relay S1, disconnects the single-pole relay S2, and connects the input end of the digital measurement system to the reference source Vref. At this time, the output voltage is D ref ;

[0024] (4) Perform the following calculations

[0025]

[0026] Get the calibrated U i Value, where: D = (D x -D os ) / (D ref -D os ), the zero drift voltage U has been eliminated os and the influence of the multiplier k (assuming that U os and k are invariants);

[0027] (5) Control the digital measurement system to work in the applied voltage measurement current FVMI mode and the applied current measurement voltage FIMV mode, control the single-pole four-throw relay PD0 to switch to different ranges, and automatically calibrate the channel errors of different working modes and different ranges.

[0028] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the method for automatically calibrating a channel error of a digital measurement system described in the present invention are implemented.

[0029] The present invention also provides a digital measurement system channel error automatic calibration system, including a digital measurement system and a channel error measurement circuit arranged in the digital measurement system. The digital measurement system includes an analog-to-digital converter ADC, a digital-to-analog converter DAC, a power amplifier OP1, a common amplifier OP2, an instrument amplifier IA, a single-pole four-throw relay PD0, a single-pole double-throw relay PD1, a single-pole double-throw relay PD2, a plurality of precision sampling resistors Rx and a load DUT, wherein the single-pole four-throw relay PD0 is used to switch to different precision sampling resistors Rx to achieve switching of different ranges; the digital measurement system realizes the conversion between the applied voltage measurement current FVMI mode and the applied current measurement voltage FIMV mode by controlling the on and off of the single-pole double-throw relay PD1 and the single-pole double-throw relay PD2. The channel error measurement circuit includes a single-pole relay S1, a single-pole relay S2, a single-pole relay S3 and a reference source Vref; the single-pole relay S1 is used to control whether the input end of the digital measurement system is connected to the analog output end of the digital-to-analog converter DAC, the single-pole relay S2 is used to control whether the input end of the digital measurement system is connected to the circuit ground, the single-pole relay S3 is used to control whether the input end of the digital measurement system is connected to the reference source Vref, and the reference source Vref is used to provide a high-precision reference voltage. It also includes a computer and a controller for controlling the single-pole relay S1, the single-pole relay S2, and the single-pole relay S3, and the controller is connected to the computer through an interface. It also includes a computer-readable storage medium described in the present invention.

[0030] The working principle of the present invention includes:

[0031] If we do not consider the step-wise nature of the transmission characteristics of the test device caused by quantization, the reason why the actual transfer function is different from the ideal transfer function (y = kx) is that there are three systematic error components. Please refer to the attached Figure 1 : Additive error Δa, which is independent of the measured value; Multiplicative error Δm, which is proportional to the measured value x; Nonlinear error Δh, which is determined by the characteristics of each component, i.e., various external factors. Error Δh is rarely corrected alone, because Δh has been partially compensated when correcting Δa and Δm. In addition, due to its uncertainty, a single correction will complicate the DMS structure and reduce the speed. When considering Δa and Δm, the transfer function of DMS is:

[0032] y'=kx+Δa+Δm=k(1+α)x+Δa (1)

[0033] In the formula, α = Δm / (kx) - multiplicative relative error.

[0034] In actual test systems, the multiplier factor k often changes with temperature and time, so when calibrating the system, the influence of both the Δa+Δm error and the k change must be eliminated.

[0035] Furthermore, the system error of DMS mainly exists in the analog measurement channel. The main reason for this system error is that the circuit state and parameters of its OPA, DAC, reference circuit and other components deviate from the standard value, and will drift with the change of temperature and time. This deviation and drift are concentrated in the zero drift and magnification change. Zero drift e means that when the input signal of the component is zero, the output is not zero, and it will change with time and temperature, which will cause additive error to the system. The magnification change means that the ratio k of the input to output of the component will change dk with the change of the input signal, which will cause multiplicative error to the system.

[0036] Furthermore, the DC parameters of the op amp include input offset voltage, input bias current, input offset current, open loop gain and rate resistance. They are the main reasons for the formation of e and dk. Please refer to the attached figure for the equivalent circuit of DMS voltage sampling. Figure 2 In the figure, e os is the input offset voltage; I b1 ,I b2 is the input bias current; R1 and R2 are the multiplier resistors; R is the input balancing resistor; R i is the equivalent internal resistance of the amplifier; U i is the input of the amplifier; U o is the output of the amplifier; I, I i , I1, I2, I3 are branch currents; U a , U b is the node voltage; the value of the balancing resistor R is usually equal to the parallel value of R1 and R2. Figure 2 It can be seen that:

[0037] U i =IR-e os +I i R i +I1R1 (2)

[0038]

[0039] Where A is the open-loop gain of the amplifier.

[0040] Substitute equation (3) and equation (4) into equation (2), and take into account I os =I b2 -I b1 , R=R1 / R2(R1+R2) and I i R i =U o / A (where, I os is called offset current), we get:

[0041]

[0042] Let 1 / d = (2R2 / AR i +R2 / AR+1), k=(R2 / R1), then:

[0043] U o =(1+k)d(U i +U os ) (6)

[0044] Furthermore, from formula (6), we can know that:

[0045] (1) The gain of the amplifier is (1+k)d, and the coefficient d = 1 / [1+(1+k) / A+2R2 / AR i ]. When the open-loop gain of the amplifier is A>>1+k, R1>>R2, the coefficient d→1, and the gain of the actual op amp is close to the gain of the ideal op amp 1+(R1 / R2). i , R1, and R2 also produce temperature drift with changes in temperature. Therefore, the actual op amp gain will also produce temperature drift with changes in temperature.

[0046] (2) Input offset voltage e os and offset current I os The effect on the amplifier output is equivalent to adding a zero drift voltage U to the input signal. os , by U os =e os +RI os We know that the offset voltage e os Direct impact os The size of the offset current I os After the current is formed through the resistor R, U os Works. os ,I os , R1, and R2 are all functions of temperature. Therefore, when the temperature changes, the equivalent zero-drift voltage U os It will also change.

[0047] Furthermore, there are offset voltages and offset currents at the input ends of components such as OP amplifiers, instrument amplifiers, and DACs, and the analysis methods for their equivalent zero drift and multiplier changes are similar to those described above.

[0048] Furthermore, in practical analog measurement channels, the analog components are often connected in series. Figure 3The following is a structural diagram of a DMS analog test channel. When PD1 and PD2 are connected to terminals 2 and 3 respectively, the ADC and instrument amplifier (IA) are connected in series to implement the applied voltage measurement current test (FVMI) of the load (DUT); when PD1 and PD2 are connected to terminals 1 and 4 respectively, the ADC and OP2 are connected in series to implement the applied current measurement voltage test (FIMV) of the load (DUT). The analog components in the sampling path of the analog channel of this device are connected in series. Figure 4 Take an example to explain how to calculate the total zero-drift voltage and multiplier.

[0049] Furthermore, k1 and k2 are the actual magnifications of component 1 and component 2, respectively. os1 , U os2 are the equivalent zero-drift voltages at their input terminals. Components 1 and 2 are connected in series, and their output voltages U o1 , U o2 They are:

[0050] U o1 = k1(U i +U os1 )(7)

[0051]

[0052] Furthermore, the two series components can be equivalent to one component. The ratio of the component is k1k2, and the zero drift voltage is U os1 +U os2 / k1, where U os2 / k2 is the value of the zero-point voltage of the second component input after being converted to the input end of the first component.

[0053] Furthermore, the zero drift voltage U os The and multiplication factor change dk are the main system errors of the analog input channel and should be calibrated. Figure 5 This is the calibration circuit schematic, including: single-pole relay S1, single-pole relay S2, single-pole relay S3 and reference source U ref Under the control of the DMS computer, they can connect the sampling input terminal to the ground and the reference source U ref and the sample value U i Connect. os It is the zero drift voltage referred to the input of the analog measurement channel.

[0054] Furthermore, using the built-in reference source U ref The influence of the magnification deviation from the rated value on the measurement can be eliminated. According to the calibration method of the present invention, the calibration steps are as follows (in the calibration process, assuming that U os and k are fixed values):

[0055] 1) The computer controls the single-pole relay S1 to conduct, disconnects the single-pole relay S2, disconnects the single-pole relay S3, and sets the output D os ,but:

[0056] D os =kU os (9)

[0057] 2) The computer controls the single-pole relay S2 to conduct, disconnects the single-pole relay S1, disconnects the single-pole relay S3, and sets the output D ref ,but:

[0058] D ref = k(U ref +U os )(10)

[0059] 3) The computer controls the single-pole relay S3 to conduct, disconnects the single-pole relay S1, disconnects the single-pole relay S2, and sets the output D x ,but:

[0060] D x = k(U i +U os )(11)

[0061] 4) The computer performs the following calculations

[0062] D1=D ref -D os =kU ref (12)

[0063] D2=D x -D os =kU i (13)

[0064]

[0065] so:

[0066]

[0067] In the above formula: D = (D x -D os ) / (D ref -D os ), eliminated U os and the influence of k.

[0068] Preferably, during the implementation of the above self-calibration, attention should be paid to:

[0069] 1) Three measurements are performed by controlling the single-pole relay S1, single-pole relay S2 and single-pole relay S3 to be turned on respectively; plus the switching time of the relays, the measurement time is increased by more than 2 times;

[0070] 2) In the three measurements, it is considered that the zero drift voltage U os and the multiple k are constants. Usually, this condition is considered to be met when the time and temperature are constant for three consecutive measurements, the measurement interval is short, and the test speed is fast;

[0071] 3) Reed relays should not be used for single-pole relays S1, S2 and S3, because the structure of this type of relay is a coil surrounding a switch, and a magnetic field is induced by applying current to the coil to close the switch. In order for the precision ADC circuit to work stably and reliably, electromagnetic interference (EMI) issues must be considered during the circuit design stage. During the hot switching process of the reed relay, the magnetic field induced by the coil will produce coupling interference to the ADC and other analog circuits. In addition, the triggering time and release time of the reed relay are both in the 10ms level, which will become a bottleneck for high-speed sampling circuits. In summary, single-pole relays S1, S2 and S3 are suitable for solid-state relays. This type of relay includes an optically isolated input that excites a solid-state switching device. This type of relay does not generate an electromagnetic field, thus avoiding electromagnetic interference issues. In addition, it is also the relay with the fastest switching speed;

[0072] 4) The built-in reference source Vref should have high reliability and stability, and its accurate value should be known.

[0073] In summary, in the actual measurement process, self-calibration can be selectively performed according to the specific requirements for measurement time and measurement accuracy. The "DMS self-calibration" function option can be added to the computer control interface. When the measurement accuracy is required to be high and the measurement time is not a key factor, this function can be selected to calibrate the zero drift and magnification.

[0074] The beneficial effects of the present invention include:

[0075] From the perspective of reducing the tool error of the DMS analog measurement channel, the present invention invents an automatic calibration and control method for zero drift and magnification change error. The required calibration circuit has a simple structure and low cost, is applicable to different types of DMS equipment, has no synchronization requirements for the measurement system, has low operation difficulty, can calibrate both relative error and absolute error, has a high degree of automation, improves the measurement accuracy of the DMS while taking into account the measurement time, and improves the reliability and stability of the measurement equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] Figure 1 is the systematic error of DMS.

[0077] Figure 2 This is the DMS voltage sampling equivalent circuit.

[0078] Figure 3 This is a structural diagram of the DMS simulation test channel of the present invention.

[0079] Figure 4 It is the equivalent analysis circuit of the series connection components of the present invention.

[0080] Figure 5 It is the principle diagram of the calibration circuit of the present invention.

[0081] Figure 6 The schematic diagram of the circuit for the specific implementation of the present invention. DETAILED DESCRIPTION

[0082] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, the description of well-known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention.

[0083] by Figure 3 The DMS shown in the figure is taken as an example to illustrate the implementation process of the present invention. The DMS can switch between the FVMI mode of applying voltage to measure current and the FIMV mode of applying current to measure voltage by controlling the on and off of the single-pole double-throw relay PD1 and the single-pole double-throw relay PD2. The DMS is composed of a DAC, an ADC, a power op amp OP1, an ordinary op amp OP2, an instrument amplifier IA, a single-pole four-throw relay PD0, two single-pole double-throw relays PD1 and PD2, four precision sampling resistors Rx (50Ω, 500Ω, 5kΩ, 50kΩ) and a load DUT. When the relays PD1 and PD2 are connected to the 1 and 4 terminals respectively, the DMS works in the FIMV state. At this time, OP1, IA and Rx form a voltage negative feedback circuit. The DMS applies a constant current to the DUT, and the current OP2 can obtain the voltage V- applied to the DUT, and the ADC collects the voltage V- output by the OP2 emitter-follower. When the relays PD1 and PD2 are connected to the 2 and 3 terminals respectively, the DMS works in the FVMI state. At this time, OP1 is an emitter follower, driving the output voltage V generated by the DAC to the DUT, and the IA obtains the voltage difference (V + -V _ ) is output to ADC. Regardless of FIMV or FVMI, PD0 can be connected to different endpoints respectively, and connected to sampling resistors of 50Ω, 500Ω, 5kΩ or 50kΩ to achieve switching of different measurement gears, and the maximum range of adjacent gears differs by 10 times. Whether DMS works in FIMV or FVMI, the present invention can be used to automatically calibrate channel errors.

[0084] like Figure 6 As shown, a method for automatically calibrating a channel error of a digital measurement system includes: a single-pole relay S1, a single-pole relay S2, a single-pole relay S3 and a reference source Vref. The single-pole relay S1 is used to control whether a DMS input terminal is connected to a DAC analog output terminal, the single-pole relay S2 is used to control whether the DMS input terminal is connected to a circuit ground, the single-pole relay S3 is used to control whether the DMS input terminal is connected to a reference source Vref, and the reference source Vref is used to provide a high-precision reference voltage.

[0085] The calibration steps are as follows:

[0086] 1) The controller controls S1 to turn on, disconnects S2 and S3, and connects the DMS input terminal to the DAC analog output terminal. At this time, the output voltage is set to D os ;

[0087] 2) The controller controls S2 to conduct, disconnects S1 and S3, and connects the DMS input terminal to the circuit ground. At this time, the output voltage is set to D x ;

[0088] 3) The controller controls S3 to conduct, disconnects S1 and S2, and connects the DMS input terminal to the reference source Vref. At this time, the output voltage is ref ;

[0089] 4) The controller performs the following calculations

[0090]

[0091] Get the calibrated U i Value, where: D = (D x -D os ) / (D ref -D os ), eliminated U os and the influence of k;

[0092] 5) Control DMS to work in FIMV and FMVI modes respectively, control PD0 to switch to different ranges respectively, and automatically calibrate the channel errors of different working modes and different ranges respectively.

[0093] It should be understood that the above specific embodiments of the present invention are only used to illustrate or explain the principles of the present invention, and do not constitute a limitation of the present invention. Therefore, any modifications, equivalent substitutions, improvements, etc. made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. In addition, the appended claims of the present invention are intended to cover all changes and modifications that fall within the scope and boundaries of the appended claims, or the equivalent forms of such scope and boundaries.

Claims

1. A method for automatically calibrating a channel error of a digital measurement system, comprising a digital measurement system, wherein the digital measurement system comprises an analog-to-digital converter ADC, a digital-to-analog converter DAC, a power amplifier OP1, an ordinary amplifier OP2, an instrument amplifier IA, a single-pole four-throw relay PD0, a single-pole double-throw relay PD1, a single-pole double-throw relay PD2, a plurality of precision sampling resistors Rx and a load DUT, wherein the single-pole four-throw relay PD0 is used to switch to different precision sampling resistors Rx to achieve switching of different ranges; the digital measurement system realizes conversion between a voltage-applied current measurement FVMI mode and a current-applied voltage measurement FIMV mode by controlling the on-off of the single-pole double-throw relay PD1 and the single-pole double-throw relay PD2; and the characteristics are: The method provides a channel error measurement circuit in the digital measurement system, wherein the channel error measurement circuit includes a single-pole relay S1, a single-pole relay S2, a single-pole relay S3 and a reference source Vref; the single-pole relay S1 is used to control whether the input end of the digital measurement system is connected to the analog output end of a digital-to-analog converter DAC, the single-pole relay S2 is used to control whether the input end of the digital measurement system is connected to a circuit ground, the single-pole relay S3 is used to control whether the input end of the digital measurement system is connected to the reference source Vref, and the reference source Vref is used to provide a high-precision reference voltage; The method comprises the following steps: (1) The controller controls the single-pole relay S1 to be turned on, and the single-pole relays S2 and S3 to be turned off, so that the input end of the digital measurement system is connected to the analog output end of the digital-to-analog converter DAC. At this time, the output voltage is set to D os ; (2) The controller controls the single-pole relay S2 to conduct, and disconnects the single-pole relays S1 and S3, so that the input end of the digital measurement system is connected to the circuit ground. At this time, the output voltage is set to D x ; (3) The controller controls the single-pole relay S3 to be turned on, and the single-pole relays S1 and S2 to be turned off, so that the input end of the digital measurement system is connected to the reference source Vref. At this time, the output voltage is D ref ; (4) Perform the following calculations: Get the calibrated U i Value, where: U ref is the reference source voltage, D=(D x -D os ) / (D ref -D os ).

2. The method according to claim 1, characterized in that: Each time automatic calibration is performed, three measurements are performed by controlling the single-pole relay S1, single-pole relay S2 and single-pole relay S3 to conduct; in the three measurements, the zero drift voltage U os and the factor k are invariants.

3. The method according to claim 1, characterized in that: The single-pole relay S1, the single-pole relay S2 and the single-pole relay S3 are solid-state relays.

4. The method according to claim 1, characterized in that: The built-in reference source Vref is required to have high reliability and stability, and its accurate value is known.

5. The method according to claim 1, characterized in that: The plurality of precision sampling resistors Rx are four precision sampling resistors with resistance values ​​of 50Ω, 500Ω, 5kΩ and 50kΩ respectively.

6. The method according to any one of claims 1 to 5, characterized in that: Also includes: (5) Control the digital measurement system to work in the applied voltage measurement current FVMI mode and the applied current measurement voltage FIMV mode, control the single-pole four-throw relay PD0 to switch to different ranges, and automatically calibrate the channel errors of different working modes and different ranges.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for automatic calibration of channel errors of a digital measurement system as described in any one of claims 1 to 6 are implemented.

8. A digital measurement system channel error automatic calibration system, characterized by: It includes a digital measurement system and a channel error measurement circuit arranged in the digital measurement system; The digital measurement system includes an analog-to-digital converter ADC, a digital-to-analog converter DAC, a power amplifier OP1, an ordinary amplifier OP2, an instrument amplifier IA, a single-pole four-throw relay PD0, a single-pole double-throw relay PD1, a single-pole double-throw relay PD2, a plurality of precision sampling resistors Rx and a load DUT. The single-pole four-throw relay PD0 is used to switch to different precision sampling resistors Rx to achieve switching of different ranges; the digital measurement system realizes the conversion between the applied voltage measurement current FVMI mode and the applied current measurement voltage FIMV mode by controlling the on and off of the single-pole double-throw relay PD1 and the single-pole double-throw relay PD2; The channel error measurement circuit comprises a single-pole relay S1, a single-pole relay S2, a single-pole relay S3 and a reference source Vref; the single-pole relay S1 is used to control whether the input end of the digital measurement system is connected to the analog output end of the digital-to-analog converter DAC, the single-pole relay S2 is used to control whether the input end of the digital measurement system is connected to the circuit ground, the single-pole relay S3 is used to control whether the input end of the digital measurement system is connected to the reference source Vref, and the reference source Vref is used to provide a high-precision reference voltage; It also includes a computer and a controller for controlling the single-pole relay S1, the single-pole relay S2, and the single-pole relay S3, wherein the controller is connected to the computer via an interface; Also included is a computer-readable storage medium as claimed in claim 7.

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