High-voltage electrostatic protection structure and electronic equipment

Abstract

The invention relates to the technical field of semiconductor manufacturing, and particularly discloses a high-voltage electrostatic protection structure and electronic equipment, the high-voltage electrostatic protection structure comprises an N-type MOS tube and a P-type triode unit connected with the N-type MOS tube, the isolation end and the drain end of the N-type MOS tube are both used for being connected with a high-voltage pin, and the P-type triode unit is used for being connected with the high-voltage pin. The gate end, the source end and the substrate end of the N-type MOS tube are short-circuited and then connected with one end of the P-type triode unit, and the other end of the P-type triode unit is connected with a ground wire pin; the P-type triode unit comprises at least one transverse P-type triode, the multiple transverse P-type triodes are connected in series, and the base electrode and the emitter electrode of each transverse P-type triode are in short circuit. According to the high-voltage electrostatic protection structure provided by the invention, the ESD device can be effectively protected, and meanwhile, the circuit cannot be influenced when the circuit works normally.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a high-voltage electrostatic protection structure and electronic equipment. Background Art

[0002] ESD (electrostatic discharge) refers to the accumulation of a certain amount of charge in the external environment or internal structure of an integrated circuit chip during its manufacture, transportation, and use. These accumulated charges will instantly enter the integrated circuit through the pins of the chip, with a peak current of several amperes. This transient high current will burn out the components inside the chip, causing the entire chip to fail. In recent years, with the continuous reduction in the size of integrated circuit components and the increase in integration, the proportion of circuit failures caused by ESD has also gradually increased, approaching 40%. Therefore, how to prevent integrated circuits from being damaged by ESD has become increasingly important.

[0003] At present, smart phones have been widely popularized, and the power chips in their chargers are also widely used in the market. Such power chips generally work in a switching state, which will generate positive and negative tip pulses, which can easily damage the circuit. In particular, the negative pulses generated should be paid more attention. Because when a negative pulse appears on the circuit switch pin, the PN junction formed by the P-type GND and the N-type area at the pin is turned on. At this time, if the other pins are connected to the PN-type area, a PNPN latch effect will be generated, causing the circuit to fail. Therefore, when the high-voltage ESD device of the circuit pin is not designed properly, it is easy to be affected by the above negative tip pulses and trigger latching, causing the circuit to burn out instantly.

[0004] Therefore, in the design of high-voltage ESD devices, how to make the ESD devices provide effective protection while not affecting the circuits when the circuits are operating normally has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0005] The present invention provides a high-voltage electrostatic protection structure and an electronic device, which solves the problem in the related art that high-voltage ESD devices cannot provide effective protection.

[0006] As a first aspect of the present invention, a high-voltage electrostatic protection structure is provided, which comprises: an N-type MOS tube and a P-type triode unit connected to the N-type MOS tube, The N-type MOS tube is a low-voltage isolation structure, the isolation end and the drain end of the N-type MOS tube are both used to connect to the high-voltage pin, the gate end, the source end and the substrate end of the N-type MOS tube are short-circuited and connected to one end of the P-type triode unit, and the other end of the P-type triode unit is connected to the ground pin; The P-type transistor unit includes at least one lateral P-type transistor, a plurality of the lateral P-type transistors are connected in series, the base and emitter of each lateral P-type transistor are short-circuited, wherein the base and emitter of the first lateral P-type transistor are short-circuited to form one end of the P-type transistor unit, and the collector of the last lateral P-type transistor forms the other end of the P-type transistor unit; When the electrostatic discharge voltage is introduced into the high-voltage pin, the energy of the electrostatic discharge voltage can sequentially break through the drain terminal and the source terminal of the N-type MOS tube to reach one end of the P-type triode unit, and sequentially break through the emitter and collector of each lateral P-type triode in the P-type triode unit to reach the ground pin to complete the energy discharge of the forward electrostatic discharge voltage; When an electrostatic discharge voltage is introduced into the ground pin, the energy of the electrostatic discharge voltage can reach one end of the P-type transistor unit through the collector and the short-circuited ends of the base and the emitter of each lateral P-type transistor in the P-type transistor unit in turn, and reach the high-voltage pin after passing through two parallel PN junctions formed between the substrate end and the drain end and between the substrate end and the isolation end of the N-type MOS tube to complete the energy discharge of the negative electrostatic voltage.

[0007] Furthermore, the breakdown voltage of the N-type MOS tube is in the range of 8V to 10V, and the breakdown voltage of each lateral P-type transistor in the P-type transistor unit is in the range of 13V to 17V.

[0008] Furthermore, the structure of the N-type MOS transistor is a first multi-finger structure, and the number of fingers of the first multi-finger structure ranges from 8 to 12. The total structural width of the N-type MOS transistor is at least 400 μm.

[0009] Furthermore, the structure of the lateral P-type transistor is a second multi-finger structure, and the fingers of the second multi-finger structure range from 10 to 16, and the total structural width of the lateral P-type transistor is at least 1200 μm.

[0010] Further, the N-type MOS transistor comprises: a P-type substrate, an N-type buried layer arranged on the surface of the P-type substrate and extending into the interior of the P-type substrate, and a P-type epitaxial layer arranged on the surface of the P-type substrate; A plurality of active regions are arranged in the P-type epitaxial layer, and a field region is formed between adjacent active regions; An outer oxide layer and a metal wire are arranged on the surface of the P-type epitaxial layer.

[0011] Furthermore, the first active region to the seventh active region are sequentially arranged in the P-type epitaxial layer, a field region is arranged between every two adjacent active regions, and a field oxide layer is arranged at the position of the field region; A deep P-well region extending inward from the surface of the P-type epitaxial layer is formed below the first active region and the seventh active region, a P-well region extending inward from the surface of the P-type epitaxial layer is formed in the deep P-well region, a P+ injection diffusion region extending inward from the surface of the P-type epitaxial layer is formed in the P-well region, the P+ injection diffusion region is connected to a metal wire as a lead-out end of the P-type epitaxial layer and the P-type substrate, and is connected to the ground pin; A deep N-well region extending inward from the surface of the P-type epitaxial layer is formed below the second active region and the sixth active region, an N-well region extending inward from the surface of the P-type epitaxial layer is formed in the deep N-well region, an N+ injection diffusion region extending inward from the surface of the P-type epitaxial layer is formed in the N-well region, and the N+ injection diffusion region is connected to a metal wire as an isolation terminal lead-out terminal of the N-type MOS tube and is connected to the high-voltage pin; A connected P-well region is formed below the third active region, the fourth active region and the fifth active region, and a P+ injection diffusion region is set at the position of the third active region and the fifth active region. The P+ injection diffusion region is connected to a metal wire to serve as a substrate terminal lead-out terminal of the N-type MOS tube.

[0012] Furthermore, polysilicon is disposed on the surface of the P-type epitaxial layer and at a position corresponding to the fourth active region, and the polysilicon is connected to the metal wire to serve as a gate lead-out terminal of the N-type MOS tube; N+ implant diffusion regions are arranged below the fourth active region and on both sides of the polysilicon. The N+ implant diffusion regions are connected to the metal wires to serve as source and drain terminals of the N-type MOS tube.

[0013] Furthermore, the metal wire as the drain lead-out terminal of the N-type MOS tube and the metal wire as the isolation end lead-out terminal of the N-type MOS tube are both connected to the high-voltage pin, and the metal wire as the gate lead-out terminal of the N-type MOS tube, the metal wire as the source lead-out terminal of the N-type MOS tube and the metal wire as the substrate end lead-out terminal of the N-type MOS tube are all short-circuited together.

[0014] Furthermore, the outer oxide layer located at corresponding positions of the active area and the polysilicon is removed to form a plurality of contact holes, and the metal wires are located in the contact holes; The bottom end of the metal wire in the contact hole contacts the active area, and the top end of the metal wire in the contact hole serves as the lead end of the N-type MOS tube.

[0015] As another aspect of the present invention, an electronic device is provided, which includes: a power supply circuit and the high-voltage electrostatic protection structure described above, the high-voltage pin of the power supply circuit is connected to the N-type MOS tube of the high-voltage electrostatic protection structure, and the ground pin of the power supply circuit is connected to the P-type transistor unit of the high-voltage electrostatic protection structure.

[0016] The high-voltage electrostatic protection structure provided by the present invention aims at the problem that the high-voltage device in the prior art has a weak electrostatic discharge capability. By adopting a lateral P-type transistor and an isolated N-type MOS tube NMOS connected in series, the electrostatic discharge level is equivalent to that of a single lateral P-type transistor or an isolated N-type MOS tube NMOS, that is, the ESD discharge capability is strong. At the same time, the present invention uses a plurality of lateral P-type transistors to connect at one end close to the ground wire pin, that is, the characteristic of the lateral P-type transistor maintaining a higher voltage is utilized to meet the requirement that the ESD structure can be used in the high-voltage pin; in addition, the present invention uses an isolated N-type MOS tube to connect the high-voltage pin and the lateral P-type transistor at one end of the high-voltage pin. Since the high-voltage pin of the present invention is connected to NMOS, that is, the high-voltage pin is not connected to the P-type region, it will not form a PNPN latch structure with the PN junction (that is, the PN junction formed by the P-type ground and the N-type region at the negative pulse pin), thereby avoiding the failure of the circuit in the case of an extreme negative pulse, and greatly improving the reliability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention, but do not constitute a limitation of the present invention.

[0018] Figure 1 This is a circuit diagram of the high-voltage electrostatic protection structure provided by the present invention.

[0019] Figure 2 This is a longitudinal cross-sectional view of the N-type MOS tube provided by the present invention.

[0020] Figure 3 A longitudinal cross-sectional view of the lateral P-type triode provided by the present invention. DETAILED DESCRIPTION

[0021] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0022] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the present invention.

[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0024] Conventional high-voltage pin ESD protection generally uses a high-voltage NMOS tube with the same voltage as the high-voltage pin as its ESD protection device. As we all know, the ESD discharge capability of the high-voltage NMOS device is weak, and its holding voltage is low, so it cannot be used on the power pin. If a high-voltage PMOS or high-voltage PNP is used for ESD protection, although the holding voltage is increased, the ESD discharge capability is also improved compared to the high-voltage NMOS. However, when a negative pulse appears on the N-type port connected to the other pins, the P-type region of the high-voltage PMOS or high-voltage PNP connected to the high-voltage pin, its N-type substrate or base, as well as the P-type ground and the aforementioned N-type negative pulse port, form a PNPN latch structure, causing the circuit to burn out instantly.

[0025] Based on this, a high-voltage electrostatic protection structure is provided in this embodiment. Figure 1 is a circuit structure diagram of a high-voltage electrostatic protection structure provided according to an embodiment of the present invention, such as Figure 1 As shown, including: An N-type MOS tube 10 and a P-type triode unit 20 connected to the N-type MOS tube 10, The N-type MOS transistor 10 is a low-voltage isolation structure. The isolation terminal 102 and the drain terminal 101 of the N-type MOS transistor 10 are both used to connect to the high-voltage pin 100. The gate terminal 103, the source terminal 105 and the substrate terminal 104 of the N-type MOS transistor 10 are short-circuited and connected to one end of the P-type triode unit 20. The other end of the P-type triode unit 20 is connected to the ground pin 115. The P-type transistor unit 20 includes at least one lateral P-type transistor, a plurality of the lateral P-type transistors are connected in series, the base and emitter of each lateral P-type transistor are short-circuited, wherein the base and emitter of the first lateral P-type transistor are short-circuited to form one end of the P-type transistor unit, and the collector of the last lateral P-type transistor forms the other end of the P-type transistor unit; When the electrostatic discharge voltage is introduced to the high voltage pin 100, the energy of the electrostatic discharge voltage can sequentially break through the drain terminal 101 and the source terminal 105 of the N-type MOS tube 10 to reach one end of the P-type transistor unit 20, and sequentially break through the emitter and collector of each lateral P-type transistor in the P-type transistor unit 20 to reach the ground pin to complete the energy discharge of the forward electrostatic discharge voltage; When an electrostatic discharge voltage is introduced into the ground pin 115, the energy of the electrostatic discharge voltage can reach one end of the P-type transistor unit 20 through the collector and the short-circuited ends of the base and the emitter of each lateral P-type transistor in the P-type transistor unit 20 in turn, and reach the high-voltage pin after passing through the two parallel PN junctions formed between the substrate end 104 and the drain end 101 of the N-type MOS tube 10 and between the substrate end and the isolation end to complete the energy discharge of the negative electrostatic voltage.

[0026] Therefore, the high-voltage electrostatic protection structure provided by the present invention aims at the problem that the high-voltage device in the prior art has a weak electrostatic discharge capability. By adopting a lateral P-type transistor and an isolated N-type MOS tube NMOS in series, the electrostatic discharge level is equivalent to that of a single lateral P-type transistor or an isolated N-type MOS tube NMOS, that is, the ESD discharge capability is strong. At the same time, the present invention uses a plurality of lateral P-type transistors to connect at one end close to the ground wire pin, that is, the characteristic of the lateral P-type transistor maintaining a higher voltage is utilized to meet the requirement that the ESD structure can be used in the high-voltage pin; in addition, the present invention uses an isolated N-type MOS tube to connect the high-voltage pin and the lateral P-type transistor at one end of the high-voltage pin. Since the high-voltage pin of the present invention is connected to NMOS, that is, the high-voltage pin is not connected to the P-type region, it will not form a PNPN latch structure with the PN junction (that is, the PN junction formed by the P-type ground and the N-type region at the negative pulse pin), thereby avoiding the failure of the circuit in the case of an extreme negative pulse, and greatly improving the reliability of the circuit.

[0027] In the embodiment of the present invention, the breakdown voltage of the N-type MOS transistor 10 is in the range of 8V to 10V, and the breakdown voltage of each lateral P-type transistor in the P-type transistor unit 20 is in the range of 13V to 17V.

[0028] It should be understood that, in the embodiment of the present invention, the number of lateral P-type transistors included in the P-type transistor unit 20 is related to the withstand voltage requirement and can be specifically set according to the requirement, which is not limited here.

[0029] In the embodiment of the present invention, the structure of the N-type MOS transistor is a first multi-finger structure, and the number of fingers of the first multi-finger structure ranges from 8 to 12. The total width of the structure of the N-type MOS transistor is at least 400 μm.

[0030] In an embodiment of the present invention, the structure of the lateral P-type transistor is a second multi-finger structure, and the fingers of the second multi-finger structure range from 10 to 16. The total width of the structure of the lateral P-type transistor is at least 1200 μm.

[0031] It should be understood that by setting the finger structure of the N-type MOS transistor to 8 to 12 and the total width of the structure of the N-type MOS transistor to at least 400μm, the basic ESD function of the high-voltage electrostatic protection structure can be achieved while ensuring the manufacturing process. Similarly, by setting the finger structure of the lateral P-type triode to 10 to 16 and the total width of the structure of the lateral P-type triode to at least 1200μm, the basic ESD function of the high-voltage electrostatic protection structure can be achieved while ensuring the manufacturing process.

[0032] In the embodiment of the present invention, Figure 2 As shown, the N-type MOS transistor 10 includes: a P-type substrate 200, an N-type buried layer 201 disposed on the surface of the P-type substrate 200 and extending into the inside of the P-type substrate 200, and a P-type epitaxial layer 202 disposed on the surface of the P-type substrate 200; A plurality of active regions are arranged in the P-type epitaxial layer 202, and a field region is formed between adjacent active regions; An outer oxide layer and metal wires are disposed on the surface of the P-type epitaxial layer 202 .

[0033] Specifically, the first active region to the seventh active region are sequentially arranged in the P-type epitaxial layer, a field region is arranged between every two adjacent active regions, and a field oxide layer is arranged at the position of the field region; A deep P-well region extending inward from the surface of the P-type epitaxial layer is formed below the first active region and the seventh active region, a P-well region extending inward from the surface of the P-type epitaxial layer is formed in the deep P-well region, a P+ injection diffusion region extending inward from the surface of the P-type epitaxial layer is formed in the P-well region, the P+ injection diffusion region is connected to a metal wire as a lead-out end of the P-type epitaxial layer and the P-type substrate, and is connected to the ground pin; A deep N-well region extending inward from the surface of the P-type epitaxial layer is formed below the second active region and the sixth active region, an N-well region extending inward from the surface of the P-type epitaxial layer is formed in the deep N-well region, an N+ injection diffusion region extending inward from the surface of the P-type epitaxial layer is formed in the N-well region, and the N+ injection diffusion region is connected to a metal wire as an isolation terminal lead-out terminal of the N-type MOS tube and is connected to the high-voltage pin; A connected P-well region is formed below the third active region, the fourth active region and the fifth active region, and a P+ injection diffusion region is set at the position of the third active region and the fifth active region. The P+ injection diffusion region is connected to a metal wire to serve as a substrate terminal lead-out terminal of the N-type MOS tube.

[0034] Specifically, polysilicon is disposed on the surface of the P-type epitaxial layer and at a position corresponding to the fourth active region, and the polysilicon is connected to the metal wire to serve as a gate lead-out terminal of the N-type MOS tube; N+ implant diffusion regions are arranged below the fourth active region and on both sides of the polysilicon. The N+ implant diffusion regions are connected to the metal wires to serve as source and drain terminals of the N-type MOS tube.

[0035] In the embodiment of the present invention, the metal wire serving as the drain lead-out terminal of the N-type MOS tube and the metal wire serving as the isolation lead-out terminal of the N-type MOS tube are both connected to the high-voltage pin, and the metal wire serving as the gate lead-out terminal of the N-type MOS tube, the metal wire serving as the source lead-out terminal of the N-type MOS tube and the metal wire serving as the substrate lead-out terminal of the N-type MOS tube are all short-circuited together.

[0036] Specifically, the outer oxide layer at corresponding positions of the active area and the polysilicon is removed to form a plurality of contact holes, and the metal wires are located in the contact holes; The bottom end of the metal wire in the contact hole contacts the active area, and the top end of the metal wire in the contact hole serves as the lead end of the N-type MOS tube.

[0037] In the embodiment of the present invention, Figure 2 , which is a schematic diagram of the longitudinal structure of the N-type MOS transistor 10. Specifically, a P-type epitaxial layer 202 is provided above the P-type substrate 200, and the isolation NMOS transistor is made in the P-type epitaxial layer. An N-type buried layer 201 is provided between the P-type substrate 200 and the P-type epitaxial layer 202. On the surface of the P-type epitaxial layer, a first active area 212, a second active area 213, a third active area 214, a fourth active area 215, a fifth active area 216, a sixth active area 217, and a seventh active area 218 are provided in sequence. On both sides of each active area, a field area is provided, and on the field area is a field oxide layer 209 with a thickness of 5500 to 7000 angstroms, which serves as isolation between the active areas.

[0038] In the embodiment of the present invention, deep P-well regions 203 are provided at the first active region 212 and the seventh active region 218, serving as the isolated ground terminal of the isolated NMOS tube. Inside the deep P-well region 203, P+ implant diffusion regions 207 and shallow P-well regions 205 are provided to increase the doping concentration at the location, and form a good ohmic contact through contact holes and metal lines, serving as the lead-out terminal of the isolated ground terminal. Deep N-well regions 204 are provided at the second active region 213 and the sixth active region 217. The deep N-well region 204 diffuses downward from the P-type epitaxial surface by 5 to 6 microns, and contacts and communicates with the N-type buried layer 201. Inside the deep N-well region 204, N+ implant diffusion regions 208 and shallow N-well regions 206 are provided to increase the doping concentration at the location, and form a good ohmic contact through contact holes and metal lines, serving as the lead-out terminal of the isolated port of the isolated NMOS tube.

[0039] In the embodiment of the present invention, a large P-well region 205 is provided below the third active region 214, the fourth active region 215 and the fifth active region 216. At the positions of the third active region 214 and the fifth active region 216 inside the large P-well region 205, P+ implant diffusion regions are provided to increase the doping concentration there, and form a good ohmic contact through contact holes and metal lines, which serve as the contact lead of the large P-well region 205, that is, the substrate end of the isolated NMOS. At the position of the fourth active region 215 inside the large P-well region 205, three N+ implant diffusion regions 208 and two polysilicon regions 211 are arranged at intervals, wherein the two N+ implant diffusion regions 208 close to the field oxide layers 209 on both sides form a good ohmic contact through contact holes and metal lines, serving as the source lead of the isolated NMOS; the middle N+ implant diffusion region 208 also forms a good ohmic contact through contact holes and metal lines, serving as the drain lead of the isolated NMOS. Two polysilicon regions 211 spaced apart between the three N+ implantation diffusion regions 208 form good ohmic contacts through contact holes and metal lines, serving as gate lead terminals of the isolated NMOS.

[0040] In the embodiment of the present invention, an outer oxide layer 210 covering the entire wafer surface is provided above all field oxide layers and active areas, and the thickness is 7000 to 12000 angstroms. The outer oxide layer 210 is removed at the corresponding positions of the P+ implantation diffusion area 207 of the first active area 212, the third active area 214, the fifth active area 216, and the seventh active area 218, and at the corresponding positions of the N+ implantation diffusion area 208 of the second active area 213, the fourth active area 215, and the sixth active area 217, to form contact holes directly reaching the silicon surface; at the position of each contact hole, a metal wire 219 is provided to contact the silicon surface, and each port of the isolated NMOS tube is led out respectively, to form a complete isolated NMOS tube structure.

[0041] In the embodiment of the present invention Figure 2 The structure shown in combination with the aforementioned Figure 1 As can be seen from the circuit structure diagram, the metal wire of the gate 211 of the isolated NMOS tube, the metal wire of the source 208 in the fourth active area 215, and the metal wire of the substrate 207 in the third active area 214 and the fifth active area 216 are short-circuited together. The metal wire of the drain 208 in the fourth active area 215 of the isolated NMOS tube is connected to the high-voltage pin; the metal wire of the isolation end 208 in the second active area 213 and the sixth active area 217 of the isolated NMOS tube is connected to the high-voltage pin.

[0042] In the embodiment of the present invention, the P-type transistor unit 20 includes three lateral P-type transistors as an example for description. Figure 1 As shown, the P-type transistor unit 20 includes a first lateral P-type transistor LPNP1, a second lateral P-type transistor LPNP2 and a third lateral P-type transistor LPNP3. The base 108 and the emitter 106 of the first lateral P-type transistor LPNP1 are short-circuited and connected to the source terminal 105 of the isolated N-type MOS transistor NMOS. The collector 107 of the first lateral P-type transistor LPNP1 is connected to the short-circuited end of the base 111 and the emitter 109 of the second lateral P-type transistor LPNP2. The collector 110 of the second lateral P-type transistor LPNP2 is connected to the short-circuited end of the base 114 and the emitter 112 of the third lateral P-type transistor LPNP3. The collector 113 of the third lateral P-type transistor LPNP3 is connected to the ground pin 115.

[0043] In the embodiment of the present invention, Figure 3 As shown, this is a schematic diagram of the longitudinal structure of the lateral PNP tube. Figure 1 The longitudinal structures and sizes of the first lateral PNP transistor LPNP1, the second lateral PNP transistor LPNP2 and the third lateral PNP transistor LPNP3 are completely the same, and the longitudinal structure of the first lateral PNP transistor LPNP1 is used for description below.

[0044] like Figure 3As shown, a P-type epitaxial layer 302 of the lateral PNP tube is provided above the P-type substrate 300 of the lateral PNP tube, and the lateral PNP tube is made in the P-type epitaxial layer 302 of the lateral PNP tube. An N-type buried layer 301 of the lateral PNP tube is provided between the P-type substrate 300 of the lateral PNP tube and the P-type epitaxial layer 302 of the lateral PNP tube. On the surface of the P-type epitaxial layer of the lateral PNP tube, a first active region 312 of the lateral PNP tube, a second active region 313 of the lateral PNP tube, a third active region 314 of the lateral PNP tube, a fourth active region 315 of the lateral PNP tube, a fifth active region 316 of the lateral PNP tube, a sixth active region 317 of the lateral PNP tube, a seventh active region 318 of the lateral PNP tube, an eighth active region 319 of the lateral PNP tube, and a ninth active region 320 of the lateral PNP tube are provided in sequence. On both sides of the active area of ​​each lateral PNP tube, there are field areas of the lateral PNP tube. On the field areas of the lateral PNP tube is a 5500 to 7000 angstrom thick lateral PNP tube field oxide layer 309, which serves as isolation between the active areas of every two lateral PNP tubes.

[0045] In this embodiment, the deep P well region 303 of the lateral PNP tube is provided at the first active region 312 of the lateral PNP tube and the ninth active region 320 of the lateral PNP tube, which serves as the isolated ground terminal of the lateral PNP tube. Inside the deep P well region 303 of the lateral PNP tube, the P+ injection diffusion region 307 of the lateral PNP tube and the shallow P well region 305 of the lateral PNP tube are provided to increase the doping concentration at this location, form a good ohmic contact through the contact hole and the metal wire, and serve as the lead-out terminal of the isolated ground terminal. Below the second active region 313 of the lateral PNP tube to the eighth active region 319 of the lateral PNP tube, a large deep N well region 304 of the lateral PNP tube is provided. The deep N well region 304 of the lateral PNP tube diffuses downward from the P-type epitaxial surface of the lateral PNP tube by 5 to 6 microns, and contacts and communicates with the N-type buried layer 301 of the lateral PNP tube. Inside the deep N-well region 304 of the lateral PNP tube at the second active region 313 of the lateral PNP tube and the eighth active region 319 of the lateral PNP tube, there are provided an N+ injection diffusion region 308 of the lateral PNP tube and a shallow N-well region 306 of the lateral PNP tube, so as to increase the doping concentration therein and form a good ohmic contact through the contact hole and the metal wire, which serves as the base lead-out terminal of the lateral PNP tube.

[0046] In the embodiment of the present invention, a P+ injection diffusion region 307 of the lateral PNP tube is provided at the active region position of each lateral PNP tube from the third active region 314 of the lateral PNP tube to the seventh active region 318 of the lateral PNP tube. Among them, the P+ injection diffusion region 307 of the lateral PNP tube at the third active region 314 of the lateral PNP tube, the fifth active region 316 of the lateral PNP tube, and the seventh active region 318 of the lateral PNP tube all form good ohmic contacts through contact holes and metal wires, serving as the collector lead-out terminal of the lateral PNP tube. The P+ injection diffusion region 307 of the lateral PNP tube at the fourth active region 315 of the lateral PNP tube and the sixth active region 317 of the lateral PNP tube form good ohmic contacts through contact holes and metal wires, serving as the emitter lead-out terminal of the lateral PNP tube.

[0047] In the embodiment of the present invention, above the field oxide layer and active area of ​​all lateral PNP tubes, an outer oxide layer 310 of the lateral PNP tube covering the entire wafer surface is provided, and the thickness is 7000 to 12000 angstroms. The outer oxide layer 310 of the lateral PNP tube is removed at the corresponding positions of the P+ injection diffusion area 307 of the first active area 312 of the lateral PNP tube, the third active area 314 of the lateral PNP tube to the seventh active area 318 of the lateral PNP tube, and the ninth active area 320 of the lateral PNP tube, and the corresponding positions of the N+ injection diffusion area 308 of the lateral PNP tube of the second active area 313 of the lateral PNP tube and the eighth active area 319 of the lateral PNP tube, to form a contact hole directly reaching the silicon surface; at the position of each contact hole, a metal wire 321 of the lateral PNP tube is provided to contact the silicon surface, and each port of the lateral PNP tube is led out respectively, to form a complete lateral PNP tube structure.

[0048] In the embodiment of the present invention, Figure 3 The structure shown in combination with the aforementioned Figure 1 As can be seen from the circuit structure diagram, the metal wires of the base 308 in the second active region 313 and the eighth active region 319 of the first lateral PNP transistor LPNP1 and the metal wires of the emitter 307 in the fourth active region 315 and the sixth active region 317 of the lateral PNP transistor are short-circuited together. At the same time, the base metal wires and the emitter metal wires of the second lateral PNP transistor LPNP2 and the third lateral PNP transistor LPNP3 are short-circuited together, just like the first lateral PNP transistor LPNP1, and the first lateral PNP transistor LPNP1 to the third lateral PNP transistor LPNP3 are connected in series.

[0049] Therefore, the high-voltage electrostatic protection structure provided in the embodiment of the present invention can be specifically composed of an isolated low-voltage NMOS and three low-voltage lateral PNP tubes connected in series, and its ESD discharge capability depends on the weakest device in the series path. Since the discharge capabilities of the low-voltage NMOS and the low-voltage lateral PNP are both very strong, the discharge capability of the high-voltage electrostatic protection structure of the embodiment of the present invention is relatively strong; and since the maintenance voltage of the low-voltage lateral PNP tube is relatively high (almost the same as its breakdown voltage), the maintenance voltage of the structure of the present invention is equal to the sum of the maintenance voltage of the NMOS and the maintenance voltage of the three PNP tubes. Therefore, the maintenance voltage of the high-voltage electrostatic protection structure of the embodiment of the present invention is relatively high (about 50V), and can be used in high-voltage pins and power pins. In addition, when a negative pulse appears on the N-type port connected to the remaining pins, since the high-voltage pin is connected to the high-voltage electrostatic protection structure of the present invention, that is, the high-voltage pin is connected to the N-type region of the isolated NMOS, it is impossible to form a PNPN latch structure with the negative pulse N-type ports of the remaining pins, which also protects the circuit very well. The following is combined with Figures 1 to 3 As shown, the process from the introduction to the release of electrostatic discharge energy is explained.

[0050] according to Figure 1 As shown in the figure, the isolated NMOS connected to the high voltage pin is specifically a structure in which the gate, source and substrate are short-circuited. The breakdown voltage of its drain and source is generally 10V, while the breakdown voltage from its isolation port to the ground is greater than 70V (i.e. Figure 2 The junction breakdown of the deep N-well region 204 and the deep P-well region 203). The lateral PNP transistor (LPNP1) connected to the isolated NMOS source is a base and emitter short-circuited structure, and its emitter and collector breakdown voltage is 13V~17V, while the breakdown voltage from the base and emitter short-circuited end to the ground end is greater than 70V (i.e. Figure 3The junction of the deep N-well region 304 and the deep P-well region 303 is broken down). LPNP2 and LPNP3 connected in series with LPNP1 have the same structure and connection method as LPNP1, and the breakdown voltage of each port is also the same as LPNP1. When the electrostatic discharge voltage is introduced to the high-voltage pin 100, the isolated NMOS is in the cut-off state with the gate and source short-circuited. Since the breakdown voltage from the isolated port to the ground terminal is greater than 70V, the electrostatic discharge energy will break down the drain-source junction (10V) of the isolated NMOS with a lower breakdown voltage, and then the electrostatic discharge energy reaches the emitter of the lateral PNP tube (LPNP1). At this time, since the emitter and base of LPNP1 are short-circuited, and the breakdown voltage from the short-circuited end to the ground terminal is greater than 70V, the electrostatic discharge energy will break down the emitter and collector of LPNP1 with a lower breakdown voltage, and then the electrostatic discharge energy reaches the emitter of the lateral PNP tube (LPNP2). Similarly, the electrostatic discharge energy gradually breaks down the emitter and collector of LPNP2 and LPNP3, and finally reaches the ground pin 115, completing the discharge of the electrostatic discharge energy from the high voltage pin 100 to the ground pin 115. It should be noted that when the electrostatic discharge current reaches a certain level, the parasitic NPN in the isolated NMOS body will be activated, and the ESD energy will be discharged by the NPN. On the contrary, when the electrostatic discharge energy is introduced from the ground pin 115, LPNP3 is in a forward biased state of the collector and base at this time, and the electrostatic discharge energy passes through a PN junction (0.7V) and reaches the base and emitter short-circuited end of LPNP3, that is, the collector of LPNP2. Similarly, LPNP2 and LPNP1 are also in a forward biased state of the collector and base, so the electrostatic discharge energy passes through two PN junctions (1.4V) and reaches the source and substrate short-circuited end of the isolated NMOS. Finally, through the two parallel PN junctions of the substrate and the drain, and the substrate and the isolation port, the electrostatic discharge energy reaches the high-voltage pin, thereby completing the discharge from the ground pin 115 to the high-voltage pin 100. Therefore, the high-voltage electrostatic protection structure of the present invention can realize the discharge of positive and negative ESD energy from the high-voltage pin to the ground pin. When the other pins have negative pulses, since the high-voltage pin is connected to the N-type region of the electrostatic discharge structure of the present invention, it will not form a destructive latch PNPN structure with the negative pulses of the other pins, thereby well ensuring the safety and reliability of the circuit under extremely harsh conditions.

[0051] In summary, the high-voltage electrostatic protection structure provided by the present invention has the following advantages: (1) The structure can perform bidirectional discharge of electrostatic discharge energy from the high-voltage pin to the ground pin; (2) The ESD discharge capacity of the high-voltage electrostatic protection structure is not reduced compared with the low-voltage ESD structure, and still has a strong discharge capacity; (3) The maintenance voltage of the high-voltage electrostatic protection structure is equal to the sum of the maintenance voltages of the isolated NMOS and multiple PNP tubes, which can meet the use of high-voltage power supply (the embodiment of the present invention is specifically the sum of the maintenance voltages of NMOS and three LPNPs, that is: 6+15+15+15=51V, so the structure can meet the use of high-voltage power supply 50V); (4) When abnormal negative pulses appear on the other pins, the high-voltage pins connected to the high-voltage electrostatic protection structure have strong shielding properties and will not form a latch structure with the other pins, thereby improving the reliability and safety of the circuit under extreme conditions and extending the service life of the circuit. Therefore, the high-voltage electrostatic protection structure of the present invention can fully achieve good electrostatic protection for the high-voltage pins (including power pins) of the circuit, and has high reliability against negative pulses.

[0052] It should be understood that, for the convenience of explanation, the present invention only exemplifies the ESD protection structure when the high-voltage pin is 50V. For those skilled in the art, it is easy to obtain high-voltage electrostatic protection structures of different voltage levels by increasing or decreasing the number of lateral PNP tubes or increasing the number of isolated NMOS tubes. At the same time, for the convenience of explanation, the present invention only exemplifies the structure with 2 fingers for both the isolated NMOS and the lateral PNP tubes. For those skilled in the art, it is easy to obtain structures with different ESD discharge capabilities by increasing the number of fingers. The high-voltage electrostatic protection structure proposed in the present invention can be applied not only between the high-voltage pin and the ground pin described in the text, but also between the other different functional pins.

[0053] As another embodiment of the present invention, an electronic device is provided, which includes: a power supply circuit and the high-voltage electrostatic protection structure described above, the high-voltage pin of the power supply circuit is connected to the N-type MOS tube of the high-voltage electrostatic protection structure, and the ground pin of the power supply circuit is connected to the P-type transistor unit of the high-voltage electrostatic protection structure.

[0054] The electronic device of the embodiment of the present invention adopts the high-voltage electrostatic protection structure mentioned above and can be applied to high-voltage power supply circuits. It can play a role in electrostatic protection under high voltage of the power supply circuit, improve the reliability and safety of the power supply circuit under extreme conditions, and extend the service life of the power supply circuit.

[0055] The specific working principle of the electronic device of the present invention can be referred to the specific description of the high-voltage electrostatic protection structure above, which will not be repeated here.

[0056] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A high voltage electrostatic protection structure, characterized in that: include: An N-type MOS tube and a P-type triode unit connected to the N-type MOS tube, The N-type MOS tube is a low-voltage isolation structure, the isolation end and the drain end of the N-type MOS tube are both used to connect to the high-voltage pin, the gate end, the source end and the substrate end of the N-type MOS tube are short-circuited and connected to one end of the P-type triode unit, and the other end of the P-type triode unit is connected to the ground pin; The P-type transistor unit includes at least one lateral P-type transistor, a plurality of the lateral P-type transistors are connected in series, the base and emitter of each lateral P-type transistor are short-circuited, wherein the base and emitter of the first lateral P-type transistor are short-circuited to form one end of the P-type transistor unit, and the collector of the last lateral P-type transistor forms the other end of the P-type transistor unit; When the electrostatic discharge voltage is introduced into the high-voltage pin, the energy of the electrostatic discharge voltage can sequentially break through the drain terminal and the source terminal of the N-type MOS tube to reach one end of the P-type triode unit, and sequentially break through the emitter and collector of each lateral P-type triode in the P-type triode unit to reach the ground pin to complete the energy discharge of the forward electrostatic discharge voltage; When an electrostatic discharge voltage is introduced into the ground pin, the energy of the electrostatic discharge voltage can reach one end of the P-type transistor unit through the collector and the short-circuited ends of the base and the emitter of each lateral P-type transistor in the P-type transistor unit in turn, and reach the high-voltage pin after passing through two parallel PN junctions formed between the substrate end and the drain end and between the substrate end and the isolation end of the N-type MOS tube to complete the energy discharge of the negative electrostatic voltage.

2. The high voltage electrostatic protection structure according to claim 1, characterized in that: The breakdown voltage of the N-type MOS tube is in the range of 8V to 10V, and the breakdown voltage of each lateral P-type transistor in the P-type transistor unit is in the range of 13V to 17V.

3. The high voltage electrostatic protection structure according to claim 1, characterized in that: The structure of the N-type MOS transistor is a first multi-finger structure, and the number of fingers of the first multi-finger structure ranges from 8 to 12. The total width of the structure of the N-type MOS transistor is at least 400 μm.

4. The high voltage electrostatic protection structure according to claim 1, characterized in that: The structure of the lateral P-type transistor is a second multi-finger structure, and the fingers of the second multi-finger structure range from 10 to 16. The total width of the structure of the lateral P-type transistor is at least 1200 μm.

5. The high voltage electrostatic protection structure according to any one of claims 1 to 4, characterized in that: The N-type MOS transistor comprises: a P-type substrate, an N-type buried layer arranged on the surface of the P-type substrate and extending into the P-type substrate, and a P-type epitaxial layer arranged on the surface of the P-type substrate; A plurality of active regions are arranged in the P-type epitaxial layer, and a field region is formed between adjacent active regions; An outer oxide layer and a metal wire are arranged on the surface of the P-type epitaxial layer.

6. The high voltage electrostatic protection structure according to claim 5, characterized in that: The first active region to the seventh active region are sequentially arranged in the P-type epitaxial layer, a field region is arranged between every two adjacent active regions, and a field oxide layer is arranged at the position of the field region; A deep P-well region extending inward from the surface of the P-type epitaxial layer is formed below the first active region and the seventh active region, a P-well region extending inward from the surface of the P-type epitaxial layer is formed in the deep P-well region, a P+ injection diffusion region extending inward from the surface of the P-type epitaxial layer is formed in the P-well region, the P+ injection diffusion region is connected to a metal wire as a lead-out end of the P-type epitaxial layer and the P-type substrate, and is connected to the ground pin; A deep N-well region extending inward from the surface of the P-type epitaxial layer is formed below the second active region and the sixth active region, an N-well region extending inward from the surface of the P-type epitaxial layer is formed in the deep N-well region, an N+ injection diffusion region extending inward from the surface of the P-type epitaxial layer is formed in the N-well region, and the N+ injection diffusion region is connected to a metal wire as an isolation terminal lead-out terminal of the N-type MOS tube and is connected to the high-voltage pin; A connected P-well region is formed below the third active region, the fourth active region and the fifth active region, and a P+ injection diffusion region is set at the position of the third active region and the fifth active region. The P+ injection diffusion region is connected to a metal wire to serve as a substrate terminal lead-out terminal of the N-type MOS tube.

7. The high voltage electrostatic protection structure according to claim 6, characterized in that: Polysilicon is disposed on the surface of the P-type epitaxial layer and at a position corresponding to the fourth active region, and the polysilicon is connected to the metal wire to serve as a gate lead-out terminal of the N-type MOS tube; N+ implant diffusion regions are arranged below the fourth active region and on both sides of the polysilicon. The N+ implant diffusion regions are connected to the metal wires to serve as source and drain terminals of the N-type MOS tube.

8. The high voltage electrostatic protection structure according to claim 7, characterized in that: The metal wire as the drain lead-out terminal of the N-type MOS tube and the metal wire as the isolation end lead-out terminal of the N-type MOS tube are both connected to the high-voltage pin, and the metal wire as the gate lead-out terminal of the N-type MOS tube, the metal wire as the source lead-out terminal of the N-type MOS tube and the metal wire as the substrate end lead-out terminal of the N-type MOS tube are all short-circuited together.

9. The high voltage electrostatic protection structure according to claim 5, characterized in that: The outer oxide layer is located at the corresponding positions of the active area and the polysilicon, and then a plurality of contact holes are formed, wherein the metal wires are located in the contact holes; The bottom end of the metal wire in the contact hole contacts the active area, and the top end of the metal wire in the contact hole serves as the lead end of the N-type MOS tube.

10. An electronic device, characterized in that: include: A power supply circuit and a high-voltage electrostatic protection structure as described in any one of claims 1 to 9, wherein the high-voltage pin of the power supply circuit is connected to the N-type MOS tube of the high-voltage electrostatic protection structure, and the ground pin of the power supply circuit is connected to the P-type transistor unit of the high-voltage electrostatic protection structure.

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