Quadrature circuit interconnect architecture with clock forwarding

Abstract

An integrated circuit communication architecture is provided and includes a clock channel, a clock divider, and a first de-skew circuit. The clock channel is configured to transmit a clock signal from the first chip to the second chip at a first rate. A clock divider is on the second chip, configured to receive the clock signal transmitted via the clock channel, and configured to create and transmit a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signal is transmitted at a reduced rate compared to the first rate. The clock divider maintains a current mode logic property of the divided clock signal. The first de-skew circuit is configured to receive and process the divided clock signal to allow sampling of data transmitted from the first chip to the second chip.

Description

Background Art

[0001] The present invention generally relates to processors used in computer systems, such as personal computers, servers, and / or other computer devices having computer chips.

[0002] With the desire for faster, more powerful, and more energy efficient computers, improved computer chip and computer chip package designs have been attempted. Improved designs have been attempted to allow for expanded processor core counts and improved memory bandwidth. Chip designs with smaller dies have been manufactured.

[0003] An embedded multi-die interconnect bridge (EMIB) has been created, and is a complex multi-layer silicon chip that allows large amounts of data to be transferred back and forth between adjacent chips at high speeds. High bandwidth memory (HBM) has been adopted as a standard in the industry, and is a high-speed memory interface for 3D stacked synchronous dynamic random access memory. EMIB and HBM designs can transmit many signals between chips, but suffer from performance penalties, especially if the two chips are not placed in close proximity to each other. For slightly longer interconnects, for example, with lengths in the high single digits to tens of millimeters, standard connections such as personal component interconnect express ("PCIe") or double data rate (DDR) have been used. However, these standard connections are power-demanding for short interfaces.

[0004] The new interconnects typically use shorter spacing between chips formed by controlled collapse chip protection, so area constraints are tighter and do not work with standard serializer / deserializers (SerDes).

[0005] US8,116,420B2 of Ali et al. provides a clock forwarding technique for high-speed links. The clock forwarding technique includes the use of a repeater circuit, such as a clock regeneration and multiplication circuit. In the repeater circuit, a clock multiplier unit (CMU) generates an internal clock signal based on the forwarded clock signal, which is received on the link.

[0006] Other interfaces, such as Bunch of Wires (BoW), have attempted to simplify the interconnect to retain the terminated SerDes aspects of a complex interface, but remove much of the complexity. However, BoW designs are performance-limited due to clock requirements on the receive side.

[0007] Clock data recovery (CDR) circuits determine the clock signal by interpreting the transmitted data without any additional clock signal path. However, CDR circuits require significant overhead to re-establish the clock from the transmitted data. This overhead can consume a lot of power.

[0008] The prior art has the following disadvantages: lack of a combination of improved bandwidth, low latency and reduced power requirements for chips and chip packages. The prior art may require high power consumption structures, such as clock data recovery (CDR) circuits in the receive macro, phase locked loops (PLLs) on the receive side, and / or redundancy of forward error correction (FEC). Summary of the invention

[0009] According to an example embodiment, an integrated circuit communication architecture is provided, and the integrated circuit communication architecture includes a clock channel, a clock divider, and a first de-skew circuit. The clock channel is configured to transmit a clock signal from a first chip to a second chip at a first rate. The clock divider is located on the second chip, configured to receive a clock signal transmitted via the clock channel, and configured to create and transmit a first divided clock signal and a second divided clock signal according to the received clock signal. The first divided clock signal and the second divided clock signal are transmitted at a rate reduced compared to the first rate. The clock divider maintains the current mode logic properties of the first divided clock signal and the second divided clock signal. The first de-skew circuit is configured to receive and process the first divided clock signal and the second divided clock signal to allow sampling of data sent from the first chip to the second chip. A method corresponding to the above-mentioned integrated circuit communication architecture is also disclosed herein.

[0010] By using this embodiment, compared with other SerDes structures, data transmission between chips is achieved with high bandwidth, low latency, and low power requirements, and at the same time a forward error correction (FEC) structure is avoided.

[0011] According to another example embodiment, another integrated circuit communication architecture is provided, which includes a clock channel, a clock divider, and a first receiver and a second receiver on a second chip. The clock channel is configured to transmit a clock signal from the first chip to the second chip at a first rate. The clock divider is located on the second chip, is configured to receive a clock signal transmitted via the clock channel, and is configured to create and transmit a first divided clock signal and a second divided clock signal according to the received clock signal. The first divided clock signal and the second divided clock signal are transmitted at a rate reduced compared to the first rate. The clock divider is configured to provide each of the first divided clock signal and the second divided clock signal to both the first receiver and the second receiver.

[0012] With this embodiment, data transmission between chips is achieved with reduced power requirements for processing the clock signal on the receiving side.Multiple clock channels for a single chip receiver can be avoided.

[0013] According to an additional embodiment, the first divided clock signal is an in-phase clock signal and operates at one-quarter the data rate. The second divided clock signal can be a quadrature clock signal and can operate at one-quarter the data rate. The quadrature clock signals can be offset by ninety degrees.

[0014] With this embodiment, high bandwidth and low latency data transmission is achieved via the interconnection between chips, the performance requirements for the clock path circuit are reduced, and the need for an IQ generator for each channel is eliminated. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof read in conjunction with the accompanying drawings. The various features of the drawings are not to scale as the illustrations are for the purpose of clarity and are intended to assist those skilled in the art in understanding the present invention in conjunction with the detailed description. In the drawings:

[0016] Figure 1 is a block diagram illustrating a chip package having a clock signal separation feature according to at least one embodiment;

[0017] Figure 2 A graphical comparison showing signal frequencies of various signals implemented using a clock signal separation feature according to at least one embodiment;

[0018] Figure 3 is another block diagram illustrating another chip package having a clock signal separation feature according to at least one embodiment;

[0019] Figure 4 is an operational flow diagram illustrating a clock signal separation process according to at least one embodiment; and

[0020] Figure 5 is a block diagram of internal and external components of a computer system in which one or more of the chip packages described herein may be implemented. DETAILED DESCRIPTION

[0021] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be implemented in a variety of forms. The present invention may be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. In the specification, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0022] The example embodiments described below provide an integrated circuit communication architecture that includes an improved interconnection between computer chips on a package. With the improved interconnection, processor core counts and memory bandwidth can be expanded for the package. A package with improved interconnection can achieve high bandwidth with low latency, allow lower power consumption, and avoid the evaluation chip structure of manufacturing. Therefore, a computer system with an improved circuit communication architecture for a processor as described herein achieves enhanced computing performance. The improved interconnection can be achieved by implementing clock signal forwarding and clock signal separation, which generates a separated clock signal with a reduced frequency. Clock signal forwarding can occur via a clock signal channel that is physically separated from one or more data channels. It is also possible to achieve improved interconnection by removing a clock divider from a chip receiver so that it is located outside any specific receiver on a receiving chip, so that the clock divider can separate the clock signal to have a reduced frequency separation signal that can serve multiple receivers on the packaged chip. With these features, the improved interconnection also reduces space requirements by requiring a single clock channel between the transmitter-receiver pair of the chip on the chip package instead of multiple clock channels.

[0023] Figure 1 A block diagram illustrating a first chip package 100 with improved interconnections according to at least one embodiment is shown. The first chip package 100 implements protection features to protect the circuit system, wiring and / or processing components of the first chip package 100. The first chip package 100 can be formed of a support material, which can include a plastic material and / or a ceramic material. The first chip package 100 has material strength and can be connected to a larger computer board, such as a printed circuit board and / or a motherboard.

[0024] Figure 1 A first chip 102 and a second chip 104 are shown, both connected to a first chip package 100. The first chip 102 and the second chip 104 may be directly connected to the first chip package 100. In the embodiment shown, the first chip 102 and the second chip 104 have a controlled collapse chip connection to the first chip package 100. Other embodiments may include separate chips connected to the chip package via other connection implementations. The chip is a computer chip and may be formed of a variety of materials including semiconductor materials such as silicon.

[0025] Each of the chips may include various components such as cores, cache, and input / output (I / O). Figure 1The transmitter 106 of the first chip 102 and the receiver 108 of the second chip 104 are illustrated to help illustrate various aspects of the interconnection between the first chip 102 and the second chip 104. The transmitter 106 can send data to the receiver 108 via the interconnection. The receiver 108 can receive and process the sent data, and transmit the received and processed data to other components on the second chip (such as cores, caches, and input / output), and / or to other chips or off-chip memories. In practice, the first chip 102 and the second chip 104 can each include multiple transmitters and multiple receivers for communicating with other chips, memories, and / or other chip components.

[0026] Figure 1 It is shown that the interconnection between the first chip 102 and the second chip 104 may include a plurality of channels, including a data channel 116 and a clock signal channel 124. Data in the form of bits having corresponding binary values ​​may be sent via the data channel 116. A clock signal may be sent via the clock signal channel 124 and may be used to coordinate the processing of data received via the data channel 116.

[0027] Figure 1 The symbol " / " in the connection / line shows that differential signaling is being implemented. For differential signaling, two complementary voltage signals can be generated and sent. When they are received, the signals can be combined to produce an information signal. In other embodiments, channels with enhanced interconnects can implement other signaling types instead of differential signaling. For example, in other embodiments, each of the channels of the interconnect can be used to perform single-ended signaling.

[0028] Figure 1 The transmitter 106 is shown to include a serializer block 110 and a data channel driver 114 for generating a data stream through a data channel 116. The receiver 108 may include an equalizer 118, one or more sampling latches, and a deserializer 130 for receiving data transmitted through the data channel 116. The equalizer 118 may perform termination and equalization of the received data. The illustrated embodiment includes a plurality of sampling latches, namely a first sampling latch 6a, a second sampling latch 6b, a third sampling latch 6c, and a fourth sampling latch 6d. The sampling latch uses a clock signal generated by a de-skew circuit 128 to accurately sample the data transmitted via the data channel 116. With the four sampling latches shown, data may be sampled at C4 clock intervals of 0, 90, 180, and 270 degrees via the first sampling latch 6a, the second sampling latch 6b, the third sampling latch 6c, and the fourth sampling latch 6d, respectively.

[0029] The clock generator 120 can generate a clock signal to send the clock signal along the clock signal channel 124. The clock generator 120 can include current mode logic, and the generated clock signal can be fed to the clock channel driver 122 and to the serializer block 110. The clock signal in the illustrated embodiment can be in the form of a square wave with a fixed, constant frequency that oscillates between a value and a zero value. The clock generator 120 can generate a full-rate clock signal. The full-rate clock signal is usually half the rate of the data transmission that occurs in the data channel 116. The clock signal can be used for synchronization at the rising edge, the falling edge, and / or the rising and falling edges of the clock signal. In some embodiments, the clock channel driver 122 can be the same structure as the data channel driver 114, but is used to drive the clock signal instead of data.

[0030] The clock generator 120 can feed the generated clock signal to the serializer block 110 inside the transmitter 106. The serializer block 110 serializes the data according to the clock signal. The serialized data will then be driven by the data channel driver 114. The data can be driven by both the rising and falling edges of the clock, thereby generating data with a rate twice the rate of the clock signal, i.e., a double data rate.

[0031] The data channel 116 and the clock signal channel 124 may each be formed via a corresponding metal trace on the protective material of the chip package 100. The metal trace physically connects the first chip 102 to the second chip 104. Signals may be transmitted via the metal trace.

[0032] like Figure 1As shown, the second chip 104 includes a clock divider 126, which is arranged outside the receiver 108. In at least some embodiments, the location of the de-skew circuit (such as the de-skew circuit 128) can be considered as the physical boundary of the receiver 108. The clock divider 126 is configured to receive a clock signal transmitted via the clock signal channel 124, and is configured to create and transmit a first divided clock signal and a second divided clock signal according to the received clock signal. The first divided clock signal and the second divided clock signal can each have a rate reduced compared to the first rate at which the original clock signal is generated. In the embodiment shown, the first divided clock signal can be an in-phase signal. The second divided clock signal can be an orthogonal clock signal. In the embodiment shown, the two divided clock signals run at half the rate of the original clock signal, that is, run at a quarter of the data rate. The in-phase signal can maintain the same phase as the phase of the original clock signal. The orthogonal clock signal can have a phase offset compared to the phase of the original clock signal. This offset is the basis for using the name "quadrature" for this divided clock signal. In at least some embodiments, this offset can be by an amount of ninety degrees.

[0033] The clock divider 126 can generate these reduced frequency clock signals while maintaining the current mode logic (CML) properties of the clock signals. CML circuits have lower output voltage swings than static CMOS circuits and are well known to those skilled in the art. CML circuits have improved performance due to the lower voltage swing and due to the differential nature of the signal. Differentiation helps make the clock signal more tolerant to power supply noise and more resilient to the possibility of collapse. The clock divider 126 receives the clock signal from the clock channel 124 without any intermediate signal buffering and without any intermediate voltage swing level adjustment of the clock signal. For example, in at least one embodiment, the clock signal is received by the clock divider 126 without the clock signal being buffered to CMOS swing levels. By maintaining the CML properties and not buffering to CMOS levels, higher bandwidth can be achieved.

[0034] Figure 2 A graphical comparison of signal frequencies of various signals implemented using a clock signal separation feature according to at least one embodiment is shown. Data signals transmitted via data channel 116 are shown as differential signaling pairs oscillating at a first rate or frequency. Baseband refers to the time between two immediately corresponding edges in a signal, such as the time between two closest rising edges in a signal or the time between two closest falling edges in a signal. C2 clock signal refers to an original clock signal generated via clock generator 120 and transmitted via clock signal channel 124. Figure 2The diagram shows that the clock signal oscillates at half the data rate. If the data signal runs at 20 Gbits per second (50 ps per bit) through the data channel 116, the clock signal will oscillate at 10 Gbits per second (100 ps period) through the clock signal channel 124. Figure 2 The C4 clock in-phase and C4 clock quadrature-phase lines shown are examples of first and second divided clock signals that are generated via a clock divider 126 that receives the clock signal from a clock signal channel 124 and oscillates at a reduced rate compared to the clock signal. Figure 2 These two signals are shown oscillating at half the rate of the C2 clock signal, ie, at one quarter the rate of the data signal. Figure 2 It is shown that the in-phase clock signal maintains the phase of the C2 clock signal, but the quadrature clock signal is shifted ninety degrees to be out of phase with respect to the C2 clock signal.

[0035] By distributing these lower frequency clock signals, the power requirements for these clock signals are reduced throughout the chips. As the frequency is reduced, the circuits distributing these clock signals can be powered down. However, the de-skew circuit 128 still successfully corrects the phase of the reduced frequency clock signal so that the data from the data channel 116 can be correctly sampled.

[0036] The clock divider 126 may additionally include a CML (current mode logic) circuit for correcting jitter in the received clock signal. Such jitter may be a timing variation of a set of signal edges relative to an ideal value and may be caused by noise or other interference in the second chip 104 or the chip package 100.

[0037] The divided clock signal is sent to the receiver 108, specifically, to the de-skew circuit 128 of the receiver 108. The de-skew circuit 128 corrects the phase of the divided clock signal so that the data received via the data channel 116 can be sampled. The de-skew circuit 128 mixes the two divided clock signals to generate a final clock signal, which can have an arbitrary phase with an edge different from the phase of the individual divided clock signals. Sampling can be based on the phase of the mixed signal. In at least one embodiment, the de-skew circuit 128 includes a first phase rotator to generate a first sampling clock signal. The de-skew circuit 128 may also include a second phase rotator to generate a second orthogonal sampling clock signal, which is offset ninety degrees relative to the first sampling clock signal. In other embodiments, the de-skew circuit 128 may include a delay line or a delay locked loop instead of a phase rotator to correct the phase of the divided clock signal. The de-skew circuit 128 synchronizes the divided clock signal with the data.

[0038] Figure 3 is another block diagram illustrating another chip package 300 having a clock signal separation feature according to at least one embodiment. The other chip package 300 includes Figure 1 The illustrated chip package 100 exhibits mostly similar clock forwarding and clock signal separation and frequency reduction concepts. Figure 3 The concept is illustrated that another clock divider 326 on another second chip 304 can create a divided clock signal that serves multiple receivers on another second chip. Figure 3 In the example shown, another clock divider 326 receives a clock signal via another clock signal channel 324, generates a first frequency-reduced divided clock signal and a second frequency-reduced divided clock signal, such as an in-phase clock signal and a quadrature clock signal, based on the received clock signal, and then transmits the two frequency-reduced divided clock signals to a first receiver 308a and to a second receiver 308b, both of which are located on another second chip 304. Although Figure 3 Another clock divider 326 is shown serving two receivers, but in other embodiments, the clock divider can generate a frequency-reduced split signal to serve more than two receivers. In this embodiment, another clock divider 326 can generate a frequency-reduced clock signal as a CMOS or CML clock signal.

[0039] therefore, Figure 3 Architectural aspects for an interconnect architecture to achieve the additional power and space saving requirements of not requiring each of the receivers to have its own clock divider channel are illustrated. Figure 3 Also includes Figure 1 Some advantages of the architecture shown in are that by distributing a lower frequency clock signal on the receiving chip, the power requirements of the receiving chip can be reduced.

[0040] for Figure 3 In the interconnect structure shown, each of the first and second receivers 308a and 308b includes its own de-skew circuit, which is equivalent to Figure 1 The first and second receivers 308a, 308b may receive data signals via first and second data channels 316a, 316b, respectively. The data signals may be transmitted via first and second transmitters 306a, 306b, respectively, on another first chip 302. Another clock generator 320 may generate a first half-rate clock signal for another clock signal channel 324. Another clock generator 320 may pass the clock signal to another driver 322, which drives the clock rate signal through another clock signal channel 324.

[0041] For simplicity, the internal components of the first and second transmitters 306a, 306b and the first and second receivers 308a, 308b are not shown in FIG. Figure 3 , but can be equivalent to Figure 1 1 and described above correspond to the internal components of the transmitter 106 and the receiver 108.

[0042] Figure 3 The symbol " / " in the connection / line shows that differential signaling is being implemented. For differential signaling, two complementary voltage signals can be generated and transmitted. When they are received, the signals can be combined to produce an information signal. In other embodiments where a clock divider on a receiving chip serves multiple receivers on a receiver chip, the channels with enhanced interconnects can implement other signaling types instead of differential signaling. For example, in other embodiments, each of the channels of the interconnect can be utilized to perform single-ended signaling.

[0043] Figure 4 is a flow chart illustrating the operation of a clock signal separation process 400 according to at least one embodiment, which may be performed using Figure 1 and / or the improved interconnect architecture shown in 3.

[0044] In step 402 of the clock signal separation process 400 , data is sent from a first chip to a second chip via a data channel. Figure 1 An example is shown where data is transmitted from the transmitter 106 of the first chip 102 to the receiver 108 of the second chip 104 via the data channel 116 . Figure 3 An example is shown where data is sent from another first chip 302 via multiple data channels, namely via a first further data channel 316a and a second further data channel 316b, to another second chip 304. Both the first chip and the second chip may be physically part of a single chip package.

[0045] In step 404 of the clock signal separation process 400 , a clock signal is sent from the first chip to the second chip via a clock signal channel. The clock signal channel may be physically separated from one or more data channels involved in step 402 . Figure 1 An example of a clock generator 120 is shown that generates a clock signal that is sent from the first chip 102 to the second chip 104 via the clock signal channel 116 . Figure 3 An example of another clock signal channel 316 for sending a clock signal from another first chip 302 to another second chip 304 is shown.

[0046] In step 406 of the clock signal separation process 400 , the clock signal is divided by a clock divider at the second chip. The clock signal refers to the clock signal sent in step 404 . Figure 1 An example of a clock divider 126 is shown that divides and separates the clock signal into a first divided clock signal and a second divided clock signal. Figure 3 An example of another clock divider 326 is shown, which divides and separates the clock signal into a first divided clock signal and a second divided clock signal. The divided clock signal may have a reduced frequency compared to the frequency of the original clock signal. The divided clock signal may include an in-phase clock signal and a quadrature clock signal, each of which runs at half the frequency of the original clock signal. The quadrature clock signal may have a phase that is offset by ninety degrees compared to the original clock signal. The clock divider may be provided external to any receiver on the second chip.

[0047] In step 408 of the clock signal separation process 400, the separated / divided clock signals are sent to de-skew circuits in one or more receivers of the second chip. The separated / divided clock signals are those generated in step 406. Figure 1 An example is shown in which the divided clock signal from the clock divider 126 is input to the de-skew circuit 128 within the receiver 108 of the second chip. Figure 3 In the illustrated embodiment, the divided signal from the further clock divider 326 is input to a de-skew circuit within the first further receiver 308 a and to another de-skew circuit within the second further receiver 308 b. The de-skew circuit may include one or more phase rotators, delay lines and / or delay locked loops for correcting the phase of the divided signal.

[0048] In step 410 of clock signal separation process 400, the separated clock signals are mixed to create the changed final clock signals. The de-skew circuit involved in step 408 can create these changed final clock signals based on the divided clock signals. The changed final clock signal can have any phase, with an edge different from the phase of the separate divided clock signal. For example, if a zero-degree phase and a ninety-degree phase are received for the separated clock signals, the changed final clock signal can have a forty-five-degree phase or a phase with any combination of the divided clock signals. The de-skew circuit can transmit a separate clock signal to each sampling latch, for example, a total of four separate clock signals can be transmitted for a total of four sampling latches.

[0049] In step 412 of the clock signal separation process 400, the mixed signal is fed to a sampling latch to sample the received data. The mixed signal refers to the altered final clock signal created in step 410. Figure 1 An exemplary embodiment with four sampling latches is shown, namely a first sampling latch 6 a , a second sampling latch 6 b , a third sampling latch 6 c and a fourth sampling latch 6 d involved in step 412 . Figure 3 A first further receiver 308a and a second further receiver 308b are shown. Each of these further receivers 308a, 308b comprises a sampling latch which receives the mixed signal from a de-skew circuit within these further receivers 308a, 308b, respectively.

[0050] In step 414 of the clock signal separation process 400, received data is sampled according to the clock signal. The received data refers to the data sent in step 402. The data is received by the same receiver that has the de-skew circuit involved in steps 408 and 410 and has the sampling latch involved in step 412. Figure 1 The data is shown sampled at a plurality of sampling latches and fed to the deserializer 130. Figure 3 In the embodiment shown in , data from the first further data channel 316a and the second further data channel 316b may be sampled according to the clock signal as part of step 414 .

[0051] Understandably, Figure 1-Figure 4 Only some embodiments are provided for illustration, without indicating any limitation on how to implement different embodiments. Many modifications may be made to the illustrated (one or more) embodiments (eg, to the described structures, process flows and / or step sequences) based on design and implementation requirements.

[0052] Figure 55 is a block diagram of internal and external components of a computer system that can implement one or more of the chip packages described herein. Computing environment 500 shows an example of one or more computers with processors in which the above-described enhanced circuit system interconnect architecture can be implemented. Computing environment 500 includes, for example, computer 501, wide area network (WAN) 502, end user device (EUD) 503, remote server 504, public cloud 505, and private cloud 506. In this embodiment, the computer 501 includes a processor set 510 (including a processing circuit 520 and a cache 521), a communication structure 511, a volatile memory 512, a persistent storage 513 (including an operating system 522 and a software program 516, a peripheral device set 514 (including a user interface (UI) device set 523, a storage 524, and an Internet of Things (IoT) sensor set 525), and a network module 515. The remote server 504 includes a remote database 530. The public cloud 505 includes a gateway 540, a cloud orchestration module 541, a host physical machine set 542, a virtual machine set 543, and a container set 544. The processing circuit 520 of the computer 501 and the processing circuit of the remote server 504 can each include an enhanced interconnect architecture as described above.

[0053] Computer 501 may take the form of a desktop computer, a laptop computer, a tablet computer, a smart phone, a smart watch or other wearable computer, a mainframe computer, a quantum computer, or any other form of computer or mobile device now known or developed in the future that is capable of running programs, accessing a network, or querying a database such as remote database 530. As is well known in the art of computer technology, and depending on the technology, the execution of computer-implemented methods may be distributed among multiple computers and / or among multiple locations. On the other hand, in this presentation of computing environment 500, the detailed discussion focuses on a single computer, and more particularly, on computer 501, to keep the presentation as simple as possible. Computer 501 may be located in the cloud, even though it is not limited to a single computer. Figure 1 It is not shown in the cloud. On the other hand, computer 501 does not necessarily have to be in the cloud.

[0054] Processor set 510 includes one or more computer processors of any type known now or to be developed in the future. Processing circuit 520 can be distributed over multiple packages, such as multiple coordinated integrated circuit chips. Processing circuit 520 can implement multiple processor threads and / or multiple processor cores. Cache 521 is a memory located in (one or more) processor chip packages, and is generally used for data or code that should be available for rapid access by threads or cores running on processor set 510. Cache memory is generally organized into multiple levels according to relative proximity to the processing circuit. Alternatively, some or all of the caches of the processor set may be located "off chip". In some computing environments, processor set 510 may be designed to work with qubits and perform quantum computing.

[0055] Computer readable program instructions are typically loaded onto the computer 501 to cause the processor set 510 of the computer 501 to perform a series of operating steps. These computer readable program instructions are stored in various types of computer readable storage media, such as cache 521 and other storage media discussed below. The program instructions and associated data are accessed by the processor set 510 to control and direct the execution of the method of the present invention.

[0056] Communications fabric 511 is a signal conduction path that allows some components of computer 501 to communicate with each other. Typically, the fabric is made up of switches and conductive paths, such as those that make up a bus, a bridge, physical input / output ports, etc. Other types of signal communication paths may be used, such as fiber optic communication paths and / or wireless communication paths.

[0057] Volatile memory 512 is any type of volatile memory now known or developed in the future. Examples include dynamic random access memory (RAM) or static RAM. Typically, volatile memory 512 is characterized by random access, but this is not required unless expressly stated. In computer 501, volatile memory 512 is located in a single package and is internal to computer 501, but, alternatively or additionally, volatile memory can be distributed over multiple packages and / or located externally relative to computer 501.

[0058] Persistent storage 513 is any form of non-volatile storage for computers known now or developed in the future. The non-volatility of the storage means that the stored data is maintained regardless of whether power is supplied to the computer 101 and / or directly to the persistent storage 513. Persistent storage 513 can be a read-only memory (ROM), but typically at least a portion of the persistent storage allows writing of data, deletion of data, and rewriting of data. Some common forms of persistent storage include magnetic disks and solid-state storage devices. Operating system 522 can take several forms, such as various known proprietary operating systems or operating systems of the type of open source portable operating system interface that employs a kernel.

[0059] The peripheral device set 514 includes a collection of peripheral devices of the computer 501. The data communication connection between the peripheral devices and other components of the computer 501 can be implemented in a variety of ways, such as a Bluetooth connection, a near field communication (NFC) connection, a connection by a cable (such as a universal serial bus (USB) type cable), a plug-in type connection (e.g., a secure digital (SD) card), a connection through a local area communication network, and even a connection through a wide area network such as the Internet. In various embodiments, the UI device set 523 may include components such as display screens, speakers, microphones, wearable devices (such as goggles and smart watches), keyboards, mice, printers, touchpads, game controllers, and tactile devices. Storage 524 is an external storage device, such as an external hard drive, or a pluggable storage device, such as an SD card. Storage 524 can be persistent and / or volatile. In some embodiments, storage 524 can take the form of a quantum computing storage device for storing data in the form of quantum bits. In embodiments where the computer 501 needs to have a large amount of storage (e.g., where the computer 501 locally stores and manages a large database), the storage can be provided by peripheral storage devices designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The IoT sensor set 525 is composed of sensors that can be used in IoT applications. For example, one sensor can be a thermometer, while another sensor can be a motion detector. The various sensors and / or UI devices can each individually include a package having an enhanced interconnect architecture as described herein.

[0060] The network module 515 is a collection of computer software, hardware, and firmware that allow the computer 501 to communicate with other computers via the WAN 502. The network module 515 may include hardware such as a modem or a Wi-Fi signal transceiver, software for packetizing and / or depacketizing data transmitted over a communication network, and / or web browser software for transmitting data over the Internet. In some embodiments, the network control function and the network forwarding function of the network module 515 are executed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software defined networks (SDN)), the control function and the forwarding function of the network module 515 are executed on physically separated devices so that the control function manages several different network hardware devices. Computer-readable program instructions for executing the method of the present invention can generally be downloaded to the computer 501 from an external computer or an external storage device via a network adapter card or a network interface included in the network module 515.

[0061] WAN 502 is any wide area network (e.g., the Internet) capable of transmitting computer data over non-local distances by any technology known now or developed in the future for transmitting computer data. In some embodiments, WAN 502 may be replaced and / or supplemented by a local area network (LAN) designed to transmit data between devices located in a local area, such as a Wi-Fi network. WANs and / or LANs typically include computer hardware, such as copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and edge servers.

[0062] End-user device (EUD) 503 is any computer system used and controlled by an end-user (e.g., a customer of an enterprise operating computer 501), and may take any form discussed above in conjunction with computer 501. EUD 503 typically receives helpful and useful data from the operation of computer 501. For example, in the hypothetical case where computer 501 is designed to provide recommendations to an end-user, the recommendation would typically be transmitted to EUD 503 from network module 515 of computer 501 via WAN 502. In this way, EUD 503 may display or otherwise present the recommendation to the end-user. In some embodiments, EUD 503 may be a client device, such as a thin client, a heavy client, a mainframe computer, a desktop computer, etc. Each EUD 503 may include a package having an enhanced interconnect architecture as described herein.

[0063] Remote server 504 is any computer system that provides at least some data and / or functionality to computer 501. Remote server 504 may be controlled and used by the same entity that operates computer 501. Remote server 504 represents a machine(s) that collects and stores helpful and useful data for use by other computers, such as computer 501. For example, in the hypothetical case where computer 501 is designed and programmed to provide recommendations based on historical data, then the historical data may be provided to computer 501 from a remote database 530 of remote server 504. Remote server 504 may include a package having an enhanced interconnect architecture as described herein.

[0064] Public cloud 505 is any computer system available for use by multiple entities that provides on-demand availability of computer system resources and / or other computer capabilities, particularly data storage (cloud storage) and computing capabilities, without direct active management by users. Cloud computing typically leverages the sharing of resources to achieve consistency and economy of scale. Direct and active management of the computing resources of public cloud 505 is performed by computer hardware and / or software of cloud orchestration module 541. The computing resources provided by public cloud 505 are typically implemented by virtual computing environments running on various computers that make up a host physical machine set 542, which is a universe of physical computers in public cloud 505 and / or available to the public cloud. Each of these physical computers may include a corresponding package with an enhanced interconnect architecture as described herein.

[0065] The virtual computing environment (VCE) typically takes the form of a virtual machine from a virtual machine set 543 and / or a container from a container set 544. It should be understood that these VCEs can be stored as images and can be transferred between and among various physical machine hosts as images or after instantiation of the VCE. The cloud orchestration module 541 manages the transmission and storage of images, deploys new instantiations of VCEs, and manages active instantiations of VCE deployments. The gateway 540 is a collection of computer software, hardware, and firmware that allows the public cloud 505 to communicate over the WAN 502.

[0066] Some further explanation of virtualized computing environments (VCEs) will now be provided. A VCE can be stored as an "image." A new active instance of the VCE can be instantiated from the image. Two common types of VCEs are virtual machines and containers. Containers are VCEs that use operating system-level virtualization. This refers to an operating system feature in which the kernel allows the existence of multiple isolated user space instances, called containers. From the perspective of the programs running in them, these isolated user space instances typically behave like actual computers. Computer programs running on a normal operating system can utilize all of the resources of that computer, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, programs running inside a container can only use the contents of the container and the devices assigned to the container, a feature known as containerization.

[0067] Private cloud 506 is similar to public cloud 505, except that computing resources can only be used by a single enterprise. Although private cloud 506 is shown as communicating with WAN 502, in other embodiments, the private cloud can be completely disconnected from the Internet and can only be accessed through a local / private network. A hybrid cloud is a combination of multiple clouds of different types (e.g., private, community, or public cloud types), usually implemented by different vendors. Each of the multiple clouds remains a separate and discrete entity, but the larger hybrid cloud architecture is bound together by standardized or proprietary technologies that enable orchestration, management, and / or data / application portability between multiple constituent clouds. In this embodiment, both public cloud 505 and private cloud 506 are part of a larger hybrid cloud.

[0068] In computing environment 500, computer 501 is shown as being connected to the Internet (see WAN 502). However, in many embodiments, computer 501 will be isolated from the communication through the communication network and is not connected to the Internet, running as an independent computer. In these embodiments, the network module 515 of computer 501 may not be necessary or even desirable to ensure isolation and prevent external communication from entering computer 501. Independent computer embodiments are potentially advantageous at least in some applications of the present invention because they are generally safer. In other embodiments, computer 501 is connected to a secure WAN or secure LAN instead of WAN 502 and / or the Internet. In these network connection (i.e., non-independent) embodiments, system designers may want to take appropriate security measures known now or developed in the future to reduce risks so that incoming network communications do not lead to security vulnerabilities.

[0069] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functions and operations of possible implementations of the system and method according to various embodiments of the present invention. In some alternative implementations, the functions noted in the boxes may not occur in the order noted in the figures. For example, two boxes shown in succession can actually be implemented as a step, executed simultaneously, substantially simultaneously, in a partially or fully time-overlapping manner, or each box can sometimes be executed in the opposite order, depending on the functions involved. It will also be noted that each box illustrated in the block diagram and / or flow chart and the combination of boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs a specified function or action, or a combination of dedicated hardware and computer instructions.

[0070] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will also be understood that the terms "comprise", "include", "includes", "have", "with", etc., when used in this specification, specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their groups.

[0071] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or improvements to existing technologies on the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An integrated circuit communication architecture, comprising: a clock channel configured to transmit a clock signal from the first chip to the second chip at a first rate; a clock divider on the second chip, the clock divider configured to receive the clock signal transmitted via the clock channel and to create and transmit a first divided clock signal and a second divided clock signal based on the received clock signal, the first divided clock signal and the second divided clock signal being transmitted at a reduced rate compared to the first rate, the clock divider maintaining a current mode logic property of the first divided clock signal and the second divided clock signal; as well as A first de-skew circuit is configured to receive and process the first divided clock signal and the second divided clock signal to allow sampling of data sent from the first chip to the second chip.

2. The integrated circuit communication architecture according to claim 1, wherein: The first rate is half rate compared to the data rate.

3. The integrated circuit communication architecture according to claim 1, wherein: The first divided clock signal is an in-phase clock signal and runs at one quarter of the data rate.

4. The integrated circuit communication architecture according to claim 1, wherein: The second divided clock signal is a quadrature clock signal and runs at one quarter of the data rate.

5. The integrated circuit communication architecture according to claim 1, wherein: The clock divider includes one or more current mode logic circuits for low clock jitter.

6. The integrated circuit communication architecture according to claim 1, wherein: The first de-skew circuit includes one or more phase rotators for rotating the first divided clock signal and the second divided clock signal.

7. The integrated circuit communications architecture of claim 1, wherein the reduced rate of the first divided clock signal is half of the first rate.

8. The integrated circuit communications architecture of claim 1, wherein the reduced rate of the second divided clock signal is half the first rate. 9 . The integrated circuit communication architecture of claim 1 , further comprising a driver on the first chip, the driver configured to drive the clock signal through the clock channel. 10 . The integrated circuit communication architecture of claim 1 , further comprising a data channel configured to transmit data from the first chip to the second chip.

11. The integrated circuit communication architecture of claim 1, wherein the first de-skew circuit is disposed in a first receiver of the second chip, and the clock divider serves a plurality of receivers on the second chip.

12. A method for integrated circuit communication, the method comprising: sending a clock signal from the first chip to the second chip via a clock channel and at a first rate; dividing the transmitted clock signal via a clock divider at the second chip to form a first divided clock signal and a second divided clock signal having a reduced rate compared to the first rate; maintaining current mode logic properties of the first divided clock signal and the second divided clock signal via the clock divider; as well as The first frequency-divided clock signal and the second frequency-divided clock signal are input into a de-skew circuit of a receiver of the first chip. The method of claim 12 , wherein the first rate is half rate.

14. The method of claim 12, wherein the first divided clock signal is an in-phase clock signal and operates at one-quarter the data rate.

15. The method of claim 12, wherein the second divided clock signal is a quadrature clock signal and operates at one quarter of the data rate.

16. The method of claim 12, wherein the clock divider comprises one or more current mode logic circuits for low clock jitter.

17. The method of claim 12, wherein the first de-skew circuit comprises one or more phase rotators for rotating the first divided clock signal and the second divided clock signal.

18. An integrated circuit communication architecture, comprising: a clock channel configured to transmit a clock signal from the first chip to the second chip at a first rate; a clock divider on the second chip, the clock divider configured to receive the clock signal transmitted via the clock channel and to create and transmit a first divided clock signal and a second divided clock signal based on the received clock signal, the first divided clock signal and the second divided clock signal being transmitted at a reduced rate compared to the first rate; as well as a first receiver and a second receiver on the second chip; Wherein the clock divider is configured to provide each of the first divided clock signal and the second divided clock signal to both the first receiver and the second receiver.

19. The integrated circuit communication architecture of claim 18, wherein the first divided clock signal is an in-phase clock signal and operates at one-quarter the data rate.

20. The integrated circuit communication architecture of claim 18, wherein the second divided clock signal is a quadrature clock signal and operates at one quarter of the data rate.

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