Automatic test vector generation for analog and mixed signal circuits

Abstract

A method includes applying a predetermined DC voltage value to an analog input of an analog or mixed signal circuit design (710); a plurality of bit value sets generated by a scan-based structure test for a circuit manufactured on the basis of the circuit design are converted into a plurality of bit value sets. One set of bit values within each of a plurality of consecutive time intervals is applied to an input of one or more node-connected devices coupled with or to be coupled with one or more selected internal nodes of the circuit design, to one or more selected digital inputs of the circuit design, or to both (720); and performing a simulation on the circuit design to determine, for each set of bit values, an expected test response bit value at an output of one or more threshold comparison converters, and if the circuit design has a selected digital signal node, an expected test response bit value at the selected digital signal node (730). These operations may be repeated in the circuit design and inject defects.

Description

Technical Field

[0001] The technology disclosed in the present invention relates to the field of testing analog and mixed-signal circuits. Various implementations of the disclosed technology may be particularly useful for test pattern generation. Background Art

[0002] Integrated circuits are used in a wide range of applications such as consumer electronics, automotive, telecommunications, cloud computing, and artificial intelligence. While digital circuits form the core of most electronic systems today, these electronic systems are increasingly adopting mixed-signal designs, embedding analog or mixed-signal blocks and digital circuits such as processors, logic blocks, and memory blocks on a single die. Here, a mixed-signal block is a circuit block that includes both analog and digital circuits.

[0003] The manufacturing of integrated circuits involves a series of lithography, printing, etching, implantation, and chemical vapor deposition steps. This process is imperfect and can lead to manufacturing defects. The continuous reduction of feature size further increases the probability of defective circuits. Very small defects can cause transistor failure or wire interconnection. Even a single transistor or wire failure can cause the entire chip to work improperly. Therefore, chips need to be tested during the manufacturing process. Faulty chips also need to be diagnosed to improve and maintain manufacturing yield.

[0004] Testing typically involves applying a collection of test stimuli (test vectors) to the circuit under test and then analyzing the responses produced by the circuit under test. Functional testing attempts to verify that the circuit under test operates according to its functional specifications. In contrast, structural testing attempts to determine that the circuit under test has been correctly assembled from some low-level building blocks as specified in the structural netlist, and that these low-level building blocks and their wiring connections have been manufactured without defects. For structural testing, the assumption is that if functional verification performed during the design phase has shown the correctness of the netlist, and structural testing performed during the manufacturing phase has confirmed the correct assembly of the structural circuit elements, then the circuit should function properly.

[0005] Structural testing has been widely used in digital circuit testing for decades. A major advantage of structural testing is that it enables test generation (test vector generation) to focus on testing a limited number of relatively simple circuit elements, rather than having to deal with an exponential explosion of multiple functional states and state transitions. However, the current practice for testing analog and mixed-signal circuits is still functional testing, also known as specification-based testing. Due to the nature of continuously variable analog signals and the various types of circuits used to process them, it becomes more challenging to find a simple and general mechanism to activate simulated faults or defects and capture test responses that do not require complex analysis.

[0006] Although it is easy to interpret the test results, specification-based testing relies on dedicated automatic test equipment (ATE) with advanced capabilities, and it takes a long time to run these tests. In addition, since the complete end-to-end functionality is tested, specification-based testing can be very time-consuming to simulate. Test generation automation has been developed only for very common and general functions, such as those of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), phase-locked loops (PLLs), serial / deserializers (SerDes), and regulators. This relies on using stimuli and transfer function analysis specific to the general functions. A general method has not yet been developed to generate tests for every type of circuit, especially for random analog circuits.

[0007] Analog defect simulation is often used to determine the defect coverage of a test set and is also time-consuming. Unlike the commonly used digital circuit fault model defined as a circuit node stuck at logic 0 or 1, modeling short circuit defects in analog circuits typically includes adding a 1Ohm to 100Ohm resistor between two circuit nodes, and modeling open circuit defects in analog circuits typically includes inserting a 0.1GOhm to 10GOhm resistor in the connection between two transistors. Each potential defect is simulated one at a time, and each such simulation can take from several minutes to several days. With traditional techniques, test equipment costs, test generation time, and test execution time have been affected and will continue to be affected. Summary of the invention

[0008] Various aspects of the disclosed technology relate to automatically generating test vectors for structural testing of analog and mixed-signal circuits. In one aspect, there is a method comprising: applying a predetermined DC voltage value to an analog input of a circuit design, if the circuit design has analog inputs, the circuit design being at least partially analog; applying a plurality of sets of bit values ​​generated for scan-based structural testing of a circuit fabricated based on the circuit design, one of the plurality of sets of bit values ​​during each of a plurality of consecutive time intervals, to inputs of one or more node connection devices coupled to or to be coupled to one or more selected internal nodes of the circuit design, to one or more selected digital inputs of the circuit design, or to both, each of the one or more node connection devices being configured to couple or decouple at least one of the one or more selected internal nodes to or from another node of the circuit based on a bit value at an input of each of the one or more input node connection devices, each of the plurality of consecutive time intervals being equal to one or more clock cycles of a scan clock signal for scan-based structural testing of the circuit; and performing simulation on the circuit design to determine, for each of the plurality of sets of bit values, an expected test response bit value at an output of one or more threshold comparison converters, and, if the circuit design has selected digital signal nodes, to determine an expected test response bit value at a selected digital signal node. Each of the one or more threshold comparison converters is coupled to or to be coupled to one of the one or more selected nodes of the circuit design and includes one or more threshold comparison subconverters. Each of the one or more threshold comparison subconverters is configured to output a bit value at one of the outputs of each of the one or more threshold comparison converters based on comparing a voltage value at one of the one or more selected nodes with one of the one or more preset thresholds. In a scan-based structural test of the circuit, at least some bits of the plurality of bit value sets are applied to each of the circuits using one or more scan chains in each of the circuits, and test response bit values ​​at at least some of the outputs of the one or more threshold comparison converters are captured by the one or more scan chains.

[0009] If the voltage value at one of the one or more selected nodes is within a preset range centered at one of the one or more preset threshold values, the bit value output by each of the one or more threshold comparison subconverters is considered to be uncertain. Alternatively or additionally, if the simulation is repeatedly performed for different combinations of process parameter values, and the bit values ​​are different for all different combinations of process parameter values, the bit value output by each of the one or more threshold comparison subconverters is considered to be uncertain.

[0010] The plurality of sets of bit values ​​may be generated based on random combinations of bit values ​​or all combinations of bit values.The one or more selected internal nodes and the one or more selected nodes may be selected based on user specifications, circuit topology, or both.

[0011] The number of bit values ​​at the input of each of the one or more input node connection devices may be 1 or 2, and each of at least some of the one or more node connection devices may be configured to couple a selected internal node to any one of two other nodes of the circuit or not to the two other nodes of the circuit based on the 2-bit value. Each of the one or more threshold comparison subconverters may be implemented by an inverter, and each of the one or more threshold comparison subconverters may include up to two threshold comparison subconverters.

[0012] The method may further include: injecting defects into the circuit design; performing operations on the circuit design with the defects injected to determine a set of test vectors that can detect at least some of the defects. The defects can be injected into the circuit design one at a time for simulation. The method may still further include: determining a reduced set of test vectors that can detect at least some of the defects based on the test vector set. The reduced set of test vectors may retain some consecutive test vectors in the test vector set. A greedy algorithm may be used to determine the reduced set of test vectors. The method may still further include: removing switching devices in the one or more node connection devices that do not make a unique contribution to the detection of the defects, removing threshold comparison sub-converters in the one or more threshold comparison converters that do not make a unique contribution to the detection of the defects, or removing both.

[0013] In another aspect, there are one or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform the above-described method.

[0014] In yet another aspect, there is a system comprising: one or more processors programmed to perform the above method.

[0015] Certain innovative aspects are set out in the accompanying independent and dependent claims. Features of the dependent claims may be combined with features of the independent claims as appropriate as well as features of other dependent claims and not only as explicitly set out in a claim.

[0016] Here, some objects and advantages of various inventive aspects have been described above. Of course, it should be understood that not all of these objects or advantages can be achieved according to any specific embodiment of the disclosed technology. Thus, for example, those skilled in the art will recognize that the disclosed technology can be embodied or performed in a manner that achieves or optimizes one advantage or a group of advantages taught herein without necessarily achieving other objects or advantages taught or suggested herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A An example scan chain is shown.

[0018] Figure 1B An example scan chain with updating storage elements is shown.

[0019] Figure 2 An example of a scan-based test circuit for testing analog / mixed-signal circuits according to various embodiments of the disclosed technology is shown.

[0020] Figure 3A An example CMOS inverter used as a threshold comparison subconverter with a high threshold and its transfer function curve are shown.

[0021] Figure 3B An example CMOS inverter used as a threshold comparison subconverter with a low threshold and its transfer function curve are shown.

[0022] Figure 3C An exemplary bias voltage generator is shown.

[0023] Figure 3D An exemplary threshold comparison converter including two threshold comparison subconverters having two different thresholds and its transfer function curve are shown.

[0024] Figure 4A An example node connection device including a switching device implemented using a PMOS transistor is shown.

[0025] Figure 4B An example node connection device including a switching device implemented using an NMOS transistor is shown.

[0026] Figure 4C An example node connection device including two switching devices each implemented using two transistors is shown.

[0027] Figure 5A An example circuit schematic for a simulation circuit is shown.

[0028] Figure 5B Shows Figure 5A An example netlist for the analog circuit in .

[0029] Figure 5C An example netlist for three node connection devices coupled to three selected internal nodes to inject test stimulus and an example netlist for a threshold comparison switch coupled to one of the three selected nodes to observe a test response is shown.

[0030] Figure 6 An example circuit schematic for a circuit that includes both analog and digital circuits is shown.

[0031] Figure 7 A flow chart is shown illustrating a process of determining expected test responses for test vectors based on simulation of a defect-free analog / mixed-signal circuit design that can be implemented according to various examples of the disclosed technology.

[0032] Figure 8 Shown is applied to Figure 5A Example of the voltage at the analog input of the circuit in Figure 1, applied as a test stimulus at nine consecutive time intervals. Figure 5A An example of nine sets of bit values ​​for the circuit in , and an example of expected test response bit values ​​captured during nine consecutive time intervals.

[0033] Fig. 9 Shown is the method for determining Figure 5A An example of an uncertain bit in the expected test response bit value for the circuit in FIG.

[0034] Fig.10 A flow chart illustrating a process of simulating an analog / mixed-signal circuit design for multiple injected defects in accordance with various embodiments of the disclosed technology is shown.

[0035] Fig.11 A flow chart is shown illustrating a process of deriving a reduced set of test vectors using a greedy algorithm according to various embodiments of the disclosed technology.

[0036] Fig. 12A Shows the Figure 5A The defect detection matrix for nine defects in the circuit forms an example of a reduced set of test vectors.

[0037] Fig. 12B shows the form for testing Figure 5A An example of a set of short sequences of reduced test vectors for a circuit in FIG.

[0038] Fig.13A shows the time intervals applied to Figure 5A A set of test vectors for the circuit in .

[0039] Fig. 13BA reduced set of test vectors for three time intervals and in the absence of rows are shown for an NMOS transistor (dftn0) and a PMOS transistor (dftp5).

[0040] Fig. 13C It shows how the reduced set of three test vectors is shifted into the serial bit stream applied to the scan chain.

[0041] Fig.14A The reduced test vector bit position set and the test response bit position are shown. Figure 5A Example defect detection matrix for the circuit in .

[0042] Fig. 14B An example of expected test response bit values ​​for each threshold comparison subconverter over nine consecutive time intervals is shown with the outlined reduced set of test vectors.

[0043] Fig. 14C Expected test response bit values ​​for only three time intervals associated with a reduced set of test vectors are shown.

[0044] Fig.14D A minimized set of expected test response bit values ​​for only the remaining threshold comparison subconverters is shown.

[0045] Fig.14E It is shown how a minimized set of expected test response bit values ​​can be shifted out along the scan chain.

[0046] Fig.15 Shown for Figure 5A Example of a test circuit for the circuit in .

[0047] Fig.16 An example of a programmable computer system is shown upon which various embodiments of the disclosed technology may be employed. DETAILED DESCRIPTION

[0048] Various aspects of the disclosed technology relate to automatically generating test vectors for structural testing of analog and mixed-signal circuits. In the following description, many details are set forth for the purpose of explanation. However, it will be appreciated by those of ordinary skill in the art that the disclosed technology can be implemented without using these specific details. In other cases, well-known features have not been described in detail to avoid obfuscating the disclosed technology.

[0049] Some of the techniques described herein may be implemented in software instructions stored on a computer-readable medium, software instructions executed on a computer, or some combination of the two. For example, some of the disclosed techniques may be implemented as part of an electronic design automation (EDA) tool. This method may be performed on a single computer or on a networked computer.

[0050] Although the operations of the disclosed methods are described in a particular order for ease of presentation, it should be understood that such description includes reordering unless specific language described below requires a particular ordering. For example, in some cases, operations described in order may be reordered or performed simultaneously. In addition, for the sake of simplicity, the disclosed flow charts and block diagrams generally do not illustrate the various ways in which a particular method may be used in conjunction with other methods.

[0051] The detailed description of the method or device sometimes uses terms such as "execution" and "application" to describe the disclosed method or device functions / structures. These terms are high-level descriptions. The actual operations or functions / structures corresponding to these terms will vary depending on the specific implementation and are easily recognized by those of ordinary skill in the art.

[0052] As used herein, the singular forms "a", "an", and "the" include plural forms unless the context clearly dictates otherwise. In addition, the term "include" means to include. Furthermore, unless the context dictates otherwise, the term "coupled" refers to an electrical or electromagnetic connection or link, and includes a direct connection or direct link as well as an indirect connection or indirect link through one or more intermediate elements that do not affect the intended operation of the circuit.

[0053] Additionally, as used herein, the term "design" is intended to encompass data that describes an entire integrated circuit device. However, the term is also intended to encompass smaller data sets that describe one or more components of the entire device (eg, a portion of an integrated circuit device).

[0054] As mentioned earlier, testing typically involves applying test vectors to the circuit under test and then capturing and analyzing the responses generated by the circuit under test. To make it easier to develop and apply test vectors, some testability features are added to the circuit design, which is called design for test or design for testability (DFT). Scan testing is the most commonly used DFT method. In the basic scan test scheme, all or most of the internal sequential state elements (latches, flip-flops, etc.) in the circuit design are made controllable and observable through a serial interface. These functional state elements are usually replaced by dual-purpose state elements called scan cells. Scan cells are connected together to form scan chains - serial shift registers for shifting in test vectors and for capturing and shifting out test responses. Scan cells have a dual purpose and can operate in functional / task mode as state elements originally intended for functional purposes, and in test mode as cells in a scan chain used to perform scan testing.

[0055] Figure 1A An example of a scan chain 100 is shown. The scan chain 100 includes a plurality of scan cells 110. Each scan cell 110 includes an edge-triggered flip-flop 120 and a bidirectional multiplexer 130 for data input. The bidirectional multiplexer 130 is typically controlled by a control signal 140 called scan_enable, which selects an input signal for the scan cell 110 from a scan signal input port 150 or a system signal input port 160 (sometimes referred to as a parallel input). The scan signal input port 150 is typically connected to the output of another scan cell in the scan chain 100, while the system signal input port 160 is connected to a functional circuit 170. Each scan cell 110 fans out into two outputs: a serial output coupled to a scan cell in the scan chain 100 and a parallel output coupled to the functional circuit 170.

[0056] In test mode, a scan cell such as scan cell 110 can be used as a control point for applying test stimulus bits to the circuit under test, or as an observation point for capturing test response bits generated by the circuit under test, or both. Test mode generally includes two types of operations: shift operation (shift mode) and capture operation (capture mode). In shift operation, a series of clock pulses, called "shift pulses" or "shift clock pulses", are applied to the scan cell. Each shift clock pulse pushes one bit of the test vector into each scan cell in the scan chain. This continues until all scan cells in the scan chain are filled with test vector bits. In capture operation, one or more clock pulses, called "capture pulses" or "capture clock pulses", are applied to the scan cell and the circuit under test as they would in normal operation. After the test vector bits stored in the scan cell are injected into the circuit under test, the results of the test (test response) are "captured" and stored in the scan cell. The scan unit then returns to the shift operation and with each additional clock pulse, one bit of the test response is pushed out or shifted out along the scan chain as each bit of the new test vector is pushed in or shifted in. The shifted out test response is then compared to the expected result to determine and locate any errors.

[0057] Figure 1B Another example of a scan chain 105 is shown. Figure 1A The parallel outputs of the scan chain 105 are indirectly coupled to the functional circuit 180 through the update storage element 190. The signal applied to the functional circuit 180 changes only when the update clock signal 195 is switched, rather than every time a shift occurs in the scan chain 105. This prevents the shift from changing the state of the functional circuit 180. Another benefit is the reduction of switching activity in the shift operation, which can significantly reduce power consumption and prevent circuit overheating. The update storage element 190 can be implemented using a latch or a flip-flop.

[0058] Figure 2An example of a scan-based test circuit 200 for testing analog / mixed signal circuits according to various embodiments of the disclosed technology is shown. The scan-based test circuit 200 includes one or more scan chains 210, threshold comparison converters 221, 222, and 223, and node connection devices 231, 232, and 233. The one or more scan chains 210 are configured to shift in and apply test vectors and capture and output test responses during testing. The threshold comparison converters 221, 222, and 223 have inputs coupled to selected nodes 226, 227, and 228 of the analog / mixed signal circuit, respectively, and outputs coupled to parallel inputs of the one or more scan chains 210. The threshold comparison converters 221, 222, and 223 can be configured to convert voltages at the selected nodes 226, 227, and 228 to test response bit values, and then the one or more scan chains 210 can capture the test response bit values ​​during testing. The node connection devices 231, 232, and 233 respectively have inputs coupled to the parallel outputs of the one or more scan chains 210 and outputs coupled to selected internal nodes 236, 237, and 238 of the analog / mixed signal circuit and their associated nodes. The node connection devices 231, 232, and 233 can be configured to apply test stimuli to the analog / mixed signal circuit through the selected internal nodes 236, 237, and 238 and their associated nodes during testing based on the test vector bit values ​​loaded in the one or more scan chains 210.

[0059] like Figure 2 As shown in , the threshold comparison converters 221, 222 and 223 include 1, 2 and 3 threshold comparison sub-converters 225, respectively. Each threshold comparison sub-converter 225 is configured to output a bit value based on comparing the voltage value at the associated selected node with a preset threshold. Specifically, the threshold comparison converter 221 can use one threshold comparison sub-converter 225 to convert the voltage at the selected node 226 into a one-bit test response value; the threshold comparison converter 222 can use two threshold comparison sub-converters 225 to convert the voltage at the selected node 227 into two one-bit test response values; the threshold comparison converter 223 can use three threshold comparison sub-converters 225 to convert the voltage at the selected node 228 into three one-bit test response values. Then, these digitized test response values ​​can be captured by one or more scan chains 210. Typically, the thresholds used by the threshold comparison sub-converters in the same threshold comparison converter are set to be different from each other, and the thresholds used by the threshold comparison sub-converters in different threshold comparison converters can be set to be the same or different.

[0060] Some circuits may have one or more digital signal nodes (such as node 229) that are selected to observe test responses. The test response bits at these selected digital signal nodes may be captured directly by one or more scan chains 210 without using a threshold comparison converter.

[0061] It should be noted that although threshold comparison converters 221, 222, and 223 are shown as having a maximum of three threshold comparison subconverters, in some embodiments of the disclosed technology, the threshold comparison converter may include more than three threshold comparison subconverters. In some other embodiments of the disclosed technology, each threshold comparison converter may include only one threshold comparison subconverter. In some other embodiments of the disclosed technology, each threshold comparison converter may include two threshold comparison subconverters. It should also be noted that the scan chain may be directly or indirectly coupled to the output of the threshold comparison converter. For example, a threshold comparison converter having four threshold comparison subconverters may have an output connected to an encoding device, which is configured to convert five possible output combinations into three-bit values. The output of the encoding device is connected to three scan units of the scan chain.

[0062] The threshold comparator subconverter can be implemented using complementary metal oxide semiconductor (CMOS) inverters. Each CMOS inverter can be constructed using a pair of p-type and n-type transistors. Figure 3A and Figure 3B Two examples of CMOS inverters 310 and 320 as threshold comparison subconverters and corresponding transfer function curves 315 and 325 are shown. Figure 3A In FIG. 3 , CMOS inverter 310 includes p-type transistor 311 and n-type transistor 312. The gate of p-type transistor 311 is coupled to input voltage signal 313, and the gate of n-type transistor 312 is coupled to bias voltage 314. Transfer function curve 315 indicates that the voltage threshold is higher than the mid-way between power supply voltage and ground. Based on whether the value of input voltage signal 313 is greater than the voltage threshold, CMOS inverter 310 can output logic "1" or "0". In FIG. Figure 3B In the embodiment, CMOS inverter 320 includes p-type transistor 321 and n-type transistor 322. The gate of p-type transistor 321 is coupled to bias voltage 324, and the gate of n-type transistor 322 is coupled to input voltage signal 323. Transfer function curve 325 indicates that the voltage threshold is lower than the intermediate value between power supply voltage and ground. Based on whether the value of input voltage signal 323 is greater than the voltage threshold, CMOS inverter 320 can output logic "1" or "0". Figure 3C An example bias voltage generator 330 is shown. The bias voltage generator 330 may generate bias voltages 314 and 324 when the enable signal 331 is "1".

[0063] Figure 3D An exemplary threshold comparison converter 340 including two threshold comparison subconverters 341 and 342 (which have two different thresholds) and a corresponding transfer function curve 345 are shown. The two threshold comparison subconverters 341 and 342 can be implemented using CMOS inverters 310 and 320, respectively. As shown in the corresponding transfer function curve 345, the threshold comparison converter 340 is equivalent to a 1.5-bit analog-to-digital converter: a 2-bit code is output when the input voltage 343 is lower than the first threshold 346, a second 2-bit code is output when the input voltage 343 is higher than the first threshold 346 but lower than the second threshold 347, and a third 2-bit code is output when the input voltage 343 is higher than the second threshold 347. The first threshold 346 is approximately the threshold voltage of an NMOS transistor higher than the reference ground voltage, and the second threshold 347 is approximately the threshold voltage of a PMOS transistor lower than the reference power supply voltage.

[0064] The threshold comparison subconverter may also be implemented using logic gates with voltage thresholds designed to be located at or offset from the mid-range between power and ground. Examples of logic gates include AND gates and multiplexers.

[0065] like Figure 2 As shown in , the node connection devices 231, 232 and 233 include two switching devices, one switching device and two switching devices, respectively. These switching devices can couple the selected internal nodes 236, 237 and 238 to their associated nodes or decouple the nodes associated with them based on the bit values ​​output by one or more scan chains 210. Specifically, the 2-bit value 241 enables the selected internal node 236 to be coupled to the node 242 or the node 243, or not to be coupled to either of the nodes 242 or 243; the 1-bit value 244 enables the selected internal node 237 to be coupled to the node 245 or decoupled from the node 245; and the 2-bit value 246 enables the selected internal node 238 to be coupled to the node 247 or the node 248, or not to be coupled to either of the nodes 247 or 248. In addition to the selected internal nodes, some circuits may also have one or more digital signal nodes, such as the node 249 selected for applying the test vector bit. Some other circuits may only select digital signal nodes to apply the test vector bit. In both cases, the test vector bits stored in the scan chain can be switched through digital multiplexers (see Fig.15 The example multiplexer 1565) in is applied to these selected digital signal nodes without the use of node connection devices.

[0066] It should be noted that although the node connection devices 231, 232, and 233 are shown as having a maximum of two switching devices, in some embodiments of the disclosed technology, the node connection devices may include more than two switching devices. In some other embodiments of the disclosed technology, each node connection device may include two switching devices. It should also be noted that the inputs of the node connection devices 231, 232, and 233 may be directly or indirectly coupled to the parallel outputs of one or more scan chains 210. In the indirect coupling, the update storage element (similar to Figure 1B The update storage element 190 in the scan chain 210 may be inserted between the inputs of the node connection devices 231 , 232 and 233 and the parallel outputs of one or more scan chains 210 .

[0067] According to various embodiments of the disclosed technology, a switching device in a node connection device may be implemented using a transistor, such as a metal oxide semiconductor field effect transistor (MOSFET). Figure 4A , Figure 4B and Figure 4C Three such examples are shown. Figure 4A In , when the 1-bit value 413 at the gate of transistor 410 is "0", transistor 410 can connect internal node 411 to power supply node (vdd0) 412 and when the 1-bit value 413 at the gate of transistor 410 is "1", transistor 410 can disconnect internal node 411 from power supply node (vdd0) 412. Figure 4B , when the 1-bit value 423 at the gate of transistor 420 is "1", transistor 420 can connect internal node 421 to ground node (Vss0) 422 and when the 1-bit value 423 at the gate of transistor 420 is "0", transistor 420 can disconnect internal node 421 from power ground node (Vss0) 422. Although node 412 is shown as a power node and node 422 is shown as a ground node, they can also be any other nodes, such as internal nodes.

[0068] exist Figure 4CIn the embodiment of the present invention, two transistors 430 and 435 can connect internal node 431 to node 432 or node 437 based on 2-bit code 433, or not be connected to any one of them. Each of node 432 and node 437 can be a power node, a ground node or other internal node. It should be noted that when node 432 and node 437 are of the same type, such as the drain (or source) of two transistors in a differential pair, two transistors 430 and 435 are usually of the same type, depending on the circuit, NMOS or PMOS, and when one of node 432 and node 437 is a power node and the other node is a ground node, two transistors 430 and 435 are usually of different types. It is usually undesirable to connect three nodes 431, 432 and 437 together at the same time, especially when one of node 432 and node 437 is a power node and the other node is a ground node. Therefore, the specific value of the 2-bit code 433 that enables this situation should be avoided. This can be achieved by adding some circuitry between the scanning unit and the gates of the switching devices 430 and 435 .

[0069] In the present disclosure, a node is any area of ​​a circuit between two or more circuit elements. In a circuit diagram, a connection is an ideal wire with zero resistance, so a node is the entire portion of wire between elements, not just a single point. An internal node of a circuit is a node that is not connected to either the circuit input (including power and ground) or the circuit output. A digital signal node is a node that is connected to at least the output or input of a digital circuit element such as a logic gate.

[0070] Nodes 226, 227, and 228 for observing test responses can be selected based on user specifications, circuit topology, or both. If the node has a sufficiently low impedance so that the input of the threshold comparison converter is connected to it without affecting the performance of the circuit, the node can be a good candidate for observing the test response. Some examples of such low impedance nodes include the output of a function and the output of an amplifier. The IEEE P1687.2 draft test access and control standard provides an instrument connection language (ICL) that specifies how to list the properties of the test-related ports of a circuit. These properties can be used to automatically identify the appropriate output ports of a circuit.

[0071] Similarly, internal nodes 236, 237, and 238 for applying test stimulus can be selected based on user specifications, circuit topology, or both. The number of circuit elements connected to the node can be used as a selection criterion, for example. The more circuit elements connected to the node, the more potential defects that the node connection device can activate. Additionally or alternatively, the parameters of the circuit elements can be used as a criterion. According to various embodiments of the disclosed technology, the channel width of the transistor can also be considered. As an example of user specifications, the source or drain of a transistor to which the user wants to add one or more switching devices for enhanced production aging testing (burn-in testing) can be selected as an internal node to apply test stimulus. Amplifiers are common analog devices, typically including differential pairs. The common drain or common source of the differential pair can be a good candidate as an internal node for applying test stimulus.

[0072] Figure 5A An example circuit schematic diagram of circuit 500 is shown, which illustrates some circuit elements, internal circuit nodes selected for application of test stimulus, and circuit nodes selected for test response observation in accordance with various embodiments of the disclosed technology. Figure 5B An example netlist of circuit 500 is shown. Circuit 500 includes two subcircuits 510 and 520. Netlist 515 represents subcircuit 510, netlist 525 represents subcircuit 520, and netlist 535 is a top-level netlist that includes instances 517 and 527 of two subcircuits 510 and 520. Circuit 500 has functional inputs 556 and 557, power input 551, ground input 552, power-down input 558, and clock input 559. Subcircuit 510 has output 547; subcircuit 520 has output 548.

[0073] In circuit 500, internal nodes 541, internal nodes 542, and internal nodes 543 are selected to apply test stimulus; node 546 and outputs 547 and 548 are selected to observe test responses. A node connection device including two switching devices can be inserted to control the connection of internal node 541 to power node (vdd0) 551 and ground node (Vss0) 552. Similarly, another node connection device including two switching devices can be inserted to control the connection of internal node 543 to power node (vdd0) 551 and ground node (Vss0) 552. Compared with the signal applied to the analog input (such as input 556 and input 557), digitally enabling the connection during the test can increase the voltage swing on more nodes of circuit 500. This may cause a small flaw in the gate oxide of the transistor to become a potential defect, which can be more easily detected by subsequent testing.

[0074] A third node connection device comprising two switching devices may be inserted to control the connection of internal node 542 to internal node 553 and another internal node 554. Through internal node 542 and two associated internal nodes 553 and 554, the equivalent of a small offset voltage may be digitally injected into the differential pair of transistors at the front end of the operational amplifier as a test stimulus. Such an amplifier may have a very high gain, so a very small stimulus amplitude is required to test whether the gain is actually high for each manufacturing implementation of the circuit. The voltage at node 547 may be used to check the gain. A threshold comparison converter (such as a threshold comparison subconverter) comprising two threshold comparison subconverters Figure 3D The threshold comparison converter 340 shown in FIG. 3 may be used for this purpose. Similarly, the threshold comparison converter may be used to convert the voltage at the nodes associated with output 547 and output 548 into digital test response bits for capture. The node connection device for injecting test vector bits at nodes 541 and 543 may be used. Figure 4C , where transistor 430 and transistor 435 are of different types; and the node connection device for injecting the test vector bit at node 542 can be implemented using a node connection device such as Figure 4C The node connection device shown in FIG. 4 is implemented in which transistor 430 and transistor 435 are both NMOS. Figure 5C Example netlists 561, 562, and 563 of three node connection devices are shown, as well as an example netlist 564 of a threshold comparison converter coupled to node 547. Netlists 561, 562, 563, and 564, as well as netlists for threshold comparison converters coupled to nodes 547 and 548, will be added to the top-level netlist.

[0075] Figure 6 An example circuit diagram of a circuit 600 including both analog circuits and digital circuits is shown. The digital circuit includes a logic gate, such as an AND gate 610. The output 620 of the AND gate 610 directly drives an analog transistor 615. Such an output node 620 has a low impedance and can therefore be selected for observing a test response. For this purpose, a threshold comparison converter with a mid-range threshold can be used. Some or all of the digital signal inputs 630, 640, and 650 (digital signal nodes) can be selected for injecting test vector bits in a test mode through a digital multiplexer. No node connection device is required. An internal node 660 can also be selected to inject a test vector bit. A node connection device can be inserted to connect the internal node 660 to a power node 680 or a ground node 690, and the internal node 660 is disconnected from both the power node 680 and the ground node 690. An output node 670 can also be selected to observe a test response. For this purpose, a threshold comparison converter can be used.

[0076] Figure 7 A flow chart 700 is shown which illustrates a process of determining a good circuit (or expected) test response for a test vector based on a simulation of a flawless analog / mixed signal circuit design that can be implemented according to various examples of the disclosed technology. For ease of understanding, reference will be made to Figure 5A The circuit 500 shown in FIG. Figure 7 700 is used to describe a method for simulating a non-defective analog / mixed signal circuit design to determine a good circuit test response for a test vector that can be used according to various embodiments of the disclosed technology. However, it should be understood that according to various embodiments of the disclosed technology, the method for simulating a non-defective analog / mixed signal circuit design to determine a good circuit test response for a test vector shown by the flowchart 700 can be applied to Figure 5A Similarly, according to various embodiments of the disclosed technology, other methods for simulating a non-defective analog / mixed-signal circuit design to determine a good circuit test response for a test vector may be used to simulate the circuit 500.

[0077] In operation 710, if the circuit design has an analog input, a predetermined DC voltage value is applied to the analog input of the circuit design. The circuit design can be an entire circuit design or a portion of a circuit design in a circuit design, such as a core or circuit block in the circuit design. The circuit design is at least partially analog. Analog circuits work with analog signals. Analog signals are continuously changing signals, as opposed to digital signals that consist of binary rises and falls (or pulses). According to various embodiments of the disclosed technology, the predetermined DC voltage value can be set to be within a mid-range of voltage values ​​that will be applied to the analog input during normal operation of the circuit.

[0078] Circuit 500 has two analog function inputs 556 and 557. The voltage values ​​applied to them when the circuit is operating normally range from 0 volts to 3.0 volts. Accordingly, the predetermined DC voltage values ​​of the two analog function inputs 556 and 557 can be set to 1.5 volts. Circuit 500 also has a clock input 559. A periodic clock signal at the nominal frequency of clock input 559 can be applied to the clock input 559. In addition to the clock input, some digital inputs (such as reset signals) may require special processing. For example, in circuit 500, for most test vectors, the power-down signal for power-down input 558 can be in its power-on mode, and for at least some test vectors, the power-down signal for power-down input 558 can be in power-down mode.

[0079] Figure 8An example of voltages applied to the analog inputs of circuit 500 is shown. Block 810, titled "Applied Voltage Values," shows that the voltages at analog function inputs 556 and 557, power input 551, and ground input 552 are 1.5 volts, 1.5 volts, 3.0 volts, and 0 volts, respectively. Row 815, titled "pdin," shows the bit value at power-down input 558 (a specially processed digital signal input). During the first seven time intervals, the bit value is "0," and circuit 500 is in power-up mode; during the last two time intervals, the bit value is "1," and circuit 500 is in power-down mode.

[0080] Return to reference Figure 7 In operation 720, a plurality of bit value sets (a bit value set in the plurality of bit value sets during each time interval in a plurality of consecutive time intervals) are applied to inputs of one or more node-connected devices coupled to or to be coupled to one or more selected internal nodes, to one or more selected digital inputs, or to both. The one or more selected internal nodes and the one or more selected digital inputs may be selected based on user specifications, circuit topology, or both. For example, the number of circuit elements connected to the internal node may be used as a criterion for selecting the internal node. Additionally or alternatively, parameters of the circuit elements may be used as a criterion. According to various embodiments of the disclosed technology, the width of the transistor may also be considered.

[0081] Each of the one or more node connection devices is configured to couple or decouple at least one of the one or more selected internal nodes to or from another node of the circuit (a node associated with one of the one or more selected internal nodes) based on a bit value at an input of each of the one or more input node connection devices. To perform the functions, each of the one or more node connection devices may include one or more switching devices, such as Figure 2 The node connection device 231, the node connection device 232 and the node connection device 233 in the switching device can be a transistor (such as a metal oxide semiconductor field effect transistor, such as FIG. 4A to FIG. 4C 4, 540, and 541). The circuit 500 can use two node connection devices to control the connection of the internal node 541 and the internal node 543 to the power supply node (vdd0) 551 and the ground node (Vss0) 552, and use a third node connection device to control the connection of the internal node 542 to two associated internal nodes 553 and the internal node 554.

[0082] A plurality of bit value sets are generated for a scan-based structural test of a circuit manufactured based on a circuit design, and used as a test stimulus. If the circuit design has one or more selected internal nodes, a plurality of bit value sets can be generated based on a random combination of bit values ​​or all combinations of bit values ​​for inputs of one or more node connection devices, and if the circuit design has one or more selected digital inputs, a plurality of bit value sets can be generated based on a random combination of bit values ​​or all combinations of bit values ​​for the one or more selected digital inputs. For the random generation method, a pseudo-random pattern generator can be used, such as a linear feedback shift register (LFSR) circuit or a software routine. According to various embodiments of the disclosed technology, the first bit value set applied can be set to a bit value set that does not cause one or more selected internal nodes to couple to their associated nodes. The defects that can be detected by this bit value set can be considered as defects that can be detected without adding any node connection devices. Because it is a circuit started in a normal functional state, this can serve as a good reference.

[0083] Each of the plurality of consecutive time intervals is equal to one or more clock cycles of a scan clock signal for a scan-based structural test of a circuit manufactured based on the circuit design. If the circuit design has a clock signal for the circuit, each of the plurality of consecutive time intervals is also equal to one or more cycles of the clock signal for the circuit. The time interval may start when the circuit clock signal rises or when the circuit clock signal falls, and the selection of the edge may be based on when the input signal of the circuit design is sampled by the clock signal of the circuit, and when the output of the circuit design changes. For example, if the circuit node is initialized when the clock signal of the circuit is logic 0, and the output signal changes shortly after the clock signal of the circuit rises to logic 1, then each of the plurality of bit value sets may be applied when the clock signal of the circuit falls to logic 0. The time interval may be set large enough so that all signals in the circuit design have stabilized to a constant value within the time interval, so that the resulting output value of the circuit design will be more independent of the sequence of the plurality of bit value sets, as is typically done for digital automatic test vector generation (ATPG). This may allow for a greater reduction in the plurality of bit value sets, as will be discussed later.

[0084] Figure 8Also shown is an example of nine bit value sets 820 applied as test stimuli to the circuit 500 at nine consecutive time intervals. The first two rows "dftn0" and "dftp1" in the nine bit value sets 820 represent bit values ​​at the inputs of the NMOS transistor and the PMOS transistor coupled to the internal node 541; the next two rows "dftn2" and "dftn3" represent bit values ​​at the inputs of the two NMOS transistors coupled to the internal node 542; and the last two rows "dftn4" and "dftn5" represent bit values ​​at the inputs of the NMOS transistor and the PMOS transistor coupled to the internal node 543. In addition to the bit values ​​for the first time interval, the nine bit value sets 820 are randomly generated. During the first time interval, for each NMOS transistor gate, the bit value is a logic '0', and for each PMOS transistor gate, the bit value is a logic '1'. These bit values ​​do not enable the transistors to pass current, and thus decouple the internal nodes 541, 542, and 543 from their associated nodes. Therefore, the circuit 500 operates in a normal functional state as if no node connection device was added during the first time interval.

[0085] Return to reference Figure 7 In operation 730, a simulation of the circuit design is performed to determine, for each of a plurality of bit value sets, an expected test response bit value at an output of one or more threshold comparison converters and, if the circuit design has a selected digital signal node, an expected test response bit value at a selected digital signal node. Each of the one or more threshold comparison converters is coupled or to be coupled to one of the one or more selected nodes of the circuit design. Figure 2 Similar to the threshold comparison converter 221, the threshold comparison converter 222 and the threshold comparison converter 223 in the embodiment, each of the one or more threshold comparison converters includes one or more threshold comparison sub-converters, each of the one or more threshold comparison sub-converters is configured to output a bit value at one of the outputs of each of the one or more threshold comparison converters based on comparing the voltage value at one of the one or more selected nodes with a preset threshold value. If the threshold comparison converter includes only one threshold comparison sub-converter, the preset threshold value can be set at the midpoint of the voltage range of the selected node. If the threshold comparison converter includes two threshold comparison sub-converters, the preset threshold value can be set at the midpoint of the voltage range of the selected node. Figure 3DThreshold 346 and threshold 347 in the example are similar, one preset threshold can be set above the midpoint of the voltage range of the selected node, and the other preset threshold can be set below the midpoint of the voltage range of the selected node. One or more threshold comparison subconverters can be implemented using CMOS inverters, logic gates, or other devices.

[0086] The one or more selected nodes coupled to the one or more threshold comparator converters may also be selected based on user specifications, circuit topology, or both. As previously described, a node may be a good candidate for observing a test response if it has a sufficiently low impedance such that connecting the input of the threshold comparator converter to it does not affect the performance of the circuit. Some examples of such low impedance nodes include the output of a function and the output of an amplifier.

[0087] In order to perform simulation of a defect-free circuit design for multiple bit value sets, at least in the early stages of the design of the test process, one or more node connection devices and one or more threshold comparison converters do not need to be inserted into the circuit design. By simulating the circuit design with defects injected (which will be discussed in detail later), some circuits that are not needed for defect detection can be identified in one or more node connection devices, in one or more threshold comparison converters, or in both. Accordingly, the node connection devices and threshold comparison converters finally inserted into the circuit design may be different from those initially selected. Through various implementations of the disclosed technology, an ideal switch can be added to the node connection device to replace the switching device, and the ideal switch has an "on" and "off" resistance similar to the "on" and "off" resistance of the replaced switching device. The voltage at the one or more selected nodes for observing the test response can be sampled, and then the voltage is compared with one or more preset thresholds to determine the expected test response bit value without inserting a threshold comparison converter in the circuit design. Similar to how bit value sets are applied to digital combinatorial logic and test response bit values ​​are captured from the digital combinatorial logic, the voltage at one or more selected nodes for observing the test response may be sampled just before each of the multiple bit value sets changes.

[0088] In circuit 500, node 546 and output 547 and output 548 are selected as nodes for observing test responses, and each threshold comparison converter used includes two threshold comparison sub-converters, such as Figure 3D The threshold comparison converter 340 in FIG. Figure 8Also shown are expected test response bit values ​​830 captured during nine consecutive time intervals obtained based on simulation of circuit 500. The first two rows of expected test response bit values ​​830, "adc1H" and "adc1L", represent bit values ​​at the output of the threshold comparison subconverter coupled to node 546; the next two rows, "adc2H" and "adc2L", represent bit values ​​at the output of the threshold comparison subconverter coupled to output 547; and the last two rows, "adc3H" and "adc3L", represent bit values ​​at the output of the threshold comparison subconverter coupled to output 548.

[0089] Return to reference Figure 7 , optional operation 740 determines whether to perform simulation for all process parameter combinations of interest. Typically, the circuit design is designed to pass all functional tests for any combination of process parameter values ​​within the manufacturing process specification. The circuit design can first be simulated with typical values ​​of each circuit element model process parameter value. Then, the circuit design can be simulated with different combinations of different process parameter values. After the process is completed, in operation 750, uncertain bits in the expected test response bit values ​​are identified. The uncertain bits in this operation are bits that have different values ​​for different combinations of process parameter values, which can be set to "X".

[0090] Fig. 9 An example is shown for determining uncertain bits in expected test response bit values ​​for circuit 500. Circuit 500 is simulated for a "typical" set of process parameter values, a "worst" or "slow" set of process parameter values, and an "optimal" or "fast" set of process parameter values. Fig. 9 The expected test response bit values ​​910, 920, and 930 for three sets of process parameter values ​​captured during nine consecutive time intervals are listed, as well as the final expected test response bit value 940 derived therefrom. By comparing the expected test response bit values ​​910, 920, and 930, three uncertain bits are identified and set to "X" in the final expected test response bit value 940. For example, during the seventh time interval 990, the test response bits 950, 960, and 970 output from the output of the threshold comparison converter (labeled "adc2H" in the figure) associated with the node 547 are "0", "0", and "1", respectively. "X" is assigned to the corresponding bit value 980 in the final expected test response bit value 940.

[0091] In addition to handling explicit process parameter variations, voltage margins may be added around the preset thresholds used by the threshold comparison subconverters to account for additional noise or process variations. If the voltage value at the selected node for observing the test response is within a preset range centered around the preset threshold, the corresponding test response bit value may be set to 'X'. For example, if the voltage samples at the node range from 1.1 volts to 1.3 volts for different process parameter values, and the threshold voltage is 1.0 volt, and the added margin is 0.2 volts, then the expected logic value for that sample may be set to 'X' because 1.1 is within the 0.2 volt margin around 1.0 volts.

[0092] The result of the process shown in flowchart 700 is a test vector (a plurality of bit value sets) and its timing of expected test response bit values. In addition to simulating defect-free circuit designs, the automatic test vector generation process may also include simulating multiple analog / mixed signal circuit designs with injected defects. Fig.10 A flowchart 1000 is shown, which illustrates a process of simulating an analog / mixed signal circuit design for multiple injection defects according to various embodiments of the disclosed technology. For ease of understanding, reference will be made to Figure 5A The circuit 500 shown in FIG. Fig.10 1000 is used to describe a method for simulating an analog / mixed signal circuit design for multiple injection defects that can be used according to various embodiments of the disclosed technology. However, it should be understood that according to various embodiments of the disclosed technology, the method for simulating an analog / mixed signal circuit design for multiple injection defects shown in flowchart 1000 can be applied to Figure 5A Similarly, the circuit 500 may be simulated using other methods for simulating analog / mixed-signal circuit designs for multiple injected defects according to various embodiments of the disclosed technology.

[0093] In operation 1010, defects are injected into the circuit design. Two common defects for analog or mixed signal circuits are open circuit defects and short circuit defects. The latter is also called a bridge defect. The defect injection site can be determined based on user specifications, circuit topology, or both. According to various embodiments of the disclosed technology, defects can be injected into the circuit design one at a time for simulation.

[0094] The next two operations in flowchart 1000 are similar to operations 710 and 720 in flowchart 700. In operation 1020, if the circuit design has analog inputs, the same predetermined DC voltage value used in operation 710 is applied to the analog inputs of the circuit design into which the defect is injected. In operation 1030, the same plurality of bit value sets used in operation 720 are applied to inputs of one or more node-connected devices coupled to or to be coupled to one or more selected internal nodes, and to one or more selected digital inputs, or to both. Here, the plurality of bit value sets are applied not only as a set in each of the plurality of consecutive time intervals, but also in the same order as they are applied in the defect-free circuit design.

[0095] In operation 1040, simulations are performed on the defect-injected circuit design to determine a set of test vectors that can detect at least some of the defects. For each simulation, the resulting test response bit value is compared with the corresponding expected test response bit value derived from simulating the defect-free circuit design. If the expected test response bit value is 'X', no comparison is made. If at least one of the test response bit values ​​is different from the corresponding expected test response bit value, one or more injected defects can be declared detected. In optional operation 1050, a defect coverage ratio measuring the number of defects detectable by the test vector set to the total number of defects is determined. If the determined defect coverage ratio is not high enough, multiple bit value sets, selected internal nodes for test stimulus injection, selected nodes for test response observation, or any combination thereof can be adjusted.

[0096] The test vector set may be obtained by selecting all bit value sets that detect defects that cannot be detected by any other bit value set. The test vector set may be compressed without affecting defect coverage. In optional operation 1060, a reduced test vector set that can detect the same defects as the test vector set is determined. In order to select the minimum number of test vectors, a digital automatic test vector generation (ATPG) minimization algorithm or a greedy algorithm may be used. Fig.11 A flow chart 1100 is shown that illustrates a process of deriving a reduced set of test vectors using a greedy algorithm according to various embodiments of the disclosed technology. In operation 1110, each test vector that is the only vector that detects a defect is selected. In operation 1120, another test vector is selected that detects the majority of the remaining defects. In operation 1130, the process checks whether there are any defects left. If the answer is yes, operations 1120 and 1130 are repeated by selecting another test vector. These selection and checking operations continue until the selected test vector is able to detect all defects detected by the original set of test vectors.

[0097] Sometimes, it may be necessary to retain a short sequence of consecutive test vectors, even if only the last test vector in the short sequence detects a defect. This is because the last test vector depends on the previous value. Without using a short sequence of consecutive test vectors, the test consistency between the original test vector set and the reduced test vector set will be affected. Retaining a short sequence can also allow the time interval between consecutive test vectors to be reduced, so that some signals deliberately have no time to stabilize, and the sampled node voltage becomes sensitive to the values ​​of resistance and capacitance. In many types of analog circuits (such as switched capacitor filters), the stabilization time and signal propagation delay are longer than the cycle of the highest frequency clock applied to the circuit. In addition, in some applied test vectors, some transistors may not conduct any current, which will cause some node voltages to drift up or down due to leakage current, and this will make the output voltage for the next combination of logic values ​​depend on the previous combination.

[0098] The short sequence of test vectors may be two, three or more consecutive test vectors. In any case, the expected logic values ​​of all test vectors except the last test vector in each selected short sequence may be set to 'X', because the test vector preceding the test vector in the reduced test vector set may be a different test vector than in the original test vector set.

[0099] Return to reference Fig.10 , in optional operation 1070, test circuits that do not contribute uniquely to the detection of defects are removed. If the bit value of the switch device in the control node connection device is always the same as the value of not enabling the switch device, then the switch device can be removed because it does not contribute uniquely to the detection of any defects. If the threshold comparison subconverter in the threshold comparison converter outputs a bit value that does not contribute uniquely to the detection of any defects, the threshold comparison subconverter can be removed. This operation can be performed after optional operation 1060. Compared with the original test vector set, the obtained reduced test vector set may result in more test circuits being removed.

[0100] Fig. 12A An example defect detection matrix for nine defects of circuit 500 detected using nine sets of bit values ​​(test vectors) applied during nine consecutive time intervals is shown. Each row indicates the results for a different defect. The letter "D" indicates that the defect of interest was detected. Fig.11In the greedy algorithm shown in , the test vector applied during time interval 1230 is selected first because it is the only vector that detects defect 3. The test vector applied during time interval 1210 is the test vector that detects most of the remaining defects, so it is selected second. The test vector applied during time interval 1220 detects the remaining defects and is selected third and last. A reduced set of three test vectors applied during time intervals 1210, 1220, and 1230 is formed. The detection coverage is not affected.

[0101] Fig. 12B An example of a collection of short sequences forming reduced test vectors is shown. If a short sequence of two test vectors is needed to maintain test consistency, for example, the test vector immediately preceding the test vector applied during time interval 3 and time interval 6 will be retained, forming two short sequences 1250 and 1260. Since time interval 1 is the first time interval with no previous time intervals except for the initial condition of indeterminate duration, its short sequence 1240 contains only one test vector.

[0102] Fig.13A A set of test vectors 1300 is shown that are applied to circuit 500 during all nine consecutive time intervals. The three test vectors 1310, 1320, and 1330 outlined correspond to the test vectors applied during time interval 1210, time interval 1220, and time interval 1230, which are identified as being associated with Fig. 12A 1300. When only the set of reduced test vectors 1310, 1320, and 1330 is considered, the NMOS transistor (dftn0) is always driven by a signal "0", and the PMOS transistor (dftp5) is always driven by a signal "1". Therefore, they are never enabled, and these rows of the set of test vectors 1300 can be crossed out, and the NMOS transistor (dftn0) and the PMOS transistor (dftp5) can be removed without affecting the test coverage. Fig. 13B A set of reduced test vectors 1340 , 1350 , and 1360 are shown for time intervals 1 , 3 , and 6 and without rows for NMOS transistors ( dftn0 ) and PMOS transistors ( dftp5 ). Fig. 13C It shows how test vector 1340, test vector 1350, and test vector 1360 are shifted into a serial bit stream applied to the scan chain as 1370, 1380, and 1390, respectively.

[0103] Fig.14A The reduced test vector bit position set 1410 (corresponding to Fig. 12A1210, 1220, 1230) and the test response bit position 1420 of the defect detection matrix in the example defect detection matrix 1400 for circuit 500. As previously described, each of the three threshold comparison converters has two threshold comparison sub-converters, one using a high threshold ("H") and the other using a low threshold ("L"), so two bit values ​​can be output. Threshold comparison sub-converters 1430, 1440, and 1450 can be selected, and the remaining threshold comparison sub-converters can be removed because they cannot uniquely detect defects. Fig. 14B An example of expected test response bit values ​​for each of the threshold comparison subconverters in nine consecutive time intervals is shown, where the reduced test vector sets in intervals 1, 3 and 6 are summarized as 1411, 1412 and 1413. Fig. 14C Expected test response bit values ​​are shown for only time intervals 1411, 1412 and 1413 associated with the reduced set of test vectors. Fig.14D A minimized set of expected test response bit values ​​for only threshold comparison subconverters 1430 , 1440 , and 1450 is shown. Fig.14E It is shown how the minimized set of expected test response bit values ​​are shifted out along the scan chain to become 1421 , 1422 , and 1423 .

[0104] In some cases, some or all switching devices in a node connection device that are not needed to achieve maximum defect coverage may not be removed because they may be considered to be used for diagnosing defects. Similarly, some or all threshold comparison subconverters in a threshold comparison converter that are not needed to achieve maximum defect coverage may not be removed because they may be considered to be used for diagnosing defects.

[0105] Fig.15 An example of a test circuit 1500 for circuit 500 is shown. Test circuit 1500 includes a scan chain 1510 and an associated update register 1520. Test circuit 1500 also includes three node connection devices 1530, 1540, and 1550, the inputs of the three node connection devices 1530, 1540, and 1550 are coupled to update register 1520, and the outputs of the three node connection devices 1530, 1540, and 1550 are coupled to three selected internal nodes of circuit 500 and their associated nodes. Here, due to the reduction of the test circuit, node connection device 1530 and node connection device 1550 have only one switching device, such as Fig.13A and 13B The test circuit 1500 also includes two threshold comparison converters 1560 and 1570 for observing the test responses at two selected nodes 1581 (X1.int) and 1582 (pout2). FIG. 14A to FIG. 14D, neither the test response at another initially selected node 547 (pout) in circuit 500 nor the low threshold test response bit of node 1582 can uniquely detect a defect. Therefore, there is no threshold comparison converter for the initially selected node 547 (pout), and threshold comparison converter 1570 has only one threshold comparison sub-converter using a high threshold.

[0106] Various examples of the disclosed technology can be implemented by executing software instructions through a computing device (e.g., a programmable computer). Fig.16 A schematic example of a computing device 1601 is shown. As seen in the figure, the computing device 1601 includes a computing unit 1603 having a processing unit 1605 and a system memory 1607. The processing unit 1605 can be any type of programmable electronic device for executing software instructions, but it is typically a microprocessor. The system memory 1607 can include both a read-only memory (ROM) 1609 and a random access memory (RAM) 1611. It will be understood by those of ordinary skill in the art that both the read-only memory (ROM) 1609 and the random access memory (RAM) 1611 can store software instructions for execution by the processing unit 1605.

[0107] The processing unit 1605 and the system memory 1607 are directly connected to or indirectly connected to one or more peripheral devices through the bus 1613 or an alternative communication structure. For example, the processing unit 1605 or the system memory 1607 can be directly or indirectly connected to one or more additional memory storage devices, such as a "hard" disk drive 1615, a removable disk drive 1617, an optical drive 1619, or a flash memory card 1621. The processing unit 1605 and the system memory 1607 can also be directly or indirectly connected to one or more input devices 1623 and one or more output devices 1625. The input device 1623 can include, for example, a keyboard, a pointing device (such as a mouse, a touchpad, a stylus, a trackball, or a joystick), a scanner, a camera, and a microphone. The output device 1625 can include, for example, a monitoring display, a printer, and a speaker. Through various examples of the computing device 1601, one or more of the peripheral devices 1615 to 1625 can be housed internally with the computing unit 1603. Alternatively, one or more peripheral devices 1615-1625 may be external to the housing of computing unit 1603 and connected to bus 1613 via, for example, a Universal Serial Bus (USB) connection.

[0108] In some embodiments, the computing unit 1603 may be directly or indirectly connected to one or more network interfaces 1627 for communicating with other devices constituting the network. The network interface 1627 converts data and control signals from the computing unit 1603 into network messages according to one or more communication protocols, such as the Transmission Control Protocol (TCP) and the Internet Protocol (IP). In addition, the network interface 1627 may use any suitable connection agent (or combination of agents) for connecting to the network, for example, including a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art and are therefore not discussed in more detail herein.

[0109] It should be understood that computing device 1601 is described only as an example and is not intended to be limiting. Various embodiments of the disclosed technology may be implemented using one or more computing devices, including Fig.16 The components of computing device 1601 shown in FIG. 1 include only Fig.16 or include alternative combinations of components, including those not shown in Fig.16 For example, various embodiments of the disclosed technology may be implemented using a multi-processor computer, multiple single-processor and / or multi-processor computers arranged in a network, or some combination of the two.

[0110] in conclusion

[0111] Having illustrated and described the principles of the disclosed technology, it will be apparent to those skilled in the art that the disclosed embodiments may be modified in arrangement and detail without departing from these principles. Considering that the principles of the disclosed technology may be applied to many possible embodiments thereof, it should be recognized that the illustrated embodiments are merely preferred examples of the technology and should not be considered as limiting the scope of the disclosed technology. Instead, the scope of the disclosed technology is defined by the following claims and their equivalents. Therefore, we claim all that falls within the scope and spirit of these claims as our disclosed technology.

Claims

1. A method executed by at least one processor of a computer, comprising: If the circuit design has an analog input, applying a predetermined DC voltage value to the analog input of the circuit design, the circuit design being at least partially analog; applying a plurality of sets of bit values ​​generated for scan-based structural testing of a circuit fabricated based on the circuit design, one set of bit values ​​from the plurality of sets of bit values ​​during each of a plurality of consecutive time intervals to inputs of one or more node connection devices coupled to or to be coupled to one or more selected internal nodes of the circuit design, to one or more selected digital inputs of the circuit design, or both, each of the one or more node connection devices being configured to cause at least one of the one or more selected internal nodes to be coupled to or decoupled from another node of the circuit based on a bit value at an input of each of the one or more input node connection devices, each of the plurality of consecutive time intervals being equal to one or more clock cycles of a scan clock signal used for the scan-based structural testing of the circuit; and performing simulation on the circuit design to determine, for each of the plurality of bit value sets, an expected test response bit value at an output of one or more threshold comparison converters and, if the circuit design has a selected digital signal node, to determine an expected test response bit value at the selected digital signal node, each of the one or more threshold comparison converters being coupled or to be coupled to one of the one or more selected nodes of the circuit design and comprising one or more threshold comparison subconverters, each of the one or more threshold comparison subconverters being configured to output a bit value at one of the outputs of each of the one or more threshold comparison converters based on comparing a voltage value at one of the one or more selected nodes to one of one or more preset thresholds, wherein, in scan-based structural testing of the circuits, at least some bits of the plurality of bit value sets are applied to each of the circuits using one or more scan chains in each of the circuits, and test response bit values ​​at at least some outputs of the one or more threshold comparison converters are captured by the one or more scan chains.

2. The method according to claim 1, wherein: If the voltage value at one of the one or more selected nodes is within a preset range centered around one of the one or more preset thresholds, the bit value output by each of the one or more threshold comparison subconverters is deemed to be indeterminate.

3. The method according to claim 1, wherein: If the simulation is repeatedly performed for different combinations of process parameter values, and the bit value is different for all different combinations of process parameter values, then the bit value output by each of the one or more threshold comparison subconverters is deemed to be indeterminate.

4. The method according to claim 1, wherein: The plurality of bit value sets are generated based on a random combination of bit values ​​or a combination of all bit values.

5. The method according to claim 1, wherein: The one or more selected internal nodes and the one or more selected nodes are selected based on user specifications, circuit topology, or both.

6. The method according to claim 1, wherein: The number of bit values ​​at the input of each of the one or more input node connection devices is 1 or 2, and each of at least some of the one or more node connection devices is configured to couple a selected internal node to either or not couple to two other nodes of the circuit based on the 2-bit value.

7. The method according to claim 1, wherein: Each of the one or more threshold comparison subconverters is implemented by an inverter, and each of the one or more threshold comparison subconverters includes up to two threshold comparison subconverters.

8. The method according to claim 1, further comprising: injecting a defect into the circuit design; and The operations of claim 1 are performed to determine a set of test vectors capable of detecting at least some of the defects.

9. The method according to claim 8, wherein: The defects are injected into the circuit design one at a time for simulation.

10. The method according to claim 8, further comprising: A reduced set of test vectors capable of detecting at least some of the defects is determined based on the set of test vectors.

11. The method according to claim 10, wherein: The reduced test vector set retains some consecutive test vectors in the test vector set.

12. The method according to claim 10, wherein: The method of determining the reduced test vector set adopts a greedy algorithm.

13. The method according to claim 8, further comprising: Removing switching devices from the one or more node connection devices that do not uniquely contribute to detecting the defect, removing threshold comparison subconverters from the one or more threshold comparison converters that do not uniquely contribute to detecting the defect, or removing both.

14. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform the method of any one of claims 1 to 13.

15. A system comprising: One or more processors programmed to perform the method according to any one of claims 1 to 13.

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