Digital storage and calculation integrated chip based on dynamic logic calculation

Abstract

The invention discloses a digital storage and calculation integrated chip based on dynamic logic calculation, which consists of a multiplier circuit and / or a half adder circuit and / or a first full adder circuit and / or a second full adder circuit, and comprises a primary circuit and a secondary circuit which comprise a pull-up network and / or a pull-down network and are used for realizing basic logic calculation; the first-stage circuit is started through a first-stage clock signal; the second-stage circuit is started through a second-stage clock signal; a charging transistor and a discharging transistor; according to the on-off of the first-stage clock signal or the second-stage clock signal, calculation control of the pull-up network or the pull-down network is realized, and a calculation result of the first-stage circuit is output to the second-stage circuit for logic calculation. The number of transistors used by the multiplication and addition unit is greatly reduced, main indexes such as time delay and power consumption are improved, and the problem that in the AI large model carrying process of a digital storage and calculation integrated chip, energy consumption and area occupation are too large is solved.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuit technology, and specifically relates to a digital storage and computing integrated chip based on dynamic logic calculation. Background Art

[0002] At present, digital storage and computing integrated chips significantly reduce the data movement in the traditional von Neumann architecture by integrating digital logic computing units inside the storage array, solving problems such as high latency and high energy consumption. However, as the core of data processing, the computing unit still has problems such as excessive area overhead and high computing latency, which is not conducive to the miniaturization and low-power design of end-side AI chips; the computing unit of the digital storage and computing integrated chip mainly refers to the addition tree structure composed of multipliers, half adders and full adders (hereinafter collectively referred to as multiplication and addition units);

[0003] The currently widely used multiplication and addition unit is a circuit based on static complementary CMOS design, which mainly consists of two parts, namely the pull-up network (PUN) and the pull-down network (PDN). The pull-up network is composed of p-type MOS tubes and is the path between the output and the high level. The pull-down network is composed of n-type MOS tubes and is the path between the output and the power ground. Both can perform logical judgment functions, and the circuit structure can be complementary or mirrored. The noise tolerance of the multiplication and addition unit designed by static complementary CMOS is very high, and the structure is stable, and the output signal quality is also very good; the disadvantage is that it has too high requirements on the number of transistors and the area overhead, because the circuit structure under the static complementary CMOS design is composed of two parts, which means that any circuit unit with n inputs will consume 2n transistors. In the full adder, a standard static complementary full adder unit will be composed of 28 transistors, which will greatly increase the area overhead, especially in AI chips such as digital storage chips. The addition tree used in the traditional static complementary CMOS design will occupy more than 70% of the area of ​​the entire chip, which is too expensive.

[0004] In the academic community, there is a multiplication-addition unit design scheme based on the transmission tube logic design, which can greatly reduce the number of transistors and area overhead of the multiplication-addition unit. The special feature of the transmission tube logic is that its input is different from the traditional static logic that only drives the gate. In fact, in the transmission tube logic, the input can drive any two ports of the gate, source and drain of the transistor, and output from the remaining third port. Although this will bring certain transmission losses, it greatly reduces the number of transistors used. Taking the full adder as an example, the circuit based on the transmission tube design uses only 16 transistors.

[0005] However, its multi-layer cascade performance and transmission signal quality are relatively poor. Because in the transmission tube logic, when the signal is input from the source of the transistor and output from the drain, there is a threshold voltage loss, so when using the transmission tube logic design for multi-layer cascade, it is necessary to insert a level restorer between each layer. This has led to the failure of the transmission tube logic design to fully utilize its area advantage in practical applications. Summary of the invention

[0006] In order to solve the deficiencies in the prior art, the present application proposes a digital storage and computing integrated chip based on dynamic logic calculation, which is composed of a multiplier circuit and / or a half adder circuit and / or a first full adder circuit and / or a second full adder circuit, including:

[0007] The primary circuit and the secondary circuit include a pull-up network and / or a pull-down network for realizing basic logic calculations; the primary circuit is started by a primary clock signal; the secondary circuit is started by a secondary clock signal;

[0008] Charging transistor and discharging transistor; turned on and off according to the primary clock signal or the secondary clock signal, used to realize the calculation control of the pull-up network or the pull-down network and output the calculation result of the primary circuit to the secondary circuit for logic calculation.

[0009] Optionally, the pull-down network includes: a first logic and pull-down network, a second logic and pull-down network, a first logic or pull-down network, a second logic or pull-down network, and a third logic or pull-down network;

[0010] The first logic and pull-down network, the first logic or pull-down network and the third logic or pull-down network each include two NMOS tubes, and the gates of the two NMOS tubes are respectively connected to the A signal and the B signal; the second logic and pull-down network and the second logic or pull-down network each include three NMOS tubes, and the gates of the three NMOS tubes are respectively connected to the A signal, the B signal and the C signal. i Signal.

[0011] Optionally, the charging transistor is a PMOS tube, including a first charging PMOS tube, a second charging PMOS tube, a third charging PMOS tube and a fourth charging PMOS tube; the discharging transistor is an NMOS tube, including a first discharging NMOS tube, a second discharging NMOS tube and a third discharging NMOS tube.

[0012] Optionally, the primary circuit of the first full adder circuit includes: a first NMOS tube, a first logic and pull-down network, a first logic or pull-down network, a first charging PMOS tube, a second charging PMOS tube, and a first discharging NMOS tube; the secondary circuit includes: a second NMOS tube, a second logic and pull-down network, a second logic or pull-down network, a third charging PMOS tube, a fourth charging PMOS tube, and a second discharging NMOS tube;

[0013] The source of the first charging PMOS tube is connected to the power supply voltage, the gate is connected to the first clock signal, the drain is connected to the drain of the first NOMS tube, and the gate of the first NOMS tube is connected to C i signal, the source of the first NMOS tube is connected to the drain of the first discharge NMOS tube, the gate of the first discharge NMOS tube is connected to the primary clock signal, and the source of the first discharge NMOS tube is grounded;

[0014] The source of the second charging PMOS tube is connected to the power supply voltage, the gate is connected to the first-level clock signal, the drain is respectively connected to the input end of the first logic or pull-down network, the input end of the first logic and pull-down network and the gate of the second NMOS tube, the output end of the first logic or pull-down network is respectively connected to the drain of the first charging PMOS tube and the drain of the first NMOS tube; the output end of the first logic and pull-down network is respectively connected to the drain of the first discharging NMOS tube and the source of the second discharging NMOS tube;

[0015] The source of the third charging PMOS tube is connected to the power supply voltage, the gate is connected to the secondary clock signal, and the drain is respectively connected to the second logic or pull-down network input terminal and the second logic and pull-down network input terminal; the output terminal of the second logic or pull-down network is respectively connected to the drain of the second NMOS tube and the drain of the fourth charging PMOS tube; the gate of the fourth charging PMOS tube is connected to the secondary clock signal, and the source is connected to the power supply voltage;

[0016] The output end of the second logic and pull-down network and the source of the second NMOS tube are respectively connected to the drain of the second discharge NMOS tube, and the gate of the second discharge NMOS tube is connected to the secondary clock signal.

[0017] Optionally, the delay time between the secondary clock signal and the primary clock signal is greater than the startup operation time of the primary circuit.

[0018] Optionally, the first-level circuit of the multiplier circuit includes: a first logic and pull-down network, a first logic or pull-down network, a first charging PMOS tube, a second charging PMOS tube, a first discharging NMOS tube, and a second discharging NMOS tube; the second-level circuit includes: a second charging PMOS tube, a third logic or pull-down network, and a third discharging NMOS tube;

[0019] The source of the first charging PMOS tube is connected to the power supply voltage, the gate is connected to the primary clock signal, the drain is connected to the input end of the first logic and pull-down network, and is connected to the gate of an NMOS tube in the third logic or pull-down network through an inverter, the output end of the first logic and pull-down network is connected to the drain of the first discharging NMOS tube, the gate of the first discharging NMOS tube is connected to the primary clock signal, and the source of the first discharging NMOS tube is grounded;

[0020] The source of the second charging PMOS tube is connected to the power supply voltage, the gate is connected to the primary clock signal, the drain is connected to the input end of the first logic or pull-down network, and is also connected to the gate of another NMOS tube in the third logic or pull-down network; the output end of the first logic or pull-down network is connected to the drain of the second discharging NMOS tube, the gate of the second discharging NMOS tube is connected to the primary clock signal, and the source of the second discharging NMOS tube is grounded;

[0021] The source of the third charging PMOS tube is connected to the power supply voltage, the gate is connected to the secondary clock signal, the drain is connected to the input end of the third logic or pull-down network, the output end of the third logic or pull-down network is connected to the drain of the third discharging NMOS tube, the gate of the third discharging NMOS tube is connected to the secondary clock signal, and the source of the third discharging NMOS tube is grounded.

[0022] Optionally, the primary circuit of the half adder circuit includes: a first logic and pull-down network, a first charging PMOS tube, a second charging PMOS tube, a fourth charging PMOS tube and a first discharging NMOS tube; the secondary circuit includes: a first NMOS tube, a first logic or pull-down network, a third charging PMOS tube, and a second discharging NMOS tube;

[0023] The source electrodes of the first charging PMOS tube, the second charging PMOS tube, the third charging PMOS tube and the fourth charging PMOS tube are connected to the power supply voltage, the gate electrodes of the first charging PMOS tube, the second charging PMOS tube and the fourth charging PMOS tube are connected to the primary clock signal, the gate electrode of the third charging PMOS tube is connected to the secondary clock signal, the drain electrode of the first charging PMOS tube is connected to the middle connection point of two series-connected NMOS tubes in the first logic and pull-down network, the drain electrode of the second charging PMOS tube is respectively connected to the input end of the first logic and pull-down network and the gate electrode of the first NMOS tube, the output end of the first logic and pull-down network is respectively connected to the drain electrode of the first discharging NMOS tube and the source electrode of the second discharging NMOS tube, the gate electrode of the first discharging NMOS tube is connected to the primary clock signal, and the source electrode is grounded; the gate electrode of the second discharging NMOS tube is connected to the secondary clock signal, and the drain electrode is connected to the source electrode of the first NMOS tube; the drain electrode of the first NMOS tube is respectively connected to the output end of the first logic or pull-down network and the drain electrode of the fourth charging PMOS tube; the input end of the first logic or pull-down network is connected to the drain electrode of the third charging PMOS tube.

[0024] Optionally, the first-level circuit of the second full adder circuit includes: a first logic and pull-down network, a first logic or pull-down network, a first NMOS tube, a first charging PMOS tube and a first discharging NMOS tube; the second-level circuit includes: a second logic and pull-down network, a second logic or pull-down network, a second NMOS tube, a second charging PMOS tube and a second discharging NMOS tube;

[0025] The output ends of the first logic and pull-down network, the second logic and pull-down network, the first logic or pull-down network, and the second logic or pull-down network are respectively connected to the drain of the first discharge NMOS tube and the drain of the second NMOS tube, the source of the first discharge NMOS tube and the source of the second NMOS tube are respectively grounded, and the gate of the first discharge NMOS tube and the gate of the second NMOS tube are respectively connected to the clock signal; the input end of the first logic non-pull-down network is connected to the source of the first NMOS tube, and the gate of the first NMOS tube is connected to C i The drain of the first NMOS tube is respectively connected to the drain of the first charging PMOS tube, the input end of the first logic and pull-down network and the gate of the second NMOS tube, the gate of the first charging PMOS tube and the gate of the second charging PMOS tube are respectively connected to the clock signal, and the source of the first charging PMOS tube and the source of the second charging PMOS tube are respectively connected to the power supply voltage; the drain of the second NMOS tube and the input end of the second logic and pull-down network are respectively connected to the drain of the second charging PMOS tube, the source of the second NMOS tube is connected to the input end of the second logic or pull-down network, and the output end of the second logic or pull-down network is connected to the drain of the second discharging NMOS tube; the gate of the second discharging NMOS tube is connected to the clock signal, and the source of the second discharging NMOS tube is grounded; the input end of the second logic or pull-down network outputs the calculation result signal.

[0026] Optionally, the primary circuit of the pull-up logic half adder circuit includes: a first logic AND non-pull-up network, a first charging PMOS tube, a first discharging NMOS tube and a second discharging NMOS tube; the secondary circuit includes: a first logic OR non-pull-up network, a second charging PMOS tube, a third discharging NMOS tube and a fourth discharging NMOS tube;

[0027] The drains of the first discharge NMOS tube, the second discharge NMOS tube, the third discharge NMOS tube, and the fourth discharge NMOS tube are grounded; the gates of the first charging PMOS tube, the first discharge NMOS tube, the second discharge NMOS tube, and the fourth discharge NMOS tube are connected to a primary clock signal, and the gates of the second charging PMOS tube and the third discharge NMOS tube are connected to a secondary clock signal; the source of the first discharge NMOS tube is connected to the middle connection of the two series-connected PMOS tubes in the first logic and non-pull-up network, and the source of the second discharge NMOS tube is connected to the first logic and non-pull-up network respectively. The input end of the network and the gate of the first PMOS tube, the output end of the first logic and non-pull-up network are respectively connected to the drain of the first charging PMOS tube and the source of the second charging PMOS tube, the gate of the first charging PMOS tube is connected to the primary clock signal, and the source is grounded; the gate of the second charging PMOS tube is connected to the secondary clock signal, and the drain is connected to the source of the first PMOS tube; the drain of the first NMOS tube is respectively connected to the output end of the first logic or non-pull-up network and the source of the fourth discharging NMOS tube; the input end of the first logic or non-pull-up network is connected to the source of the third discharging NMOS tube.

[0028] Optionally, the first-level circuit of the pull-up logic multiplier circuit includes: a first logic or non-pull-up network, a first logic and non-pull-up network, a first charging PMOS tube, a second charging PMOS tube, a first discharging NMOS tube, and a second discharging NMOS tube; the second-level circuit includes: a third charging PMOS tube, a third logic and non-pull-up network, and a third discharging NMOS tube;

[0029] The source of the first charging PMOS tube is connected to the power supply voltage, the gate is connected to the primary clock signal, the drain is connected to the input end of the first logic or non-pull-up network, and is connected to the gate of a PMOS tube in the third logic and non-pull-up network through an inverter, the output end of the first logic or non-pull-up network is connected to the drain of the first discharging NMOS tube, the gate of the first discharging NMOS tube is connected to the primary clock signal, and the source of the first discharging NMOS tube is grounded;

[0030] The source of the second charging PMOS tube is connected to the power supply voltage, the gate is connected to the primary clock signal, the drain is connected to the input end of the first logic and non-pull-up network, and is also connected to the gate of another PMOS tube in the third logic and non-pull-up network; the output end of the first logic and non-pull-up network is connected to the drain of the second discharging NMOS tube, the gate of the second discharging NMOS tube is connected to the primary clock signal, and the source of the second discharging NMOS tube is grounded;

[0031] The source of the third charging PMOS tube is connected to the power supply voltage, the gate is connected to the secondary clock signal, the drain is connected to the input end of the third logic and non-pull-up network, the output end of the third logic and non-pull-up network is connected to the drain of the third discharging NMOS tube, the gate of the third discharging NMOS tube is connected to the secondary clock signal, and the source of the third discharging NMOS tube is grounded.

[0032] Optionally, the primary circuit of the pull-up logic full adder circuit includes: a first logic or non-pull-up network, a first logic and non-pull-up network, a first PMOS tube, a first charging PMOS tube, a first discharging NMOS tube and a second discharging NMOS tube; the secondary circuit includes: a second logic or non-pull-up network, a second logic and non-pull-up network, a second PMOS tube, a second charging PMOS tube, a third discharging NMOS tube and a fourth discharging NMOS tube;

[0033] The first logic or non-pull-up network, the first logic and non-pull-up network and the gate of the second PMOS tube are connected to the drain of the second discharge NMOS tube; the output ends of the second logic or non-pull-up network and the second logic and non-pull-up network are connected to the drain of the third discharge NMOS tube; the source of the second discharge NMOS tube and the source of the third discharge NMOS tube are grounded respectively, and the gate of the second discharge NMOS tube and the gate of the third discharge NMOS tube are connected to the first and second level clock signals respectively; the input end of the first logic or non-pull-up network is connected to the drain of the first PMOS tube, and the gate of the first PMOS tube is connected to C i The signal is that the source of the first PMOS tube is respectively connected to the drain of the first charging PMOS tube, the input end of the first logic and non-pull-up network and the source of the second charging PMOS tube, the gate of the first charging PMOS tube and the gate of the second charging PMOS tube are respectively connected to the first and second clock signals, and the source of the first charging PMOS tube is connected to the power supply voltage; the source of the second PMOS tube and the input end of the second logic and non-pull-up network are respectively connected to the drain of the second charging PMOS tube, the drain of the second PMOS tube is connected to the input end of the second logic or non-pull-up network, and the output end of the second logic or non-pull-up network is connected to the drain of the second discharging NMOS tube; the drain of the first discharging NMOS tube is connected to the middle connection of the first logic or non-pull-up network and the first PMOS tube, and the source of the first discharging NMOS tube is grounded; the drain of the fourth discharging NMOS tube is connected to the middle connection of the second logic or non-pull-up network and the second PMOS tube, and the source of the fourth discharging NMOS tube is grounded; the output end of the second logic or non-pull-up network outputs the calculation result signal.

[0034] The beneficial effects brought about by the technical solutions provided by some embodiments of the present application include at least:

[0035] 1. While ensuring the calculation accuracy and output signal margin, the number of transistors required for the multiplication and addition unit is reduced, the demand for hardware resource overhead of the addition tree is reduced, and the surface efficiency and energy efficiency of the digital storage and computing integrated chip are maximized;

[0036] 2. Compared with the circuit based on static complementary CMOS design, the number of transistors used is less; because each static complementary logic calculation unit needs to use the pull-up network and the pull-down network to work together to output the result, while the dynamic logic calculation unit uses the "charge + discharge" transistor to replace a set of calculation circuits in the two networks, thereby reducing the overall transistor count overhead and reducing the static power consumption of the calculation unit;

[0037] 3. Compared with the multiplication and addition unit circuit designed based on transmission tube logic, the signal margin of the dynamic logic calculation unit is larger and the calculation result is more accurate; because in the transmission tube logic, when the input signal enters from the source / drain, the transistor will divide the voltage, resulting in the upper limit of the output signal being one V lower than the input signal.th This means that if the transmission tube logic is to be cascaded, the voltage upper limit will be reduced by one each time the output signal passes through a circuit. If the voltage is to be restored, more inverter overhead will be incurred. In dynamic logic, because the output signal of the calculation unit drives the gate of the transistor, the output signal will not produce a continuous voltage drop, thus ensuring the accuracy of the signal and the calculation result.

[0038] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The purpose and other advantages of the present application are realized and obtained by the structures specifically pointed out in the description, claims and drawings.

[0039] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings.

[0040] Advantages of additional aspects of the present application will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0042] Figure 1 A circuit wiring diagram of a static complementary logic full adder shown in an embodiment of the present application;

[0043] Figure 2 This is a wiring diagram of the first version of the dynamic pull-down logic full adder circuit shown in the embodiment of the present application;

[0044] Figure 3 This is a final circuit wiring diagram of the dynamic pull-down logic full adder shown in the embodiment of the present application;

[0045] Figure 4 This is a signal timing diagram of a dynamic pull-down logic full adder shown in an embodiment of the present application;

[0046] Figure 5 It is a wiring diagram of a dynamic pull-down logic half adder circuit shown in an embodiment of the present application;

[0047] Figure 6 It is a wiring diagram of a dynamic pull-down logic multiplier circuit shown in an embodiment of the present application;

[0048] Figure 7 This is a wiring diagram of a dynamic pull-up logic half adder circuit shown in an embodiment of the present application;

[0049] Figure 8 This is a wiring diagram of a dynamic pull-up logic multiplier circuit shown in an embodiment of the present application;

[0050] Fig. 9 This is a wiring diagram of a dynamic pull-up logic full adder circuit shown in an embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0052] When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples of methods and systems consistent with some aspects of the present application as detailed in the attached claims.

[0053] In the description of the present application, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances. In addition, in the description of the present application, unless otherwise specified, "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship.

[0054] With the rapid development of large AI models, the parameters and calculation types of the models are becoming more and more complex, which means greater memory and power consumption overhead for chips with traditional architectures. As a breakthrough in the traditional von Neumann architecture, the integrated storage and computing architecture integrates storage and computing in hardware, greatly increasing the computing bandwidth while reducing data movement. For compute-intensive networks such as large AI models, it has high memory and power consumption benefits. However, there is an upper limit to the acceleration of network performance by the architecture. If you want to achieve a comprehensive improvement in digital chip performance based on the digital storage and computing architecture, you also need to make corresponding optimizations to the underlying multiplication and addition unit structure and computing logic.

[0055] The multiplication and addition unit is the core module of the digital storage and computing integrated computing array, and is also the main source of power consumption and delay. Improving the logic and computing structure of the multiplication and addition unit will effectively improve the energy efficiency and surface efficiency of the digital storage and computing core. This application intends to use dynamic logic to complete the design of the computing unit in the digital storage and computing integrated chip: on the one hand, the dynamic CMOS logic circuit design uses an independent pull-up / pull-down network to achieve the same addition function as the static complementary logic, and the number of transistors is reduced by half; on the other hand, dynamic CMOS logic has been widely used in the readout circuit of the memory, which can increase the stability of data storage and readout, can support higher frequencies, and is feasible.

[0056] The technical solution of this application is described in detail as follows:

[0057] The present application discloses a digital storage and calculation integrated chip based on dynamic logic calculation, which is composed of a multiplier circuit and / or a half adder circuit and / or a first full adder circuit and / or a second full adder circuit, including:

[0058] The primary circuit and the secondary circuit include a pull-up network and / or a pull-down network for realizing basic logic calculations; the primary circuit is started by a primary clock signal; the secondary circuit is started by a secondary clock signal;

[0059] In a specific implementation, the pull-down network includes: a first logic and a pull-down network, a second logic and a pull-down network, a first logic or a pull-down network, a second logic or a pull-down network, and a third logic or a pull-down network;

[0060] The first logic and pull-down network, the first logic or pull-down network and the third logic or pull-down network each include two NMOS tubes, and the gates of the two NMOS tubes are respectively connected to the A signal and the B signal; the second logic and pull-down network and the second logic or pull-down network each include three NMOS tubes, and the gates of the three NMOS tubes are respectively connected to the A signal, the B signal and the C signal. i Signal.

[0061] Charging transistor and discharging transistor; turned on and off according to the primary clock signal or the secondary clock signal, used to realize the calculation control of the pull-up network or the pull-down network and output the calculation result of the primary circuit to the secondary circuit for logic calculation.

[0062] Specifically in this embodiment, the charging transistor is a PMOS tube, including a first charging PMOS tube, a second charging PMOS tube, a third charging PMOS tube and a fourth charging PMOS tube; the discharging transistor is an NMOS tube, including: a first discharging NMOS tube, a second discharging NMOS tube and a third discharging NMOS tube.

[0063] In the specific design process, by referring to the basic CMOS unit structure under static complementary logic, the circuit analysis of basic logic units such as simple gate circuits, multipliers, half adders and full adders is completed. Then, the core logic calculation circuit is extracted, and an attempt is made to build a new logic calculation unit using the dynamic logic design method. It consists of a "pull-up network (PUN) / pull-down network (PDN) + charging transistor + discharging transistor", which can significantly reduce the number of transistors required for the adder. Finally, the obtained dynamic logic unit is simulated in a simulation environment, and an attempt is made to optimize the circuit structure to ensure correct function and increase signal margin.

[0064] Taking the full adder as an example, the logical expression of the full adder can be written as follows:

[0065] C o =A×B+C i (A+B)

[0066]

[0067] The obtained static complementary logic full adder structure is as follows Figure 1 As shown;

[0068] right Figure 1 The circuit structure of the circuit used to calculate S and Co is analyzed. The circuit structure used to calculate S and Co uses a pull-up network (PUN) and a pull-down network (PDN). Under dynamic logic design, only one set of networks can be selected. This application adopts the structure of "pull-down network + charging transistor + discharging transistor" to build the circuit structure of the first version of the dynamic pull-down logic full adder (the second full adder circuit), such as Figure 2 As shown,

[0069] Specifically, the first-level circuit of the second full adder circuit includes: a first logic and pull-down network, a first logic or pull-down network, a first NMOS tube, a first charging PMOS tube and a first discharging NMOS tube; the second-level circuit includes: a second logic and pull-down network, a second logic or pull-down network, a second NMOS tube, a second charging PMOS tube and a second discharging NMOS tube;

[0070] The output ends of the first logic and pull-down network, the second logic and pull-down network, the first logic or pull-down network, and the second logic or pull-down network are respectively connected to the drain of the first discharge NMOS tube and the drain of the second NMOS tube, the source of the first discharge NMOS tube and the source of the second NMOS tube are respectively grounded, and the gate of the first discharge NMOS tube and the gate of the second NMOS tube are respectively connected to the clock signal; the input end of the first logic non-pull-down network is connected to the source of the first NMOS tube, and the gate of the first NMOS tube is connected to C iThe drain of the first NMOS tube is respectively connected to the drain of the first charging PMOS tube, the input end of the first logic and pull-down network and the gate of the second NMOS tube, the gate of the first charging PMOS tube and the gate of the second charging PMOS tube are respectively connected to the clock signal, and the source of the first charging PMOS tube and the source of the second charging PMOS tube are respectively connected to the power supply voltage; the drain of the second NMOS tube and the input end of the second logic and pull-down network are respectively connected to the drain of the second charging PMOS tube, the source of the second NMOS tube is connected to the input end of the second logic or pull-down network, and the output end of the second logic or pull-down network is connected to the drain of the second discharging NMOS tube; the gate of the second discharging NMOS tube is connected to the clock signal, and the source of the second discharging NMOS tube is grounded; the input end of the second logic or pull-down network outputs the calculation result signal.

[0071] After completing the circuit structure design of the dynamic pull-down logic full adder, it was placed in a simulation environment for functional testing and verification. After testing, it was found that the parasitic capacitor used to store calculation information in the first version of the dynamic full adder was prone to charge leakage. In order to solve this problem, on the one hand, the transistor that is more difficult to leak is placed close to the charging transistor to increase the parasitic capacitance used to store charge information under the charging transistor. On the other hand, a charging transistor is added to the middle node to ensure that the potential on both sides of the transistor that is prone to leakage is balanced, so that the charge stored in the parasitic capacitor leaks less to the middle node. At the same time, because the full adder is a two-stage structure, the signal calculated by the previous stage needs a certain time delay to be transmitted to the next stage, and in one clock cycle, the next stage circuit is only allowed to calculate once. In order to ensure that the signal received by the next stage circuit is the result of the calculation of the previous stage, the delay between the next stage clock and the previous stage clock must be greater than the calculation and transmission delay.

[0072] After improvement Figure 3 The dynamic pull-down logic full adder (first full adder circuit) shown is described in detail as follows:

[0073] The first-level circuit of the first full adder circuit includes: a first NMOS tube, a first logic and pull-down network, a first logic or pull-down network, a first charging PMOS tube, a second charging PMOS tube, and a first discharging NMOS tube; the second-level circuit includes: a second NMOS tube, a second logic and pull-down network, a second logic or pull-down network, a third charging PMOS tube, a fourth charging PMOS tube, and a second discharging NMOS tube;

[0074] The source of the first charging PMOS tube is connected to the power supply voltage, the gate is connected to the first clock signal, the drain is connected to the drain of the first NOMS tube, and the gate of the first NOMS tube is connected to C i signal, the source of the first NMOS tube is connected to the drain of the first discharge NMOS tube, the gate of the first discharge NMOS tube is connected to the primary clock signal, and the source of the first discharge NMOS tube is grounded;

[0075] The source of the second charging PMOS tube is connected to the power supply voltage, the gate is connected to the first-level clock signal, the drain is respectively connected to the input end of the first logic or pull-down network, the input end of the first logic and pull-down network and the gate of the second NMOS tube, the output end of the first logic or pull-down network is respectively connected to the drain of the first charging PMOS tube and the drain of the first NMOS tube; the output end of the first logic and pull-down network is respectively connected to the drain of the first discharging NMOS tube and the source of the second discharging NMOS tube;

[0076] The source of the third charging PMOS tube is connected to the power supply voltage, the gate is connected to the secondary clock signal, and the drain is respectively connected to the second logic or pull-down network input terminal and the second logic and pull-down network input terminal; the output terminal of the second logic or pull-down network is respectively connected to the drain of the second NMOS tube and the drain of the fourth charging PMOS tube; the gate of the fourth charging PMOS tube is connected to the secondary clock signal, and the source is connected to the power supply voltage;

[0077] The output end of the second logic and pull-down network and the source of the second NMOS tube are respectively connected to the drain of the second discharge NMOS tube, and the gate of the second discharge NMOS tube is connected to the secondary clock signal.

[0078] The clock signal and input signal should meet the following requirements: Figure 4 The timing shown is:

[0079] Among them, the input signals A, B and C i It is established before the rising edge of the first-level clock, and after a certain delay (determined by the rise time, calculation delay and transmission delay), the output signal C of the first-level circuit is obtained. o ; The rising edge of the secondary clock needs to be obtained before C o After that, the input signals A, B and C i Still in the maintenance stage, A, B, C i and C o They participate in the operation of the secondary circuit together, and after a certain delay (determined by the rise time, calculation delay and transmission delay), the output signal S of the secondary circuit is obtained.

[0080] Similarly, the circuit structure design of dynamic pull-down logic half adder and dynamic pull-down logic multiplier can be obtained, such as Figure 5 and Figure 6 shown.

[0081] The logic expression of the dynamic pull-down logic half adder can be written as follows:

[0082]

[0083] The logical expression of the dynamic drop-down logic multiplier can be written as follows:

[0084]

[0085] The details are as follows:

[0086] The primary circuit of the half adder circuit includes: a first logic and pull-down network, a first charging PMOS tube, a second charging PMOS tube, a fourth charging PMOS tube and a first discharging NMOS tube; the secondary circuit includes: a first NMOS tube, a first logic or pull-down network, a third charging PMOS tube, and a second discharging NMOS tube;

[0087] The source electrodes of the first charging PMOS tube, the second charging PMOS tube, the third charging PMOS tube and the fourth charging PMOS tube are connected to the power supply voltage, the gate electrodes of the first charging PMOS tube, the second charging PMOS tube and the fourth charging PMOS tube are connected to the primary clock signal, the gate electrode of the third charging PMOS tube is connected to the secondary clock signal, the drain electrode of the first charging PMOS tube is connected to the middle connection point of two series-connected NMOS tubes in the first logic and pull-down network, the drain electrode of the second charging PMOS tube is respectively connected to the input end of the first logic and pull-down network and the gate electrode of the first NMOS tube, the output end of the first logic and pull-down network is respectively connected to the drain electrode of the first discharging NMOS tube and the source electrode of the second discharging NMOS tube, the gate electrode of the first discharging NMOS tube is connected to the primary clock signal, and the source electrode is grounded; the gate electrode of the second discharging NMOS tube is connected to the secondary clock signal, and the drain electrode is connected to the source electrode of the first NMOS tube; the drain electrode of the first NMOS tube is respectively connected to the output end of the first logic or pull-down network and the drain electrode of the fourth charging PMOS tube; the input end of the first logic or pull-down network is connected to the drain electrode of the third charging PMOS tube.

[0088] The primary circuit of the multiplier circuit includes: a first logic and pull-down network, a first logic or pull-down network, a first charging PMOS tube, a second charging PMOS tube, a first discharging NMOS tube, and a second discharging NMOS tube; the secondary circuit includes: a second charging PMOS tube, a third logic or pull-down network, and a third discharging NMOS tube;

[0089] The source of the first charging PMOS tube is connected to the power supply voltage, the gate is connected to the primary clock signal, the drain is connected to the input end of the first logic and pull-down network, and is connected to the gate of an NMOS tube in the third logic or pull-down network through an inverter, the output end of the first logic and pull-down network is connected to the drain of the first discharging NMOS tube, the gate of the first discharging NMOS tube is connected to the primary clock signal, and the source of the first discharging NMOS tube is grounded;

[0090] The source of the second charging PMOS tube is connected to the power supply voltage, the gate is connected to the primary clock signal, the drain is connected to the input end of the first logic or pull-down network, and is also connected to the gate of another NMOS tube in the third logic or pull-down network; the output end of the first logic or pull-down network is connected to the drain of the second discharging NMOS tube, the gate of the second discharging NMOS tube is connected to the primary clock signal, and the source of the second discharging NMOS tube is grounded;

[0091] The source of the third charging PMOS tube is connected to the power supply voltage, the gate is connected to the secondary clock signal, the drain is connected to the input end of the third logic or pull-down network, the output end of the third logic or pull-down network is connected to the drain of the third discharging NMOS tube, the gate of the third discharging NMOS tube is connected to the secondary clock signal, and the source of the third discharging NMOS tube is grounded.

[0092] The logic expressions of the half adder circuit, full adder circuit, and multiplier circuit of the dynamic pull-up logic are the same as above and will not be repeated here;

[0093] Similarly, the half adder circuit, full adder circuit, and multiplier circuit of dynamic pull-up logic designed according to the above expression are as follows Figure 7 , Figure 8 , Fig. 9 As shown, the details are as follows:

[0094] The primary circuit of the dynamic pull-up logic half adder circuit includes: a first logic and non-pull-up network, a first charging PMOS tube, a first discharging NMOS tube and a second discharging NMOS tube; the secondary circuit includes: a first logic or non-pull-up network, a second charging PMOS tube, a third discharging NMOS tube and a fourth discharging NMOS tube;

[0095] The drains of the first discharge NMOS tube, the second discharge NMOS tube, the third discharge NMOS tube, and the fourth discharge NMOS tube are grounded; the gates of the first charging PMOS tube, the first discharge NMOS tube, the second discharge NMOS tube, and the fourth discharge NMOS tube are connected to a primary clock signal, and the gates of the second charging PMOS tube and the third discharge NMOS tube are connected to a secondary clock signal; the source of the first discharge NMOS tube is connected to the middle connection of the two series-connected PMOS tubes in the first logic and non-pull-up network, and the source of the second discharge NMOS tube is connected to the first logic and non-pull-up network respectively. The input end of the network and the gate of the first PMOS tube, the output end of the first logic and non-pull-up network are respectively connected to the drain of the first charging PMOS tube and the source of the second charging PMOS tube, the gate of the first charging PMOS tube is connected to the primary clock signal, and the source is grounded; the gate of the second charging PMOS tube is connected to the secondary clock signal, and the drain is connected to the source of the first PMOS tube; the drain of the first NMOS tube is respectively connected to the output end of the first logic or non-pull-up network and the source of the fourth discharging NMOS tube; the input end of the first logic or non-pull-up network is connected to the source of the third discharging NMOS tube.

[0096] The first-level circuit of the dynamic pull-up logic multiplier circuit includes: a first logic or non-pull-up network, a first logic and non-pull-up network, a first charging PMOS tube, a second charging PMOS tube, a first discharging NMOS tube, and a second discharging NMOS tube; the second-level circuit includes: a third charging PMOS tube, a third logic and non-pull-up network, and a third discharging NMOS tube;

[0097] The source of the first charging PMOS tube is connected to the power supply voltage, the gate is connected to the primary clock signal, the drain is connected to the input end of the first logic or non-pull-up network, and is connected to the gate of a PMOS tube in the third logic and non-pull-up network through an inverter, the output end of the first logic or non-pull-up network is connected to the drain of the first discharging NMOS tube, the gate of the first discharging NMOS tube is connected to the primary clock signal, and the source of the first discharging NMOS tube is grounded;

[0098] The source of the second charging PMOS tube is connected to the power supply voltage, the gate is connected to the primary clock signal, the drain is connected to the input end of the first logic and non-pull-up network, and is also connected to the gate of another PMOS tube in the third logic and non-pull-up network; the output end of the first logic and non-pull-up network is connected to the drain of the second discharging NMOS tube, the gate of the second discharging NMOS tube is connected to the primary clock signal, and the source of the second discharging NMOS tube is grounded;

[0099] The source of the third charging PMOS tube is connected to the power supply voltage, the gate is connected to the secondary clock signal, the drain is connected to the input end of the third logic and non-pull-up network, the output end of the third logic and non-pull-up network is connected to the drain of the third discharging NMOS tube, the gate of the third discharging NMOS tube is connected to the secondary clock signal, and the source of the third discharging NMOS tube is grounded.

[0100] The primary circuit of the dynamic pull-up logic full adder circuit includes: a first logic or non-pull-up network, a first logic and non-pull-up network, a first PMOS tube, a first charging PMOS tube, a first discharging NMOS tube and a second discharging NMOS tube; the secondary circuit includes: a second logic or non-pull-up network, a second logic and non-pull-up network, a second PMOS tube, a second charging PMOS tube, a third discharging NMOS tube and a fourth discharging NMOS tube;

[0101] The first logic or non-pull-up network, the first logic and non-pull-up network and the gate of the second PMOS tube are connected to the drain of the second discharge NMOS tube; the output ends of the second logic or non-pull-up network and the second logic and non-pull-up network are connected to the drain of the third discharge NMOS tube; the source of the second discharge NMOS tube and the source of the third discharge NMOS tube are grounded respectively, and the gate of the second discharge NMOS tube and the gate of the third discharge NMOS tube are connected to the first and second level clock signals respectively; the input end of the first logic or non-pull-up network is connected to the drain of the first PMOS tube, and the gate of the first PMOS tube is connected to C i The signal is that the source of the first PMOS tube is respectively connected to the drain of the first charging PMOS tube, the input end of the first logic and non-pull-up network and the source of the second charging PMOS tube, the gate of the first charging PMOS tube and the gate of the second charging PMOS tube are respectively connected to the first and second clock signals, and the source of the first charging PMOS tube is connected to the power supply voltage; the source of the second PMOS tube and the input end of the second logic and non-pull-up network are respectively connected to the drain of the second charging PMOS tube, the drain of the second PMOS tube is connected to the input end of the second logic or non-pull-up network, and the output end of the second logic or non-pull-up network is connected to the drain of the second discharging NMOS tube; the drain of the first discharging NMOS tube is connected to the middle connection of the first logic or non-pull-up network and the first PMOS tube, and the source of the first discharging NMOS tube is grounded; the drain of the fourth discharging NMOS tube is connected to the middle connection of the second logic or non-pull-up network and the second PMOS tube, and the source of the fourth discharging NMOS tube is grounded; the output end of the second logic or non-pull-up network outputs the calculation result signal.

[0102] This application proposes a new multiplication and addition unit solution based on dynamic logic, which mainly optimizes the structure of multipliers and adders. The number of transistors used in the optimized multipliers and adders is greatly reduced, and the main indicators such as delay and power consumption are improved, which solves the problem of excessive energy consumption and area occupation in the process of digital storage and computing integrated chips for large AI models.

[0103] Although this specification is described according to implementation modes, not every implementation mode includes only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0104] In the description of the present application, it should be noted that relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, invention, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, invention, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, invention, article or device including the elements.

[0105] Therefore, the above description is only a preferred embodiment of the present application and is not intended to limit the scope of implementation of the present application; that is, all equivalent changes made according to the scope of the claims of the present application are within the protection scope of the claims of the present application.

[0106] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

[0107] The applicant of this application has made a detailed explanation and description of the implementation examples of this application in conjunction with the drawings in the specification. However, those skilled in the art should understand that the above implementation examples are only preferred implementation schemes of this application, and the detailed description is only to help readers better understand the spirit of this application, and it is not a limitation on the scope of protection of this application. On the contrary, any improvements or modifications based on the inventive spirit of this application should fall within the scope of protection of this application.

Claims

1. A digital storage and computing integrated chip based on dynamic logic calculation, characterized in that: The digital storage and computing integrated chip is composed of a multiplier circuit and / or a half adder circuit and / or a first full adder circuit and / or a second full adder circuit, including: The primary circuit and the secondary circuit include a pull-up network and / or a pull-down network for realizing basic logic calculations; the primary circuit is started by a primary clock signal; the secondary circuit is started by a secondary clock signal; Charging transistor and discharging transistor; turned on and off according to the primary clock signal or the secondary clock signal, used to realize the calculation control of the pull-up network or the pull-down network and output the calculation result of the primary circuit to the secondary circuit for logic calculation.

2. The digital storage and computing integrated chip based on dynamic logic calculation according to claim 1 is characterized in that: The pull-down network includes: a first logic and pull-down network, a second logic and pull-down network, a first logic or pull-down network, a second logic or pull-down network, and a third logic or pull-down network; The first logic and pull-down network, the first logic or pull-down network and the third logic or pull-down network each include two NMOS tubes, and the gates of the two NMOS tubes are respectively connected to the A signal and the B signal; the second logic and pull-down network and the second logic or pull-down network each include three NMOS tubes, and the gates of the three NMOS tubes are respectively connected to the A signal, the B signal and the C signal. i Signal.

3. The digital storage and computing integrated chip based on dynamic logic calculation according to claim 1 is characterized in that: The charging transistor is a PMOS tube, including a first charging PMOS tube, a second charging PMOS tube, a third charging PMOS tube and a fourth charging PMOS tube; the discharging transistor is an NMOS tube, including a first discharging NMOS tube, a second discharging NMOS tube and a third discharging NMOS tube.

4. The digital storage and computing integrated chip based on dynamic logic calculation according to claim 1 is characterized in that: The first-level circuit of the first full adder circuit includes: a first NMOS tube, a first logic and pull-down network, a first logic or pull-down network, a first charging PMOS tube, a second charging PMOS tube, and a first discharging NMOS tube; the second-level circuit includes: a second NMOS tube, a second logic and pull-down network, a second logic or pull-down network, a third charging PMOS tube, a fourth charging PMOS tube, and a second discharging NMOS tube; The source of the first charging PMOS tube is connected to the power supply voltage, the gate is connected to the first clock signal, the drain is connected to the drain of the first NOMS tube, and the gate of the first NOMS tube is connected to C i signal, the source of the first NMOS tube is connected to the drain of the first discharge NMOS tube, the gate of the first discharge NMOS tube is connected to the primary clock signal, and the source of the first discharge NMOS tube is grounded; The source of the second charging PMOS tube is connected to the power supply voltage, the gate is connected to the first-level clock signal, the drain is respectively connected to the input end of the first logic or pull-down network, the input end of the first logic and pull-down network and the gate of the second NMOS tube, the output end of the first logic or pull-down network is respectively connected to the drain of the first charging PMOS tube and the drain of the first NMOS tube; the output end of the first logic and pull-down network is respectively connected to the drain of the first discharging NMOS tube and the source of the second discharging NMOS tube; The source of the third charging PMOS tube is connected to the power supply voltage, the gate is connected to the secondary clock signal, and the drain is respectively connected to the second logic or pull-down network input terminal and the second logic and pull-down network input terminal; the output terminal of the second logic or pull-down network is respectively connected to the drain of the second NMOS tube and the drain of the fourth charging PMOS tube; the gate of the fourth charging PMOS tube is connected to the secondary clock signal, and the source is connected to the power supply voltage; The output end of the second logic and pull-down network and the source of the second NMOS tube are respectively connected to the drain of the second discharge NMOS tube, and the gate of the second discharge NMOS tube is connected to the secondary clock signal.

5. The digital storage and computing integrated chip based on dynamic logic calculation according to claim 4 is characterized in that: The delay time between the secondary clock signal and the primary clock signal is greater than the startup operation time of the primary circuit.

6. The digital storage and computing integrated chip based on dynamic logic calculation according to claim 1 is characterized in that: The first-level circuit of the multiplier circuit includes: a first logic and pull-down network, a first logic or pull-down network, a first charging PMOS tube, a second charging PMOS tube, a first discharging NMOS tube, and a second discharging NMOS tube; the second-level circuit includes: a third charging PMOS tube, a third logic or pull-down network, and a third discharging NMOS tube; The source of the first charging PMOS tube is connected to the power supply voltage, the gate is connected to the primary clock signal, the drain is connected to the input end of the first logic and pull-down network, and is connected to the gate of an NMOS tube in the third logic or pull-down network through an inverter, the output end of the first logic and pull-down network is connected to the drain of the first discharging NMOS tube, the gate of the first discharging NMOS tube is connected to the primary clock signal, and the source of the first discharging NMOS tube is grounded; The source of the second charging PMOS tube is connected to the power supply voltage, the gate is connected to the primary clock signal, the drain is connected to the input end of the first logic or pull-down network, and is also connected to the gate of another NMOS tube in the third logic or pull-down network; the output end of the first logic or pull-down network is connected to the drain of the second discharging NMOS tube, the gate of the second discharging NMOS tube is connected to the primary clock signal, and the source of the second discharging NMOS tube is grounded; The source of the third charging PMOS tube is connected to the power supply voltage, the gate is connected to the secondary clock signal, the drain is connected to the input end of the third logic or pull-down network, the output end of the third logic or pull-down network is connected to the drain of the third discharging NMOS tube, the gate of the third discharging NMOS tube is connected to the secondary clock signal, and the source of the third discharging NMOS tube is grounded.

7. The digital storage and computing integrated chip based on dynamic logic calculation according to claim 1 is characterized in that: The primary circuit of the half adder circuit includes: a first logic and pull-down network, a first charging PMOS tube, a second charging PMOS tube, a fourth charging PMOS tube and a first discharging NMOS tube; the secondary circuit includes: a first NMOS tube, a first logic or pull-down network, a third charging PMOS tube, and a second discharging NMOS tube; The source electrodes of the first charging PMOS tube, the second charging PMOS tube, the third charging PMOS tube and the fourth charging PMOS tube are connected to the power supply voltage, the gate electrodes of the first charging PMOS tube, the second charging PMOS tube and the fourth charging PMOS tube are connected to the primary clock signal, the gate electrode of the third charging PMOS tube is connected to the secondary clock signal, the drain electrode of the first charging PMOS tube is connected to the middle connection point of two series-connected NMOS tubes in the first logic and pull-down network, the drain electrode of the second charging PMOS tube is respectively connected to the input end of the first logic and pull-down network and the gate electrode of the first NMOS tube, the output end of the first logic and pull-down network is respectively connected to the drain electrode of the first discharging NMOS tube and the source electrode of the second discharging NMOS tube, the gate electrode of the first discharging NMOS tube is connected to the primary clock signal, and the source electrode is grounded; the gate electrode of the second discharging NMOS tube is connected to the secondary clock signal, and the drain electrode is connected to the source electrode of the first NMOS tube; the drain electrode of the first NMOS tube is respectively connected to the output end of the first logic or pull-down network and the drain electrode of the fourth charging PMOS tube; the input end of the first logic or pull-down network is connected to the drain electrode of the third charging PMOS tube.

8. The digital storage and computing integrated chip based on dynamic logic calculation according to claim 1 is characterized in that: The first-level circuit of the second full adder circuit includes: a first logic and pull-down network, a first logic or pull-down network, a first NMOS tube, a first charging PMOS tube and a first discharging NMOS tube; the second-level circuit includes: a second logic and pull-down network, a second logic or pull-down network, a second NMOS tube, a second charging PMOS tube and a second discharging NMOS tube; The output ends of the first logic and pull-down network, the second logic and pull-down network, the first logic or pull-down network, and the second logic or pull-down network are respectively connected to the drain of the first discharge NMOS tube and the drain of the second NMOS tube, the source of the first discharge NMOS tube and the source of the second NMOS tube are respectively grounded, and the gate of the first discharge NMOS tube and the gate of the second NMOS tube are respectively connected to the clock signal; the input end of the first logic non-pull-down network is connected to the source of the first NMOS tube, and the gate of the first NMOS tube is connected to C i The drain of the first NMOS tube is respectively connected to the drain of the first charging PMOS tube, the input end of the first logic and pull-down network and the gate of the second NMOS tube, the gate of the first charging PMOS tube and the gate of the second charging PMOS tube are respectively connected to the clock signal, and the source of the first charging PMOS tube and the source of the second charging PMOS tube are respectively connected to the power supply voltage; the drain of the second NMOS tube and the input end of the second logic and pull-down network are respectively connected to the drain of the second charging PMOS tube, the source of the second NMOS tube is connected to the input end of the second logic or pull-down network, and the output end of the second logic or pull-down network is connected to the drain of the second discharging NMOS tube; the gate of the second discharging NMOS tube is connected to the clock signal, and the source of the second discharging NMOS tube is grounded; the input end of the second logic or pull-down network outputs the calculation result signal.

9. The digital storage and computing integrated chip based on dynamic logic calculation according to claim 1 is characterized in that: The primary circuit of the pull-up logic half adder circuit includes: a first logic AND non-pull-up network, a first charging PMOS tube, a first discharging NMOS tube and a second discharging NMOS tube; the secondary circuit includes: a first logic OR non-pull-up network, a second charging PMOS tube, a third discharging NMOS tube and a fourth discharging NMOS tube; The drains of the first discharge NMOS tube, the second discharge NMOS tube, the third discharge NMOS tube, and the fourth discharge NMOS tube are grounded; the gates of the first charging PMOS tube, the first discharge NMOS tube, the second discharge NMOS tube, and the fourth discharge NMOS tube are connected to a primary clock signal, and the gates of the second charging PMOS tube and the third discharge NMOS tube are connected to a secondary clock signal; the source of the first discharge NMOS tube is connected to the middle connection of the two series-connected PMOS tubes in the first logic and non-pull-up network, and the source of the second discharge NMOS tube is connected to the first logic and non-pull-up network respectively. The input end of the network and the gate of the first PMOS tube, the output end of the first logic and non-pull-up network are respectively connected to the drain of the first charging PMOS tube and the source of the second charging PMOS tube, the gate of the first charging PMOS tube is connected to the primary clock signal, and the source is grounded; the gate of the second charging PMOS tube is connected to the secondary clock signal, and the drain is connected to the source of the first PMOS tube; the drain of the first NMOS tube is respectively connected to the output end of the first logic or non-pull-up network and the source of the fourth discharging NMOS tube; the input end of the first logic or non-pull-up network is connected to the source of the third discharging NMOS tube.

10. The digital storage and computing integrated chip based on dynamic logic calculation according to claim 1, characterized in that: The primary circuit of the pull-up logic multiplier circuit includes: a first logic or non-pull-up network, a first logic and non-pull-up network, a first charging PMOS tube, a second charging PMOS tube, a first discharging NMOS tube, and a second discharging NMOS tube; the secondary circuit includes: a third charging PMOS tube, a third logic and non-pull-up network, and a third discharging NMOS tube; The source of the first charging PMOS tube is connected to the power supply voltage, the gate is connected to the primary clock signal, the drain is connected to the input end of the first logic or non-pull-up network, and is connected to the gate of a PMOS tube in the third logic and non-pull-up network through an inverter, the output end of the first logic or non-pull-up network is connected to the drain of the first discharging NMOS tube, the gate of the first discharging NMOS tube is connected to the primary clock signal, and the source of the first discharging NMOS tube is grounded; The source of the second charging PMOS tube is connected to the power supply voltage, the gate is connected to the primary clock signal, the drain is connected to the input end of the first logic and non-pull-up network, and is also connected to the gate of another PMOS tube in the third logic and non-pull-up network; the output end of the first logic and non-pull-up network is connected to the drain of the second discharging NMOS tube, the gate of the second discharging NMOS tube is connected to the primary clock signal, and the source of the second discharging NMOS tube is grounded; The source of the third charging PMOS tube is connected to the power supply voltage, the gate is connected to the secondary clock signal, the drain is connected to the input end of the third logic and non-pull-up network, the output end of the third logic and non-pull-up network is connected to the drain of the third discharging NMOS tube, the gate of the third discharging NMOS tube is connected to the secondary clock signal, and the source of the third discharging NMOS tube is grounded.

11. The digital storage and computing integrated chip based on dynamic logic calculation according to claim 1, characterized in that: The primary circuit of the pull-up logic full adder circuit includes: a first logic or non-pull-up network, a first logic and non-pull-up network, a first PMOS tube, a first charging PMOS tube, a first discharging NMOS tube and a second discharging NMOS tube; the secondary circuit includes: a second logic or non-pull-up network, a second logic and non-pull-up network, a second PMOS tube, a second charging PMOS tube, a third discharging NMOS tube and a fourth discharging NMOS tube; The first logic or non-pull-up network, the first logic and non-pull-up network and the gate of the second PMOS tube are connected to the drain of the second discharge NMOS tube; the output ends of the second logic or non-pull-up network and the second logic and non-pull-up network are connected to the drain of the third discharge NMOS tube; the source of the second discharge NMOS tube and the source of the third discharge NMOS tube are grounded respectively, and the gate of the second discharge NMOS tube and the gate of the third discharge NMOS tube are connected to the first and second level clock signals respectively; the input end of the first logic or non-pull-up network is connected to the drain of the first PMOS tube, and the gate of the first PMOS tube is connected to C i The signal is that the source of the first PMOS tube is respectively connected to the drain of the first charging PMOS tube, the input end of the first logic and non-pull-up network and the source of the second charging PMOS tube, the gate of the first charging PMOS tube and the gate of the second charging PMOS tube are respectively connected to the first and second clock signals, and the source of the first charging PMOS tube is connected to the power supply voltage; the source of the second PMOS tube and the input end of the second logic and non-pull-up network are respectively connected to the drain of the second charging PMOS tube, the drain of the second PMOS tube is connected to the input end of the second logic or non-pull-up network, and the output end of the second logic or non-pull-up network is connected to the drain of the second discharging NMOS tube; the drain of the first discharging NMOS tube is connected to the middle connection of the first logic or non-pull-up network and the first PMOS tube, and the source of the first discharging NMOS tube is grounded; the drain of the fourth discharging NMOS tube is connected to the middle connection of the second logic or non-pull-up network and the second PMOS tube, and the source of the fourth discharging NMOS tube is grounded; the output end of the second logic or non-pull-up network outputs the calculation result signal.

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