Linear gating design for multi-core chip power grid model

Abstract

The invention relates to the field of integrated circuit design and optimization, and discloses a gating design method for a multi-core chip power grid model. According to the technology, simulation tool requirements and an actual power grid model are combined, control over the core start-stop position of the multi-core chip is optimized, and boundary difference is effectively eliminated. The method mainly comprises the following steps of: selecting and determining a layer of circuit structure as an interlayer structure, and partitioning a 64-core chip through a partition circuit; gating is realized above each chip by adopting a structure of combining a current source and a resistor. When the core is closed, a large resistor and an extremely small current are set to ensure that a gating position has stable voltage drop; when the core is turned on, the electrical characteristic of the position is consistent with other interlayer resistors of the IBM, and the current source is turned off. By adjusting the resistance value and the size of the current source, accurate regulation and control of the core position in the gating process are achieved, and global optimization of SPICE simulation is supported.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design and optimization, and in particular relates to a gate control design method applied to a multi-core chip power grid model. Background Art

[0002] At present, the thermal management of system-level chips mainly relies on dynamic voltage and frequency scaling (DVFS) and task migration. In the process of adjusting chip voltage and frequency, voltage drop (IrDrop) is a crucial factor. For modern multi-core chips, since most cores are usually in dark silicon state, many standardized models often default to the worst voltage drop of the entire chip as a unified assumption when formulating thermal management solutions. Although this simplified strategy improves the implementation efficiency of the DVFS algorithm, it also introduces considerable errors. To address this problem, the present invention proposes a new gating design and model construction method, which can combine the dark silicon state and the start and stop positions of different cores under transient and steady-state analysis to complete accurate modeling and simulation of core power and frequency.

[0003] In addition, in the design and optimization process of multi-core chips, the analysis of the power supply network is also crucial, especially in circuits using gated design, which need to be evaluated from two key aspects: one is to ensure that the voltage drop in the placement area is always kept within the allowable range; the other is to ensure that the peak current during the wake-up process does not exceed the system's tolerance. Voltage drop analysis is usually based on steady-state analysis. By evaluating the voltage drop distribution, the position of the current switch is adjusted to determine whether the switch needs to be added or removed. For the analysis of the peak wake-up current, transient analysis is required to ensure that the maximum current flowing through the Vdd or Vss grid does not cause any functional interference to the adjacent modules that are still working.

[0004] The present invention provides an innovative solution to these key issues, which can not only significantly improve the accuracy and efficiency of thermal management of multi-core chips, but also optimize the performance and reliability of the power supply network, providing more comprehensive and efficient technical support for chip design. Summary of the invention

[0005] In view of the shortcomings of the prior art, the present invention proposes a linear gating design model for solving the voltage drop of multi-core chips. The model can realize grid gating with a simple circuit model on the basis of ensuring the isomorphism of multi-core chips. This model can be applied to most simulation tools and provides a good solution for solving the voltage drop of multi-core chips.

[0006] The present invention is based on the ibmpg2 model in IBM Power Grid Benchmarks. The original model includes 8 metal layers and more than 127238 nodes, and has sufficient complexity to simulate the power grid structure of multi-core chips. During the experiment, in order to collect data to train neural networks, we have high requirements on the speed of simulation tools. However, traditional simulation tools (such as Hspice) have limitations in CMOS circuit calculations and are difficult to meet experimental requirements. Therefore, the present invention proposes an improved model, using voltage source and resistor to realize gate control function, to replace traditional methods.

[0007] In the IBM power grid model, there are line resistance and layer resistance between the 8 metal layers. The transistors and power consumption parts between the fourth and fifth layers are replaced by current sources: the first layer is connected to Vdd, and the eighth layer is connected to GND. In order to optimize the model, the present invention makes the following improvements to the original structure: copy the fourth layer nodes to the fifth layer, renumber the original fifth to eighth layers as the sixth to ninth layers, and add a resistor R and a current source Ids in parallel between the newly added fourth and fifth layers (such as Figure 1 shown).

[0008] For a specific map, such as a 64-core chip, we divide the fifth layer into an 8×8 grid according to the number of cores. For the cores that are turned on, the resistors at the corresponding positions are set to normal interlayer resistors, and the current source value is set to 0mA; for the cores that are turned off, the resistors are set to a larger value, and the current source value is calculated according to the formula V (about 60% Vdd) / resistance value, so as to ensure that the interlayer voltage drop is a certain value.

[0009] Finally, by modifying the model's boundaries, integrating and removing irregular nodes, we generated a regularized 64-core power grid model, which provides an efficient and accurate basis for the power network simulation of multi-core chips. This improved model is not only suitable for training neural networks, but also improves simulation speed and stability.

[0010] The following important points also serve as auxiliary evidence for the creativity of the claims of the present invention: (1) the expected benefits and commercial value of the technical solution of the present invention after transformation: (2) the technical solution of the present invention fills the technical gaps in the industry at home and abroad: (3) whether the technical solution of the present invention solves the technical problems that people have been eager to solve but have never succeeded in solving: (4) whether the technical solution of the present invention overcomes technical prejudice. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solution of the embodiment of the present invention, the following briefly introduces the drawings involved in the embodiment of the present invention. It should be noted that the following drawings are only some embodiments of the present invention, and technicians in the relevant fields can derive other drawings based on these drawings without creative work.

[0012] Figure 1 : Shows the schematic diagram of the structure of the IBM power grid three-dimensional original model used in the linear gating design of the multi-core chip power grid model of the present invention.

[0013] Figure 2 : It illustrates the improved structure of the multi-core chip power grid model of the present invention, reflecting the overall layout of the linear gating design.

[0014] Figure 3 : Provides a schematic diagram of the functional unit layout (FLP) of a 64-core chip in the present invention.

[0015] Figure 4 : A specific schematic diagram showing the 4th layer interlayer connection structure of the IBM power grid model in the present invention.

[0016] Figure 5 : Displays the voltage distribution of the 6th and 7th layers (Vdd and VSS) of the IBM power grid model in the present invention. DETAILED DESCRIPTION

[0017] Step 1: Get the original grid model

[0018] Download and obtain the ibmpg2 model in IBM Power Grid Benchmarks, observe and analyze the inter-layer structure and interconnection mode of each layer (such as Figure 4 ), and obtain the distribution of power nodes (as shown Figure 5 By analyzing the connection mode between layers and the positions of current sources and voltage sources in the original model, a structural schematic diagram of the original 3D model of the IBM power grid is generated (as shown in Figure 1 shown).

[0019] Step 2: Transform the grid model

[0020] 1. Extract the node array data of the fourth layer, copy this data as a new layer and insert it between the fourth and fifth layers of the original model.

[0021] 2. Partition the new layer according to the 8×8 core position distribution:

[0022] o The new layer and the fourth layer are interconnected through a variable current source and a variable resistor connected in parallel.

[0023] oThe new layer is connected to the fifth layer by a transistor-equivalent current source that can be adjusted according to the core frequency and core voltage.

[0024] 3. Observe the interconnection method between layers. The nodes between the new layer and the fifth layer are interconnected by a unified offset instead of a direct corresponding connection. For example:

[0025] o iBG_0_v n1_200_809400

[0026] o iBG_0_g 0n0_176_80580

[0027] o iBG_1_v n1_200_816600

[0028] o iBG_1_g 0n0_176_81300

[0029] 4. Considering the particularity of the boundary, a node in the new layer may be connected to two nodes in the fifth layer, which will introduce boundary differences when calculating voltage drop and current amplitude, resulting in a large voltage drop in the boundary core. To solve this problem, the nodes in the new layer are strictly constrained to be connected to a single node in the fifth layer, thereby maintaining consistency within the core and minimizing the structural voltage drop error between the 64 cores.

[0030] Step 3: Simulation and iterative calculation

[0031] 1. According to different core powers, frequencies and open core positions, the entire power grid model is assigned values, and the voltage drop is calculated using Hspice simulation.

[0032] 2. Determine the initial value:

[0033] o Core voltage V core =Vdd0-IR0

[0034] o Core current I core =Core power / Vcore

[0035] 3. Use Hspice simulation to get new IR1 and Vdd1, and update the voltage and current values ​​of each core.

[0036] 4. Repeat the above steps iteratively until the voltage drop of the entire chip network converges and the accurate calculation is completed.

[0037] Step 4: Model optimization

[0038] oThe simulation speed and accuracy of the model can be further optimized by adjusting parameters such as current sources, resistors, and offset rules.

[0039] o The optimized model is suitable for more complex multi-core chip power networks and improves support for dynamic voltage and frequency scaling (DVFS) and thermal management.

[0040] Through the above method, the design and optimization of the multi-core chip power grid model can be completed efficiently and accurately, and technical support can be provided for power network analysis and thermal management in practical applications.

Claims

1. A multi-core chip voltage drop fast prediction method based on convolutional neural network, characterized in that: The performance and frequency of the system are improved by modifying the dynamic frequency-voltage matching relationship in real time. The method includes: obtaining the initial training value by running multiple benchmark tests, using an iterative method to process data and obtain the voltage drop of multi-core chips, building a deep learning architecture based on a convolutional neural network, and testing and using the new method based on the Hotsniper tool.

2. The multi-core chip voltage drop fast prediction method based on convolutional neural network as claimed in claim 1, characterized in that The iterative method is used to deal with the problem of IRDrop having no initial value, and a convolutional neural network is used to replace the Hspice iterative calculation process.

3. The multi-core chip voltage drop fast prediction method according to claim 2, characterized in that The frequency range of the training data is 1GHz to 4GHz, and the power budget range is 0.1W to 5.1W.

4. The multi-core chip voltage drop fast prediction method according to claim 3 is characterized in that A gating grid model has been added and a method for replacing nonlinear gating with linear gating has been added.

5. The multi-core chip voltage drop fast prediction method according to claim 4, characterized in that A handshake method for internal and external links in Docker.

6. The application of the multi-core chip voltage drop fast prediction method according to claims 1 to 5, characterized in that In the dark silicon state, multi-core chips solve the on-chip voltage drop to solve the matching pair problem of the dynamic voltage and frequency adjustment algorithm, including but not limited to the iterative solution of voltage drop involved in task migration in thermal management and dynamic voltage adjustment.

7. A neural network solves power grid wiring prediction, characterized in that The information data processing and gate setting method replaces the nonlinear method with the linear method as shown in claims 3 to 4.

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