Semiconductor device, manufacturing method thereof and electronic device

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and an electronic device, and the manufacturing method comprises the steps: providing a wafer which comprises a semiconductor substrate and a hard mask layer; a first edge protection ring is arranged on the edge of the wafer, the hard mask layer on the inner side of the first edge protection ring is etched to form an opening for defining a deep trench isolation structure in the hard mask layer, and the inner diameter of the first edge protection ring is smaller than the diameter of the wafer; and a second edge protection ring is arranged on the edge of the wafer, the semiconductor substrate below the opening on the inner side of the second edge protection ring is etched so as to form a deep groove in the semiconductor substrate, and the inner diameter of the second edge protection ring is larger than that of the first edge protection ring. According to the invention, grass growth at the bottom of the deep groove at the edge of the wafer can be avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] Deep Trench Isolation (DTI) is an isolation technology used in integrated circuit manufacturing. It is mainly used to isolate different devices to prevent mutual influence. This technology is usually used in deep submicron and nanometer scale integrated circuit manufacturing processes. Deep trench isolation can effectively prevent device crosstalk and current leakage, realize high-density device layout on the chip, reduce capacitance, and help improve chip performance. Therefore, it is widely used in integrated circuit manufacturing.

[0003] The formation process of deep trench isolation structure mainly includes etching semiconductor to form deep trench and then filling the deep trench with insulating material. During the etching reaction, an edge protection ring is usually set at the edge of the wafer. The existence of the edge protection ring will change the electric field strength near the ring, which will reduce the etching rate near the ring, thus causing grass to form at the bottom of the deep trench and even cause the wafer to crack. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In view of the existing problems, an embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: Providing a wafer, the wafer comprising a semiconductor substrate and a hard mask layer formed on the semiconductor substrate; Disposing a first edge protection ring at the edge of the wafer, and etching the hard mask layer inside the first edge protection ring to form an opening defining a deep trench isolation structure in the hard mask layer, wherein the inner diameter of the first edge protection ring is smaller than the diameter of the wafer; A second edge protection ring is disposed at the edge of the wafer, and the semiconductor substrate below the opening inside the second edge protection ring is etched to form a deep groove in the semiconductor substrate, wherein the inner diameter of the second edge protection ring is greater than the inner diameter of the first edge protection ring.

[0006] In one embodiment, a difference between the inner diameters of the second edge protection ring and the first edge protection ring is greater than or equal to 1 mm.

[0007] In one embodiment, the inner diameter of the first edge protection ring is 297 mm, and the inner diameter of the second edge protection ring is 298 mm.

[0008] In one embodiment, providing a first edge protection ring at the edge of the wafer includes: Placing the wafer in a first etching reaction chamber provided with the first edge protection ring; The step of providing a second edge protection ring at the edge of the wafer comprises: The wafer is placed in a second etching reaction chamber equipped with the second edge protection ring.

[0009] In one embodiment, the first etching reaction chamber or the second etching reaction chamber comprises an upper radio frequency system and a lower radio frequency system, wherein the upper radio frequency system is used to dissociate the etching reaction gas to form plasma. The lower radio frequency system is used to apply a bias voltage to the wafer to pull the plasma to move toward the wafer.

[0010] In one embodiment, the method further comprises: During the process of etching the semiconductor substrate, the bias voltage and / or the gas pressure of the etching reaction gas is adjusted in real time to control the moving direction of the plasma.

[0011] In one embodiment, etching the semiconductor substrate below the opening inside the second edge protection ring to form a deep trench in the semiconductor substrate comprises cyclically performing the following steps: Etching step: etching the semiconductor substrate to form a groove; Deposition step: depositing a passivation layer on the bottom and sidewalls of the trench; Removing step: removing the passivation layer at the bottom of the trench to expose the semiconductor substrate at the bottom of the trench.

[0012] In one embodiment, the method further comprises: In the process of etching the semiconductor substrate, the execution time of the etching step, the deposition step and the cleaning step is adjusted in real time to adjust the morphology of the deep trench.

[0013] A second aspect of an embodiment of the present invention provides a semiconductor device, wherein the semiconductor device is manufactured by using the above method.

[0014] A third aspect of an embodiment of the present invention provides an electronic device, which includes the semiconductor device described above.

[0015] According to the semiconductor device and its manufacturing method and electronic device provided by the present invention, a first edge protection ring with a smaller inner diameter is used in the process of etching the hard mask layer, so that the remaining amount of the hard mask layer shielded by the first edge protection ring is larger; a second edge protection ring with a larger inner diameter is used in the process of etching the semiconductor substrate, and the hard mask layer retained near the second edge protection ring blocks the etching of the semiconductor substrate below, thereby avoiding the low etching rate near the second edge protection ring causing grass to grow at the bottom of the deep trench, thereby improving the yield of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following drawings of the present invention are used as part of the present invention for understanding the present invention. The drawings show embodiments of the present invention and their descriptions to explain the principles of the present invention. In the drawings: Figures 1A to 1C A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing various steps according to a method for manufacturing a semiconductor device in the related art is shown; Figure 2 A schematic diagram showing an edge protection ring shielding a wafer edge; Figure 3 A curve diagram showing the change of electric field intensity at the edge of the wafer under different edge masking widths; Figure 4 The SEM (scanning electron microscope) image shows the grass growth at the bottom of the deep trench on the edge of the wafer; Figure 5 A schematic flow chart showing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention; Fig. 6A and Figure 6B A schematic diagram showing replacement of an edge protection ring during implementation of a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown; 7A to 7C A schematic cross-sectional view of a semiconductor device obtained by sequentially implementing each step of a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown; Figure 8 A SEM cross-sectional view of a wafer edge obtained by a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown; Fig. 9 A SEM cross-sectional view of the interior of a groove at the edge of a wafer obtained by a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown. DETAILED DESCRIPTION

[0017] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0018] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0019] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0020] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0021] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0022] The deep trench etching process mainly includes two parts: hard mask layer etching and semiconductor substrate etching. Figure 1A and Figure 1B As shown, the hard mask layer etching includes forming a photoresist layer 103 on the hard mask layer 102, and etching the hard mask layer 102 using the photoresist layer 103 as a mask to form an opening; as shown in FIG. Figure 1C As shown, the semiconductor substrate etching includes etching the semiconductor substrate 101 based on the patterned hard mask layer 102 to form a deep trench.

[0023] Among them, the Bosch etching process is usually used to etch the semiconductor substrate, that is, the etching step, the deposition step and the cleaning step are performed cyclically. The etching step is to etch the semiconductor substrate to form a groove, the deposition step is to deposit a passivation layer in the groove, and the cleaning step is to remove the passivation layer at the bottom of the groove to expose the semiconductor substrate, so that the semiconductor substrate exposed at the bottom of the groove continues to be etched downward in the next cycle. Through the alternating execution of the above steps, the Bosch etching process can achieve high aspect ratio etching, and the passivation layer is used to protect the sidewall of the groove during the etching process, ensuring that the sidewall is vertically cut and smooth, reducing lateral etching, and is therefore more suitable for manufacturing deep trench isolation structures.

[0024] like Figure 2 As shown, in order to protect the edge of the wafer, an edge protection ring 202 made of ceramic material is usually provided on the electrostatic chuck 201 of the reaction chamber during the etching process. Figure 3 As shown, the presence of the edge protection ring 202 will change the electric field strength in the vicinity, which will reduce the etching rate at the edge of the wafer 200, making the etching ability at this location weaker and making it impossible to completely remove the passivation layer 104 at the bottom of the groove (see Figure 1B and Figure 1C ), which causes etching barrier to the semiconductor substrate under the residual passivation layer, and finally produces Figure 4 The silicon spikes, or "grass," shown here may in turn cause cracks in the semiconductor substrate.

[0025] In view of the existence of the above technical problems, an embodiment of the present invention provides a method for preparing a semiconductor device. Figures 5 to 9 The method for preparing a semiconductor device according to an embodiment of the present invention is described in detail, wherein: Figure 5 A schematic flow chart showing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown. Fig. 6A and Figure 6B A schematic diagram showing replacement of an edge protection ring during implementation of a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown; 7A to 7C A schematic cross-sectional view of a semiconductor device obtained by sequentially implementing each step of a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown; Figure 8 and Fig. 9 A SEM cross-sectional view of a wafer obtained by a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown.

[0026] First, step S501 is performed to provide a wafer, such as Fig. 7A As shown, the wafer includes a semiconductor substrate 701 and a hard mask layer 702 formed on the semiconductor substrate 701 .

[0027] The material of the semiconductor substrate 701 includes but is not limited to at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, or silicon on dielectric (SOI), stacked silicon on dielectric (SSOI), stacked silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI) and germanium on dielectric (GeOI).

[0028] A hard mask layer 702 is formed on the semiconductor substrate 701. Since the depth of the deep trench isolation structure is relatively large, the photoresist layer will be seriously damaged when being etched using the photoresist layer, and therefore a thicker photoresist layer needs to be formed. The increase in the thickness of the photoresist layer will also increase the possibility of its tipping. In contrast, if the pattern of the photoresist layer is first transferred to the hard mask layer 702, and then the semiconductor substrate 701 is etched using the hard mask layer 702 as a mask, since the thickness of the hard mask layer 702 is relatively thin, the photoresist layer is basically not damaged when etching the hard mask layer 702; when etching the semiconductor substrate 701 using the hard mask layer 702 as a mask, it is also easier to reach a higher etching depth due to the minimal damage to the hard mask layer 702.

[0029] The material of the hard mask layer 702 may include one or more combinations of nitride, oxide, oxynitride, fluorinated silicon dioxide (FSG), carbon-doped silicon oxide, etc. Methods for forming the hard mask layer 702 include but are not limited to chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc.

[0030] After forming the hard mask layer 702, a photoresist layer 703 is formed on the hard mask layer 702, and the photoresist layer 703 is exposed and developed to form a window defining a deep trench isolation structure. The main components of the photoresist layer 703 are resin and photosensitive agent. The photosensitive agent has photosensitive properties, and the resin has adhesive properties. For positive photoresist, the resin is relatively insoluble before exposure, and a chemical reaction occurs after exposure, changing from insoluble to soluble, so that it is removed in the development step, and a window is formed in the photoresist layer.

[0031] Next, execute step S502, such as Fig. 6A As shown, a first edge protection ring 601 is disposed at the edge of the wafer 600, and the inner diameter of the first edge protection ring 601 is smaller than the diameter of the wafer 600; Figure 7B As shown, the hard mask layer 702 inside the first edge protection ring 601 is etched to form an opening in the hard mask layer 702 .

[0032] Exemplarily, the first edge protection ring 601 is arranged at the edge of the wafer 600, specifically comprising: placing the wafer 600 in a first etching reaction chamber provided with the first edge protection ring 601. The first etching reaction chamber can place the wafer 600 and introduce etching reaction gas, and form plasma by applying energy through a radio frequency system, thereby completing etching, so the etching reaction chamber can also be called a plasma reaction chamber.

[0033] The embodiment of the present invention may use two etching reaction chambers, the first etching reaction chamber is configured with a first edge protection ring 601 for etching the hard mask layer 702, and the second etching reaction chamber is configured with a second edge protection ring 602 for etching the semiconductor substrate 701. Optionally, the etching of the hard mask layer 702 and the semiconductor substrate 701 may be completed in the same etching reaction chamber by replacing the edge protection rings.

[0034] Placing the wafer 600 in the first etching reaction chamber may specifically include fixing the wafer 600 on an electrostatic chuck in the first etching reaction chamber. Exemplarily, the electrostatic chuck includes at least a base and an electrostatic adsorption layer. An RF feed-in may be provided in the base, which is used to be electrically connected to an RF power supply so as to apply a bias voltage to the wafer. The electrostatic adsorption layer is usually made of an insulating material such as ceramic, and an adsorption electrode is provided therein for fixing the wafer 600 on the electrostatic chuck by electrostatic adsorption. Optionally, a temperature regulating layer is also provided between the base and the electrostatic adsorption layer for regulating the temperature of the wafer 600.

[0035] After the wafer 600 is placed on the electrostatic chuck, a first edge protection ring 601 is disposed at the edge of the wafer 600 to protect the edge of the wafer and avoid etching of the inclined area at the edge of the wafer 600. Fig. 6A As shown, the inner diameter (inner diameter) of the first edge protection ring 601 is smaller than the diameter of the wafer 600, so as to shield a certain range of the edge of the wafer 600. In one example, for a wafer with a diameter of about 300 mm, a first edge protection ring 601 with an inner diameter of 297 mm can be used, that is, the annular area with a width of about 1.5 mm at the edge of the wafer 600 will not be bombarded by plasma because it is shielded by the first edge protection ring 601.

[0036] After the wafer 600 is set, the etching reaction gas is introduced into the first etching reaction chamber, and the radio frequency system is started to etch the hard mask layer 702. Specifically, the first etching reaction chamber includes an upper radio frequency system and a lower radio frequency system, the upper radio frequency system is used to dissociate the etching reaction gas to form plasma, and the lower radio frequency system is used to apply a bias voltage to the wafer to pull the plasma to move toward the wafer.

[0037] Furthermore, the upper RF system can output a 13.56 MHz continuous wave and maintain the dissociation of the reaction gas, and the lower RF system can output a 400 KHz adjustable frequency pulse wave, with a pulse frequency range of 150 Hz -5000 Hz and a duty cycle range of 10% -90%. The lower RF system allows an external bias to be applied to the wafer 600, pulling the plasma generated by the upper RF ignition to move toward the surface of the wafer 600.

[0038] In addition, the etching reaction parameters used for etching the hard mask layer 702 also include but are not limited to: chamber gas pressure 20mT-80mT; upper RF power 2000W-3000W; lower RF power 0-800W; lower RF pulse frequency 1000Hz; lower RF pulse duty cycle 100%, and etching reaction gas is CF4, O2, Ar, etc.

[0039] Next, execute step S503, such as Figure 6BAs shown, a second edge protection ring 602 is disposed at the edge of the wafer 600, and the inner diameter of the second edge protection ring 602 is greater than the inner diameter of the first edge protection ring 601; Figure 7C As shown, the semiconductor substrate 701 below the opening inside the second edge protection ring 602 is etched to form a deep trench in the semiconductor substrate 701 .

[0040] In one embodiment, disposing a second edge protection ring 602 at the edge of the wafer 600 specifically includes: placing the wafer 600 in a second etching reaction chamber equipped with the second edge protection ring 602. The second etching reaction chamber is the same as or different from the first etching reaction chamber.

[0041] like Figure 6B As shown, since the inner diameter of the second edge protection ring 602 is larger than the inner diameter of the first edge protection ring 601, the area 603 near the edge of the wafer 600 that was originally shielded by the first edge protection ring 601 is exposed by the second edge protection ring 602. In other words, the area inside the second edge protection ring 602 includes a shielded area (i.e., an area shielded by the first edge protection ring 601 in step S502) and an unshielded area (i.e., an area not shielded by the first edge protection ring 601 in step S502). Figure 7C As shown, in the shielded area, the hard mask layer 702 is not etched and thus no opening exposing the semiconductor substrate 701 is formed. Therefore, in step S503, a deep trench is formed only in the unshielded area, but not in the shielded area.

[0042] As mentioned above, the shielding area is close to the edge of the second edge protection ring 602, and the electric field therein is reduced by the influence of the second edge protection ring 602, so that the etching ability is weakened. If the semiconductor substrate 701 is etched as usual to form a deep trench, it is easy to have a grass growth phenomenon at the bottom of the deep trench. In the embodiment of the present invention, no deep trench is formed in the shielding area, thereby avoiding the occurrence of the grass growth phenomenon.

[0043] In one embodiment, the difference between the inner diameters of the second edge protection ring 602 and the first edge protection ring 601 is greater than or equal to 1 mm, that is, the width of the shielding area is greater than or equal to 0.5 mm. This ensures that no deep trench isolation structure is formed within a width of at least 0.5 mm inside the second edge protection ring 602, thereby avoiding the occurrence of grass growth to the greatest extent.

[0044] For example, for a wafer with a diameter of about 300 mm, the inner diameter of the first edge protection ring is 297 mm, and the inner diameter of the second edge protection ring is 298 mm, with a diameter difference of 1 mm between the two. By completing the etching process of the hard mask layer 702 in the first etching reaction chamber equipped with a 297 mm first edge protection ring 601, the hard mask layer 702 in the area outside the wafer radius of 148.5 mm is not etched, and a large amount of residue remains; then the semiconductor substrate 701 is etched by the Bosch etching process in the second etching reaction chamber equipped with a 298 mm second edge protection ring 602. In the range of 148.5 mm to 149 mm of the wafer radius, the etching rate of this area is reduced due to the proximity to the second edge protection ring 602, and the remaining hard mask layer 702 cannot be removed, causing etching to stop. However, the etching rate within the range of 148.5 mm of the wafer radius is high, and the problem of incomplete etching will not occur, thereby avoiding the generation of grassy areas.

[0045] Specifically, the semiconductor substrate 701 can be etched by a Bosch etching process to form a deep groove. The Bosch etching process is to perform an etching step, a deposition step, and a cleaning step in a cycle. The etching step includes: etching the semiconductor substrate 701 to form a groove. Among them, the semiconductor substrate 701 can be isotropically etched by generating fluorine radicals in a second etching reaction chamber. The deposition step includes: depositing a passivation layer at the bottom and sidewall of the groove, and the passivation layer includes but is not limited to a uniformly deposited polymer layer. The cleaning step is to remove the passivation layer at the bottom of the groove to expose the semiconductor substrate 701 at the bottom of the groove, so that etching can continue downward in the next cycle, and the passivation layer retained on the sidewall of the groove can avoid the generation of lateral etching. As the cycle proceeds, the aspect ratio of the groove gradually increases, and finally a deep groove with a high aspect ratio is formed in the semiconductor substrate 701.

[0046] Exemplarily, the etching depth obtained in each cycle of the Bosch etching process is between several hundred nanometers and several micrometers, and the number of cycles can be determined according to the target depth of the deep trench isolation structure and the etching depth of each cycle of each Bosch etching process. The number of cycles is usually more than 50 times, and in one example, 400 cycles can be performed to complete the etching of the deep trench.

[0047] In the process of etching the semiconductor substrate 701 by performing the Bosch etching process, the execution time of the etching step, the deposition step and the cleaning step can be adjusted in real time to adjust the morphology of the deep groove, so that the depth of the deep groove increases but still maintains a good vertical morphology. Specifically, the execution time of the deposition step can be gradually increased during the etching process to increase the thickness of the passivation layer formed on the sidewall of the groove to prevent the groove from lateral expansion. At the same time, the execution time of the cleaning step can also be increased to ensure the complete removal of the passivation layer at the bottom of the groove.

[0048] In addition, during the process of etching the semiconductor substrate 701, the bias voltage applied to the wafer 600 and / or the gas pressure of the etching reaction gas can be adjusted in real time to control the movement direction of the plasma, realize the control of the etching directionality, and further ensure the vertical morphology of the deep trench. For example, the bias voltage can be gradually increased during the etching process to improve the directionality of the plasma movement.

[0049] Exemplarily, the process parameters of the above etching step include: reaction chamber gas pressure 20mT-80mT; upper RF power 1000W-3000W; lower RF power 0-200W; lower RF pulse frequency 200Hz-1000Hz; lower RF pulse duty cycle 20%~70%, and the etching reaction gas includes SF6, etc.

[0050] The process parameters of the deposition step include: reaction chamber gas pressure 20mT-80mT; upper RF power 1000W-3000W; lower RF power 0-200W; lower RF pulse frequency 200Hz-1000Hz; lower RF pulse duty cycle 20%~70%, and etching reaction gases include C4F8, etc.

[0051] The process parameters of the cleaning step include: reaction chamber pressure 20mT-80mT; upper RF power 1000W-3000W; lower RF power 0-200W; lower RF pulse frequency 20Hz-1000Hz; lower RF pulse duty cycle 20%~70%, and etching reaction gas includes SF6, etc.

[0052] After etching is completed, the deep trench can also be cleaned to remove the residues in the etching process, and the deep trench after cleaning is filled with an isolation material to form a deep trench isolation structure. In some embodiments, the isolation material can be deposited by a chemical vapor deposition process, and the isolation material can include insulating materials such as tetraethoxysilane and silicon oxide.

[0053] like Figure 8 As shown, according to the above method, the formation of a deep trench isolation structure in the edge area of ​​the wafer can be avoided, thereby avoiding the problem of grass growing at the bottom of the deep trench isolation structure at the edge of the wafer. Fig. 9 As shown, the deep trench formed according to the above method has a good vertical morphology.

[0054] At this point, the process steps implemented in the method for manufacturing a semiconductor device according to the first aspect of the present invention have been completed. It can be understood that the method for manufacturing a semiconductor device in this embodiment not only includes the above steps, but may also include other necessary steps before, during or after the above steps, which are all included in the scope of the manufacturing method of this embodiment.

[0055] According to the manufacturing method of the semiconductor device provided by the embodiment of the present invention, a first edge protection ring with a smaller inner diameter is used in the process of etching the hard mask layer, so that a larger amount of the hard mask layer is left shielded by the first edge protection ring; a second edge protection ring with a larger inner diameter is used in the process of etching the semiconductor substrate, and the hard mask layer retained near the second edge protection ring blocks the etching of the semiconductor substrate below, thereby avoiding the low etching rate near the second edge protection ring causing grass to grow at the bottom of the deep trench, thereby improving the yield of the semiconductor device.

[0056] An embodiment of the present invention further provides a semiconductor device, which can be manufactured by the method in the aforementioned embodiment, but is not limited thereto.

[0057] The semiconductor device of the present invention is introduced and described in detail below. It is worth mentioning that in order to avoid repetition, only a brief description is given for the same components and structures as in the aforementioned embodiments. For specific explanations and descriptions, reference can be made to the description in Embodiment 1.

[0058] Specifically, the semiconductor device of the embodiment of the present invention includes a wafer, the wafer includes a semiconductor substrate, and a deep trench is formed in the semiconductor substrate. The wafer includes a first peripheral region located at the edge, a second peripheral region located inside the first peripheral region, and a central region located inside the second peripheral region, and the deep trench is located in the central region. Exemplarily, a hard mask layer is formed on the semiconductor substrate of the first peripheral region and the second peripheral region, and the thickness of the hard mask layer in the second peripheral region is less than the thickness of the hard mask layer in the first peripheral region.

[0059] Since the semiconductor device of the embodiment of the present invention is manufactured by adopting the above method, the problem of grass growing at the bottom of the deep trench at the edge of the wafer is avoided, thereby improving the yield of the semiconductor device.

[0060] The third aspect of the present invention further provides an electronic device in an embodiment, comprising the aforementioned semiconductor device, wherein the semiconductor device is manufactured according to the aforementioned method.

[0061] The electronic device of this embodiment can be any electronic product or device such as a mobile phone, a tablet computer, a laptop computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a voice recorder, an MP3, an MP4, a PSP, etc., or any intermediate product including a circuit. The electronic device of the embodiment of the present invention has better performance because the above-mentioned semiconductor device is used.

[0062] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: Providing a wafer, the wafer comprising a semiconductor substrate and a hard mask layer formed on the semiconductor substrate; Disposing a first edge protection ring at the edge of the wafer, and etching the hard mask layer inside the first edge protection ring to form an opening defining a deep trench isolation structure in the hard mask layer, wherein the inner diameter of the first edge protection ring is smaller than the diameter of the wafer; A second edge protection ring is disposed at the edge of the wafer, and the semiconductor substrate below the opening inside the second edge protection ring is etched to form a deep groove in the semiconductor substrate, wherein the inner diameter of the second edge protection ring is greater than the inner diameter of the first edge protection ring.

2. The manufacturing method according to claim 1, characterized in that A difference between an inner diameter of the second edge protection ring and an inner diameter of the first edge protection ring is greater than or equal to 1 mm.

3. The manufacturing method according to claim 1 or 2, characterized in that: The inner diameter of the first edge protection ring is 297 mm, and the inner diameter of the second edge protection ring is 298 mm.

4. The manufacturing method according to claim 1, characterized in that: The step of providing a first edge protection ring at the edge of the wafer comprises: Placing the wafer in a first etching reaction chamber provided with the first edge protection ring; The step of providing a second edge protection ring at the edge of the wafer comprises: The wafer is placed in a second etching reaction chamber equipped with the second edge protection ring.

5. The manufacturing method according to claim 4, characterized in that: The first etching reaction chamber or the second etching reaction chamber comprises an upper radio frequency system and a lower radio frequency system, wherein the upper radio frequency system is used to dissociate the etching reaction gas to form plasma. The lower radio frequency system is used to apply a bias voltage to the wafer to pull the plasma to move toward the wafer.

6. The manufacturing method according to claim 5, characterized in that: The method further comprises: During the process of etching the semiconductor substrate, the bias voltage and / or the gas pressure of the etching reaction gas is adjusted in real time to control the moving direction of the plasma.

7. The manufacturing method according to claim 1, characterized in that: The etching of the semiconductor substrate below the opening inside the second edge protection ring to form a deep trench in the semiconductor substrate comprises cyclically performing the following steps: Etching step: etching the semiconductor substrate to form a groove; Deposition step: depositing a passivation layer on the bottom and sidewalls of the trench; Removing step: removing the passivation layer at the bottom of the trench to expose the semiconductor substrate at the bottom of the trench.

8. The manufacturing method according to claim 7, characterized in that: The method further comprises: In the process of etching the semiconductor substrate, the execution time of the etching step, the deposition step and the cleaning step is adjusted in real time to adjust the morphology of the deep trench.

9. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic apparatus includes the semiconductor device according to claim 9.

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