Electronic circuit and apparatus

Abstract

The invention relates to an electronic circuit and a device. The present specification relates to an electronic circuit having an impedance matching circuit, including: a first inductor coupling a first node to a second node; and a second inductor coupling the second node to a third node, the third node being coupled to a ground level; the first and second inductors are configured to form a positive magnetic coupling between each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to French patent application No. 2311360, entitled “Circuitélectronique”, filed on October 20, 2023, which is incorporated herein by reference to the maximum extent permitted by law. Technical Field

[0003] The disclosure relates generally to electronic circuits and devices including such electronic circuits, particularly radio frequency communication devices. Background Art

[0004] Many electronic circuits and devices, especially radio frequency communication devices, require an impedance matching circuit between a bias circuit coupled to a matching circuit and an antenna. In some cases, such as in a test circuit, the bias circuit is coupled to the antenna. Therefore, the impedance matching circuit must be modified to limit signal loss and cost. Summary of the invention

[0005] It is desirable to provide a broadband impedance matching circuit that limits signal losses and costs.

[0006] One embodiment overcomes all or part of the disadvantages of known electronic circuits.

[0007] One embodiment provides an electronic circuit having an impedance matching circuit, comprising:

[0008] a first inductor coupling the first node to the second node; and

[0009] a second inductor coupling the second node to a third node, the third node coupled to a ground level;

[0010] The first and second inductors are configured to form a positive magnetic coupling between each other.

[0011] According to an embodiment, the third node is coupled to the ground level via a capacitive element.

[0012] According to an embodiment, the first and second inductors are formed by planar conductive windings.

[0013] According to an embodiment, the second node is intended to be biased by a test device.

[0014] According to an embodiment, the third node is intended to be biased by a power supply of the electronic circuit.

[0015] According to an embodiment, the first node is intended to be coupled to an amplifier.

[0016] According to an embodiment, the magnetic coupling is greater than 0.5.

[0017] According to an embodiment, the first inductor and the second inductor are configured such that current can flow in the same direction.

[0018] According to an embodiment, the first inductor and the second inductor are stacked.

[0019] According to an embodiment, the number of windings of the second inductor is greater than the number of windings of the first inductor.

[0020] According to an embodiment, one or more first conductive tracks insulated from the second inductor completely or partially surround an outer region of the winding of the second inductor.

[0021] According to an embodiment, one or more second conductive tracks insulated from the second inductor are arranged between a central portion of the second inductor not covered by the winding and an inner region of the winding of the second inductor.

[0022] According to an embodiment, one or more third conductive tracks insulated from the first inductor completely or partially surround an outer region of the winding of the first inductor.

[0023] According to an embodiment, one or more fourth conductive tracks insulated from the first inductor are arranged between a central portion of the winding of the first inductor not covered by the winding and an inner region of the winding of the first inductor.

[0024] According to an embodiment, the value of the capacitive element is configured to limit the occurrence of current loops.

[0025] According to an embodiment, the impedance matching circuit comprises a further capacitive element coupling the first and second nodes.

[0026] According to one embodiment, the electromagnetic field generated by the first inductor and the electromagnetic field generated by the second inductor are superimposed in the same direction.

[0027] An embodiment provides an electronic device, including:

[0028] - an electronic circuit as described above; and

[0029] an amplifier coupled to the first node.

[0030] In one embodiment, the apparatus further comprises a testing device configured to bias the second node.

[0031] In one embodiment, the test equipment is configured to bias the second node with a bias tee.

[0032] In one embodiment, the apparatus further comprises an antenna coupled to the biaser.

[0033] In one embodiment, the amplifier comprises a bipolar transistor and the first node is coupled to a collector of the transistor.

[0034] An embodiment provides a 5G radio frequency communication system, which includes the electronic device as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0036] Figure 1 An example of an electronic device is shown very schematically;

[0037] Figure 2 An electronic device according to an embodiment is shown very schematically;

[0038] Figure 3 It shows that according to the embodiment Figure 2 electronic devices;

[0039] Figure 4 It shows that according to the embodiment Figure 3 A top view of a portion of an electronic device;

[0040] Figure 5 It shows that according to the embodiment Figure 3 A top view of another portion of the electronic device;

[0041] Figure 6 Shows Figure 4 and Figure 5 A combined cross-sectional view of an embodiment of the present invention;

[0042] Figure 7 Shows Figure 3 simulation of the operation of the equipment; and

[0043] Figure 8 Shows Figure 3 An alternative embodiment of a circuit. DETAILED DESCRIPTION

[0044] In the various drawings, the same features are represented by the same reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may be provided with the same structure, dimensions and material properties.

[0045] For clarity, only those steps and elements that are useful for understanding the embodiments are shown and described in detail.

[0046] Unless otherwise stated, when referring to two elements being connected together, this means a direct connection without any intermediate elements other than conductors, and when referring to two elements being connected together, this means that the two elements may be connected or they may be coupled via one or more other elements. When two elements are magnetically coupled without contact, there will be a specific "magnetic coupling".

[0047] In the following description, when reference is made to terms defining absolute positions (such as terms “front”, “back”, “top”, “bottom”, “left”, “right”, etc.) or relative positions (such as terms “up”, “down”, “upper”, “lower”, etc.) or terms defining directions (such as terms “horizontal”, “vertical”, etc.), reference is made to the direction of the drawing unless otherwise specified.

[0048] Unless otherwise stated, the expressions "about", "approximately", "substantially" and "in the order of" mean plus or minus 10%, preferably plus or minus 5%.

[0049] Figure 1 Very schematically, an example of an electronic device 100 is shown. The device 100 is, for example, a device for use in a system for processing radio frequencies.

[0050] The electronic device 100 comprises an amplification module 110 (amplifier), which comprises, for example, a CMOS or bipolar transistor. In the example shown, a bias block 120 (bias) couples the amplification block 110 at node N1 to an impedance matching circuit 130 (impedance matching) at node N2. The impedance matching circuit 130 is itself coupled, preferably connected to a load 140 (load). The load 140 is, for example, a circuit comprising an antenna. In the case where the amplification module 110 comprises a bipolar transistor, the bias module 120 is, for example, coupled to, preferably connected to the collector of the transistor. The bias block 120 is, for example, formed by a biaser comprising an inductor coupling the power rail to the node N1 and a capacitive element coupling the node N1 to the node N2.

[0051] Bias tees are used, for example, to power a device with voltage or current while enabling high-speed and ultra-wideband signals to flow with minimal degradation of the signal.

[0052] The impedance matching circuit 130 has the function of matching the output impedance of the amplification module 110, which is, for example, 17 ohms, with a capacitance of 1 to 3 μF at the impedance of the load (for example, 50 ohms) without degrading the signal level.

[0053] Figure 2 An electronic device 200 according to an embodiment is shown very schematically.

[0054] Device 200 is similar to device 100, except that impedance matching circuit 230 is coupled to (preferably connected to) amplification module 110 at node N3 and coupled to biasing module 120 at node N4. Here biasing block 120 couples load 140 to node N4 to allow biasing of second node N4.

[0055] For example, the structure of the device 200 is obtained when the bias block 120 and possible load 140 are arranged on a circuit having a different substrate than the impedance matching circuit 230 and / or the amplification block 110. In one example, the bias block 120 and possible load 140 are arranged on a test circuit. In another example, the impedance matching circuit 130 and / or the amplification block 110 are formed in a semiconductor substrate, such as a silicon substrate.

[0056] and Figure 1 Compared to the example of FIG. 2 , the device 200 requires a new architecture for redefining the impedance matching circuit 230, which has neither a series capacitive element nor a shunt inductor, while limiting the surface area used. The constraints in terms of performance remain the same, such as matching the output impedance of the amplification module 110, which is, for example, 17 ohms, with a capacitance from 1 to 3 μF under a load impedance of, for example, 50 ohms, over a bandwidth of, for example, greater than 1 GHz, without degrading the signal and the signal.

[0057] The described embodiments provide an impedance matching circuit, comprising:

[0058] a first inductor coupling the first node to the second node; and

[0059] a second inductor coupling the second node to a third node, the third node coupled to a ground level;

[0060] The first and second inductors are configured to form a positive magnetic coupling between each other.

[0061] In other words, the first and second inductors are configured so that the electromagnetic field generated by the first inductor and the electromagnetic field generated by the second inductor are superimposed in the same direction. This generates positive magnetic coupling between the two inductors.

[0062] The described embodiments can avoid the use of series capacitive elements and shunt inductors while limiting the space used. The broadband transformed impedance is relatively flat and has low losses over a multi-GHz frequency band.

[0063] Figure 3 It shows that according to the embodiment Figure 2 An electronic device 200.

[0064] More precisely, Figure 3Examples of embodiments of the impedance matching circuit 230 and the bias block 120 are described in detail.

[0065] In the example shown, the bias block 120 is formed, for example, by a biaser including an inductor 360 coupling the power rail VBAT to the node N4 and a capacitive element 350 coupling the node N4 to the load 140 .

[0066] The impedance matching circuit 230 includes a first inductor 330 coupling the node N3 to the node N4, and a second inductor 340 coupling the node N4 to the node N5. The first and second inductors 330, 340 are thus connected at the node N4.

[0067] In the example shown, a capacitive element 320 may be incorporated by coupling node N5 to ground in the case where the bias (of bias block 120) is external to circuit 230. Capacitive element 320 is, for example, selected to limit the occurrence of current loops and has a value of, for example, tens of picofarads.

[0068] In an example, the impedance matching circuit further comprises an optional capacitive element 310 coupling nodes N3 and N4. Capacitive element 310 enables a flatter response across the entire bandwidth, for example between 1 and 5 GHz. Capacitive element 310 has a value of, for example, about 1 μF.

[0069] In the example shown, the first and second inductors 330, 340 are configured to form a positive magnetic coupling between each other. To this end, the currents i1 and i2 flowing through the two inductors 330, 340, respectively, flow in the same direction (i.e., toward the node N4). Therefore, if the electromagnetic fields generated by the first inductor and the second inductor are emitted at the same location, they can be added.

[0070] Positive coupling is preferred over negative coupling because this limits the bandwidth and losses in the matching network.

[0071] A positive coupling as close to 1 as possible can limit losses and gain efficiency while limiting the size of the inductor relative to the circuit. To this end, the first and second inductors 330, 340 can advantageously be stacked on top of each other, e.g. with a maximum overlap between the windings of the first inductor 330 and the windings of the second inductor 340. This can further limit the encroachment of the inductor in the circuit.

[0072] Figure 4 It shows that according to the embodiment Figure 3 More specifically, Figure 4 The magnetic coupling line of the inductor 330 is shown, which forms the main part of the magnetic coupling.

[0073] Figure 5 It shows that according to the embodiment Figure 3 More specifically, Figure 5 The magnetically coupled lines of the inductor 340 are shown, which form the secondary part of the magnetic coupling.

[0074] More specifically, Figure 4 and Figure 5 The first and second inductors 330, 340 are shown in top view, respectively. For clarity, the inductors 330 and 340 are shown separately, but it is advantageous to stack them with maximum overlap.

[0075] In the example shown, the first inductor 330 includes two windings 430 and the second inductor 340 includes four windings 530. The length of the windings defines the value of the inductance. In one example, the winding 430 has a width of about 30 μm and the winding has a width of about 10 μm. The width difference between the windings 430 and 530 enables the two windings to be stacked along most of their lengths, despite the large difference between their respective lengths. The innermost winding of the first inductor 330 is configured to have a track width that can be superimposed on the two innermost windings of the second inductor 340. The outermost winding of the first inductor 330 is configured to have a track width that can be superimposed on the two outermost windings of the second inductor 340.

[0076] exist Figure 5 In the example shown, one or more conductive tracks 510 insulated from the second inductor 340 completely or partially surround an outer region of the winding of the second inductor 340 .

[0077] exist Figure 5 In another example shown, one or more conductive tracks 520 insulated from the second inductor 340 are arranged between a central portion 540 of the second inductor 340 not covered by the winding and an inner region 542 of the inner winding of the second inductor.

[0078] In an example not shown, one or more conductive tracks insulated from the first inductor 330 completely or partially surround an outer region of the winding of the first inductor 330 .

[0079] In another example not shown, one or more conductive tracks insulated from the first inductor are arranged between a central portion 440 of the winding of the first inductor 330 not covered by the winding and an inner region of the winding of the first inductor.

[0080] Tracks 510 and 520 are coupled to the first inductor 330 , for example, through vias.

[0081] In another example, the tracks 510 and 520 are coupled to tracks surrounding the winding of the first inductor through vias.

[0082] Tracks 510 and 520 can increase the positive magnetic coupling between inductors 330 and 340 .

[0083] In one example, the first and second inductors 330 , 340 are coupled, for example, via a via.

[0084] Figure 6 Shows Figure 4 and Figure 5 . More specifically, the cross section AA is formed on the stack of the first and second inductors 330, 340. The cross section AA cuts through one of the tracks 510 and one of the tracks 520, as well as the three windings 530 of the second inductor located between these tracks 510 and 520. The cross section AA also shows the winding 430 of the first inductor 330, which is superimposed on the winding of the inductor 340 shown in the cross section.

[0085] In the example shown, the winding 530 and the tracks 510, 520 of the second inductor 340 are formed by metal deposition, for example, performed on a semiconductor substrate. The winding 530 and the tracks 510, 520 of the second inductor 340 are coupled, for example, via an insulator 620. The winding 430 of the first inductor 330 is formed, for example, by metal deposition performed inside and / or on top of the insulator 620.

[0086] In the example shown, the tracks 510 and 520 are coupled to the first inductor 330, for example, by vias 630 formed through the insulator 620. The positive magnetic coupling between the first and second inductors 330, 340 is thus enhanced.

[0087] By superimposing the first and second inductors 330 and 340 , and by having currents of the same direction in both inductors 330 , 340 , a positive magnetic coupling greater than 0.5 or even about 0.9 can be obtained by using the tracks 510 , 520 .

[0088] Figure 7 Shows Figure 3 Simulation of the operation of the device.

[0089] More specifically, Figure 7 is a graph showing the impedance (impedance) in Henry at the node N3 as a function of frequency between 2.3 GHz and 5 GHz, with (curve 720) and without (curve 710) the optional capacitive element 310. Figure 7 and Figure 8 In the example of FIG. 1 , the capacitor 310 is in the order of 1 pF, and the inductors 330, 340 are similar to Figure 4 and Figure 5 The inductor, once stacked, has a footprint of 330μm x 230μm in top view.

[0090] With the capacitive element 310 , the impedance is slightly reduced at high frequencies, which makes the response at the output of the amplifier block flatter than without the capacitive element 310 .

[0091] Figure 8 yes Figure 3 Alternative embodiments of the circuit. Figure 8 The circuit 300 is similar to Figure 3 circuit, except that the bias voltage VBAT is generated by a power supply inside the circuit 230, rather than provided by the block 120, and is applied to the node N5. Figure 3 In comparison, Figure 8 In the example of FIG. 1 , the inductor 360 is not implemented because the bias is generated internally. For example, the power supply generated voltage VBAT is referenced to ground. In another example, the capacitive element 320 may not exist or be small in size. Figure 3 Compared to the example, Figure 8 The example allows for reduced cost and size because the inductor 360 is not used.

[0092] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that those skilled in the art will recognize other variations. In particular, the number of windings of the first and second inductors 330, 340 and their widths may be modified to optimize positive magnetic coupling or accommodate circuit constraints.

[0093] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art. In particular, regarding the overlap of the first and second inductors, a person skilled in the art can adjust it to maximize the positive magnetic coupling between the two inductors 330 and 340.

[0094] The disclosed embodiments may, for example, be integrated into a 5G radio frequency communication system including the electronic device 200 .

Claims

1. An electronic circuit comprising: Impedance matching circuit, comprising: A first inductor coupled between the first node and the second node; and a second inductor coupled between the second node and a third node, wherein the third node is coupled to a ground level; The first inductor and the second inductor are configured to have positive magnetic coupling between each other.

2. The circuit according to claim 1, wherein the third node is coupled to a ground level via a capacitive element.

3. The circuit of claim 1, wherein the first inductor and the second inductor are formed by planar conductive windings. The circuit of claim 1 , wherein the second node is configured to be biased by a test device. 5 . The circuit of claim 1 , wherein the third node is configured to be biased by a power supply of the electronic circuit. The circuit of claim 1 , wherein the first node is configured to be coupled to an amplifier. The circuit of claim 1 , wherein the magnetic coupling is greater than 0.

5. 8 . The circuit of claim 1 , wherein the first inductor and the second inductor are configured such that current can flow through the first inductor and the second inductor in the same direction.

9. The circuit of claim 1, wherein the first inductor and the second inductor are stacked.

10. The circuit of claim 3, wherein the number of windings of the second inductor is greater than the number of windings of the first inductor.

11. The circuit of claim 3, wherein one or more first conductive tracks insulated from the second inductor completely or partially surround an outer region of the winding of the second inductor.

12. The circuit of claim 3, wherein one or more second conductive tracks insulated from the second inductor are arranged between a central portion of the second inductor not covered by the winding and an inner region of the winding of the second inductor.

13. The circuit of claim 3, wherein one or more third conductive tracks insulated from the first inductor completely or partially surround an outer region of the winding of the first inductor.

14. The circuit of claim 3, wherein one or more fourth conductive tracks insulated from the first inductor are arranged between a central portion of the winding of the first inductor not covered by the winding and an inner region of the winding of the first inductor.

15. The circuit of claim 2, wherein the value of the capacitive element is configured to limit the occurrence of a current loop.

16. The circuit of claim 1, wherein the impedance matching circuit comprises another capacitive element coupling the first node and the second node.

17. The circuit of claim 1, wherein the electromagnetic field generated by the first inductor and the electromagnetic field generated by the second inductor are superimposed in the same direction.

18. An electronic device, comprising: An electronic circuit having an impedance matching circuit, comprising: A first inductor coupled between the first node and the second node; and a second inductor coupled between the second node and a third node, wherein the third node is coupled to a ground level; wherein the first inductor and the second inductor are configured to have a positive magnetic coupling between each other; and An amplifier is coupled to the first node.

19. The apparatus of claim 18, further comprising a test device configured to bias the second node.

20. The apparatus of claim 19, wherein the test apparatus is configured to bias the second node using a biaser.

21. The apparatus of claim 20, further comprising an antenna coupled to the biaser.

22. The apparatus of claim 18, wherein the amplifier comprises a bipolar transistor, and wherein the first node is coupled to a collector of the transistor.

23. A 5G radio frequency communication system, comprising: An electronic circuit having an impedance matching circuit, comprising: A first inductor coupled between the first node and the second node; and a second inductor coupled between the second node and a third node, wherein the third node is coupled to a ground level; wherein the first inductor and the second inductor are configured to have a positive magnetic coupling between each other; an amplifier coupled to the first node; a test device configured to bias the second node using a bias device; and An antenna is coupled to the bias tee.

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