Time amplifier, sensor, chip, electronic device and time control method

Abstract

The invention relates to a time amplifier, a sensor, a chip, electronic equipment and a time control method, and the time amplifier comprises a digital control module which is used for dividing a plurality of input time pulse signals into a first time pulse signal group and a second time pulse signal group; the signal processing module is used for performing charging processing or discharging processing according to the first time pulse signal group to obtain a first voltage, and performing charging processing or discharging processing according to the second time pulse signal group to obtain a second voltage; and the comparison module is used for comparing the first voltage and the second voltage with a preset voltage, and determining and outputting a time pulse width signal according to a comparison result. The time amplifier disclosed by the invention can realize differential operation on a plurality of time pulse signals.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic technology, and in particular to a time amplifier, a sensor, a chip, an electronic device and a time control method. Background Art

[0002] When processing the short pulse width input signal T_IN, if a time-to-digital converter is used directly, the accuracy may be limited because the pulse width of the short pulse width input signal T_IN is too short. To solve this problem, a time amplifier is usually added before the time-to-digital converter.

[0003] The time amplifier can extend the pulse width of the short pulse width input signal T_IN, thereby improving the measurement accuracy of the time-to-digital converter and ensuring accurate capture and conversion of the short pulse width input signal T_IN. Although the existing time amplifier can improve the measurement accuracy of the time-to-digital converter, its operation mode is relatively single. Summary of the invention

[0004] The present disclosure provides a time amplifier, a sensor, a chip, an electronic device and a time control method. The time amplifier of the embodiment of the present disclosure divides the input multiple time pulse signals into two parts of time pulse signals through a digital control module, performs charging or discharging processing according to the two parts of time pulse signals through a signal processing module to obtain corresponding voltages, and determines and outputs a time pulse width signal according to the two voltages after charging or discharging processing through a comparison module, so that the time amplifier can realize differential operation of multiple time pulse signals. The technical solution of the present disclosure is as follows:

[0005] The first aspect of the present disclosure provides a time amplifier, comprising:

[0006] A digital control module, used for dividing the input multiple time pulse signals into a first time pulse signal group and a second time pulse signal group;

[0007] a signal processing module, configured to perform charging or discharging according to the first time pulse signal group to obtain a first voltage, and to perform charging or discharging according to the second time pulse signal group to obtain a second voltage;

[0008] The comparison module is used to compare the corresponding first voltage and second voltage with a preset voltage respectively, and determine and output a time pulse width signal according to the comparison result.

[0009] A second aspect of the present disclosure provides a sensor, including: a time amplifier as described above.

[0010] A third aspect of the present disclosure provides a chip, including: a time amplifier as described above.

[0011] A fourth aspect of the present disclosure provides an electronic device, including: a time amplifier as described above.

[0012] A fifth aspect of the present disclosure provides a time control method, which is characterized by comprising:

[0013] Dividing the input multiple time pulse signals into a first time pulse signal group and a second time pulse signal group;

[0014] Performing charging or discharging according to the first time pulse signal group to obtain a first voltage, and performing charging or discharging according to the second time pulse signal group to obtain a second voltage;

[0015] The first voltage and the second voltage are respectively compared with a preset voltage, and a time pulse width signal is determined and output according to the comparison result.

[0016] The sixth aspect embodiment of the present disclosure proposes a non-temporary computer-readable storage medium on which computer program instructions are stored, and the computer program instructions implement the steps of the above method when executed by a processor.

[0017] A seventh aspect of the present disclosure provides a computer program product, including a computer program, which implements the steps of the above method when executed by a processor.

[0018] The technical solution provided by the embodiments of the present disclosure brings at least the following beneficial effects:

[0019] The time amplifier of the embodiment of the present disclosure is composed of a digital control module, a signal processing module and a comparison module, wherein the digital control module is used to divide the input multiple time pulse signals into a first time pulse signal group and a second time pulse signal group, the signal processing module is used to perform charging or discharging processing according to the first time pulse signal group to obtain a first voltage, and to perform charging or discharging processing according to the second time pulse signal group to obtain a second voltage, and the comparison module is used to compare the corresponding first voltage and the second voltage with the preset voltage respectively, and determine and output the time pulse width signal according to the comparison result. Therefore, the time amplifier of the present disclosure can realize differential operation of multiple time pulse signals.

[0020] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description are used to explain the principles of the present disclosure, and do not constitute improper limitations on the present disclosure.

[0022] Figure 1 is a schematic diagram of a time-to-digital conversion system in the related art;

[0023] Figure 2 is a circuit diagram of an amplifier in the related art;

[0024] Figure 3 It is a working timing diagram of a time amplifier in the related art;

[0025] Figure 4 is a block diagram of a time amplifier according to an embodiment of the present disclosure;

[0026] Figure 5 is a working flow chart of a current charging type time amplifier according to an embodiment of the present disclosure;

[0027] Figure 6 is a circuit diagram of a current charging type time amplifier according to an embodiment of the present disclosure;

[0028] Figure 7 is a working timing diagram of a current charging type time amplifier according to an embodiment of the present disclosure;

[0029] Figure 8 is a working timing diagram of a current charging type time amplifier according to another embodiment of the present disclosure;

[0030] Fig. 9 is a working flow chart of a current discharge type time amplifier according to an embodiment of the present disclosure;

[0031] Fig.10 is a circuit diagram of a current discharge type time amplifier according to an embodiment of the present disclosure;

[0032] Fig.11 is a working timing diagram of a current discharge type time amplifier according to an embodiment of the present disclosure;

[0033] Fig.12 is a working timing diagram of a current discharge type time amplifier according to another embodiment of the present disclosure;

[0034] Fig.13 is a flow chart of a time control method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] In order to enable ordinary persons in the art to better understand the technical solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings.

[0036] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0037] The time amplifier, sensor, chip, electronic device and time control method of the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0038] Before introducing the time amplifier of the embodiment of the present disclosure, Figure 1-Figure 3 The following is an introduction to the time amplifier in the related technology.

[0039] When processing short pulse width input signal T_IN, directly using time-to-digital converter may encounter accuracy limitations. To solve this problem, a time amplifier is usually added before the time-to-digital converter. Figure 1 The main function of the time amplifier is to amplify the short pulse width input signal T_IN to generate an output signal T_OUT with a longer pulse width, and send the output signal T_OUT to the time-to-digital converter, which converts the output signal T_OUT into a digital signal Digits for output.

[0040] like Figure 2 and Figure 3 As shown, first, the reset signal RST sets the voltage on the capacitor C1 and the capacitor C2 to zero. After the input signal t1 jumps high (jumping high is used to indicate that the level signal changes from a low level signal to a high level signal), the capacitor C1 and the capacitor C2 start to charge with the current I1. Since the capacity of the capacitor C2 is much larger than that of the capacitor C1, the voltage V_C1 on the positive plate of the capacitor C1 rises much faster than the voltage V_C2 on the positive plate of the capacitor C2. At this time, the output signal T_OUT of the comparator CMP is a high level signal. When the input signal t1 is pulled low again (pulling low is used to indicate that the level signal changes from a high level signal to a low level signal), the capacitor C1 stops charging, and the voltage V_C1 on the positive plate of the capacitor C1 is maintained at I1*t1 / C1. The capacitor C2 continues to charge with the current I1 until the voltage V_C2 on the positive plate exceeds the voltage I1*t1 / C1, pulling the output of the comparator CMP low, and the output signal T_OUT at this time is t1*C2 / C1. The time pulse width t1 of the input signal is amplified by C2 / C1 times.

[0041] The advantages of the time amplifier in the related art are simple structure and timing, but the disadvantages are: the operation mode is relatively simple, and it can only process the sum signal of the input time, and cannot process the signal that needs to be differentiated.

[0042] To this end, the present disclosure proposes a new time amplifier, which divides the input multiple time pulse signals into two parts of time pulse signals through a digital control module, performs charging or discharging processing on the two parts of the time pulse signals through a signal processing module to obtain corresponding voltages, and determines and outputs a time pulse width signal based on the two voltages after the charging or discharging processing through a comparison module, so that the time amplifier can realize differential operations on multiple time pulse signals.

[0043] Figure 4 is a block diagram of a time amplifier according to an embodiment of the present disclosure.

[0044] like Figure 4 As shown, the time amplifier 100 of the embodiment of the present disclosure includes: a digital control module 10 , a signal processing module 20 and a comparison module 30 .

[0045] The digital control module 10 is used to divide the input multiple time pulse signals IN_PULSE into a first time pulse signal group CHARGE1 and a second time pulse signal group CHARGE2. The signal processing module 20 is used to perform charging or discharging processing according to the first time pulse signal group CHARGE1 to obtain a first voltage V1, and to perform charging or discharging processing according to the second time pulse signal group CHARGE2 to obtain a second voltage V2. The comparison module 30 is used to compare the corresponding first voltage V1 and the second voltage V2 with the preset voltage V_th, respectively, and determine and output the time pulse width signal T_OUT according to the comparison result.

[0046] In this embodiment, the signal processing module 20 performs charging or discharging processing according to the first time pulse signal group CHARGE1 to obtain a first voltage V1, and performs charging or discharging processing according to the second time pulse signal group CHARGE2 to obtain a second voltage V2, which can be achieved in the following two ways.

[0047] First way:

[0048] The signal processing module 20 is used for performing a pre-charging process according to the first time pulse signal group CHARGE1 to obtain a first pre-charging voltage V_pre11 after receiving the first reset signal RST_CAP1, and performing a pre-charging process according to the second time pulse signal group CHARGE2 to obtain a second pre-charging voltage V_pre12;

[0049] The signal processing module 20 is also used to, after receiving the first interrupt trigger signal T_CHARGE1, continue the charging process based on the first pre-charge voltage V_pre11 to obtain the first voltage V1, and continue the charging process based on the second pre-charge voltage V_pre12 to obtain the second voltage V2; wherein the first interrupt trigger signal T_CHARGE1 is a signal generated and sent by the digital control module 10 when the signal processing module 20 completes the pre-charge operation.

[0050] Second way:

[0051] The signal processing module 20 is used for performing a pre-discharge process according to the first time pulse signal group CHARGE1 to obtain a first pre-discharge voltage V_pre21 after receiving the third reset signal RST_CAP3, and performing a pre-discharge process according to the second time pulse signal group CHARGE2 to obtain a second pre-discharge voltage V_pre22;

[0052] The signal processing module 20 is also used to, after receiving the second interrupt trigger signal T_CHARGE2, continue the discharge process based on the first pre-discharge voltage V_pre21 to obtain the first voltage V1, and continue the discharge process based on the second pre-discharge voltage V_pre22 to obtain the second voltage V2; wherein the second interrupt trigger signal T_CHARGE2 is a signal generated and sent by the digital control module 10 when the signal processing module 20 completes the pre-discharge operation.

[0053] The comparison module 30 compares the first voltage V1 with the preset voltage V_th, and compares the second voltage V2 with the preset voltage V_th, and determines and outputs the time pulse width signal T_OUT according to the two comparison results.

[0054] It can be seen that when the signal processing module in the time amplifier of the embodiment of the present disclosure performs a charging processing operation in the first manner, as a current charging type time amplifier, the working principle of the current charging type time amplifier is: the input multiple time pulse signals are divided into two parts of time pulse signals through the digital control module, and the signal processing module performs charging processing according to the two parts of time pulse signals to obtain corresponding voltages, and the comparison module determines and outputs the time pulse width signal according to the two voltages after the charging processing, so that the current charging type time amplifier can realize differential operations on multiple time pulse signals; when the signal processing module in the time amplifier of the embodiment of the present disclosure performs a discharge processing operation in the second manner, as a current discharge type time amplifier, the working principle of the current discharge type time amplifier is: the input multiple time pulse signals are divided into two parts of time pulse signals through the digital control module, and the signal processing module performs discharge processing according to the two parts of time pulse signals to obtain corresponding voltages, and the comparison module determines and outputs the time pulse width signal according to the two voltages after the discharge processing, so that the current discharge type time amplifier can realize differential operations on multiple time pulse signals.

[0055] Combine the following Figure 5-Figure 8 Now, the current charging type time amplifier according to the embodiment of the present disclosure will be introduced.

[0056] like Figure 5 As shown, the input time pulse signal IN_PULSE is described by taking two time pulse signals as an example. It should be noted that the embodiment of the present disclosure can process two or more time pulse signals and perform time amplification. Exemplarily, if the input time pulse signal IN_PULSE includes a first time pulse signal t1 and a second time pulse signal t2, then the first time pulse signal group CHARGE1 includes the first time pulse signal t1, and the second time pulse signal group CHARGE2 includes the second time pulse signal t2. The input time pulse signal IN_PULSE is divided into two parts through the digital control module 10, wherein the first time pulse signal t1 enters the signal processing module 20 for pre-charging and generates a first pre-charging voltage V_pre11, and the second time pulse signal t2 enters the signal processing module 20 for pre-charging and generates a second pre-charging voltage V_pre12. After the two ends of the two capacitors in the signal processing module 20 are pre-charged, the two capacitors in the signal processing module 20 are charged simultaneously, and the first voltage V1 and the second voltage V2 generated by the charging are sent to the comparison module 30 for comparison, and an output time pulse width signal T_OUT is generated.

[0057] like Figure 6As shown, the signal processing module 20 includes: a first current source IS1, a current mirror circuit composed of a first transistor M1 to a fifth transistor M5, a first switch S1 to a tenth switch S10, a first energy storage element 21, and a second energy storage element 22; wherein,

[0058] The first end of the first transistor M1 to the first end of the fifth transistor M5 are respectively connected to the first power supply terminal VCC1, and the second end of the first transistor M1 is respectively connected to the control end of the first transistor M1 to the control end of the fifth transistor M5 and then connected to the ground terminal through the first current source IS1;

[0059] The second end of the second transistor M2 is connected to the ground terminal through the first switch S1, and is also connected to the ground terminal through the second switch S2 and the first energy storage element 21 in sequence;

[0060] The second end of the third transistor M3 is connected to the ground terminal through the third switch S3 and the first energy storage element 21 in sequence, and is also connected to the ground terminal through the fourth switch S4;

[0061] The second end of the fourth transistor M4 is connected to the ground terminal through the fifth switch S5, and is also connected to the ground terminal through the sixth switch S6 and the second energy storage element 22 in sequence;

[0062] The second end of the fifth transistor M5 is connected to the ground terminal through the seventh switch S7 and the second energy storage element 22 in sequence, and is also connected to the ground terminal through the eighth switch S8;

[0063] The first energy storage element 21 is connected in parallel with the ninth switch S9, and the first node where the first energy storage element 21 is respectively connected with the second switch S2, the third switch S3 and the ninth switch S9 serves as the first charging voltage output terminal VINN1;

[0064] The second energy storage element 22 is connected in parallel with the tenth switch S10 , and a second node where the second energy storage element 22 is respectively connected to the sixth switch S6 , the seventh switch S7 and the tenth switch S10 serves as a second charging voltage output terminal VINP1 .

[0065] In this embodiment, the first energy storage element 21 is a first capacitor C1 , and the second energy storage element 22 is a second capacitor C2 ; wherein the capacity of the first energy storage element 21 is equal to the capacity of the second energy storage element 22 .

[0066] like Figure 6 As shown, the comparison module 30 includes: a first inverter INV1, a second inverter INV2, a first buffer BUF1, a second buffer BUF2, a first trigger DFF1, a second trigger DFF2 and a first XOR gate circuit XOR1; wherein,

[0067] The output end of the first inverter INV1 is connected to the input end of the first buffer BUF1, and the output end of the second inverter INV2 is connected to the input end of the second buffer BUF2;

[0068] The digital control module 10 is further used to send a first frequency control signal F_CHOP1 to control the input end of the first inverter INV1 to be connected to one of the first charging voltage output terminal VINN1 or the second charging voltage output terminal VINP1, the input end of the second inverter INV2 to be connected to the other of the first charging voltage output terminal VINN1 or the second charging voltage output terminal VINP1, and the output end of the first buffer BUF1 to be connected to one of the clock input terminal Clkn of the first trigger DFF1 or the clock input terminal Clkn of the second trigger DFF2, and the output end of the second buffer BUF2 to be connected to the other of the clock input terminal Clkn of the first trigger DFF1 or the clock input terminal Clkn of the second trigger DFF2;

[0069] The first input terminal of the first XOR gate circuit XOR1 is connected to the input terminal D of the first flip-flop DFF1 and the output terminal D of the first flip-flop DFF1 respectively. The second input terminal of the first XOR gate circuit XOR1 is connected to the input terminal D of the second flip-flop DFF2 and the output terminal D of the second flip-flop DFF2 respectively. The output terminal TCOUNTER of the first XOR gate circuit XOR1 outputs a time pulse width signal T_OUT.

[0070] In this embodiment, both the first flip-flop DFF1 and the second flip-flop DFF2 are falling-edge triggered flip-flops.

[0071] like Figure 6 As shown, the digital control module 10 includes: a first controller 11, a third trigger DFF3 and a first OR gate circuit OR1; wherein,

[0072] The clock input terminal Clk of the third flip-flop DFF3 receives the first clock signal CLK1 output by the first controller 11, and the input terminal D of the third flip-flop DFF3 is connected to the clock input terminal Clkn of the second flip-flop DFF2;

[0073] A first input terminal of the first OR gate circuit OR1 and an output terminal of the third flip-flop DFF3 The first input end of the first OR gate circuit OR1 receives the second reset signal RST1 output by the first controller 11, and the output end of the first OR gate circuit OR1 outputs the first reset signal RST_CAP1; wherein the second reset signal RST1 is a signal generated by the first controller 11 according to the received first reset instruction.

[0074] The third trigger DFF3 is a rising edge triggered trigger.

[0075] like Figure 7 As shown, the signal T_ERR1 does not actually exist, but is only used to explain the reason for adding the first trigger DFF1 and the second trigger DFF2. When the second reset signal RST1 is enabled as a high-level signal, the first reset signal RST_CAP1 is pulled high (pulling high indicates that the level signal changes from a low-level signal to a high-level signal), the first switch S1, the fourth switch S4, the fifth switch S5, the eighth switch S8, the ninth switch S9, and the tenth switch S10 are closed, and the second switch S2, the third switch S3, the sixth switch S6, and the seventh switch S7 are opened. At this time, the voltage of the positive plate of the first capacitor C1 (i.e., the first charging voltage output terminal VINN1) and the voltage of the positive plate of the second capacitor C2 (i.e., the second charging voltage output terminal VINP1) are both zero, the signal T13 input to the first input terminal of the first XOR gate circuit XOR1, the signal T14 input to the second input terminal, and the signal output from the output terminal TCOUNTER1 are low-level signals, and the outputs of the signals T11 and T12 are high-level signals. When the first reset signal RST_CAP1 is pulled low, the ninth switch S9 and the tenth switch S10 are disconnected, and the states of the remaining switches remain unchanged. The input time pulse signal IN_PULSE is controlled by the first controller 11 to be divided into a first time pulse signal group CHARGE1 and a second time pulse signal group CHARGE2, and sequentially controls the first capacitor C1 and the second capacitor C2 to charge with the first current I11, and the first charging voltage output terminal VINN1 generates a first pre-charging voltage V_pre11, and the second charging voltage output terminal VINP1 generates a second pre-charging voltage V_pre12. Among them, when the output signal of the first time pulse signal group CHARGE1 is a high-level signal, the second switch S2 is closed and the first switch S1 is opened, and the first capacitor C1 starts to charge with the first current I11. After the output signal of the first time pulse signal group CHARGE1 is pulled low, the second switch S2 is opened and the first S1 is closed; when the output signal of the second time pulse signal group CHARGE2 is a high-level signal, the seventh switch S7 is closed and the eighth switch S8 is opened, and the second capacitor C2 starts to charge with the first current I11. After the output signal of the second time pulse signal group CHARGE2 is pulled low, the seventh switch S7 is opened and the eighth switch S8 is closed.

[0076] When the second capacitor C2 completes pre-charging and the output signal of the second time pulse signal group CHARGE2 is pulled low, the first interrupt trigger signal T_CHARGE1 output by the first controller 11 changes from a low level signal to a high level signal, the third switch S3 and the sixth switch S6 are closed, and the fourth switch S4 and the fifth switch S5 are opened. At this time, the positive plates of the first capacitor C1 and the second capacitor C2 start with the first pre-charging voltage V_pre11 and the second pre-charging voltage V_pre12, and continue to charge using the second current I12 until the signal T11 and the signal T12 are all pulled low, that is, the outputs of the first buffer BUF1 and the second buffer BUF2 are all pulled low.

[0077] The falling edges of the signals T11 and T12 trigger the first trigger DFF1 and the second trigger DFF2 respectively, pull the outputs of the signals T13 and T14 high, and then obtain the output time level TCOUNTER1 through the first XOR gate circuit XOR1. This process is essential to eliminate the non-ideal time pulse problem caused by parasitic capacitance and the mismatch of electrical parameters between the first inverter INV1 and the second inverter INV2. Figure 6 As shown, when there is a mismatch between the frequency control signal routing of the first inverter INV1 and the second inverter INV2, and there is a voltage difference between the first capacitor C1 and the second capacitor C2, if the first trigger DFF1 and the second trigger DFF2 are not added, but the first XOR gate circuit XOR1 is directly used to calculate the XOR, a T_ERR1 signal may be generated, such as Figure 7 As shown, there are non-ideal pulses, which will affect the operation of the circuit.

[0078] When the second charging voltage output terminal VINP1 pulls the signal T12 low, the first clock signal CLK1 outputs a high level signal. At this time, the first reset signal RST_CAP1 is a high level signal again, so that the voltage across the first capacitor C1 and the second capacitor C2 can be set to 0 again to start the next cycle.

[0079] Combining the above contents, we can get the following formulas (1) and (2):

[0080] (I11*CHARGE1) / C1+(I12*T_trans11) / C1=V_th (1)

[0081] (I11*CHARGE2) / C2+(I12*T_trans12) / C2=V_th (2)

[0082] Wherein, C1=C2=C, TCOUNTER1=T_trans12-T_trans11, T_trans11 is the first charging time length for charging the first capacitor C1 with the second current I12, T_trans12 is the second charging time length for charging the second capacitor C2 with the second current I12, and V_th is the preset voltage. Thus, the expression of the output time level TCOUNTER can be obtained as the following formula (3):

[0083] TCOUNTER1=(CHARGE1-CHARGE2)*I11 / I12 (3)

[0084] It can be seen from the above formula (3) that the difference (CHARGE1-CHARGE2) is amplified or reduced by I11 / I12 times, thereby achieving amplification and reduction, and its gain can be achieved by adjusting the size of the second transistor M2 to the fifth transistor M5, that is, the current ratio. In addition, the first time pulse signal group CAHRGE1 and the second time pulse signal group CHARGE2 can be used as a generalized concept of time, and are not simply treated as a single time pulse, that is, CHARGE1 and CHARGE2 can be the result of adding N time pulses, thereby achieving the addition and subtraction of any number of pulse signals. Figure 8 As shown, the input time pulse signal IN_PULSE includes the first time pulse signal t1 to the sixth time pulse signal t6, and the first time pulse signal t1 to the fourth time pulse signal t4 are used as the first time pulse signal group CHARGE1 to charge the voltage of the first charging voltage output terminal VINN1 to the first voltage V_pre1; the fifth time pulse signal t5 and the sixth time pulse signal t6 are used as the second time pulse signal group CHARGE2 to charge the voltage of the second charging voltage output terminal VINP1 to the second voltage V_pre2. The rest of the working sequence is the same as Figure 7 Consistent.

[0085] Since the output time level TCOUNTER1 is the result of the difference between the two-end signals, the quantization error introduced by the preset voltage V_th due to the process variation, temperature and voltage (Process Variation-Temperature-Voltage, PVT) can be eliminated. In addition, the inverter-based comparison module 30 proposed in the present disclosure can achieve fast response, that is, when the voltage output by the first charging voltage output terminal VINN1 and the voltage output by the second charging voltage output terminal VINP1 reach the corresponding inverter flip threshold (i.e., the preset voltage V_th), the signal T11 and the signal T12 can be quickly flipped at a ps-level speed, thereby reducing the quantization error.

[0086] The error introduced by the mismatch between the first inverter INV1 and the second inverter INV2 can be solved by switching the positions of the two inverters each time. For example, in the first cycle, the first charging voltage output terminal VINN1, the first inverter INV1, and the first buffer BUF1 are connected, and the second charging voltage output terminal VINP1, the second inverter INV2, and the second buffer BUF2 are connected; in the second cycle, the first charging voltage output terminal VINN1, the second inverter INV2, and the second buffer BUF2 are connected, and the second charging voltage output terminal VINP1, the first inverter INV1, and the first buffer BUF1 are connected. Repeat the above rules, and an even number of cycles is regarded as a data conversion cycle. Therefore, in the first cycle, the following formulas (4) and (5) can be obtained:

[0087] (I11*CHARGE1) / C1+(I12*T_trans11) / C1=V_th (4)

[0088] (I11*CHARGE2) / C2+(I12*T_trans12) / C2=V_th+V_os (5)

[0089] In the second cycle, the following formulas (6) and (7) can be obtained:

[0090] (I11*CHARGE1) / C1+(I12*T_trans11) / C1=V_th+V_os (6)

[0091] (I11*CHARGE2) / C2+(I12*T_trans12) / C2=V_th (7)

[0092] Where V_os represents the offset voltage. From the above, the expression of TCOUNTER1 output after two cycles is as follows (8):

[0093] TCOUNTER1=2*(CHARGE1-CHARGE2)*I11 / I12 (8)

[0094] Therefore, the current charging type time amplifier disclosed in the present invention can not only realize the addition operation of the input signal, but also realize the differential operation of the input signal; in addition, the current charging type time amplifier disclosed in the present invention can also be adjusted to different gains according to different needs; in addition, the current charging type time amplifier disclosed in the present invention is less sensitive to process, voltage and temperature, and can eliminate the PVT problem introduced by the comparison module.

[0095] The above-mentioned current charging type time amplifier is described. The time amplifier disclosed in the present invention can also be a current discharging type. Figure 9-12 Introducing the current discharge type time amplifier.

[0096] like Fig. 9 As shown, the input time pulse signal IN_PULSE is described by taking two time pulse signals as an example. It should be noted that the embodiment of the present disclosure can process two or more time pulse signals and perform time amplification. Exemplarily, if the input time pulse signal IN_PULSE includes a first time pulse signal t1 and a second time pulse signal t2, then the first time pulse signal group CHARGE1 includes the first time pulse signal t1, and the second time pulse signal group CHARGE2 includes the second time pulse signal t2. The input time pulse signal IN_PULSE is divided into two parts by the digital control module 10, wherein the first time pulse signal t1 enters the signal processing module 20 for pre-discharge and generates a first pre-discharge voltage V_pre21, and the second time pulse signal t2 enters the signal processing module 20 for pre-discharge and generates a second pre-discharge voltage V_pre22. After the two capacitors in the signal processing module 20 are pre-discharged, they are discharged simultaneously. The first voltage V1 and the second voltage V2 generated by the discharge are sent to the comparison module 30 for comparison, and an output time pulse width signal T_OUT is generated.

[0097] like Fig.10 As shown, the signal processing module 20 includes: a second current source IS2, a current mirror circuit composed of a sixth transistor M6 to a tenth transistor M10, an eleventh switch S11 to a twentieth switch S20, a third energy storage element 23 and a fourth energy storage element 24; wherein,

[0098] The first end of the sixth transistor M6 to the first end of the tenth transistor M10 are all connected to the ground end, and the second end of the sixth transistor M6 is respectively connected to the control end of the sixth transistor M6 to the control end of the tenth transistor M10 and then connected to the second power supply end VCC2 through the second current source IS2;

[0099] a second power supply terminal VCC2, connected to the second end of the seventh transistor M7 through the eleventh switch S11, connected to the ground terminal through the twelfth switch S12 and the third energy storage element 23 in sequence, connected to the second end of the eighth transistor M8 through the twelfth switch S12 and the thirteenth switch S13 in sequence, connected to the second end of the eighth transistor M8 through the fourteenth switch S14, connected to the second end of the ninth transistor M9 through the fifteenth switch S15, connected to the ground terminal through the sixteenth switch S16 and the fourth energy storage element 24 in sequence, connected to the second end of the tenth transistor M10 through the sixteenth switch S16 and the seventeenth switch S17 in sequence, connected to the second end of the tenth transistor M10 through the eighteenth switch S18, connected to the second end of the seventh transistor M7 through the twelfth switch S12 and the nineteenth switch S19 in sequence, and connected to the second end of the ninth transistor M9 through the sixteenth switch S16 and the twentieth switch S20 in sequence;

[0100] A third node of the third energy storage unit 23 connected to the twelfth switch S12, the thirteenth switch S13, and the nineteenth switch S19 respectively serves as a first discharge voltage output terminal VINN2;

[0101] A fourth node of the fourth energy storage unit 24 connected to the sixteenth switch S16 , the seventeenth switch S17 , and the twentieth switch S20 respectively serves as the second discharge voltage output terminal VINP2 .

[0102] The third energy storage element 23 and the fourth energy storage element 24 are capacitors; the capacity of the third energy storage element 23 is equal to the capacity of the fourth energy storage element 24 .

[0103] like Fig.10 As shown, the comparison module 30 includes: a third inverter INV3, a fourth inverter INV4, a third buffer BUF3, a fourth buffer BUF4, a fourth trigger DFF4, a fifth trigger DFF5 and a second XOR gate circuit XOR2; wherein,

[0104] The output end of the third inverter INV3 is connected to the input end of the third buffer BUF3, and the output end of the fourth inverter INV4 is connected to the input end of the fourth buffer BUF4;

[0105] The digital control module 10 is further used to send a second frequency control signal F_CHOP2 to control the input end of the third inverter INV3 to be connected to one of the first discharge voltage output end VINN2 or the second discharge voltage output end VINP2, the input end of the fourth inverter INV4 to be connected to the other of the first discharge voltage output end VINN2 or the second discharge voltage output end VINP2, and the output end of the third buffer BUF3 to be connected to one of the clock input end Clk of the fourth flip-flop DFF4 or the clock input end Clk of the fifth flip-flop DFF5, and the output end of the fourth buffer BUF4 to be connected to the other of the clock input end Clk of the fourth flip-flop DFF4 or the clock input end Clk of the fifth flip-flop DFF5;

[0106] The first input terminal of the second XOR gate circuit XOR2 is connected to the input terminal D of the fourth flip-flop DFF4 and the output terminal Q of the fourth flip-flop DFF4 respectively, and the second input terminal of the second XOR gate circuit XOR2 is connected to the input terminal D of the fifth flip-flop DFF5 and the output terminal Q of the fifth flip-flop DFF5 respectively. The output end of the second XOR gate circuit XOR2 outputs a time pulse width signal T_OUT.

[0107] The fourth trigger DFF4 and the fifth trigger DFF5 are rising edge triggered triggers.

[0108] like Fig.10 As shown, the digital control module 10 includes: a second controller 12, a sixth trigger DFF6 and a second OR gate circuit OR1; wherein,

[0109] The clock input terminal Clk of the sixth flip-flop DFF6 receives the second clock signal CLK2 output by the second controller 12, and the input terminal D of the sixth flip-flop DFF6 is connected to the clock input terminal Clk of the fifth flip-flop DFF5;

[0110] The first input end of the second OR gate circuit OR2 is connected to the output end Q of the sixth flip-flop DFF6, the first input end of the second OR gate circuit OR2 receives the fourth reset signal RST2 output by the second controller 12, and the output end of the second OR gate circuit OR2 outputs the third reset signal RST_CAP2; wherein, the fourth reset signal RST2 is a signal generated by the second controller 12 based on the received second reset instruction.

[0111] Among them, the sixth trigger DFF6 is a trigger triggered by a rising edge.

[0112] like Fig.11As shown, the signal T_ERR2 does not actually exist, but is only used to explain the reason for adding the fourth trigger DFF4 and the fifth trigger DFF5. When the fourth reset signal RST2 is enabled as a high-level signal, the third reset signal RST_CAP2 is pulled high, the twelfth switch S12, the fourteenth switch S14, the sixteenth switch S16, the eighteenth switch S18, the eleventh switch S11, and the fifteenth switch S15 are closed, and the thirteenth switch S13, the nineteenth switch S19, the seventeenth switch S17, and the twentieth switch S20 are disconnected. At this time, the voltages of the positive plate of the third capacitor C3 (i.e., the first discharge voltage output terminal VINN2) and the positive plate of the fourth capacitor C4 (i.e., the second discharge voltage output terminal VINP2) are both the power supply voltage Vdd of the second power supply, and the outputs of the signals T21, T22, T23, T24, and TCOUNTER2 are low-level signals. When the third reset signal RST_CAP2 is pulled low, the twelfth switch S12 and the sixteenth switch S16 are disconnected, and the states of the other switches remain unchanged. The input time pulse signal IN_PULSE is controlled by the second controller 12 and is divided into a first time pulse signal group CHARGE1 and a second time pulse signal group CHARGE2, and sequentially controls the third capacitor C3 and the fourth capacitor C4 to discharge with the third current I21, the first discharge voltage output terminal VINN2 generates a first pre-discharge voltage V_pre21, and the second discharge voltage output terminal VINP2 generates a second pre-discharge voltage V_pre22. Wherein, when the first time pulse signal group CHARGE1 is a high level signal, the nineteenth switch S19 is closed and the eleventh switch S11 is opened, and the third capacitor C3 starts to discharge with the third current I21. After the signal of the first time pulse signal group CHARGE1 is pulled low, the nineteenth switch S19 is opened and the eleventh switch S11 is closed; when the second time pulse signal group CHARGE2 is a high level signal, the seventeenth switch S17 is closed and the eighteenth switch S18 is opened, and the fourth capacitor C4 starts to discharge with the third current I21. After the second time pulse signal group CHARGE2 is pulled low, the seventeenth switch S17 is opened and the eighteenth switch S18 is closed.

[0113] When the fourth capacitor C4 completes the discharge and the signal of the second time pulse signal group CHARGE2 is pulled low, the second interrupt trigger signal T_CHARGE2 output by the second controller 12 changes from a low level signal to a high level signal, the thirteenth switch S13 and the twentieth switch S20 are closed, and the fourteenth switch S14 and the fifteenth switch S15 are opened. At this time, the positive plates of the third capacitor C3 and the fourth capacitor C4 start with the first pre-discharge voltage V_pre21 and the second pre-discharge voltage V_pre22, and use the fourth current I22 to discharge until the signal T21 and the signal T22 are all pulled high, that is, the outputs of the fourth buffer BUF4 and the fifth buffer BUF5 are all pulled high.

[0114] The falling edges of the signals T21 and T22 trigger the fourth trigger DFF4 and the fifth trigger DFF5 respectively, pull the outputs of the signals T23 and T24 high, and then obtain the output time level TCOUNTER2 through the second XOR gate circuit XOR2. This process is essential to eliminate the non-ideal time pulse problem caused by parasitic capacitance and the mismatch of electrical parameters of the third inverter INV3 and the fourth inverter INV4. Fig.10 As shown, when the frequency control signal routing of the third inverter INV3 and the fourth inverter INV4 is mismatched, and there is a voltage difference between the third capacitor C3 and the fourth capacitor C4, if the fourth trigger DFF4 and the fifth trigger DFF5 are not added, but the second XOR gate circuit XOR2 is directly used to calculate the XOR, a T_ERR2 signal may be generated, such as Fig.11 As shown, there are non-ideal pulses, which affect the operation of the circuit.

[0115] When the second discharge voltage output terminal VINP2 pulls the signal T22 low, the second clock signal CLK2 will output a high level. At this time, the third reset signal RST_CAP2 is a high level signal again, so that the voltage across the third capacitor C3 and the fourth capacitor C4 can be set to the power supply voltage Vdd to start the next cycle.

[0116] Based on the above, the expressions can be expressed as the following formulas (9) and (10):

[0117] (I21*CHARGE1) / C3+(I22*T_trans21) / C4=Vdd-V_th (9)

[0118] (I21*CHARGE2) / C3+(I22*T_trans22) / C4=Vdd-V_th (10)

[0119] Wherein, C3=C4=C, TCOUNTER2=T_trans22-T_trans21, T_trans21 is the first discharge time length of discharging the third capacitor C3 with the fourth current I22, T_trans22 is the second discharge time length of discharging the fourth capacitor C4 with the fourth current I22, and V_th is the preset voltage. Thus, the expression of the output time level TCOUNTER2 can be obtained as the following formula (11):

[0120] TCOUNTER2=(CHARGE1-CHARGE2)*I21 / I22 (11)

[0121] It can be seen from the above formula (11) that the difference (CHARGE1-CHARGE2) is amplified or reduced by I21 / I22 times, thereby achieving amplification and reduction, and its gain can be achieved by adjusting the sizes of the seventh transistor M7 to the tenth transistor M10, that is, the current ratio. In addition, the first time pulse signal group CAHRGE1 and the second time pulse signal group CHARGE2 can be used as a generalized concept of time, and are not simply treated as a single time pulse, that is, CHARGE1 and CHARGE2 can be the result of adding N time pulses, thereby achieving the addition and subtraction of any number of pulse signals. Fig.12 As shown, the input time pulse signal IN_PULSE includes the first time pulse signal t1 to the sixth time pulse signal t6, and the first time pulse signal t1 to the fourth time pulse signal t4 are used as the first time pulse signal group CHARGE1, which discharges the voltage of the first discharge voltage output terminal VINN2 to the first voltage V_pre21; the fifth time pulse signal t5 and the sixth time pulse signal t6 are used as the second time pulse signal group CHARGE2, which discharges the voltage of the second discharge voltage output terminal VINP2 to the second voltage V_pre22. The rest of the working sequence is the same as Fig.11 Consistent.

[0122] The error introduced by the mismatch between the third inverter INV3 and the fourth inverter INV4 can be solved by switching the positions of the two inverters each time. For example, in the first cycle, the first discharge voltage output terminal VINN2, the third inverter INV3, and the fourth buffer BUF1 are connected, and the second discharge voltage output terminal VINP2, the fourth inverter INV4, and the fourth buffer BUF4 are connected; in the second cycle, the first discharge voltage output terminal VINN2, the fourth inverter INV4, and the fourth buffer BUF4 are connected, and the second discharge voltage output terminal VINP2, the third inverter INV3, and the fourth buffer BUF1 are connected. Repeat the above rules, and an even number of cycles is regarded as a data conversion cycle. Therefore, in the first cycle, the following formulas (12) and (13) can be obtained:

[0123] (I21*CHARGE1) / C3+(I22*T_trans21) / C3=Vdd-V_th (12)

[0124] (I21*CHARGE2) / C4+(I22*T_trans22) / C4=Vdd-(V_th+V_os) (13)

[0125] In the second cycle, the following formulas (14) and (15) can be obtained:

[0126] (I21*CHARGE1) / C3+(I22*T_trans21) / C3=Vdd-(V_th+V_os) (14)

[0127] (I21*CHARGE2) / C4+(I22*T_trans22) / C4=Vdd-V_th (15)

[0128] Where V_os represents the offset voltage. From the above, the expression of TCOUNTER2 output after two cycles is as follows (16):

[0129] TCOUNTER2=2*(CHARGE1-CHARGE2)*I21 / I22 (16)

[0130] Therefore, the current discharge type time amplifier disclosed in the present invention can not only realize the addition operation of the input signal, but also realize the differential operation of the input signal; in addition, the current discharge type time amplifier disclosed in the present invention can also be adjusted to different gains according to different needs; in addition, the current discharge type time amplifier disclosed in the present invention is less sensitive to process, voltage and temperature, and can eliminate the PVT problem introduced by the comparison module.

[0131] In summary, the time amplifier of the embodiment of the present disclosure is composed of a digital control module, a signal processing module and a comparison module, wherein the digital control module is used to divide the input multiple time pulse signals into a first time pulse signal group and a second time pulse signal group, the signal processing module is used to perform charging or discharging processing according to the first time pulse signal group to obtain a first voltage, and to perform charging or discharging processing according to the second time pulse signal group to obtain a second voltage, and the comparison module is used to compare the corresponding first voltage and the second voltage with the preset voltage respectively, and determine and output the time pulse width signal according to the comparison result. Therefore, the time amplifier of the present disclosure can realize differential operation of multiple time pulse signals.

[0132] Based on the above embodiments, the present disclosure also proposes a sensor.

[0133] The sensor of the embodiment of the present disclosure includes the above-mentioned time amplifier.

[0134] The sensor of the embodiment of the present disclosure can realize differential operation on multiple time pulse signals by using the above-mentioned time amplifier.

[0135] Based on the above embodiments, the present disclosure further proposes a chip, which includes the above-mentioned time amplifier.

[0136] In the embodiments of the present disclosure, the chip may be an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA).

[0137] It should be noted that for details not disclosed in the chip of the embodiment of the present disclosure, please refer to the details disclosed in the time amplifier of the embodiment of the present disclosure, and no further details will be given here.

[0138] The chip of the embodiment of the present disclosure can realize differential operation on multiple time pulse signals by using the above-mentioned time amplifier.

[0139] Based on the above embodiments, the present disclosure also proposes an electronic device, which includes the above time amplifier.

[0140] In the embodiments of the present disclosure, the electronic device may be a vehicle, a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0141] It should be noted that for details not disclosed in the electronic device of the embodiment of the present disclosure, please refer to the details disclosed in the time amplifier of the embodiment of the present disclosure, and the details will not be repeated here.

[0142] The electronic device according to the embodiment of the present disclosure can realize differential operation on a plurality of time pulse signals by using the above-mentioned time amplifier.

[0143] Fig.13 is a flow chart of a time control method according to an embodiment of the present disclosure.

[0144] like Fig.13 As shown, the time control method of the embodiment of the present disclosure includes the following steps:

[0145] S1, dividing a plurality of input time pulse signals into a first time pulse signal group and a second time pulse signal group.

[0146] S2, performing charging or discharging according to the first time pulse signal group to obtain a first voltage, and performing charging or discharging according to the second time pulse signal group to obtain a second voltage.

[0147] S3, respectively comparing the first voltage and the second voltage with a preset voltage, and determining and outputting a time pulse width signal according to the comparison result.

[0148] In one embodiment of the present disclosure, performing charging processing according to a first time pulse signal group to obtain a first voltage, and performing charging processing according to a second time pulse signal group to obtain a second voltage, includes:

[0149] After receiving the first reset signal, pre-charging is performed according to the first time pulse signal group to obtain a first pre-charging voltage, and pre-charging is performed according to the second time pulse signal group to obtain a second pre-charging voltage;

[0150] After receiving the first interrupt trigger signal, the charging process is continued based on the first pre-charge voltage to obtain the first voltage, and the charging process is continued based on the second pre-charge voltage to obtain the second voltage; wherein the first interrupt trigger signal is a signal generated and sent when the pre-charge operation is completed.

[0151] The first reset signal is generated by the following steps:

[0152] In response to receiving the first reset instruction, generating a second reset signal;

[0153] A first reset signal is generated according to the second reset signal and the first clock signal.

[0154] In another embodiment of the present disclosure, performing charging processing according to a first time pulse signal group to obtain a first voltage, and performing charging processing according to a second time pulse signal group to obtain a second voltage, includes:

[0155] After receiving the third reset signal, performing pre-discharge processing according to the first time pulse signal group to obtain a first pre-discharge voltage, and performing pre-discharge processing according to the second time pulse signal group to obtain a second pre-discharge voltage;

[0156] After receiving the second interrupt trigger signal, the discharge process is continued based on the first pre-discharge voltage to obtain the first voltage, and the discharge process is continued based on the second pre-discharge voltage to obtain the second voltage; wherein the second interrupt trigger signal is a signal generated and sent when the pre-discharge operation is completed.

[0157] The third reset signal is generated by following the steps below:

[0158] In response to receiving the second reset instruction, generating a fourth reset signal;

[0159] A third reset signal is generated according to the fourth reset signal and the second clock signal.

[0160] It should be noted that for details not disclosed in the time control method of the embodiment of the present disclosure, please refer to the details disclosed in the time amplifier of the embodiment of the present disclosure, and the details will not be repeated here.

[0161] According to the time control method of the embodiment of the present disclosure, the input multiple time pulse signals are divided into a first time pulse signal group and a second time pulse signal group, and then charging processing or discharging processing is performed according to the first time pulse signal group to obtain a first voltage, and charging processing or discharging processing is performed according to the second time pulse signal group to obtain a second voltage. Thereafter, the first voltage and the second voltage are respectively compared with the preset voltage, and based on the comparison result, the time pulse width signal is determined and output, thereby realizing differential operation of multiple time pulse signals.

[0162] Based on the above embodiments, the present disclosure proposes a non-transitory computer-readable storage medium.

[0163] The non-transitory computer-readable storage medium of the embodiment of the present disclosure stores computer program instructions, and when the computer program instructions are executed by a processor, the steps of the above method are implemented.

[0164] Based on the above embodiments, the present disclosure proposes a computer program product.

[0165] The computer program product of the embodiment of the present disclosure includes a computer program, and when the computer program is executed by a processor, the steps of the above method are implemented.

[0166] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0167] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0168] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0169] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in conjunction with such instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in conjunction with such instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wirings (electronic devices), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and editable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0170] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA for short), a field programmable gate array (FPGA for short), etc.

[0171] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0172] In addition, each functional unit in each embodiment of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0173] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present application.

[0174] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

[0175] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A time amplifier, characterized in that: include: A digital control module, used for dividing the input multiple time pulse signals into a first time pulse signal group and a second time pulse signal group; a signal processing module, configured to perform charging or discharging according to the first time pulse signal group to obtain a first voltage, and to perform charging or discharging according to the second time pulse signal group to obtain a second voltage; The comparison module is used to compare the first voltage and the second voltage with a preset voltage respectively, and determine and output a time pulse width signal according to the comparison result.

2. The time amplifier according to claim 1, characterized in that: The signal processing module is used to perform charging processing according to the first time pulse signal group to obtain a first voltage, and to perform charging processing according to the second time pulse signal group to obtain a second voltage, including: The signal processing module is used to perform a pre-charge process according to the first time pulse signal group to obtain a first pre-charge voltage after receiving the first reset signal, and to perform a pre-charge process according to the second time pulse signal group to obtain a second pre-charge voltage; The signal processing module is also used to, after receiving a first interrupt trigger signal, continue the charging process based on the first pre-charge voltage to obtain the first voltage, and continue the charging process based on the second pre-charge voltage to obtain the second voltage; wherein the first interrupt trigger signal is a signal generated and sent by the digital control module when the signal processing module completes the pre-charge operation.

3. The time amplifier according to claim 2, characterized in that: The signal processing module includes: a first current source, a current mirror circuit composed of first to fifth transistors, first to tenth switches, a first energy storage element and a second energy storage element; wherein, The first end of the first transistor to the first end of the fifth transistor are respectively connected to the first power supply end, and the second end of the first transistor is respectively connected to the control end of the first transistor to the control end of the fifth transistor and then connected to the ground end through the first current source; The second end of the second transistor is connected to the ground end through the first switch, and is also connected to the ground end through the second switch and the first energy storage element in sequence; The second end of the third transistor is connected to the ground terminal through the third switch and the first energy storage element in sequence, and is also connected to the ground terminal through the fourth switch; The second end of the fourth transistor is connected to the ground terminal through the fifth switch, and is also connected to the ground terminal through the sixth switch and the second energy storage element in sequence; The second end of the fifth transistor is connected to the ground terminal through the seventh switch and the second energy storage element in sequence, and is also connected to the ground terminal through the eighth switch; The first energy storage element is connected in parallel with the ninth switch, and the first node where the first energy storage element is respectively connected with the second switch, the third switch and the ninth switch serves as a first charging voltage output terminal; The second energy storage element is connected in parallel with the tenth switch, and a second node where the second energy storage element is respectively connected to the sixth switch, the seventh switch and the tenth switch serves as a second charging voltage output terminal.

4. The time amplifier according to claim 3, characterized in that: The comparison module comprises: a first inverter, a second inverter, a first buffer, a second buffer, a first trigger, a second trigger and a first XOR gate circuit; wherein, The output end of the first inverter is connected to the input end of the first buffer, and the output end of the second inverter is connected to the input end of the second buffer; The digital control module is further used to send a first frequency control signal to control the input terminal of the first inverter to be connected to one of the first charging voltage output terminal or the second charging voltage output terminal, the input terminal of the second inverter to be connected to the other of the first charging voltage output terminal or the second charging voltage output terminal, and the output terminal of the first buffer to be connected to one of the clock input terminal Clkn of the first trigger or the clock input terminal Clkn of the second trigger, and the output terminal of the second buffer to be connected to the other of the clock input terminal Clkn of the first trigger or the clock input terminal Clkn of the second trigger; The first input terminal of the first XOR gate circuit is respectively connected to the input terminal D of the first trigger and the output terminal of the first trigger The second input terminal of the first XOR gate circuit is connected to the input terminal D of the second trigger and the output terminal of the second trigger respectively. The output end of the first XOR gate circuit outputs the time pulse width signal.

5. The time amplifier according to claim 4, characterized in that: The digital control module comprises: a first controller, a third trigger and a first OR gate circuit; wherein, The clock input terminal Clk of the third flip-flop receives the first clock signal output by the first controller, and the input terminal D of the third flip-flop is connected to the clock input terminal Clkn of the second flip-flop; The first input terminal of the first OR gate circuit and the output terminal of the third trigger The first input end of the first OR gate circuit receives the second reset signal output by the first controller, and the output end of the first OR gate circuit outputs the first reset signal; wherein, the second reset signal is a signal generated by the first controller when receiving the first reset instruction.

6. The time amplifier according to claim 1, characterized in that: The signal processing module is used to perform a discharge process according to the first time pulse signal group to obtain a first voltage, and to perform a discharge process according to the second time pulse signal group to obtain a second voltage, including: The signal processing module is used to perform pre-discharge processing according to the first time pulse signal group to obtain a first pre-discharge voltage, and perform pre-discharge processing according to the second time pulse signal group to obtain a second pre-discharge voltage after receiving the third reset signal; The signal processing module is further used to, after receiving a second interrupt trigger signal, continue the discharge process based on the first pre-discharge voltage to obtain the first voltage, and continue the discharge process based on the second pre-discharge voltage to obtain the second voltage; wherein the second interrupt trigger signal is a signal generated and sent by the digital control module when the signal processing module completes the pre-discharge operation.

7. The time amplifier according to claim 6, characterized in that: The signal processing module includes: a second current source, a current mirror circuit composed of a sixth transistor to a tenth transistor, an eleventh switch to a twentieth switch, a third energy storage element and a fourth energy storage element; wherein, The first end of the sixth transistor to the first end of the tenth transistor are all connected to the ground end, and the second end of the sixth transistor is respectively connected to the control end of the sixth transistor to the control end of the tenth transistor and then connected to the second power supply end through the second current source; The second power supply terminal is connected to the second end of the seventh transistor through the eleventh switch, is connected to the ground terminal through the twelfth switch and the third energy storage element in sequence, is connected to the second end of the eighth transistor through the twelfth switch and the thirteenth switch in sequence, is connected to the second end of the eighth transistor through the fourteenth switch, is connected to the second end of the ninth transistor through the fifteenth switch, is connected to the ground terminal through the sixteenth switch and the fourth energy storage element in sequence, is connected to the second end of the tenth transistor through the sixteenth switch and the seventeenth switch in sequence, is connected to the second end of the tenth transistor through the eighteenth switch, is connected to the second end of the seventh transistor through the twelfth switch and the nineteenth switch in sequence, and is connected to the second end of the ninth transistor through the sixteenth switch and the twenty-third switch in sequence; A third node of the third energy storage unit connected to the twelfth switch, the thirteenth switch, and the nineteenth switch respectively serves as a first discharge voltage output terminal; A fourth node of the fourth energy storage unit connected to the sixteenth switch, the seventeenth switch, and the twentieth switch respectively serves as a second discharge voltage output terminal.

8. The time amplifier according to claim 7, characterized in that: The comparison module includes: a third inverter, a fourth inverter, a third buffer, a fourth buffer, a fourth trigger, a fifth trigger and a second XOR gate circuit; wherein, The output end of the third inverter is connected to the input end of the third buffer, and the output end of the fourth inverter is connected to the input end of the fourth buffer; The digital control module is further used to send a frequency control signal to control the input end of the third inverter to be connected to one of the first discharge voltage output end or the second discharge voltage output end, the input end of the fourth inverter to be connected to the other of the first discharge voltage output end or the second discharge voltage output end, and the output end of the third buffer to be connected to one of the clock input end Clk of the fourth trigger or the clock input end Clk of the fifth trigger, and the output end of the fourth buffer to be connected to the other of the clock input end Clk of the fourth trigger or the clock input end Clk of the fifth trigger; The first input terminal of the second XOR gate circuit is respectively connected to the input terminal D of the fourth trigger and the output terminal of the fourth trigger The second input terminal of the second XOR gate circuit is connected to the input terminal D of the fifth trigger and the output terminal of the fifth trigger respectively. The output end of the second XOR gate circuit outputs the time pulse width signal.

9. The time amplifier according to claim 8, characterized in that: The digital control module includes: a second controller, a sixth trigger and a second OR gate circuit; wherein, The clock input terminal Clk of the sixth flip-flop receives the second clock signal output by the second controller, and the input terminal D of the sixth flip-flop is connected to the clock input terminal Clk of the fifth flip-flop; The first input terminal of the second OR gate circuit is connected to the output terminal Q of the sixth trigger, the first input terminal of the second OR gate circuit receives the fourth reset signal output by the second controller, and the output terminal of the second OR gate circuit outputs the third reset signal; wherein, the fourth reset signal is a signal generated by the second controller when receiving the second reset instruction.

10. The time amplifier according to claim 3 or 7, characterized in that: The first energy storage element, the second energy storage element, the third energy storage element and the fourth energy storage element are all capacitors; wherein, The capacity of the first energy storage element is equal to the capacity of the second energy storage element; The capacity of the third energy storage element is equal to the capacity of the fourth energy storage element.

11. The time amplifier according to claim 5 or 9, characterized in that: The first trigger and the second trigger are falling edge triggered triggers, and the third to sixth triggers are rising edge triggered triggers.

12. A sensor, characterized in that: include: A time amplifier as claimed in any one of claims 1 to 11.

13. A chip, characterized in that: include: A time amplifier as claimed in any one of claims 1 to 11.

14. An electronic device, characterized in that: include: A time amplifier as claimed in any one of claims 1 to 11.

15. A time control method, characterized in that: include: Dividing the input multiple time pulse signals into a first time pulse signal group and a second time pulse signal group; Performing charging or discharging according to the first time pulse signal group to obtain a first voltage, and performing charging or discharging according to the second time pulse signal group to obtain a second voltage; The first voltage and the second voltage are respectively compared with a preset voltage, and a time pulse width signal is determined and output according to the comparison result.

16. The time control method according to claim 15, characterized in that: The step of performing charging processing according to the first time pulse signal group to obtain a first voltage, and performing charging processing according to the second time pulse signal group to obtain a second voltage, comprises: After receiving the first reset signal, pre-charging is performed according to the first time pulse signal group to obtain a first pre-charging voltage, and pre-charging is performed according to the second time pulse signal group to obtain a second pre-charging voltage; After receiving the first interrupt trigger signal, the charging process is continued based on the first pre-charge voltage to obtain the first voltage, and the charging process is continued based on the second pre-charge voltage to obtain the second voltage; wherein the first interrupt trigger signal is a signal generated and sent when the pre-charge operation is completed.

17. The time control method according to claim 16, characterized in that: The first reset signal is generated by the following steps: In response to receiving the first reset instruction, generating a second reset signal; The first reset signal is generated according to the second reset signal and the first clock signal.

18. The time control method according to claim 15, characterized in that: The step of performing charging processing according to the first time pulse signal group to obtain a first voltage, and performing charging processing according to the second time pulse signal group to obtain a second voltage, comprises: After receiving the third reset signal, performing a pre-discharge process according to the first time pulse signal group to obtain a first pre-discharge voltage, and performing a pre-discharge process according to the second time pulse signal group to obtain a second pre-discharge voltage; After receiving the second interrupt trigger signal, the discharge process is continued based on the first pre-discharge voltage to obtain the first voltage, and the discharge process is continued based on the second pre-discharge voltage to obtain the second voltage; wherein the second interrupt trigger signal is a signal generated and sent when the pre-discharge operation is completed.

19. The time control method according to claim 18, characterized in that: The third reset signal is generated by following steps: In response to receiving the second reset instruction, generating a fourth reset signal; The third reset signal is generated according to the fourth reset signal and the second clock signal.

20. A non-transitory computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the steps of the method according to any one of claims 15 to 19 are implemented.

21. A computer program product, characterized in that The method comprises a computer program, which, when executed by a processor, implements the steps of the method according to any one of claims 15 to 19.

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