SST Driver decoding circuit capable of reducing power consumption

Abstract

The invention relates to the technical field of serial communication, in particular to an SST Driver decoding circuit capable of reducing power consumption, which is characterized in that a differential conduction branch is bridged between a P branch and an N branch; the differential conduction branch is used for controlling the P branch to be in single-side conduction when the input code is all 0; when the input codes are all 1, single-side conduction of the N branches is controlled; and when the input code is the middle bit code, controlling the P branch and the N branch not to be conducted. In order to solve the problem that in the prior art, an SST driving stage is large in power consumption, in the scheme, a differential conduction circuit is introduced between a P branch and an N branch of the SST driving stage and is used for controlling the conduction condition of a differential output end, when a specific decoding mode occurs and P branch or N branch output is not needed, an output channel is controlled through the differential conduction circuit, and therefore the power consumption of the SST driving stage is reduced. Therefore, the circuit realizes a specific conduction mode, and the current maximum value is reduced to half of the current maximum value in a traditional decoding mode, so that the power consumption is reduced.

Description

Technical Field

[0001] The invention relates to the technical field of serial communication, and in particular to an SST Driver decoding circuit with reduced power consumption. Background Art

[0002] SST Driver decoding circuit, also known as source series terminated (SST), is a voltage mode driver stage structure, which is widely used in the transmitter of serial communication circuit. Serial communication is a time division multiplexing (TDM) and point-to-point (P2P) high-speed serial communication technology. Among them, the transmitter converts the low-speed parallel signal into a high-speed serial signal, and then sends it out after encoding, emphasis and other operations. In the process of converting the parallel signal into a serial signal, a decoding circuit is required. Usually, the decoding circuit includes two parts: the pre-stage driver and the driver stage. The pre-stage driver receives the parallel signal, reads the parallel signal in sequence, and outputs it to the rear driver stage for transmission. In the process of transmission, considering the higher frequency of the serial signal, it is often sent through a differential circuit to improve the anti-interference performance. Common driver stages include CML drivers and SST drivers.

[0003] In the prior art, the SST driving circuit is usually composed of pull-up and pull-down branches, which are composed of PMOS and NMOS switch transistors and a series terminal resistor R. Each branch is connected in series with a series terminal resistor to match the impedance of the transmission line. When the driving voltage is high, the P tube is turned on and the pull-up part works. When the driving voltage is low, the N tube is turned on and the pull-down part works, thereby completing the signal transmission.

[0004] In the above structure, the SST control code is 10 bits, and the decoding process is that when the code changes from 10'b0000000000 to 10'b1111111111, the P branch and the N branch are turned on at the same time, increasing and decreasing, and the output amplitude is obtained when the impedance matching is met. The case with the lowest power consumption corresponds to the code being 10'b0000000000 / 10'b1111111111, at which time the output amplitude is +-VDD / 2, and at this time, all the P branches are turned on or all the N branches are turned on. In the case of known impedance matching, the resistance from the power supply to the low side is 4*RL, so the current is VDD / 4RL. When the code is 10'b1000000000, the output amplitude is 0, that is, outp=outn=VDD / 2. For the P branch, since the code is half, the resistance from the power supply to outp of the P branch is 2RL, and the resistance from outp to ground is 2RL. The resistance from the power supply to outn of the N branch is 2RL, and the resistance from outn to ground is 2RL. Therefore, the current of the P branch is VDD / 2 / 2RL. Similarly, the current of the N branch is VDD / 2 / 2RL, so the total current is VDD / 4RL.

[0005] Based on the above process, it is easy to conclude that the SST driving circuit in the prior art has a problem of high circuit power consumption due to a large conduction current during operation. Summary of the invention

[0006] In view of the above problems existing in the prior art, a SST Driver decoding circuit with reduced power consumption is now provided.

[0007] The specific technical solutions are as follows:

[0008] A power-saving SST Driver decoding circuit includes a P branch and an N branch;

[0009] A differential conduction branch is connected between the P branch and the N branch;

[0010] The differential conduction branch is used for:

[0011] When the input code is all 0, the P branch is controlled to be turned on on one side;

[0012] When the input code is all 1, the N branch is controlled to be turned on on one side;

[0013] When the input code is an intermediate bit code, both the P branch and the N branch are controlled to be non-conductive.

[0014] On the other hand, the P branch includes a P branch output terminal and a first output impedance matching resistor;

[0015] The output end of the P branch is connected to the first end of the first output impedance matching resistor, and the second end of the first output impedance matching resistor is connected to the first differential output end of the SST Driver decoding circuit;

[0016] The N branch includes an N branch output terminal and a second output impedance matching resistor;

[0017] The N-branch output end is connected to the first end of the second output impedance matching resistor, and the second end of the second output impedance matching resistor is connected to the second differential output end of the SST Driver decoding circuit.

[0018] On the other hand, the differential conduction branch includes a first branch and a second branch;

[0019] The first end of the first branch is connected to the output end of the P branch;

[0020] The second end of the first branch is connected to the output end of the N branch;

[0021] The first end of the second branch is connected to the output end of the N branch;

[0022] The second end of the second branch is connected to the output end of the P branch;

[0023] When the input code is all 0, the first branch is turned on and the second branch is turned off;

[0024] When the input code is all 1s, the first branch is closed and the second branch is turned on.

[0025] On the other hand, when the input code is a 10-bit code, the intermediate bit code is 1000000000;

[0026] When the input code is the intermediate bit code, all of the differential conduction branches are turned on.

[0027] On the other hand, the P branch includes:

[0028] A first PMOS tube, wherein an input end of the first PMOS tube is connected to a power supply circuit;

[0029] The gate of the first PMOS tube is connected to the pre-stage driver;

[0030] A first NMOS tube, wherein an input end of the first NMOS tube is connected to an output end of the first PMOS tube;

[0031] The input end of the first NMOS tube is also connected to the output end of the P branch;

[0032] The gate of the first NMOS tube is connected to the pre-stage driver;

[0033] The output end of the first NMOS tube is grounded.

[0034] On the other hand, the N branch includes:

[0035] A second NMOS tube, wherein an output end of the second NMOS tube is grounded;

[0036] The gate of the second NMOS tube is connected to the pre-stage driver;

[0037] a second PMOS tube, wherein an output end of the second PMOS tube is connected to an input end of the second NMOS tube;

[0038] The output end of the second PMOS tube is also connected to the output end of the N branch;

[0039] The gate of the second PMOS tube is connected to the pre-stage driver;

[0040] The input end of the second PMOS tube is connected to the power supply circuit.

[0041] On the other hand, the first branch comprises:

[0042] a third NMOS transistor, wherein an input end of the third NMOS transistor is connected to a first end of the first branch;

[0043] The gate of the third NMOS tube is connected to an external control circuit;

[0044] a fourth NMOS tube, wherein an input end of the fourth NMOS tube is connected to an output end of the third NMOS tube;

[0045] The gate of the fourth NMOS tube is connected to the control circuit;

[0046] The output end of the fourth NMOS tube is connected to the second end of the first branch.

[0047] On the other hand, the second branch comprises:

[0048] a third PMOS tube, wherein an input end of the third PMOS tube is connected to a first end of the first branch;

[0049] The gate of the third PMOS tube is connected to an external control circuit;

[0050] a fourth PMOS tube, wherein an input end of the fourth PMOS tube is connected to an output end of the third PMOS tube;

[0051] The gate of the fourth PMOS tube is connected to the control circuit;

[0052] The output end of the fourth PMOS tube is connected to the second end of the first branch.

[0053] On the other hand, the SST Driver decoding circuit includes a plurality of slice units;

[0054] Each of the slice units includes a group of the P branches, the N branches and the differential conduction branches.

[0055] The above technical solution has the following advantages or beneficial effects:

[0056] In order to solve the problem of high power consumption of the SST driving stage in the prior art, in this solution, a differential conduction circuit is introduced between the P branch and the N branch of the SST driving stage to control the conduction status of the differential output end. When a specific decoding method occurs so that the P branch or N branch output is not required, the output channel is controlled by the differential conduction circuit to enable the circuit to achieve a specific conduction method and reduce the maximum current to half of the maximum current under the traditional decoding method, thereby reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The embodiments of the present invention will be described more fully with reference to the attached drawings, which are provided for illustration and description only and are not intended to limit the scope of the present invention.

[0058] Figure 1 It is an overall schematic diagram of an embodiment of the present invention;

[0059] Figure 2 It is a code-current comparison diagram of the SST driver in the prior art;

[0060] Figure 3 This is a code-current comparison diagram of an embodiment of the present invention. DETAILED DESCRIPTION

[0061] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0062] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0063] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0064] The present invention comprises:

[0065] A power-saving SST Driver decoding circuit includes a P branch 1 and an N branch 2;

[0066] A differential conduction branch 3 is connected between the P branch 1 and the N branch 2;

[0067] The differential conduction branch 3 is used to control the P branch 1 or the N branch 2 to be unilaterally conducted when the corresponding decoding mode is triggered.

[0068] Specifically, in response to the problem of high power consumption of the SST driving stage in the prior art, in this solution, a differential conduction circuit is introduced between the P branch and the N branch of the SST driving stage to control the conduction status of the differential output end. When a specific decoding method occurs so that the P branch or N branch output is not required, the output channel is controlled by the differential conduction circuit to make the circuit only single-sided, thereby reducing the maximum current to half of the maximum current under the traditional decoding method, thereby reducing power consumption.

[0069] Specifically, taking a 10-bit SST decoder as an example, the 10-bit SST decoder includes multiple parallel slice units, which are used for signals on multiple bits. Each slice unit includes a pair of P branches and N branches. The P branch is used to generate a pull-up signal, and the N branch is used to generate a pull-down signal.

[0070] The P branch is implemented by a PMOS tube, and the N branch is implemented by an NMOS tube. The implementation principle is determined based on the triggering characteristics of the PMOS tube and the NMOS tube for the rising edge and the falling edge of the signal.

[0071] Correspondingly, the control signal of the decoder is also 10 bits, which is used to control the conduction status of the branches in each slice unit.

[0072] Generally speaking, the first 5 bits and the last 5 bits are decoded in different ways. For example, in a typical decoder, the first 5 bits are decoded using a thermometer method, while the last 5 bits are decoded using a binary method.

[0073] The decoding process is that when the code changes from 10'b0000000000 to 10'b1111111111, the P branch and the N branch are turned on and off simultaneously in increasing and decreasing order, and the output amplitude is obtained when the impedance matching is satisfied.

[0074] In particular, for the case of multiple slice units connected in parallel, the impedance of a single slice unit connected in series is N*R, and the total impedance of N slice units connected in parallel is R.

[0075] The lowest power consumption condition is when all 10 bits are 0 or 1, that is, code = 10'b0000000000 or code = 10'b1111111111. At this time, the output amplitude of the driver is +-VDD / 2, and all P branches are turned on or all N branches are turned on.

[0076] In the case of known impedance matching, the resistance from the power supply to the low voltage is 4*RL. At this time, it can be calculated that the lowest current point is VDD / 4RL.

[0077] When the code is 10'b1000000000, the output amplitude is 0, that is, outp=outn=VDD / 2.

[0078] For the P branch, since the code is half, the resistance from the power supply to outp of the P branch is 2RL, and the resistance from outp to ground is 2RL. The resistance from the power supply to outn of the N branch is 2RL, and the resistance from outn to ground is 2RL.

[0079] Therefore, the P branch current is VDD / 2 / 2RL, and similarly the N branch current is VDD / 2 / 2RL, so the maximum total current is VDD / 2RL.

[0080] Based on the above derivation process, we can get Figure 2 From the code-current comparison diagram shown, it can be seen that in the process of code=10'b0000000000 to 10'b1000000000, the current gradually increases from VDD / 4RL to VDD / 2RL.

[0081] In the process of flipping bit by bit from 10'b1000000000 to 10'b1111111111, the current gradually decreases from VDD / 2RL to VDD / 4RL.

[0082] Based on the above coding-current comparison diagram, it can be seen that the power consumption is relatively high during the overall decoding process. To address this problem, the inventors have proposed that the P branch 1 and the N branch 2 can be controlled to conduct under specific working conditions through the differential conduction branch 3, thereby reducing power consumption.

[0083] Specifically, when the decoding mode is all 0, that is, Din[9]=1'b0, by controlling the conduction direction of the differential conduction branch 3, only the P branch 1 is turned on; when the decoding mode is all 1, that is, Din[9]=1'b1, by controlling the conduction direction of the differential conduction branch 3, only the N branch 2 is turned on.

[0084] It can be seen that when the code is 10'b0000000000, the current is the largest. At this time, only P branch 1 is fully turned on, so the resistance between the power supply and the ground is 4RL, and the current is VDD / 4RL;

[0085] When the code is 10'b1000000000, the P branch 1 is completely closed, the differential conduction branch 3 is turned on, and the N branch 2 is also turned off. At this time, the output amplitude is 0, no current is generated between the differential paths, and the P / N branches are all closed, and the obtained current is 0.

[0086] It should be noted that since the P branch 1 and the N branch 2 are all closed, the impedance of the two branches will change. In order to match the impedance with the output line impedance, it is necessary to generate a matching impedance through the differential conduction branch 3.

[0087] Correspondingly, when the code is 10'b1111111111, the P branch 1 is completely closed, the N branch 2 is turned on, the resistance between the power supply and the ground is 4RL, and the current is VDD / 4RL;

[0088] Based on the above analysis results, the code-current comparison diagram is drawn as follows Figure 3 shown.

[0089] exist Figure 3 The maximum current occurs when the code at both ends is 10'b0000000000 or 10'b1111111111. At this time, the maximum current is VDD / 4RL.

[0090] When the code is flipped bit by bit from 10'b0000000000 to 10'b1000000000, the current value decreases in the opposite direction and drops to 0 when it reaches 10'b0000000000.

[0091] Correspondingly, when the code flips bit by bit from 10'b1000000000 to 10'b1111111111, the current value increases and reaches the maximum value VDD / 4RL when reaching 10'b11111111111.

[0092] In this decoding mode, when the code is completely scanned, the maximum current is half of the maximum current in the above decoding mode, and the corresponding overall power consumption should be half, thereby reducing power consumption. Accordingly, the power consumption of the above circuit will also be reduced during normal operation.

[0093] In one embodiment, the P branch 1 includes a P branch output terminal and a first output impedance matching resistor R1;

[0094] The output end of the P branch is connected to the first end of the first output impedance matching resistor R1, and the second end of the first output impedance matching resistor R1 is connected to the first differential output end TXP;

[0095] The N branch includes an N branch output terminal and a second output impedance matching resistor R2;

[0096] The output end of the N branch is connected to the first end of the second output impedance matching resistor R2, and the second end of the second output impedance matching resistor R2 is connected to the second differential output end TXN;

[0097] A third resistor R3 is connected in series between the first differential output terminal TXP and the second differential output terminal TXN.

[0098] The differential conduction branch 3 includes a first branch 31 and a second branch 32;

[0099] The first end of the first branch 31 is connected to the output end of the P branch;

[0100] The second end of the first branch 31 is connected to the output end of the N branch;

[0101] A first end of the second branch 32 is connected to the output end of the N branch;

[0102] The second end of the second branch 32 is connected to the output end of the P branch;

[0103] When the input code is all 0, the first branch 31 is turned on and the second branch 32 is turned off;

[0104] When the input code is all 1s, the first branch 31 is closed and the second branch 32 is turned on.

[0105] Specifically, considering the problem of high power consumption of the existing SST driving stage, the inventor proposed a solution of adding a group of differential conduction branches 3 in P branch 1 and N branch 2 to control the conduction status of specific branches, such as P branch 1 and N branch 2, during the decoding process, thereby reducing the current.

[0106] However, in the process of controlling the SST driver stage, it is usually necessary to pay attention to the performance of two parts, mainly including: the circuit needs to achieve sufficient output voltage difference swing, and the output line is impedance matched. Among them, the output voltage difference swing is mainly determined by the ratio between the third resistor R3 and the first output impedance matching resistor R1 and the second output impedance matching resistor R2.

[0107] The impedance matching process of the output line is related to the P branch 1 and the N branch 2. When the P branch 1 and / or the N branch 2 are gradually turned off, impedance matching problems are likely to occur.

[0108] To address this problem, in this solution, the differential conduction branch 3 is set at the node between the output end of the P branch and the first output impedance matching resistor R1, and between the output end of the N branch and the second output impedance matching resistor R2, and bridges the lines at both ends respectively.

[0109] When the P branch 1 and the N branch 2 are both turned off, the first branch 31 and the second branch 32 of the differential conduction branch 3 are both turned on, thereby forming a loop between the third resistor R3 and the first output impedance matching resistor R1 and the second output impedance matching resistor R2, so as to meet the impedance matching requirements.

[0110] In the implementation process, in order to realize the above circuit, the P branch 1 includes:

[0111] A first PMOS transistor P1, an input end of the first PMOS transistor P1 is connected to a power supply circuit VDD;

[0112] The gate of the first PMOS tube P1 is connected to the pre-stage driver;

[0113] A first NMOS transistor N1, wherein an input end of the first NMOS transistor N1 is connected to an output end of the first PMOS transistor P1;

[0114] The input end of the first NMOS tube N1 is also connected to the output end of the P branch;

[0115] The gate of the first NMOS tube N1 is connected to the pre-stage driver;

[0116] An output terminal of the first NMOS transistor N1 is grounded.

[0117] N branch 2 includes:

[0118] A second NMOS transistor N2, an output end of the second NMOS transistor N2 is grounded;

[0119] The gate of the second NMOS tube N2 is connected to the pre-stage driver;

[0120] A second PMOS tube P2, wherein the output end of the second PMOS tube P2 is connected to the input end of the second NMOS tube;

[0121] The output end of the second PMOS tube P2 is also connected to the output end of the N branch 2;

[0122] The gate of the second PMOS tube P2 is connected to the pre-stage driver;

[0123] An input end of the second PMOS tube P2 is connected to a power supply circuit VDD.

[0124] The first branch 31 comprises:

[0125] A third NMOS transistor N3, wherein an input end of the third NMOS transistor N3 is connected to a first end of the first branch;

[0126] The gate of the third NMOS tube N3 is connected to an external control circuit;

[0127] a fourth NMOS transistor N4, wherein an input end of the fourth NMOS transistor N4 is connected to an output end of the third NMOS transistor N3;

[0128] The gate of the fourth NMOS tube N4 is connected to the control circuit;

[0129] The output end of the fourth NMOS transistor N4 is connected to the second end of the first branch 31 .

[0130] The second branch 32 comprises:

[0131] A third PMOS transistor P3, wherein an input end of the third PMOS transistor P3 is connected to a first end of the first branch 31;

[0132] The gate of the third PMOS tube P3 is connected to an external control circuit;

[0133] A fourth PMOS tube P4, wherein an input end of the fourth PMOS tube P4 is connected to an output end of the third PMOS tube P3;

[0134] The gate of the fourth PMOS tube P4 is connected to the control circuit;

[0135] The output end of the fourth PMOS transistor P4 is connected to the second end of the first branch 31 .

[0136] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A SST Driver decoding circuit with reduced power consumption, characterized in that: Including P branch and N branch; A differential conduction branch is connected between the P branch and the N branch; The differential conduction branch is used for: When the input code is all 0, the P branch is controlled to be turned on on one side; When the input code is all 1, the N branch is controlled to be turned on on one side; When the input code is an intermediate bit code, both the P branch and the N branch are controlled to be non-conductive.

2. The SST Driver decoding circuit according to claim 1, characterized in that: The P branch includes a P branch output end and a first output impedance matching resistor; The output end of the P branch is connected to the first end of the first output impedance matching resistor, and the second end of the first output impedance matching resistor is connected to the first differential output end of the SST Driver decoding circuit; The N branch includes an N branch output terminal and a second output impedance matching resistor; The N-branch output end is connected to the first end of the second output impedance matching resistor, and the second end of the second output impedance matching resistor is connected to the second differential output end of the SST Driver decoding circuit.

3. The SST Driver decoding circuit according to claim 2, characterized in that: The differential conduction branch includes a first branch and a second branch; The first end of the first branch is connected to the output end of the P branch; The second end of the first branch is connected to the output end of the N branch; The first end of the second branch is connected to the output end of the N branch; The second end of the second branch is connected to the output end of the P branch; When the input code is all 0, the first branch is turned on and the second branch is turned off; When the input code is all 1s, the first branch is closed and the second branch is turned on.

4. The SST Driver decoding circuit according to claim 1, characterized in that: When the input code is a 10-bit code, the intermediate bit code is 1000000000; When the input code is the intermediate bit code, all of the differential conduction branches are turned on.

5. The SST Driver decoding circuit according to claim 2, characterized in that: The P branch includes: A first PMOS tube, wherein an input end of the first PMOS tube is connected to a power supply circuit; The gate of the first PMOS tube is connected to the pre-stage driver; A first NMOS tube, wherein an input end of the first NMOS tube is connected to an output end of the first PMOS tube; The input end of the first NMOS tube is also connected to the output end of the P branch; The gate of the first NMOS tube is connected to the pre-stage driver; The output end of the first NMOS tube is grounded.

6. The SST Driver decoding circuit according to claim 2, characterized in that: The N branches include: A second NMOS tube, wherein an output end of the second NMOS tube is grounded; The gate of the second NMOS tube is connected to the pre-stage driver; a second PMOS tube, wherein an output end of the second PMOS tube is connected to an input end of the second NMOS tube; The output end of the second PMOS tube is also connected to the output end of the N branch; The gate of the second PMOS tube is connected to the pre-stage driver; The input end of the second PMOS tube is connected to the power supply circuit.

7. The SST Driver decoding circuit according to claim 3, characterized in that: The first branch comprises: a third NMOS transistor, wherein an input end of the third NMOS transistor is connected to a first end of the first branch; The gate of the third NMOS tube is connected to an external control circuit; a fourth NMOS tube, wherein an input end of the fourth NMOS tube is connected to an output end of the third NMOS tube; The gate of the fourth NMOS tube is connected to the control circuit; The output end of the fourth NMOS tube is connected to the second end of the first branch.

8. The SST Driver decoding circuit according to claim 3, characterized in that: The second branch comprises: a third PMOS tube, wherein an input end of the third PMOS tube is connected to a first end of the first branch; The gate of the third PMOS tube is connected to an external control circuit; a fourth PMOS tube, wherein an input end of the fourth PMOS tube is connected to an output end of the third PMOS tube; The gate of the fourth PMOS tube is connected to the control circuit; The output end of the fourth PMOS tube is connected to the second end of the first branch.

9. The SST Driver decoding circuit according to claim 1, characterized in that: The SST Driver decoding circuit includes a plurality of slice units; Each of the slice units includes a group of the P branches, the N branches and the differential conduction branches.

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