Comparator offset voltage error correction structure

Abstract

The invention discloses a comparator offset voltage error correction structure, which comprises a short circuit unit, an accumulator, a counter, a digital correction module and an error compensation unit, and is characterized in that the digital correction module is used for adjusting an output level value according to an output value of the accumulator when a counting value of the counter reaches a preset counting threshold value; and the error compensation unit is used for generating a corresponding compensation signal according to the level value output by the digital correction module to compensate the offset error of the comparator. According to the invention, the polarity of the offset voltage is judged according to the number of high levels, the offset voltage of the comparator is corrected, and the offset voltage of the comparator can be always kept within 1 / 4 LSB, so that systematic errors caused by the offset of the comparator are effectively suppressed.

Description

Technical Field

[0001] The invention belongs to the field of comparator error correction, and in particular relates to a comparator offset voltage error correction structure. Background Art

[0002] With the development of high-precision ADC, the systematic offset caused by the mismatch of transistor size in the comparator has become a problem that cannot be ignored. For the comparator, if the offset error introduced is greater than 1 / 2LSB, it will cause serious comparison errors, and even eventually affect the accuracy and output results of the entire ADC. Therefore, it is necessary to use error correction to complete the offset voltage correction of the comparator. This design is based on the accumulator and counter, combined with the matching DAC module, to carry out a design of a background correction algorithm for the offset voltage error of the comparator. Summary of the invention

[0003] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a comparator offset voltage error correction structure.

[0004] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0005] A comparator offset voltage error correction structure, comprising:

[0006] A short-circuiting unit, used for short-circuiting the input terminal of the comparator when calibrating the comparator;

[0007] An accumulator, used for accumulating the number of high levels in the output signal of the comparator;

[0008] A counter, used for counting the output signal of the comparator;

[0009] A digital correction module, used for adjusting the output level value according to the output value of the accumulator when the count value of the counter reaches a preset count threshold; and

[0010] The error compensation unit is used to generate a corresponding compensation signal according to the level value output by the digital correction module to compensate for the offset error of the comparator.

[0011] Furthermore, the digital correction module includes

[0012] A judgment unit, used for comparing the output value of the accumulator with a preset high level value range when the count value of the counter reaches a preset count threshold, and outputting a corresponding adjustment signal to the parameter adjustment unit according to the comparison result;

[0013] a parameter adjustment unit, configured to adjust the level parameter accordingly according to the received adjustment signal and then output the adjusted level parameter to the control code generation unit; and

[0014] The correction level generating unit is used to output a corresponding level value to the error compensation unit according to the level parameter.

[0015] Further, when the output value of the accumulator is higher than the upper limit of the preset high-level numerical range, the judgment unit outputs a first adjustment signal; when the output value of the accumulator is lower than the lower limit of the preset high-level numerical range, the judgment unit outputs a second adjustment signal; when the output value of the accumulator is within the preset high-level numerical range, the judgment unit outputs a third adjustment signal;

[0016] When receiving the first adjustment signal, the parameter adjustment unit steps the level parameter downward and outputs it to the control code generation unit; when receiving the second adjustment signal, the parameter adjustment unit steps the level parameter upward and outputs it to the control code generation unit.

[0017] Furthermore, the correction level generating unit includes

[0018] A control code generating unit, used to generate a corresponding control code to the correction level generating unit according to the level parameter;

[0019] A DAC unit, used to generate a multi-level equal-difference level signal; and

[0020] The level selection unit is used to select a level signal of a corresponding level from the level signal generated by the DAC unit according to the control code and send it to the error compensation unit.

[0021] Further, the DAC unit includes a comparison amplifier A1, a comparison amplifier A2, a PMOS tube M21, an NMOS tube M22, a capacitor C1, a capacitor C2, a resistor R35, a resistor R36, a resistor R37, a resistor R38 and N adjustment resistors with the same resistance value; the non-inverting input terminal of the comparison amplifier A1 is used to connect the positive power supply voltage V+, the inverting input terminal of the comparison amplifier A1 is electrically connected to its output terminal through the capacitor C1, and the inverting input terminal of the comparison amplifier A1 is also grounded through the resistor R36;

[0022] The output terminal of the comparison amplifier A1 is electrically connected to the gate of the PMOS tube M21, the source of the PMOS tube M21 is connected to the power supply voltage VDD, and the drain of the PMOS tube M21 is electrically connected to the inverting input terminal of the comparison amplifier A1 through the resistor R35;

[0023] The drain of the PMOS tube M21 is also electrically connected to the drain of the NMOS tube M22 through N series-connected adjustment resistors, and the connection ends of every two adjacent adjustment resistors respectively output a first-level equal-difference level signal to the level selection unit;

[0024] The drain of the NMOS tube M22 is electrically connected to the in-phase input terminal of the comparison amplifier A2 through the resistor R37; the source of the NMOS tube M22 is grounded, and the gate of the NMOS tube M22 is electrically connected to the output terminal of the comparison amplifier A2;

[0025] The non-inverting input terminal of the comparison amplifier A2 is electrically connected to its output terminal via a capacitor C2, and the non-inverting input terminal of the comparison amplifier A2 is also grounded via a resistor R38; the inverting input terminal of the comparison amplifier A2 is used to connect to a negative power supply voltage V-.

[0026] Furthermore, the voltage difference between the positive power supply voltage V+ and the negative power supply voltage V- is 200mV.

[0027] Furthermore, the level value output by the digital correction module includes a first level value REF_T1 and a second level value REF_T2, the first level value REF_T1 is obtained according to the level parameter, and the second level value REF_T2 is a fixed value; the error compensation unit generates corresponding current signals according to the first level value REF_T1 and the second level value REF_T2 to adjust the charging and discharging speed of the comparator, thereby compensating for the offset error of the comparator.

[0028] Further, the error compensation unit includes an NMOS tube NM7 and an NMOS tube NM8, the gate of the NMOS tube NM7 is connected to a first level value REF_T1, the source of the NMOS tube NM7 is grounded, and the drain of the NMOS tube NM7 is connected to a comparator; the gate of the NMOS tube NM8 is connected to a second level value REF_T2, the source of the NMOS tube NM8 is grounded, and the drain of the NMOS tube NM8 is connected to the comparator.

[0029] Further, the comparator includes an inverter D1, an inverter D2, a PMOS tube PM1, a PMOS tube PM2, a PMOS tube PM3, a PMOS tube PM4, an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3, an NMOS tube NM4, an NMOS tube NM5, an NMOS tube NM6, an NMOS tube NM9 and an NMOS tube NM10;

[0030] The sources of the PMOS tubes PM1, PM2, PM3 and PM4 are all connected to the power supply voltage VDD, the gate of the PMOS tube PM1 is electrically connected to the gate of the NMOS tube NM1 and the drain of the PMOS tube PM2, the drain of the PMOS tube PM1 is electrically connected to the input end of the inverter D1 and the drain of the NMOS tube NM1, and the output end of the inverter D1 serves as the first output end of the comparator;

[0031] The gate of the PMOS tube PM2 is electrically connected to the gate of the NMOS tube NM2 and the drain of the PMOS tube PM1 respectively, the drain of the PMOS tube PM2 is electrically connected to the input end of the inverter D2 and the drain of the NMOS tube NM2 respectively, and the output end of the inverter D2 serves as the second output end of the comparator;

[0032] The gates of the PMOS transistor PM3 and the PMOS transistor PM4 are both connected to the clock signal CLK, the drain of the PMOS transistor PM3 is electrically connected to the source of the NMOS transistor NM1, the drain of the NMOS transistor NM3, the drain of the NMOS transistor NM5, and the drain of the NMOS transistor NM8; the drain of the PMOS transistor PM4 is electrically connected to the source of the NMOS transistor NM2, the drain of the NMOS transistor NM4, the drain of the NMOS transistor NM6, and the drain of the NMOS transistor NM7;

[0033] The gate of the NMOS tube NM3 is connected to the input signal Vi p, and the gate of the NMOS tube NM4 is connected to the reference voltage signal V REF14 The sources of the NMOS tubes NM3 and NMOS tubes NM4 are electrically connected to the drain of the NMOS tube NM9, the gate of the NMOS tube NM9 is connected to the clock signal CLK, and the source of the NMOS tube NM9 is grounded;

[0034] The gate of the NMOS tube NM5 is connected to the reference voltage signal V REF0 The gate of the NMOS tube NM6 is connected to the input signal Vin; the sources of the NMOS tubes NM5 and NMOS tubes NM6 are electrically connected to the drain of the NMOS tube NM10, the gate of the NMOS tube NM10 is connected to the clock signal CLK, and the source of the NMOS tube NM10 is grounded.

[0035] Further, the short-circuit unit includes a PMOS tube PM5, a PMOS tube PM6, an NMOS tube NM11 and an NMOS tube NM12, the gate of the NMOS tube NM3 is also electrically connected to the drain of the PMOS tube PM5 and the source of the NMOS tube NM11, respectively, and the gate of the NMOS tube NM4 is also electrically connected to the source of the PMOS tube PM5 and the drain of the NMOS tube NM11, respectively; the gate of the PMOS tube PM5 is connected to the clock signal CLK_P, and the gate of the NMOS tube NM11 is connected to the clock signal CLK_N; the gate of the NMOS tube NM5 is also electrically connected to the drain of the PMOS tube PM6 and the source of the NMOS tube NM12, respectively, and the gate of the NMOS tube NM6 is also electrically connected to the source of the PMOS tube PM6 and the drain of the NMOS tube NM12, respectively; the gate of the PMOS tube PM6 is connected to the clock signal CLK_P, and the gate of the NMOS tube NM12 is connected to the clock signal CLK_N.

[0036] In the present invention, the polarity of the offset voltage is judged by accumulating the number of high and low levels, and the offset voltage of the comparator is corrected by selecting the gate voltage of the correction tube to control the current of the correction tube. The offset voltage of the comparator can be kept within 1 / 4LSB at all times, and the correction range can be adjusted by adjusting the values ​​of the positive power supply voltage V+ and the negative power supply voltage V- in the DAC unit and the number of adjustment resistors, thereby effectively suppressing the systematic error caused by the comparator offset. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0038] Figure 1 FIG. 4 is a structural block diagram of an embodiment of a comparator offset voltage error correction structure of the present invention.

[0039] Figure 2 is the circuit diagram of the DAC unit.

[0040] Figure 3 FIG. 4 is a code value diagram of a control code generated by correction in an example.

[0041] Figure 4 Schematic diagram of the comparator, short-circuit unit and error compensation unit.

[0042] Figure 5 Figure 2 is a simulation diagram of the comparator before digital correction.

[0043] Figure 6 Figure 2 is the simulation data of the comparator after digital correction. DETAILED DESCRIPTION

[0044] The following describes the implementation methods of the present invention through specific examples. The illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention. The following embodiments and features in the embodiments may be combined with each other without conflict.

[0045] See also Figure 1 , Figure 1 The present invention is a block diagram of an embodiment of a comparator offset voltage error correction structure. The comparator offset voltage error correction structure of this embodiment includes a short-circuit unit, an accumulator, a counter, a digital correction module and an error compensation unit. The short-circuit unit is used to short-circuit the input end of the comparator when calibrating the comparator. The accumulator is used to accumulate the number of high levels (i.e., signal "1") in the output signal of the comparator. The counter is used to count the output signal of the comparator. The digital correction module is used to adjust the output level value according to the output value of the accumulator when the count value of the counter reaches a preset count threshold (for example: 128 times). The error compensation unit is used to generate a corresponding compensation signal according to the level value output by the digital correction module to compensate for the offset error of the comparator.

[0046] Please continue reading Figure 1 , the digital correction module may include a judgment unit, a parameter adjustment unit, a parameter adjustment unit and a correction level generating unit. The judgment unit is used to compare the output value of the accumulator with the preset high-level numerical range when the count value of the counter reaches the preset count threshold, and output a corresponding adjustment signal to the parameter adjustment unit according to the comparison result. Specifically, when the output value of the accumulator is higher than the upper limit of the preset high-level numerical range, the judgment unit outputs a first adjustment signal; when the output value of the accumulator is lower than the lower limit of the preset high-level numerical range, the judgment unit outputs a second adjustment signal; when the output value of the accumulator is within the preset high-level numerical range, the judgment unit outputs a third adjustment signal. At this time, the counter and the accumulator are also restored to the initial state, waiting to start the next correction process. The high-level numerical range can be set according to the accuracy requirement. Specifically, when the accuracy requirement is high, the high-level numerical range can be set to a smaller range. For example, when the counting threshold is 128 times, the high-level numerical range can be set to 44 to 84. If the accuracy requirement is high, the high-level numerical range can be set to 56 to 72.

[0047] The parameter adjustment unit is used to adjust the level parameter accordingly according to the received adjustment signal and then output it to the control code generation unit. Specifically, when the parameter adjustment unit receives the first adjustment signal, the level parameter is stepped down and then output to the control code generation unit; when the parameter adjustment unit receives the second adjustment signal, the level parameter is stepped up and then output to the control code generation unit.

[0048] The correction level generating unit is used to output the corresponding level value to the error compensation unit according to the level parameter. Figure 2 The correction level generating unit may include a control code generating unit, a DAC unit and a level selecting unit. The control code generating unit is used to generate a corresponding control code to the correction level generating unit according to the level parameter. Figure 3 , is a code value diagram of the control code generated in an example, where the correction port signal is the level code value input by the correction tube, and the input signal B <0> The DAC unit is used to generate multi-level equal-difference level signals, and the level selection unit is used to select the level signal of the corresponding level from the level signal generated by the DAC unit according to the control code and send it to the error compensation unit.

[0049] Please continue reading Figure 2 In this embodiment, the DAC unit includes a comparison amplifier A1, a comparison amplifier A2, a PMOS tube M21, an NMOS tube M22, a capacitor C1, a capacitor C2, a resistor R35, a resistor R36, a resistor R37, a resistor R38 and N adjustment resistors with the same resistance. The comparison amplifier A1 and the comparison amplifier A2 are both LDO amplifiers; the PMOS tube M21 and the NMOS tube M22 are both large-size current tubes. In this embodiment, a total of 34 adjustment resistors are provided, namely, adjustment resistor R0, adjustment resistor R1, adjustment resistor R2, ..., adjustment resistor R32 and adjustment resistor R33.

[0050] The non-inverting input terminal of the comparison amplifier A1 is used to connect to the positive power supply voltage V+, the inverting input terminal of the comparison amplifier A1 is electrically connected to its output terminal through the capacitor C1, and the inverting input terminal of the comparison amplifier A1 is also grounded through the resistor R36.

[0051] The output end of the comparison amplifier A1 is electrically connected to the gate of the PMOS tube M21, the source of the PMOS tube M21 is connected to the power supply voltage VDD, and the drain of the PMOS tube M21 is electrically connected to the inverting input end of the comparison amplifier A1 through the resistor R35.

[0052] The drain of the PMOS tube M21 is also electrically connected to the drain of the NMOS tube M22 through 34 adjustment resistors connected in series. The connection ends of every two adjacent adjustment resistors output a first-level equal-difference level signal to the level selection unit, thereby forming V <0> 0~V <0> 32 has 33 levels of level signals. The specific voltage division can be controlled by adjusting the resistance value of the resistor R, thereby achieving the precision adjustment of the calibration. In this embodiment, the resistance value of a single resistor is preferably 10.69 ohms.

[0053] The drain of the NMOS tube M22 is electrically connected to the non-inverting input terminal of the comparison amplifier A2 through the resistor R37; the source of the NMOS tube M22 is grounded, and the gate of the NMOS tube M22 is electrically connected to the output terminal of the comparison amplifier A2.

[0054] The non-inverting input terminal of the comparison amplifier A2 is electrically connected to its output terminal via a capacitor C2, and the non-inverting input terminal of the comparison amplifier A2 is also grounded via a resistor R38; the inverting input terminal of the comparison amplifier A2 is used to connect a negative power supply voltage V-.

[0055] In this embodiment, the voltage difference between the positive power supply voltage V+ and the negative power supply voltage V- is 200mV, for example, V+=650mV, V-=450mV, so that each level of 6.25mV correction error voltage adjustment can be achieved, and the total adjustment range is plus or minus 100mV.

[0056] The level value output by the digital correction module includes a first level value REF_T1 and a second level value REF_T2. The first level value REF_T1 is a value selected by the level selection unit from V <0> 0~V <0> 32, the second level value REF_T2 is a fixed value and does not change with the level parameter; the level selection unit generally selects the middle level signal as the second level value REF_T2, such as the second level value REF_T2 in this embodiment is V <0> 16. Of course, the initial value of the first level value REF_T1 can also be V <0> 16, and then adjust to the previous level signal or the next level signal according to the calibration result.

[0057] The error compensation unit generates corresponding current signals according to the first level value REF_T1 and the second level value REF_T2 to adjust the charging and discharging speed of the comparator, thereby compensating for the offset error of the comparator. Figure 4In this embodiment, the error compensation unit includes a pair of correction tubes, namely, NMOS tube NM7 and NMOS tube NM8, the gate of the NMOS tube NM7 is connected to the first level value REF_T1, the source of the NMOS tube NM7 is grounded, and the drain of the NMOS tube NM7 is connected to the comparator. The gate of the NMOS tube NM8 is connected to the second level value REF_T2, the source of the NMOS tube NM8 is grounded, and the drain of the NMOS tube NM8 is connected to the comparator.

[0058] Please continue reading Figure 4 The comparator includes an inverter D1, an inverter D2, a PMOS tube PM1, a PMOS tube PM2, a PMOS tube PM3, a PMOS tube PM4, an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3, an NMOS tube NM4, an NMOS tube NM5, an NMOS tube NM6, an NMOS tube NM9 and an NMOS tube NM10. Among them, the NMOS tube NM3, the NMOS tube NM4, the NMOS tube NM5 and the NMOS tube NM6 are input pairs, and the inverter D1 and the inverter D2 are output shaping inverters.

[0059] Specifically, the sources of the PMOS tube PM1, the PMOS tube PM2, the PMOS tube PM3 and the PMOS tube PM4 are all connected to the power supply voltage VDD, the gate of the PMOS tube PM1 is electrically connected to the gate of the NMOS tube NM1 and the drain of the PMOS tube PM2, the drain of the PMOS tube PM1 is electrically connected to the input end of the inverter D1 and the drain of the NMOS tube NM1, and the output end of the inverter D1 serves as the first output end of the comparator.

[0060] The gate of the PMOS tube PM2 is electrically connected to the gate of the NMOS tube NM2 and the drain of the PMOS tube PM1 respectively, the drain of the PMOS tube PM2 is electrically connected to the input end of the inverter D2 and the drain of the NMOS tube NM2 respectively, and the output end of the inverter D2 serves as the second output end of the comparator.

[0061] The gates of the PMOS transistor PM3 and the PMOS transistor PM4 are both connected to the clock signal CLK, and the drain of the PMOS transistor PM3 is electrically connected to the source of the NMOS transistor NM1, the drain of the NMOS transistor NM3, the drain of the NMOS transistor NM5, and the drain of the NMOS transistor NM8. The drain of the PMOS transistor PM4 is electrically connected to the source of the NMOS transistor NM2, the drain of the NMOS transistor NM4, the drain of the NMOS transistor NM6, and the drain of the NMOS transistor NM7.

[0062] The gate of the NMOS tube NM3 is connected to the input signal Vi p, and the gate of the NMOS tube NM4 is connected to the reference voltage signal VREF14 The sources of the NMOS tubes NM3 and NMOS tubes NM4 are electrically connected to the drain of the NMOS tube NM9, the gate of the NMOS tube NM9 is connected to the clock signal CLK, and the source of the NMOS tube NM9 is grounded.

[0063] The gate of the NMOS tube NM5 is connected to the reference voltage signal V REF0 The gate of the NMOS tube NM6 is connected to the input signal Vin; the sources of the NMOS tubes NM5 and NMOS tubes NM6 are electrically connected to the drain of the NMOS tube NM10, the gate of the NMOS tube NM10 is connected to the clock signal CLK, and the source of the NMOS tube NM10 is grounded.

[0064] Please continue reading Figure 4 The short-circuit unit includes a PMOS tube PM5, a PMOS tube PM6, an NMOS tube NM11 and an NMOS tube NM12. The PMOS tube PM5, the PMOS tube PM6, the NMOS tube NM11 and the NMOS tube NM12 constitute a switch structure for controlling the input pair of tubes to be short-circuited. The gate of the NMOS tube NM3 is also electrically connected to the drain of the PMOS tube PM5 and the source of the NMOS tube NM11, respectively; the gate of the NMOS tube NM4 is also electrically connected to the source of the PMOS tube PM5 and the drain of the NMOS tube NM11, respectively; the gate of the PMOS tube PM5 is connected to the clock signal CLK_P, and the gate of the NMOS tube NM11 is connected to the clock signal CLK_N; the gate of the NMOS tube NM5 is also electrically connected to the drain of the PMOS tube PM6 and the source of the NMOS tube NM12, respectively; the gate of the NMOS tube NM6 is also electrically connected to the source of the PMOS tube PM6 and the drain of the NMOS tube NM12, respectively; the gate of the PMOS tube PM6 is connected to the clock signal CLK_P, and the gate of the NMOS tube NM12 is connected to the clock signal CLK_N. The clock signal CLK_P and the clock signal CLK_N are used to control the short-circuiting of the input terminal of the comparator during calibration.

[0065] The working principle of this embodiment is as follows:

[0066] See also Figures 1 to 4 Taking the counting threshold as 128 and the high level value range as 56 to 72 as an example, when the calibration starts, the clock signal CLK_P and the clock signal CLK_N short-circuit the input pair of the comparator, and the counter counts the output signal of the comparator. At the same time, the accumulator accumulates the number of high levels (i.e. "1") in the output signal of the comparator.

[0067] When the count value of the counter reaches 128, the judgment unit compares the output value of the accumulator with the high level value range. If the output value of the accumulator is greater than 72, the level parameter will be stepped down to generate a control code. The level selection unit selects the next level value of the DAC unit as the first level value REF_T1 according to the control code, thereby increasing the first level value REF_T1 from V <0> 16 Adjust to V <0> 15. By changing the input voltage of the gate of the NMOS tube NM7, the output current of the drain of the NMOS tube NM7 can be changed, and by changing the current of the node B, the charging and discharging speed of the comparator can be changed, thereby performing the first compensation for the offset error of the comparator.

[0068] After that, the second calibration process begins. If the output value of the accumulator is still greater than 72, the level parameter continues to step down, so that the first level value REF_T1 increases from V <0> 15 Adjust to V <0> 14, the current of node B is changed again to compensate the offset error of the comparator. Then the calibration is performed again until the output value of the accumulator is within the high level value range, that is, the offset error of the comparator is compensated. In this process, since the second level value REF_T2 is always V <0> 16, so the current at node A remains unchanged.

[0069] Similarly, if the output value of the accumulator is less than 56 during the first calibration, the level parameter will be stepped up to generate a control code, so that the first level value REF_T1 increases from V <0> 16 Adjust to V <0> 17; Then calibrate again until the output value of the accumulator is within the high level value range, thus completing the compensation of the comparator offset error. <0> 16 is the middle level value, and there are only 16 level values ​​upward or downward. Therefore, only 16 corrections are required at most to complete the offset voltage error correction process of the comparator.

[0070] See also Figure 5 and Figure 6 , where Tcpar_I and Tcpar_Q are analog signals output by the comparator after being re-quantized by the DAC, and ENOB is the effective number of bits of the post-simulation data of the comparator. After the correction structure of this embodiment, ENOB is improved from 3.61dB to 3.82dB, thereby effectively improving the linearity of the comparator.

[0071] In this embodiment, the offset voltage polarity is judged by accumulating the number of high and low levels, and then the offset voltage of the comparator is corrected by selecting the gate voltage of the correction tube to control the current of the correction tube. By introducing the offset voltage correction algorithm, the offset voltage of the comparator can be kept within 1 / 4LSB at all times, and the offset voltage correction range can achieve a voltage difference value of plus or minus 100mV, and the correction range can be adjusted by adjusting the value of the positive power supply voltage V+ and the negative power supply voltage V- in the DAC unit and the number of adjustment resistors. It can be seen that the offset voltage correction algorithm of the comparator in this embodiment can effectively suppress the systematic error caused by the offset of the comparator.

[0072] The above embodiments only express the preferred implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A comparator offset voltage error correction structure, characterized in that: include A short-circuiting unit, used for short-circuiting the input terminal of the comparator when calibrating the comparator; An accumulator, used for accumulating the number of high levels in the output signal of the comparator; A counter, used for counting the output signal of the comparator; A digital correction module is used to adjust the output level value according to the output value of the accumulator when the count value of the counter reaches a preset count threshold; as well as The error compensation unit is used to generate a corresponding compensation signal according to the level value output by the digital correction module to compensate for the offset error of the comparator.

2. The comparator offset voltage error correction structure according to claim 1, wherein: The digital correction module includes A judgment unit, used for comparing the output value of the accumulator with a preset high level value range when the count value of the counter reaches a preset count threshold, and outputting a corresponding adjustment signal to the parameter adjustment unit according to the comparison result; A parameter adjustment unit, used to adjust the level parameter accordingly according to the received adjustment signal and then output it to the control code generation unit; as well as The correction level generating unit is used to output a corresponding level value to the error compensation unit according to the level parameter.

3. The comparator offset voltage error correction structure as claimed in claim 2, characterized in that: When the output value of the accumulator is higher than the upper limit of the preset high-level numerical range, the judgment unit outputs a first adjustment signal; when the output value of the accumulator is lower than the lower limit of the preset high-level numerical range, the judgment unit outputs a second adjustment signal; when the output value of the accumulator is within the preset high-level numerical range, the judgment unit outputs a third adjustment signal; When receiving the first adjustment signal, the parameter adjustment unit steps the level parameter downward and outputs it to the control code generation unit; when receiving the second adjustment signal, the parameter adjustment unit steps the level parameter upward and outputs it to the control code generation unit.

4. The comparator offset voltage error correction structure as claimed in claim 2, characterized in that: The correction level generating unit includes A control code generating unit, used to generate a corresponding control code to the correction level generating unit according to the level parameter; DAC unit, used to generate multi-level equal-difference level signals; as well as The level selection unit is used to select a level signal of a corresponding level from the level signal generated by the DAC unit according to the control code and send it to the error compensation unit.

5. The comparator offset voltage error correction structure as claimed in claim 4, characterized in that: The DAC unit includes a comparison amplifier A1, a comparison amplifier A2, a PMOS tube M21, an NMOS tube M22, a capacitor C1, a capacitor C2, a resistor R35, a resistor R36, a resistor R37, a resistor R38 and N adjustment resistors with the same resistance value; the non-inverting input terminal of the comparison amplifier A1 is used to connect the positive power supply voltage V+, the inverting input terminal of the comparison amplifier A1 is electrically connected to its output terminal through the capacitor C1, and the inverting input terminal of the comparison amplifier A1 is also grounded through the resistor R36; The output terminal of the comparison amplifier A1 is electrically connected to the gate of the PMOS tube M21, the source of the PMOS tube M21 is connected to the power supply voltage VDD, and the drain of the PMOS tube M21 is electrically connected to the inverting input terminal of the comparison amplifier A1 through the resistor R35; The drain of the PMOS tube M21 is also electrically connected to the drain of the NMOS tube M22 through N series-connected adjustment resistors, and the connection ends of every two adjacent adjustment resistors respectively output a first-level equal-difference level signal to the level selection unit; The drain of the NMOS tube M22 is electrically connected to the non-inverting input terminal of the comparison amplifier A2 through the resistor R37; The source of the NMOS tube M22 is grounded, and the gate of the NMOS tube M22 is electrically connected to the output end of the comparison amplifier A2; The non-inverting input terminal of the comparison amplifier A2 is electrically connected to its output terminal via a capacitor C2, and the non-inverting input terminal of the comparison amplifier A2 is also grounded via a resistor R38; the inverting input terminal of the comparison amplifier A2 is used to connect to a negative power supply voltage V-.

6. The comparator offset voltage error correction structure as claimed in claim 5, characterized in that: The voltage difference between the positive power supply voltage V+ and the negative power supply voltage V- is 200mV.

7. The comparator offset voltage error correction structure according to any one of claims 1 to 6, characterized in that: The level value output by the digital correction module includes a first level value REF_T1 and a second level value REF_T2, wherein the first level value REF_T1 is obtained according to a level parameter, and the second level value REF_T2 is a fixed value; the error compensation unit generates corresponding current signals according to the first level value REF_T1 and the second level value REF_T2 to adjust the charging and discharging speed of the comparator, thereby compensating for the offset error of the comparator.

8. The comparator offset voltage error correction structure as claimed in claim 7, characterized in that: The error compensation unit includes an NMOS tube NM7 and an NMOS tube NM8, wherein the gate of the NMOS tube NM7 is connected to a first level value REF_T1, the source of the NMOS tube NM7 is grounded, and the drain of the NMOS tube NM7 is connected to a comparator; the gate of the NMOS tube NM8 is connected to a second level value REF_T2, the source of the NMOS tube NM8 is grounded, and the drain of the NMOS tube NM8 is connected to the comparator.

9. The comparator offset voltage error correction structure as claimed in claim 8, characterized in that: The comparator includes an inverter D1, an inverter D2, a PMOS tube PM1, a PMOS tube PM2, a PMOS tube PM3, a PMOS tube PM4, an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3, an NMOS tube NM4, an NMOS tube NM5, an NMOS tube NM6, an NMOS tube NM9 and an NMOS tube NM10; The sources of the PMOS tubes PM1, PM2, PM3 and PM4 are all connected to the power supply voltage VDD, the gate of the PMOS tube PM1 is electrically connected to the gate of the NMOS tube NM1 and the drain of the PMOS tube PM2, the drain of the PMOS tube PM1 is electrically connected to the input end of the inverter D1 and the drain of the NMOS tube NM1, and the output end of the inverter D1 serves as the first output end of the comparator; The gate of the PMOS tube PM2 is electrically connected to the gate of the NMOS tube NM2 and the drain of the PMOS tube PM1 respectively, the drain of the PMOS tube PM2 is electrically connected to the input end of the inverter D2 and the drain of the NMOS tube NM2 respectively, and the output end of the inverter D2 serves as the second output end of the comparator; The gates of the PMOS transistor PM3 and the PMOS transistor PM4 are both connected to the clock signal CLK, the drain of the PMOS transistor PM3 is electrically connected to the source of the NMOS transistor NM1, the drain of the NMOS transistor NM3, the drain of the NMOS transistor NM5, and the drain of the NMOS transistor NM8; the drain of the PMOS transistor PM4 is electrically connected to the source of the NMOS transistor NM2, the drain of the NMOS transistor NM4, the drain of the NMOS transistor NM6, and the drain of the NMOS transistor NM7; The gate of the NMOS tube NM3 is connected to the input signal Vip, and the gate of the NMOS tube NM4 is connected to the reference voltage signal V REF14 The sources of the NMOS tubes NM3 and NMOS tubes NM4 are electrically connected to the drain of the NMOS tube NM9, the gate of the NMOS tube NM9 is connected to the clock signal CLK, and the source of the NMOS tube NM9 is grounded; The gate of the NMOS tube NM5 is connected to the reference voltage signal V REF0 The gate of the NMOS tube NM6 is connected to the input signal Vin; the sources of the NMOS tubes NM5 and NMOS tubes NM6 are electrically connected to the drain of the NMOS tube NM10, the gate of the NMOS tube NM10 is connected to the clock signal CLK, and the source of the NMOS tube NM10 is grounded.

10. The comparator offset voltage error correction structure according to claim 9, wherein: The short-circuit unit includes a PMOS tube PM5, a PMOS tube PM6, an NMOS tube NM11 and an NMOS tube NM12. The gate of the NMOS tube NM3 is also electrically connected to the drain of the PMOS tube PM5 and the source of the NMOS tube NM11, respectively. The gate of the NMOS tube NM4 is also electrically connected to the source of the PMOS tube PM5 and the drain of the NMOS tube NM11, respectively. The gate of the PMOS tube PM5 is connected to the clock signal CLK_P, and the gate of the NMOS tube NM11 is connected to the clock signal CLK_N. The gate of the NMOS tube NM5 is also electrically connected to the drain of the PMOS tube PM6 and the source of the NMOS tube NM12, respectively. The gate of the NMOS tube NM6 is also electrically connected to the source of the PMOS tube PM6 and the drain of the NMOS tube NM12, respectively. The gate of the PMOS tube PM6 is connected to the clock signal CLK_P, and the gate of the NMOS tube NM12 is connected to the clock signal CLK_N.

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