RESURF GaN-based HEMT with multi-crystal face structure and preparation method thereof

Abstract

The invention discloses an RESURF GaN-based HEMT (High Electron Mobility Transistor) with a multi-crystal face structure and a preparation method thereof, and belongs to the technical field of semiconductor power devices. The device sequentially comprises a substrate layer (101), a GaN buffer layer (102), a mask layer (103), a composite channel structure (104), a source electrode (105), a drain electrode (106), a p-NiO layer (107), a p +-NiO layer (108) and a grid electrode (109) from bottom to top, by controlling the crystal orientation and epitaxial growth conditions of GaN, a three-dimensional GaN mesa with a specific structure is formed, so that etching damage is effectively avoided; meanwhile, 2DEG in the p-NiO layer (107) and 2DEG in the composite channel structure (104) are mutually exhausted, electric field distribution is remarkably optimized, breakdown voltage is improved, and on-resistance is effectively reduced through the multi-channel design of the composite channel structure (104).

Description

Technical Field

[0001] The invention relates to a RESURF GaN-based HEMT with a polycrystalline surface structure and a preparation method thereof, belonging to the technical field of semiconductor power devices. Background Art

[0002] With the development of modern power electronics technology, the demand for high-efficiency and high-reliability semiconductor power devices is increasing. Gallium nitride (GaN) materials have become important materials in the field of power devices due to their excellent wide bandgap characteristics, high electron mobility and high thermal conductivity, especially in high-frequency, high-power and high-temperature applications, showing great potential. Gallium nitride-based high electron mobility transistor (HEMT) is an important structure widely used in power electronic devices, and its performance is particularly outstanding under high voltage, high current and high temperature environments. Especially in high-power applications such as power electronics, communication systems and radars, GaN-based HEMT devices have broad application prospects. However, with the continuous reduction of device size and the increase of operating frequency, GaN-based HEMT still faces some challenges in practical applications, especially in terms of breakdown voltage, on-resistance, reliability and preparation process.

[0003] At present, the performance of GaN-based HEMT devices is limited by multiple factors: on the one hand, most of the existing device structures need to go through an etching process during the preparation process, and the etching process is easy to introduce defects on the surface of the GaN material and increase the surface roughness, thereby causing the device performance to decline, which is specifically manifested in problems such as increased on-resistance, increased surface defects, and reduced thermal stability; on the other hand, under high voltage operating conditions, the local electric field may be too large on the surface or edge area of ​​the device, causing the device to break down prematurely, and the on-resistance is too high, and the dynamic performance of the HEMT device is too low; field plate structure, optimized device area and p-GaN RESURF (Reduced Surface Field) structure are usually used to achieve high breakdown voltage and low on-resistance, but the field plate structure will introduce a large parasitic capacitance, and optimizing the device area will increase the resistance. Etching is required when filling p-GaN, and there is etching damage, which increases the complexity of device manufacturing. Therefore, it is of great significance to be able to design a GaN-based HEMT device with no etching damage, optimized electric field distribution, increased breakdown voltage, reduced on-resistance, improved device dynamic performance and excellent switching efficiency. Summary of the invention

[0004] The present invention discloses a polycrystalline face structure RESURF GaN-based HEMT and a preparation method thereof. The device forms a specific three-dimensional GaN table by growing the {20-21} face and the {10-11} face, or the {1-102} face and the {11-23} face of GaN, thereby avoiding the damage to the surface caused by the traditional etching process. A p-NiO layer (107) with a gradient doping concentration is arranged on the composite channel structure (104), wherein the high doping concentration NiO can reduce the barrier width, making it easier for holes in the p-NiO to be injected into GaN. The p-type doped NiO and the 2DEG in multiple channels can deplete each other, and the reasonably distributed carriers will expand the depletion region, thereby making the electric field distribution in the drift region more uniform, thereby improving the breakdown voltage of the device. The high doping concentration p + The NiO layer (108) further improves the hole injection capability, optimizes the current collapse, and forms an ohmic contact with the gate (109). Through the optimization of the structural design and the preparation process, the present invention provides a new structure and method for realizing a GaN-based HEMT device with no etching damage, high breakdown voltage, low on-resistance and high dynamic performance.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] On the one hand, the present invention provides a polycrystalline face structure RESURF GaN-based HEMT, characterized in that it comprises a substrate layer (101) arranged in sequence from bottom to top, a GaN buffer layer (102) whose upward crystal plane is a (0002) plane, a mask layer (103) containing a specific hole array, a composite channel structure (104) in the holes of the mask layer (103) and in contact with the GaN buffer layer (102), a source electrode (105) and a drain electrode (106) located at both ends of the composite channel structure (104), a p-NiO layer (107) covering the composite channel structure (104) in a three-dimensional form, and a p-NiO layer (107) covering the p-NiO layer (107). + -NiO layer (108), covering the p + - A gate (109) on a NiO layer (108); wherein the hole of the mask layer (103) is a hexagonal long strip hole symmetrical along directions 1 and 2, the angle between any two adjacent sides is 120°, the two sides parallel to direction 1 are long sides with a length of a, and two sides at both ends of direction 1 with an angle of 60° to direction 1 are short sides with a length of b; the direction 1 is a lateral direction, and the direction 2 is a third direction perpendicular to both the lateral direction and the vertical direction; the composite channel structure (104) is a table structure extending upward from the long strip hole of the mask layer (103), and comprises 2 to 5 pairs of GaN channel layers (1041) and Indium channel layers (1042) arranged in sequence from bottom to top. x Al y Ga 1-x-yThe N barrier layer (1042) has a bottom surface of (000-2) crystal plane and contacts the GaN buffer layer (102), a top surface of (0002) crystal plane, and the bottom and top surfaces are made of P m crystal planes m and P n The composite channel structure (104) is connected to a plurality of crystal planes n, and both the crystal planes m and n are inclined planes that are not perpendicular to the top plane; the source electrode (105) covers the inclined plane and the top plane on one side of the composite channel structure (104) along direction 1 in the form of ohmic contact, and the drain electrode (106) covers the inclined plane and the top plane on the other side of the composite channel structure (104) in the form of ohmic contact; the p-NiO layer (107) covers the surface of the composite channel structure (104) and does not contact the edge of the source electrode (105) and the edge of the drain electrode (106); + The p-NiO layer (108) covers the surface of the p-NiO layer (107) and is close to the source (105), and the gate (109) covers the p-NiO layer (107). + - The surface of the NiO layer (108).

[0007] Preferably, the substrate layer (101) is made of one of Si, SiC, GaN or Al2O3.

[0008] Preferably, the mask layer (103) is made of SiO2, SiN x , hBN or Al2O3, with a thickness of 10 to 100 nm. These materials have excellent corrosion resistance, insulation and chemical stability, and effectively avoid direct contact between the GaN buffer layer (102) and the p-NiO layer (107). The hexagonal hole array pattern in the mask layer (103) is arranged along direction 1, and the hexagonal hole array pattern is etched out by process technology to expose the GaN buffer layer (102) at the bottom layer. The angle between any two adjacent sides of the hexagonal hole is 120°, and the two sides parallel to direction 1 are long sides with a length of a. At both ends of direction 1, there are two sides with an angle of 60° with direction 1, which are short sides with a length of b. The range of a is 10 to 25 μm, and the numerical relationship between a and b satisfies a=20×1.73×b. The long side with a length of a ensures the drift region length of the hole array in the device structure, which can improve the breakdown voltage of the device. At the same time, too long will increase the on-resistance, so it needs to be limited; while the length b of the short side optimizes the channel width of 2DEG and improves the current carrying capacity, but too large an area will make it difficult for the p-NiO layer (107) to deplete 2DEG, and will occupy too much effective area, thereby affecting the overall area utilization of the device. This numerical relationship is the optimal solution obtained after experimental optimization, which not only improves the breakdown voltage but also reduces the on-resistance. The main purpose is to achieve a balance among the various performances of the power device. A certain angle is formed between different sides to meet the shape of the GaN crystal surface distribution.

[0009] Preferably, the composite channel structure (104) comprises 2 to 5 pairs of GaN channel layers (1041) and In x Al y Ga 1-x-y The composite channel structure (104) has a (000-2) crystal plane on the bottom and is in contact with the GaN buffer layer (102), and a (0002) crystal plane on the top. The bottom and top surfaces are made of P m crystal planes m and P n The crystal planes m and n are connected, and both the crystal planes m and n are inclined planes that are not perpendicular to the top plane. A structure with inclined planes is formed by combining the crystal planes m and n, wherein the crystal plane m is a {20-21} plane or a {1-102} plane, and the crystal plane n is a {10-11} plane or a {11-23} plane. These inclined planes connect the bottom (000-2) crystal plane and the top (0002) crystal plane of the composite channel structure (104), and have specific growth directions and surface characteristics during the preparation process, effectively avoiding etching damage. In the composite channel structure (104), the thickness of each GaN channel layer (1041) ranges from 30 to 100 nm, and the In x Al y Ga 1-x-y The thickness of the N barrier layer (1042) is in the range of 20 to 30 nm. x Al y Ga 1-x-y The In component x of N is 0 to 0.15, and the Al component y is 0.15 to 0.35. x Al y Ga 1-x-y The N barrier layer (1042) can change the band gap and electronic structure by adjusting the ratio of In and Al, thereby affecting the carrier mobility and electron density.

[0010] Preferably, the material of the source electrode (105) and the drain electrode (106) is one or more combinations of Ti, Al, Ni, and Au, the width of the source electrode (105) along direction 1 is 1 to 3 μm, the width of the drain electrode (106) along direction 1 is 1 to 3 μm, and the thickness is 30 to 100 nm. When the source electrode (105) and the drain electrode (106) are a combination of Ti / Al / Ni / Au, the thickness is set to 10 nm, 20 nm, 10 nm, and 30 nm, respectively. Ti as the first layer can improve adhesion to reduce contact resistance, Al improves overall conductivity, Ni provides mechanical stability and thermal stability, and Au provides anti-oxidation protection and excellent conductivity. In addition, when the source (105) and the drain (106) cover the multiple composite channel structures (104), they contact the composite channel structures (104) in an inclined shape, rather than in a traditional vertical contact, which significantly increases the actual contact area between the source (105) and the drain (106) and the channel, improves the current injection and extraction efficiency, reduces the contact resistance, and effectively enhances the conductive performance of the device. This inclined design can also increase the area and effectively dissipate heat.

[0011] Preferably, the p-NiO layer (107) covers the top surface and the inclined surface of the composite channel structure (104), and the spacing from the boundary of one side of the source electrode (105) is 2 to 4 μm, and the spacing from the boundary of one side of the drain electrode (106) is 2 to 8 μm, and the thickness ranges from 100 to 300 nm. By controlling the distance between the p-NiO layer (107) and the source electrode (105) and the drain electrode (106), current leakage or a bad current conduction path can be avoided. The p-NiO layer (107) is doped in a gradient manner, and the closer to the composite channel structure (104), the higher the doping concentration. A heterojunction of p-NiO and n-GaN is formed between the NiO with high doping concentration and GaN, thereby forming a potential barrier. The NiO with a higher doping concentration can reduce the barrier width at the interface, thereby improving the injection efficiency of holes, and entering GaN through the barrier through the tunneling effect. The doping concentration is b×x1×x2, where b is in μm and x1 is 1×10 17 cm -3 , the range of x2 is 5~20μm -1 The width b directly affects the matching relationship between holes and electrons. When the width is larger, a higher p-type doping concentration is required to deplete 2DEG. The parameter x2 controls the change of doping concentration to optimize the breakdown voltage, on-resistance and reliability of the device. x2 is the optimal interval after optimization, providing a reliable doping concentration range.

[0012] Preferably, the p + The p-NiO layer (108) covers the surface of the p-NiO layer (107) close to the source electrode (105), and has a width of 2 to 6 μm along direction 1 and a thickness of 30 to 100 nm.+ The doping concentration of the NiO layer (108) is 1×10 19 cm -3 ~1×10 20 cm -3 , with high doping concentration of p + The NiO layer (108) can improve the hole injection capability, which helps to improve the switching performance of the GaN HEMT device, especially to optimize the current collapse phenomenon.

[0013] Preferably, the gate (109) covers the p + -NiO layer (108) surface, can enhance the gate control ability, thickness of 30 ~ 100nm, gate (109) material can be selected Pt, Au, Pd and other high work function metal, help with p + - The NiO layer (108) forms a good ohmic contact. A good ohmic contact can improve the conductivity, switching speed and reliability of the device.

[0014] On the other hand, the present invention provides a structural feature and a preparation method of a RESURF GaN-based HEMT with a polycrystalline face structure. The structural features of the device are arranged in order from bottom to top: a substrate layer (101), a GaN buffer layer (102) whose upward crystal face is a (0002) face, a mask layer (103) containing a specific hole array, a composite channel structure (104) in the holes of the mask layer (103) and in contact with the GaN buffer layer (102), a source electrode (105) and a drain electrode (106) located at both ends of the composite channel structure (104), a p-NiO layer (107) covering the composite channel structure (104) in a three-dimensional form, and a p-NiO layer (107) covering the p-NiO layer (107). + -NiO layer (108), covering the p + - A gate (109) on a NiO layer (108); wherein the hole of the mask layer (103) is a hexagonal long strip hole symmetrical along directions 1 and 2, the angle between any two adjacent sides is 120°, the two sides parallel to direction 1 are long sides with a length of a, and two sides at both ends of direction 1 with an angle of 60° to direction 1 are short sides with a length of b; the direction 1 is a lateral direction, and the direction 2 is a third direction perpendicular to both the lateral direction and the vertical direction; the composite channel structure (104) is a table structure extending upward from the long strip hole of the mask layer (103), and comprises 2 to 5 pairs of GaN channel layers (1041) and Indium channel layers (1042) arranged in sequence from bottom to top. x Al y Ga 1-x-y The N barrier layer (1042) has a bottom surface of (000-2) crystal plane and contacts the GaN buffer layer (102), a top surface of (0002) crystal plane, and the bottom and top surfaces are made of P m crystal planes m and Pn The composite channel structure (104) is connected to a plurality of crystal planes n, and both the crystal planes m and n are inclined planes that are not perpendicular to the top plane; the source electrode (105) covers the inclined plane and the top plane on one side of the composite channel structure (104) along direction 1 in the form of ohmic contact, and the drain electrode (106) covers the inclined plane and the top plane on the other side of the composite channel structure (104) in the form of ohmic contact; the p-NiO layer (107) covers the surface of the composite channel structure (104) and does not contact the edge of the source electrode (105) and the edge of the drain electrode (106); + The p-NiO layer (108) covers the surface of the p-NiO layer (107) and is close to the source (105), and the gate (109) covers the p-NiO layer (107). + - the surface of the NiO layer (108); when P m and P n When the values ​​of the crystal planes are 4 and 2 respectively, the crystal plane m is a {20-21} plane, named m1 to m4, and the crystal plane n is a {10-11} plane, named n1 to n2; wherein two {10-11} planes: n1 and n2 extend along direction 1, and the bottoms thereof are in contact with the long sides of the long strip holes of the mask layer (103), and the p-NiO layer (107) covers the n1 and n2; the side for preparing the source electrode (105) comprises two {20-21} planes, m1 and m2, which are in contact with each other and with n1 and n2; the side for preparing the drain electrode (106) comprises two {20-21} planes, m3 and m4, which are in contact with each other and with n1 and n2; the preparation method of the device comprises the following steps: a) selecting one of commercially available Si, SiC, GaN or Al2O3 on which GaN thin film can be directly epitaxially grown as a substrate layer (101), and epitaxially growing a GaN buffer layer (102) using one of MOCVD, MBE or HVPE technologies; b) Depositing SiO2 or SiN on the GaN buffer layer (102) using PECVD technology x as a mask layer (103); using standard ultraviolet lithography technology to achieve pattern transfer on the mask layer (103) to obtain a specially designed hexagonal array pattern, and further using RIE technology to etch away the hexagonal area to expose the hexagonal hole array of the GaN buffer layer (102) on the mask layer (103), thereby completing the preparation of the mask layer (103) containing the specific hole array; c) using an MOCVD system and a hexagonal hole array in a mask layer to achieve selective epitaxy, the bottom GaN channel layer (1041) is grown under the following growth conditions: growth temperature of 1050-1080°C, V / III ratio (N source and Al, The molar flow ratio of the Ga source is 800-1500, the growth pressure is 600-760 Torr, and the total flow rate v (in sccm) of the carrier gas introduced into the reaction chamber satisfies 50PA<760v<80PA, wherein P is the growth pressure (in Torr), and A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters); the upward crystal plane of the composite channel structure (104) is the 0002 plane, and a three-dimensional growth mode can be triggered by controlling a higher growth temperature and a higher V / III ratio to realize selective epitaxy in the hexagonal hole; at the same time, the edge of the three-dimensional structure is realized with a higher potential The {10-11} and {20-21} crystal planes are terminated to form a specific three-dimensional GaN table; a relatively low carrier gas flow rate is controlled to ensure that the reactant source is normally transported to the surface of the GaN buffer layer (102) in the hole to achieve growth; after the growth of the bottommost GaN channel layer (1041) is completed, the growth temperature, V / III ratio and pressure are maintained unchanged, and the total carrier gas flow v introduced into the reaction chamber is increased to 1.1 to 1.3 times to complete the growth of the remaining part of the composite channel structure (104); the flow rate is appropriately increased to control the lateral epitaxial growth rate to ensure that the growth is mainly vertically upward to form a neat edge bevel; d) using standard ultraviolet lithography technology to form an area on the composite channel structure (104) where a p-NiO layer (107) needs to be deposited; using magnetron sputtering to deposit NiO, the target material is high-purity nickel metal, and the sputtering conditions are as follows: the gases introduced are O2 and Ar, the sputtering power is 100-200W, and the gas pressure is 3-5mTorr; during the deposition process, the ratio of the introduced O2 to Ar is gradually adjusted from the initial 7:3 to 5:5; for the doping concentration control of p-NiO, p-type doping in NiO is mainly manifested as Ni vacancies and O interstitials, so the carrier concentration can be controlled by adjusting the O2 flow rate, and the O2 flow rate is gradually reduced to achieve a gradient distribution of the doping concentration; then the preparation of the p-NiO layer (107) is completed; similarly, using ultraviolet lithography technology to form a region on the p-NiO layer (107) where a p-NiO layer needs to be sputtered + - NiO layer (108), deposited p + - NiO layer (108); e) In p + - A photoresist is coated on the surface of the NiO layer (108), exposed and developed, and then a gate (109) is deposited. A corresponding source (105) and drain (106) are prepared on the surface of the composite channel structure (104), and then a rapid annealing process is performed to complete the preparation of the device structure.

[0015] The present invention also provides a structural feature and a preparation method of a RESURF GaN-based HEMT with a polycrystalline face structure. The structural features of the device are arranged in sequence from bottom to top: a substrate layer (101), a GaN buffer layer (102) whose upward crystal face is a (0002) face, a mask layer (103) containing a specific hole array, a composite channel structure (104) in the holes of the mask layer (103) and in contact with the GaN buffer layer (102), a source electrode (105) and a drain electrode (106) located at both ends of the composite channel structure (104), a p-NiO layer (107) covering the composite channel structure (104) in a three-dimensional form, and a p-NiO layer (107) covering the p-NiO layer (107). + -NiO layer (108), covering the p + - A gate (109) on a NiO layer (108); wherein the hole of the mask layer (103) is a hexagonal long strip hole symmetrical along directions 1 and 2, the angle between any two adjacent sides is 120°, the two sides parallel to direction 1 are long sides with a length of a, and two sides at both ends of direction 1 with an angle of 60° to direction 1 are short sides with a length of b; the direction 1 is a lateral direction, and the direction 2 is a third direction perpendicular to both the lateral direction and the vertical direction; the composite channel structure (104) is a table structure extending upward from the long strip hole of the mask layer (103), and comprises 2 to 5 pairs of GaN channel layers (1041) and Indium channel layers (1042) arranged in sequence from bottom to top. x Al y Ga 1-x-y The N barrier layer (1042) has a bottom surface of (000-2) crystal plane and contacts the GaN buffer layer (102), a top surface of (0002) crystal plane, and the bottom and top surfaces are made of P m crystal planes m and P n The composite channel structure (104) is connected to a plurality of crystal planes n, and both the crystal planes m and n are inclined planes that are not perpendicular to the top plane; the source electrode (105) covers the inclined plane and the top plane on one side of the composite channel structure (104) along direction 1 in the form of ohmic contact, and the drain electrode (106) covers the inclined plane and the top plane on the other side of the composite channel structure (104) in the form of ohmic contact; the p-NiO layer (107) covers the surface of the composite channel structure (104) and does not contact the edge of the source electrode (105) and the edge of the drain electrode (106); + The p-NiO layer (108) covers the surface of the p-NiO layer (107) and is close to the source (105), and the gate (109) covers the p-NiO layer (107). + - the surface of the NiO layer (108); when P m and P nWhen the crystal planes are 3 and 6 respectively, the crystal plane m is a {1-102} plane, named m1 to m3, and the crystal plane n is a {11-23} plane, named n1 to n6; wherein two {11-23} planes: n1 and n2 extend along direction 1, and the bottoms are in contact with the long sides of the long strip holes of the mask layer (103), and the p-NiO layer (107) covers the n1 and n2; one side of the source electrode (105) includes two {11-23} planes m1 and m2. 1-102} plane and two {11-23} planes of n3 and n4, m1 and m2 are in contact with n1 and n2, n3 and n4 are in contact with each other and are in contact with m1 and m2 respectively; one side of the drain (106) is prepared to include a {1-102} plane of m3 and two {11-23} planes of n5 and n6, and n5 and n6 are in contact with n1 and n2, and m3 is in contact with n5 and n6; the preparation method of the device comprises the following steps: a) selecting one of commercially available Si, SiC, GaN or Al2O3 on which GaN thin film can be directly epitaxially grown as a substrate layer (101), and epitaxially growing a GaN buffer layer (102) using one of MOCVD, MBE or HVPE techniques; b) Depositing SiO2 or SiN on the GaN buffer layer (102) using PECVD technology x as a mask layer (103); using standard ultraviolet lithography technology to achieve pattern transfer on the mask layer (103) to obtain a specially designed hexagonal array pattern, and further using RIE technology to etch away the hexagonal area to expose the hexagonal hole array of the GaN buffer layer (102) on the mask layer (103), thereby completing the preparation of the mask layer (103) containing the specific hole array; c) using an MOCVD system and utilizing the hexagonal hole array of the mask layer (103) to realize selective epitaxy and grow the bottom GaN channel layer (102), the growth conditions being as follows: growth temperature of 1050-1080°C, V / III ratio (molar flow ratio of N source to Al and Ga sources) of 500-700, growth pressure of 600-760 Torr, and the total flow v (in sccm) of the carrier gas introduced into the reaction chamber satisfying 50PA<760v<80PA, and the flow Nv (in sccm) of NH3 satisfying 50A<Nv<100A; wherein P is the growth pressure (in Torr), and A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters); composite channel structure (104) The upward crystal plane is the 0002 plane. By controlling a higher growth temperature and a higher V / III ratio, a three-dimensional growth mode can be triggered to achieve selective epitaxy in hexagonal holes. Because {11-23} and {1-102} are stable high-potential energy crystal planes, reducing the flow rate of the reactant source (NH3 and MO source) during growth can reduce the growth rate. At this time, the edge of the three-dimensional structure can be controlled to end with the {11-23} plane and the {1-102} plane to form a specific three-dimensional GaN table. Controlling a lower carrier gas The flow rate can ensure that the reactant source is normally transported to the surface of the GaN buffer layer (102) in the hole to achieve growth; after the growth of the bottom GaN channel layer (1041) is completed, the growth temperature, V / III ratio and pressure are maintained unchanged, and the total flow rate v of the carrier gas introduced into the reaction chamber is increased to 1.1 to 1.3 times to complete the growth of the remaining part of the composite channel structure (104); the flow rate is appropriately increased to control the lateral epitaxial growth rate to ensure that the growth is mainly vertically upward to form a neat edge bevel; d) using standard ultraviolet lithography technology, forming a p-NiO layer on the composite channel structure (104) (107) region; NiO is deposited by magnetron sputtering, the target material is high-purity nickel metal, and the sputtering conditions are as follows: the gases introduced are O2 and Ar, the sputtering power is 100-200W, and the gas pressure is 3-5mTorr; during the deposition process, the ratio of O2 to Ar is gradually adjusted from the initial 7:3 to 5:5; for the doping concentration control of p-NiO, p-type doping in NiO is mainly manifested as Ni vacancies and O interstitials, so the carrier concentration can be controlled by adjusting the O2 flow rate, and the O2 flow rate is gradually reduced to achieve a gradual distribution of doping concentration; then the p-NiO layer is completed (107) preparation; similarly, using ultraviolet lithography technology to form a p-NiO layer (107) on top of the sputtering p + - NiO layer (108), deposited p + - NiO layer (108); e) In p + - A photoresist is coated on the surface of the NiO layer (108), exposed and developed, and then a gate (109) is deposited. A corresponding source (105) and drain (106) are prepared on the surface of the composite channel structure (104), and then a rapid annealing process is performed to complete the preparation of the device structure.

[0016] Beneficial effects:

[0017] The present invention forms a specific three-dimensional GaN table by growing the {20-21} surface and the {10-11} surface, or the {1-102} surface and the {11-23} surface of GaN, thereby avoiding the damage to the surface caused by the traditional etching process. This design not only improves the material quality and crystal growth stability of the GaN-based HEMT, but also optimizes the contact interface between the source (105) and the drain (106) and the composite channel structure (104), and optimizes the traditional single vertical surface to an inclined surface structure, thereby increasing the contact area, reducing the contact resistance, and improving the current injection and extraction efficiency. At the same time, this inclined surface contact method is also conducive to heat dissipation, reducing local overheating, and thus improving the reliability of the device.

[0018] In addition, the addition of multiple 2DEG channels can increase the current density and reduce the on-resistance of the entire device. During the transition from the on state to the off state of the GaN-based HEMT device, the resistance increases and the current decreases. The introduction of the p-NiO layer (107) with a gradient doping concentration can form a thinner depletion region at the interface between NiO and GaN, thereby reducing the barrier width. This design enhances the hole injection capability of NiO, improves the interface tunneling efficiency, and helps to optimize the conductive performance and dynamic response characteristics of the device. The p-NiO layer (107) can also mutually deplete with multiple 2DEG channels, expand the depletion region, form a better electric field distribution, and maximize the breakdown voltage. The high doping concentration p + -NiO layer (108) can significantly improve hole injection capability, fill trap states, reduce barrier height, and thus reduce the current drop caused by trap effect. This can significantly reduce the current collapse phenomenon and improve the dynamic performance and stability of the device. + -NiO layer (108) forms an excellent ohmic contact, and the entire gate (109) covers the p + -NiO layer (108) surface can enhance gate control capability and improve switching efficiency. The invention provides a new structure and method for designing high-performance GaN-based HEMT devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] exist Figure 1 to Figure 7 In the figure, 101 is a substrate layer; 102 is a GaN buffer layer; 103 is a mask layer; 104 is a composite channel structure; 1041 is a GaN channel layer; 1042 is an In x Al y Ga 1-x-y N barrier layer; 105 is the source; 106 is the drain; 107 is the p-NiO layer; 108 is the p + -NiO layer; 109 is a gate;

[0020] Figure 1A cross-sectional view of a polycrystalline face structure RESURF GaN-based HEMT device provided by the present invention taken along direction 1 at the symmetrical center position in direction 2;

[0021] Figure 2 A cross-sectional view of a RESURF GaN-based HEMT device with a polycrystalline face structure provided by the present invention, taken along direction 2 on a gate (109);

[0022] Figure 3 A schematic diagram of a hexagonal hole array pattern obtained by etching a mask layer (103) in a preparation process flow of a RESURF GaN-based HEMT device with a polycrystalline face structure provided by the present invention; wherein the GaN buffer layer (102) is exposed in the hexagonal pattern after etching, the holes of the mask layer (103) are hexagonal long strip holes symmetrical along directions 1 and 2, the angle between any two adjacent sides is 120°, the two sides parallel to direction 1 are long sides with a length of a, and two sides at both ends of direction 1 with an angle of 60° to direction 1 are short sides with a length of b;

[0023] Figure 4 A top view of a polycrystalline face structure RESURF GaN-based HEMT device provided by the present invention after a composite channel structure (104) is grown in the preparation process flow; wherein the overall structure is a mask layer (103) and three pairs of GaN channel layers (1041) and In x Al y Ga 1-x-y The N barrier layer (1042) has a bottom surface of (000-2) crystal plane and contacts the GaN buffer layer (102), a top surface of (0002) crystal plane, and the bottom and top surfaces are made of P m crystal planes m and P n The crystal planes m and n are connected, and both the crystal planes m and n are inclined planes that are not perpendicular to the top surface; the current P m and P n 4 and 2 respectively, the crystal plane m is a {20-21} plane, named m1 to m4, and the crystal plane n is a {10-11} plane, named n1 to n2; wherein two {10-11} planes: n1 and n2 extend along direction 1, and the bottoms are in contact with the long sides of the long strip holes of the mask layer (103); the side for preparing the source (105) comprises two {20-21} planes, m1 and m2, which are in contact with each other and with n1 and n2; the side for preparing the drain (106) comprises two {20-21} planes, m3 and m4, which are in contact with each other and with n1 and n2;

[0024] Figure 5A top view of a polycrystalline face structure RESURF GaN-based HEMT device provided by the present invention after another composite channel structure (104) is grown in the preparation process flow; wherein the overall structure is a mask layer (103) and three pairs of GaN channel layers (1041) and In x Al y Ga 1-x-y The N barrier layer (1042) has a bottom surface of (000-2) crystal plane and contacts the GaN buffer layer (102), a top surface of (0002) crystal plane, and the bottom and top surfaces are made of P m crystal planes m and P n The crystal planes m and n are connected, and both the crystal planes m and n are inclined planes that are not perpendicular to the top surface; the current P m and P n 3 and 6 respectively, the crystal plane m is a {1-102} plane, named m1 to m3, and the crystal plane n is a {11-23} plane, named n1 to n6; wherein two {11-23} planes: n1 and n2 extend along direction 1, and the bottoms are in contact with the long sides of the long strip holes of the mask layer (103); the side for preparing the source (105) comprises two {1-102} planes, m1 and m2, and two {11-23} planes, n3 and n4, m1 and m2 are in contact with n1 and n2, n3 and n4 are in contact with each other and are in contact with m1 and m2 respectively; the side for preparing the drain (106) comprises one {1-102} plane, m3, and two {11-23} planes, n5 and n6, and n5 and n6 are in contact with n1 and n2, and m3 is in contact with n5 and n6;

[0025] Figure 6 A RESURF GaN-based HEMT device with a polycrystalline face structure provided by the present invention is Figure 4 A top view of the final device prepared on the basis of FIG. 1 ; wherein, in order to facilitate observation of the situation below the source electrode (105), the overlapping portion of the source electrode (105) and the composite channel structure (104) is marked as a dotted line state, and the source electrode (105) can be referred to below the drain electrode (106);

[0026] Figure 7 A RESURF GaN-based HEMT device with a polycrystalline face structure provided by the present invention is Figure 5 A top view of the final device prepared on the basis of FIG. 1 ; wherein, in order to facilitate observation of the situation below the source (105), the overlapping portion of the source (105) and the composite channel structure (104) is marked as a dotted line, and the source (105) can be referenced below the drain (106). DETAILED DESCRIPTION

[0027] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

[0028] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0029] Embodiment 1:

[0030] A top view of a polycrystalline face structure RESURF GaN-based HEMT device provided in Example 1 of the present invention is shown in FIG. Figure 6 As shown, the cross-sectional view along direction 1 at the symmetrical center position of direction 2 is as follows Figure 1 As shown, the cross-sectional view along direction 2 on the gate (109) is as follows Figure 2 The structural features of the device are arranged in order from bottom to top: a substrate layer (101), a GaN buffer layer (102) whose upward crystal plane is the (0002) plane, a mask layer (103) containing a specific hole array, a composite channel structure (104) in the holes of the mask layer (103) and in contact with the GaN buffer layer (102), a source electrode (105) and a drain electrode (106) located at both ends of the composite channel structure (104), a p-NiO layer (107) covering the composite channel structure (104) in a three-dimensional form, and a p-NiO layer (107) covering the p-NiO layer (107). + -NiO layer (108), covering the p + - A gate (109) on a NiO layer (108); wherein the hole of the mask layer (103) is a hexagonal long strip hole symmetrical along directions 1 and 2, the angle between any two adjacent sides is 120°, the two sides parallel to direction 1 are long sides with a length of a, and two sides at both ends of direction 1 with an angle of 60° to direction 1 are short sides with a length of b; the direction 1 is a lateral direction, and the direction 2 is a third direction perpendicular to both the lateral direction and the vertical direction; the composite channel structure (104) is a table structure extending upward from the long strip hole of the mask layer (103), and comprises 2 to 5 pairs of GaN channel layers (1041) and Indium channel layers (1042) arranged in sequence from bottom to top. x Al y Ga 1-x-yThe N barrier layer (1042) has a bottom surface of (000-2) crystal plane and contacts the GaN buffer layer (102), a top surface of (0002) crystal plane, and the bottom and top surfaces are made of P m crystal planes m and P n The composite channel structure (104) is connected to a plurality of crystal planes n, and both the crystal planes m and n are inclined planes that are not perpendicular to the top plane; the source electrode (105) covers the inclined plane and the top plane on one side of the composite channel structure (104) along direction 1 in the form of ohmic contact, and the drain electrode (106) covers the inclined plane and the top plane on the other side of the composite channel structure (104) in the form of ohmic contact; the p-NiO layer (107) covers the surface of the composite channel structure (104) and does not contact the edge of the source electrode (105) and the edge of the drain electrode (106); + The p-NiO layer (108) covers the surface of the p-NiO layer (107) and is close to the source (105), and the gate (109) covers the p-NiO layer (107). + - The surface of the NiO layer (108).

[0031] P m and P n 4 and 2 respectively, the crystal plane m is a {20-21} plane, named m1~m4, and the crystal plane n is a {10-11} plane, named n1~n2; among them, two {10-11} planes: n1 and n2 extend along direction 1, and the bottoms are in contact with the long sides of the long strip holes of the mask layer (103), and the p-NiO layer (107) covers these n1 and n2; the side for preparing the source (105) includes two {20-21} planes m1 and m2, m1 and m2 are in contact with each other and with n1 and n2; the side for preparing the drain (106) includes two {20-21} planes m3 and m4, m3 and m4 are in contact with each other and with n1 and n2.

[0032] A 5 μm GaN buffer layer (102) is grown on a substrate layer (101), a 30 nm SiO2 film is deposited on the GaN buffer layer (102) as a mask layer (103), and a hexagonal hole array pattern is etched, wherein the holes are hexagonal long strip holes symmetrical along directions 1 and 2, and the angle between any two adjacent sides is 120°, exposing the underlying GaN buffer layer (102), and the length a of the long side of the hole is 15 μm. Since the numerical relationship between a and b satisfies a=20×1.73×b, b is 0.43 μm.

[0033] The composite channel structure (104) comprises three pairs of GaN channel layers (1041) and In x Al y Ga 1-x-y N barrier layer (1042), wherein the thickness of the GaN channel layer (1041) is 75nm, and the In x Al y Ga1-x-y The thickness of the N barrier layer (1042) is 25 nm. x Al y Ga 1-x-y The In composition x of N is 0.1, and the Al composition y is 0.25.

[0034] The width of the source electrode (105) along direction 1 is 1 μm, and the material used for the source electrode (105) is a combination of Ti / Al / Ni / Au, and the thickness of each material is 10 nm, 20 nm, 10 nm, and 30 nm respectively; the width of the drain electrode (106) along direction 1 is 1 μm, and the material used for the drain electrode (106) is a combination of Ti / Al / Ni / Au, and the thickness of each material is 10 nm, 20 nm, 10 nm, and 30 nm respectively.

[0035] The distance between the p-NiO layer (107) and the source electrode (105) is 3 μm, the distance between the p-NiO layer (107) and the drain electrode (106) is 3 μm, and the thickness is 200 nm. The gradient p-type doping concentration ranges from 2.2×10 17 cm -3 ~8.6×10 17 cm -3 .

[0036] p + The width of the NiO layer (108) along direction 1 is 3 μm, the thickness is 50 nm, and the p-type doping concentration is 5×10 19 cm -3 .

[0037] The gate (109) is made of high work function metal Pt with a thickness of 50 nm.

[0038] Embodiment 1 of the present invention provides a method for preparing a polycrystalline RESURF GaN-based HEMT device, comprising the following steps: a) selecting commercial SiC on which GaN thin film can be directly epitaxially grown as a substrate layer (101), and using MOCVD to epitaxially grow a GaN buffer layer (102); b) using PECVD technology to deposit SiO2 as a mask layer (103) on the GaN buffer layer (102); using standard ultraviolet lithography technology to achieve pattern transfer on the mask layer (103) to obtain a specially designed hexagonal array pattern, and further using RIE technology to etch away the hexagonal area to expose the hexagonal hole array of the GaN buffer layer (102) on the mask layer (103), thereby completing the preparation of the mask layer (103) containing a specific hole array, such as Figure 3 As shown; c) using an MOCVD system to achieve selective epitaxy using the hexagonal hole array of the mask layer (103) to grow a bottom GaN channel layer (1041), the growth conditions being as follows: a growth temperature of 1060°C, a V / III ratio of 1000, a growth pressure of 700 Torr, and a total flow rate v (in sccm) of the carrier gas introduced into the reaction chamber satisfying 760v=70PA, wherein P is the growth pressure (in Torr), and A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters); after the growth of the bottom GaN channel layer (1041) is completed, the growth temperature, The V / III ratio and pressure remain unchanged, and the total flow rate v of the carrier gas introduced into the reaction chamber is increased to 1.2 times to complete the growth of the remaining part of the composite channel structure (104), such as Figure 4 As shown; d) Using standard UV lithography technology, a region where a p-NiO layer (107) needs to be deposited is formed on the composite channel structure (104); NiO is deposited by magnetron sputtering, the target material is high-purity nickel metal, and the sputtering conditions are as follows: the gases introduced are O2 and Ar, the sputtering power is 150W, and the gas pressure is 4mTorr; during the deposition process, the ratio of the introduced O2 to Ar is adjusted from the initial 7:3 to 5:5, and the oxygen flow rate is gradually reduced, and then the preparation of the p-NiO layer (107) is completed. Similarly, using UV lithography technology, a region where a p-NiO layer (107) needs to be sputtered is formed on the p-NiO layer (107). + - NiO layer (108), deposited p + - NiO layer (108); e) In p + -A photoresist is coated on the surface of the NiO layer (108), exposed and developed, and then a gate electrode (109) is deposited, and a corresponding source electrode (105) and a drain electrode (106) are prepared on the surface of the composite channel structure (104), and then a rapid annealing process is performed; the preparation of the device structure is completed, such as Figure 6 shown.

[0039] Embodiment 2:

[0040] A top view of a polycrystalline face structure RESURF GaN-based HEMT device provided in Example 2 of the present invention is shown in FIG. Figure 7 As shown, the cross-sectional view along direction 1 at the symmetrical center position of direction 2 is as follows Figure 1 As shown, the cross-sectional view along direction 2 on the gate (109) is as follows Figure 2The structural features of the device are arranged in order from bottom to top: a substrate layer (101), a GaN buffer layer (102) whose upward crystal plane is the (0002) plane, a mask layer (103) containing a specific hole array, a composite channel structure (104) in the holes of the mask layer (103) and in contact with the GaN buffer layer (102), a source electrode (105) and a drain electrode (106) located at both ends of the composite channel structure (104), a p-NiO layer (107) covering the composite channel structure (104) in a three-dimensional form, and a p-NiO layer (107) covering the p-NiO layer (107). + -NiO layer (108), covering the p + - A gate (109) on a NiO layer (108); wherein the hole of the mask layer (103) is a hexagonal long strip hole symmetrical along directions 1 and 2, the angle between any two adjacent sides is 120°, the two sides parallel to direction 1 are long sides with a length of a, and two sides at both ends of direction 1 with an angle of 60° to direction 1 are short sides with a length of b; the direction 1 is a lateral direction, and the direction 2 is a third direction perpendicular to both the lateral direction and the vertical direction; the composite channel structure (104) is a table structure extending upward from the long strip hole of the mask layer (103), and comprises 2 to 5 pairs of GaN channel layers (1041) and Indium channel layers (1042) arranged in sequence from bottom to top. x Al y Ga 1-x-y The N barrier layer (1042) has a bottom surface of (000-2) crystal plane and contacts the GaN buffer layer (102), a top surface of (0002) crystal plane, and the bottom and top surfaces are made of P m crystal planes m and P n The composite channel structure (104) is connected to a plurality of crystal planes n, and both the crystal planes m and n are inclined planes that are not perpendicular to the top plane; the source electrode (105) covers the inclined plane and the top plane on one side of the composite channel structure (104) along direction 1 in the form of ohmic contact, and the drain electrode (106) covers the inclined plane and the top plane on the other side of the composite channel structure (104) in the form of ohmic contact; the p-NiO layer (107) covers the surface of the composite channel structure (104) and does not contact the edge of the source electrode (105) and the edge of the drain electrode (106); + The p-NiO layer (108) covers the surface of the p-NiO layer (107) and is close to the source (105), and the gate (109) covers the p-NiO layer (107). + - The surface of the NiO layer (108).

[0041] P m and P n3 and 6 respectively, the crystal plane m is a {1-102} plane, named m1~m3, and the crystal plane n is a {11-23} plane, named n1~n6; among them, two {11-23} planes: n1 and n2 extend along direction 1, and the bottom is in contact with the long side of the long strip hole of the mask layer (103), and the p-NiO layer (107) covers these n1 and n2; the side for preparing the source (105) includes two {1-102} planes m1 and m2 and two {11-23} planes n3 and n4, m1 and m2 are in contact with n1 and n2, n3 and n4 are in contact with each other and are in contact with m1 and m2 respectively; the side for preparing the drain (106) includes one {1-102} plane m3 and two {11-23} planes n5 and n6, and n5 and n6 are in contact with n1 and n2, and m3 is in contact with n5 and n6.

[0042] A 6μm GaN buffer layer (102) is grown on a substrate layer (101), a 40nm SiO2 film is deposited on the GaN buffer layer (102) as a mask layer (103), and a hexagonal hole array pattern is etched. The holes are hexagonal long strip holes that are symmetrical along directions 1 and 2, and the angle between any two adjacent sides is 120°, exposing the underlying GaN buffer layer (102). The length a of the long side of the hole is 20μm. Since the numerical relationship between a and b satisfies a=20×1.73×b, b is 0.58μm.

[0043] The composite channel structure (104) comprises three pairs of GaN channel layers (1041) and In x Al y Ga 1-x-y N barrier layer (1042), wherein the thickness of the GaN channel layer (1041) is 85nm, and the In x Al y Ga 1-x-y The thickness of the N barrier layer (1042) is 25 nm. x Al y Ga 1-x-y The In composition x of N is 0, and the Al composition y is 0.25.

[0044] The width of the source electrode (105) along direction 1 is 2 μm, and the material used for the source electrode (105) is a combination of Ti / Al / Ni / Au, and the thickness of each material is 10 nm, 20 nm, 10 nm, and 30 nm respectively; the width of the drain electrode (106) along direction 1 is 2 μm, and the material used for the drain electrode (106) is a combination of Ti / Al / Ni / Au, and the thickness of each material is 10 nm, 20 nm, 10 nm, and 30 nm respectively.

[0045] The distance between the p-NiO layer (107) and the source electrode (105) is 4 μm, the distance between the p-NiO layer (107) and the drain electrode (106) is 4 μm, and the thickness is 250 nm. The gradient p-type doping concentration ranges from 2.9×10 17 cm -3 ~1.2×10 18 cm -3 .

[0046] p + The width of the NiO layer (108) along direction 1 is 4 μm, the thickness is 50 nm, and the p-type doping concentration is 6×10 19 cm -3 .

[0047] The gate (109) is made of high work function metal Pt with a thickness of 50 nm.

[0048] Embodiment 2 of the present invention provides a method for preparing a RESURF GaN-based HEMT device with a polycrystalline face structure, comprising the following steps: a) selecting commercially available Si on which GaN thin film can be directly epitaxially grown as a substrate layer (101), and using MOCVD to epitaxially grow a GaN buffer layer (102); b) using PECVD technology to deposit SiO2 as a mask layer (103) on the GaN buffer layer (102); using standard ultraviolet lithography technology to achieve pattern transfer on the mask layer (103) to obtain a specially designed hexagonal array pattern, and further using RIE technology to etch away the hexagonal area to expose the hexagonal hole array of the GaN buffer layer (102) on the mask layer (103), thereby completing the preparation of the mask layer (103) containing a specific hole array, such as Figure 3 As shown; c) using an MOCVD system and utilizing the hexagonal hole array of the mask layer (103) to realize selective epitaxy, growing the bottom GaN channel layer (1041), the growth conditions are as follows: growth temperature is 1070°C, V / III ratio is 600, growth pressure is 750 Torr, and the total flow rate v of the carrier gas introduced into the reaction chamber (in sccm) satisfies 760v=70PA, and the flow rate Nv of NH3 (in sccm) satisfies Nv=80A. Wherein P is the growth pressure (in Torr), and A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters); after the growth of the bottom GaN channel layer (1041) is completed, the growth temperature, V / III ratio and pressure are maintained unchanged, and the total flow rate v of the carrier gas introduced into the reaction chamber is increased to 1.2 times, and the growth of the remaining part of the composite channel structure (104) is completed, such as Figure 5 As shown; d) Using standard UV lithography technology, a region where a p-NiO layer (107) needs to be deposited is formed on the composite channel structure (104); NiO is deposited by magnetron sputtering, the target material is high-purity nickel metal, and the sputtering conditions are as follows: the gases introduced are O2 and Ar, the sputtering power is 150W, and the gas pressure is 4mTorr; during the deposition process, the ratio of the introduced O2 to Ar is adjusted from the initial 7:3 to 5:5, and the oxygen flow rate is gradually reduced, and then the preparation of the p-NiO layer (107) is completed. Similarly, using UV lithography technology, a region where a p-NiO layer (107) needs to be sputtered is formed on the p-NiO layer (107). + - NiO layer (108), deposited p + - NiO layer (108); e) In p + -A photoresist is coated on the surface of the NiO layer (108), exposed and developed, and then a gate electrode (109) is deposited, and a corresponding source electrode (105) and a drain electrode (106) are prepared on the surface of the composite channel structure (104), and then a rapid annealing process is performed; the preparation of the device structure is completed, such as Figure 7 shown.

[0049] Working principle of the present invention:

[0050] The composite channel structure (104) adopts a slope design, and forms a specific three-dimensional GaN table by growing the {20-21} plane and the {10-11} plane or the {1-102} plane and the {11-23} plane of GaN, thereby avoiding damage during etching. In addition, the composite channel structure (104) is composed of alternating GaN channel layers (1041) and In x Al y Ga 1-x-y The composite channel structure (104) is composed of a N barrier layer (1042), and the multi-channel structure forms multiple current paths, thereby reducing the on-resistance of the device. The p-NiO layer (107) is deposited on the surface and inclined surface of the composite channel structure (104), and the doping concentration is adjusted by a gradient doping technology, and the closer to the composite channel structure (104), the higher the doping concentration. The p-NiO layer (107) with a higher concentration can effectively reduce the barrier width between NiO and GaN, enhance the hole injection capability, and improve the current transmission characteristics. At the same time, through the interaction with the 2DEG, the electric field distribution is optimized, and the breakdown voltage and dynamic performance of the device are improved. + The high concentration of NiO in the NiO layer (108) can optimize the current collapse and form an ohmic contact with the gate (109). The gate (109) covers the p +-NiO layer (108) surface, enhancing the gate control capability. In summary, the polycrystalline surface structure RESURF GaN-based HEMT device of the present invention achieves high breakdown voltage, low on-resistance and excellent dynamic performance through optimized structural design and gradient doping process without etching damage, and is suitable for high-power electronic devices.

Claims

1. A RESURF GaN-based HEMT with a polycrystalline face structure, characterized in that: The invention comprises a substrate layer (101) arranged in sequence from bottom to top, a GaN buffer layer (102) whose upward crystal plane is a (0002) plane, a mask layer (103) containing a specific hole array, a composite channel structure (104) in the holes of the mask layer (103) and in contact with the GaN buffer layer (102), a source electrode (105) and a drain electrode (106) located at both ends of the composite channel structure (104), a p-NiO layer (107) covering the composite channel structure (104) in a three-dimensional form, and a p-NiO layer (107) covering the p-NiO layer (107). + -NiO layer (108), covering the p + - A gate (109) on a NiO layer (108); wherein the hole of the mask layer (103) is a hexagonal long strip hole symmetrical along directions 1 and 2, the angle between any two adjacent sides is 120°, the two sides parallel to direction 1 are long sides with a length of a, and two sides at both ends of direction 1 with an angle of 60° to direction 1 are short sides with a length of b; the direction 1 is a lateral direction, and the direction 2 is a third direction perpendicular to both the lateral direction and the vertical direction; the composite channel structure (104) is a table structure extending upward from the long strip hole of the mask layer (103), and comprises 2 to 5 pairs of GaN channel layers (1041) and Indium channel layers (1042) arranged in sequence from bottom to top. x Al y Ga 1-x-y The N barrier layer (1042) has a bottom surface of (000-2) crystal plane and contacts the GaN buffer layer (102), a top surface of (0002) crystal plane, and the bottom and top surfaces are made of P m crystal planes m and P n The composite channel structure (104) is connected to a plurality of crystal planes n, and both the crystal planes m and n are inclined planes that are not perpendicular to the top plane; the source electrode (105) covers the inclined plane and the top plane on one side of the composite channel structure (104) along direction 1 in the form of ohmic contact, and the drain electrode (106) covers the inclined plane and the top plane on the other side of the composite channel structure (104) in the form of ohmic contact; the p-NiO layer (107) covers the surface of the composite channel structure (104) and does not contact the edge of the source electrode (105) and the edge of the drain electrode (106); + The p-NiO layer (108) covers the surface of the p-NiO layer (107) and is close to the source (105), and the gate (109) covers the p-NiO layer (107). + - The surface of the NiO layer (108).

2. A polycrystalline face structured RESURF GaN-based HEMT according to claim 1, characterized in that: P m and P n When the values ​​of the crystal planes are 4 and 2 respectively, the crystal plane m is a {20-21} plane, named m1 to m4, and the crystal plane n is a {10-11} plane, named n1 to n2; wherein two {10-11} planes: n1 and n2 extend along direction 1, and the bottoms thereof are in contact with the long sides of the long strip holes of the mask layer (103), and the p-NiO layer (107) covers the n1 and n2; the side for preparing the source electrode (105) comprises two {20-21} planes, m1 and m2, which are in contact with each other and with n1 and n2; the side for preparing the drain electrode (106) comprises two {20-21} planes, m3 and m4, which are in contact with each other and with n1 and n2; or, P m and P n When they are 3 and 6 respectively, the crystal plane m is a {1-102} plane, named m1~m3, and the crystal plane n is a {11-23} plane, named n1~n6; among them, two {11-23} planes: n1 and n2 extend along direction 1, and the bottoms are in contact with the long sides of the long strip holes of the mask layer (103), and the p-NiO layer (107) covers these n1 and n2; the side for preparing the source (105) includes two {1-102} planes m1 and m2 and two {11-23} planes n3 and n4, m1 and m2 are in contact with n1 and n2, n3 and n4 are in contact with each other and are in contact with m1 and m2 respectively; the side for preparing the drain (106) includes one {1-102} plane m3 and two {11-23} planes n5 and n6, and n5 and n6 are in contact with n1 and n2, and m3 is in contact with n5 and n6.

3. A polycrystalline face structured RESURF GaN-based HEMT according to claim 1, characterized in that: The mask layer (103) is made of SiO2, SiN x , hBN or Al2O3, with a thickness of 10 to 100 nm; in the hexagonal long strip holes in the mask layer (103), the numerical relationship between the long side length a and the short side length b satisfies a=20×1.73×b, wherein the length range of a is 10 to 25 μm.

4. The polycrystalline face structure RESURF GaN-based HEMT according to claim 1, characterized in that: The thickness of the GaN channel layer (1041) in the composite channel structure (104) is in the range of 30 to 100 nm. x Al y Ga 1-x-y The thickness of the N barrier layer (1042) is in the range of 20 to 30 nm; x Al y Ga 1-x-y The In component x in N is 0 to 0.15, and the Al component y is 0.15 to 0.

35.

5. The polycrystalline RESURF GaN-based HEMT according to claim 1, characterized in that: The width of the source electrode (105) along direction 1 is 1 to 3 μm, and the width of the drain electrode (106) along direction 1 is 1 to 3 μm; the material of the source electrode (105) and the drain electrode (106) can be any one of Ti, Al, Ni, and Au, and the thickness thereof is 30 to 100 nm; or, the source electrode (105) and the drain electrode (106) can be composed of a multilayer structure of Ti / Al / Ni / Au, and the thickness of each material is 10 nm, 20 nm, 10 nm, and 30 nm, respectively.

6. The polycrystalline RESURF GaN-based HEMT according to claim 1, characterized in that: The p-NiO layer (107) covers the top surface and the inclined surface of the composite channel structure (104), the distance from the boundary of one side of the source electrode (105) is 2 to 4 μm, the distance from the boundary of one side of the drain electrode (106) is 2 to 8 μm, and the thickness is 100 to 300 nm; the p-NiO layer (107) is a gradient p-type doping, the doping concentration near the composite channel structure (104) is higher, and the doping concentration is b×x1×x2, wherein b is in μm, x1 is 1×10 17 cm -3 , the range of x2 is 5~20μm -1 .

7. The polycrystalline RESURF GaN-based HEMT according to claim 1, characterized in that: The p + The p-NiO layer (108) covers the surface of the p-NiO layer (107) close to the source electrode (105), has a width of 2 to 6 μm along direction 1, a thickness of 30 to 100 nm, and a doping concentration in the range of 1×10 19 cm -3 ~1×10 20 cm -3 .

8. The polycrystalline RESURF GaN-based HEMT according to claim 1, characterized in that: The gate (109) covers the p + The surface of the NiO layer (108) is made of one or more combinations of high work function metals such as Pt, Au and Pd, and has a thickness of 30 to 100 nm.

9. A structural feature and preparation method of a polycrystalline face structured RESURF GaN-based HEMT, characterized in that: The structural features of the device are arranged in order from bottom to top: a substrate layer (101), a GaN buffer layer (102) whose upward crystal plane is a (0002) plane, a mask layer (103) containing a specific hole array, a composite channel structure (104) in the holes of the mask layer (103) and in contact with the GaN buffer layer (102), a source electrode (105) and a drain electrode (106) located at both ends of the composite channel structure (104), a p-NiO layer (107) covering the composite channel structure (104) in a three-dimensional form, and a p-NiO layer (107) covering the p-NiO layer (107). + -NiO layer (108), covering the p + - A gate (109) on a NiO layer (108); wherein the hole of the mask layer (103) is a hexagonal long strip hole symmetrical along directions 1 and 2, the angle between any two adjacent sides is 120°, the two sides parallel to direction 1 are long sides with a length of a, and two sides at both ends of direction 1 with an angle of 60° to direction 1 are short sides with a length of b; the direction 1 is a lateral direction, and the direction 2 is a third direction perpendicular to both the lateral direction and the vertical direction; the composite channel structure (104) is a table structure extending upward from the long strip hole of the mask layer (103), and comprises 2 to 5 pairs of GaN channel layers (1041) and Indium channel layers (1042) arranged in sequence from bottom to top. x Al y Ga 1-x-y The N barrier layer (1042) has a bottom surface of (000-2) crystal plane and contacts the GaN buffer layer (102), a top surface of (0002) crystal plane, and the bottom and top surfaces are made of P m crystal planes m and P n The composite channel structure (104) is connected to a plurality of crystal planes n, and both the crystal planes m and n are inclined planes that are not perpendicular to the top plane; the source electrode (105) covers the inclined plane and the top plane on one side of the composite channel structure (104) along direction 1 in the form of ohmic contact, and the drain electrode (106) covers the inclined plane and the top plane on the other side of the composite channel structure (104) in the form of ohmic contact; the p-NiO layer (107) covers the surface of the composite channel structure (104) and does not contact the edge of the source electrode (105) and the edge of the drain electrode (106); + The p-NiO layer (108) covers the surface of the p-NiO layer (107) and is close to the source (105), and the gate (109) covers the p-NiO layer (107). + - the surface of the NiO layer (108); when P m and P n When the values ​​of the crystal planes are 4 and 2 respectively, the crystal plane m is a {20-21} plane, named m1 to m4, and the crystal plane n is a {10-11} plane, named n1 to n2; wherein two {10-11} planes: n1 and n2 extend along direction 1, and the bottoms thereof are in contact with the long sides of the long strip holes of the mask layer (103), and the p-NiO layer (107) covers the n1 and n2; the side for preparing the source electrode (105) comprises two {20-21} planes, m1 and m2, which are in contact with each other and with n1 and n2; the side for preparing the drain electrode (106) comprises two {20-21} planes, m3 and m4, which are in contact with each other and with n1 and n2; the preparation method of the device comprises the following steps: a) selecting one of commercially available Si, SiC, GaN or Al2O3 on which GaN thin film can be directly epitaxially grown as a substrate layer (101), and epitaxially growing a GaN buffer layer (102) using one of MOCVD, MBE or HVPE techniques; b) Depositing SiO2 or SiN on the GaN buffer layer (102) using PECVD technology x as a mask layer (103); using standard ultraviolet lithography technology to achieve pattern transfer on the mask layer (103) to obtain a specially designed hexagonal array pattern, and further using RIE technology to etch away the hexagonal area to expose the hexagonal hole array of the GaN buffer layer (102) on the mask layer (103), thereby completing the preparation of the mask layer (103) containing the specific hole array; c) using an MOCVD system and utilizing the hexagonal hole array of the mask layer (103) to realize selective epitaxy and grow the bottom GaN channel layer (1041), wherein the growth conditions are as follows: a growth temperature of 1050-1080°C, a V / III ratio of 800-1500, a growth pressure of 600-760 Torr, and a total flow rate v (in sccm) of carrier gas introduced into the reaction chamber satisfies 50PA<760v<80PA, wherein P is the growth pressure (in Torr) and A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters); after the growth of the bottom GaN channel layer (1041) is completed, the growth temperature, V / III ratio and pressure are maintained unchanged, and the total flow rate v of carrier gas introduced into the reaction chamber is increased to 1.1-1.3 times to complete the growth of the remaining portion of the composite channel structure (104); d) using standard ultraviolet lithography technology to form an area on the composite channel structure (104) where a p-NiO layer (107) needs to be deposited; using magnetron sputtering to deposit NiO, the target material is high-purity metal nickel, and the sputtering conditions are as follows: the gases introduced are O2 and Ar, the sputtering power is 100-200W, and the gas pressure is 3-5mTorr; during the deposition process, the ratio of the introduced O2 to Ar is adjusted from the initial 7:3 to 5:5, and the oxygen flow rate is gradually reduced, and then the preparation of the p-NiO layer (107) is completed; similarly, using ultraviolet lithography technology to form a region on the p-NiO layer (107) where a p-NiO layer (107) needs to be sputtered + - NiO layer (108), deposited p + - NiO layer (108); e) In p + - coating the surface of the NiO layer (108) with photoresist, performing exposure and development, then depositing a gate electrode (109), preparing a corresponding source electrode (105) and a drain electrode (106) on the surface of the composite channel structure (104), and then performing a rapid annealing process; The preparation of this device structure is completed.

10. A structural feature and preparation method of a polycrystalline face structured RESURF GaN-based HEMT, characterized in that: The structural features of the device are arranged in order from bottom to top: a substrate layer (101), a GaN buffer layer (102) whose upward crystal plane is a (0002) plane, a mask layer (103) containing a specific hole array, a composite channel structure (104) in the holes of the mask layer (103) and in contact with the GaN buffer layer (102), a source electrode (105) and a drain electrode (106) located at both ends of the composite channel structure (104), a p-NiO layer (107) covering the composite channel structure (104) in a three-dimensional form, and a p-NiO layer (107) covering the p-NiO layer (107). + -NiO layer (108), covering the p + - A gate (109) on a NiO layer (108); wherein the hole of the mask layer (103) is a hexagonal long strip hole symmetrical along directions 1 and 2, the angle between any two adjacent sides is 120°, the two sides parallel to direction 1 are long sides with a length of a, and two sides at both ends of direction 1 with an angle of 60° to direction 1 are short sides with a length of b; the direction 1 is a lateral direction, and the direction 2 is a third direction perpendicular to both the lateral direction and the vertical direction; the composite channel structure (104) is a table structure extending upward from the long strip hole of the mask layer (103), and comprises 2 to 5 pairs of GaN channel layers (1041) and Indium channel layers (1042) arranged in sequence from bottom to top. x Al y Ga 1-x-y The N barrier layer (1042) has a bottom surface of (000-2) crystal plane and contacts the GaN buffer layer (102), a top surface of (0002) crystal plane, and the bottom and top surfaces are made of P m crystal planes m and P n The composite channel structure (104) is connected to a plurality of crystal planes n, and both the crystal planes m and n are inclined planes that are not perpendicular to the top plane; the source electrode (105) covers the inclined plane and the top plane on one side of the composite channel structure (104) along direction 1 in the form of ohmic contact, and the drain electrode (106) covers the inclined plane and the top plane on the other side of the composite channel structure (104) in the form of ohmic contact; the p-NiO layer (107) covers the surface of the composite channel structure (104) and does not contact the edge of the source electrode (105) and the edge of the drain electrode (106); + The p-NiO layer (108) covers the surface of the p-NiO layer (107) and is close to the source (105), and the gate (109) covers the p-NiO layer (107). + - the surface of the NiO layer (108); when P m and P n When the crystal planes are 3 and 6 respectively, the crystal plane m is a {1-102} plane, named m1 to m3, and the crystal plane n is a {11-23} plane, named n1 to n6; wherein two {11-23} planes: n1 and n2 extend along direction 1, and the bottoms are in contact with the long sides of the long strip holes of the mask layer (103), and the p-NiO layer (107) covers the n1 and n2; one side of the source electrode (105) includes two {11-23} planes m1 and m2. 1-102} plane and two {11-23} planes of n3 and n4, m1 and m2 are in contact with n1 and n2, n3 and n4 are in contact with each other and are in contact with m1 and m2 respectively; one side of the drain (106) is prepared to include a {1-102} plane of m3 and two {11-23} planes of n5 and n6, and n5 and n6 are in contact with n1 and n2, and m3 is in contact with n5 and n6; the preparation method of the device comprises the following steps: a) selecting one of commercially available Si, SiC, GaN or Al2O3 on which GaN thin film can be directly epitaxially grown as a substrate layer (101), and epitaxially growing a GaN buffer layer (102) using one of MOCVD, MBE or HVPE techniques; b) Depositing SiO2 or SiN on the GaN buffer layer (102) using PECVD technology x as a mask layer (103); using standard ultraviolet lithography technology to achieve pattern transfer on the mask layer (103) to obtain a specially designed hexagonal array pattern, and further using RIE technology to etch away the hexagonal area to expose the hexagonal hole array of the GaN buffer layer (102) on the mask layer (103), thereby completing the preparation of the mask layer (103) containing the specific hole array; c) using an MOCVD system and the hexagonal hole array of the mask layer (103) to realize selective epitaxy and grow the bottom GaN channel layer (1041), the growth conditions are as follows: growth temperature is 1050-1080°C, V / III ratio is 500-700, growth pressure is 600-760 Torr, and the total flow rate v (in sccm) of the carrier gas introduced into the reaction chamber satisfies 50PA<760v<80PA, and the flow rate Nv (in sccm) of NH3 satisfies 50A<Nv<100A; wherein P is the growth pressure (in Torr), and A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters); after the growth of the bottom GaN channel layer (1041) is completed, the growth temperature, V / III ratio and pressure are maintained unchanged, and the total flow rate v of the carrier gas introduced into the reaction chamber is increased to 1.1-1.3 times to complete the growth of the remaining part of the composite channel structure (104); d) using standard ultraviolet lithography technology to form an area on the composite channel structure (104) where a p-NiO layer (107) needs to be deposited; using magnetron sputtering to deposit NiO, the target material is high-purity metal nickel, and the sputtering conditions are as follows: the gases introduced are O2 and Ar, the sputtering power is 100-200W, and the gas pressure is 3-5mTorr; during the deposition process, the ratio of the introduced O2 to Ar is adjusted from the initial 7:3 to 5:5, and the oxygen flow rate is gradually reduced, and then the preparation of the p-NiO layer (107) is completed; similarly, using ultraviolet lithography technology to form a region on the p-NiO layer (107) where a p-NiO layer (107) needs to be sputtered + -NiO layer (108), deposited p + - NiO layer (108); e) In p + - A photoresist is coated on the surface of the NiO layer (108), exposed and developed, and then a gate (109) is deposited. A corresponding source (105) and drain (106) are prepared on the surface of the composite channel structure (104), and then a rapid annealing process is performed to complete the preparation of the device structure.

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