Transistor arrangement and method for measuring on-resistance of transistor arrangement

Abstract

A transistor device is disclosed. The invention relates to a transistor arrangement comprising a first transistor device (1) and a second transistor device (2), each comprising a load path and a control node (G1, G2) and each being at least partially integrated in a semiconductor body (100), with the load paths of the first transistor device (1) and the second transistor device (2) being connected in parallel. The transistor arrangement further comprises a first control pad (41) connected to a control node (G1) of the first transistor device (1) through a first resistor (31); and a second control pad (42) connected to a control node (G2) of the second transistor device (2) and connected to the first control pad (41) through a second resistor (32).

Description

Technical Field

[0001] The present disclosure generally relates to transistor devices and methods for measuring on-resistance of transistor devices. Background Art

[0002] The process of manufacturing power transistor devices such as power MOSFETs generally includes producing multiple power transistor devices at once based on a semiconductor wafer. Towards the end of the manufacturing process, the wafer is divided into individual semiconductor bodies (semiconductor dies), each of which includes at least one transistor device and which can be packaged later.

[0003] In many cases, it is desirable to measure the on-resistance of transistor devices included in one wafer before singulating the wafer and packaging the semiconductor die. This allows individual semiconductor dies to be discarded if the transistors contained therein do not meet certain on-resistance requirements before packaging consumes more resources and incurs more costs.

[0004] Measuring the on-resistance of wafer-level transistor devices can include using a test device that is capable of continuously operating individual transistor devices in an on-state and measuring the respective on-resistances. However, in some cases, the parasitic resistance of the test device associated with the on-resistance measurement inevitably adds to the on-resistance. This parasitic resistance may be generated by a conductive carrier (chuck) on top of which the wafer is mounted in the test device. The parasitic resistance added by the test device is typically low and, for example, in the milliohm range, so the parasitic resistance does not negatively affect the on-resistance measurement.

[0005] However, if the on-resistance is in the same range as the parasitic resistance, the parasitic resistance becomes a problem. Summary of the invention

[0006] What is needed is a transistor device and a corresponding method that can achieve relatively accurate on-resistance measurement even if the on-resistance is very low.

[0007] One example relates to a transistor arrangement. The transistor arrangement includes a first transistor device and a second transistor device, each including a load path and a control node, and each at least partially integrated in a semiconductor body, wherein the load paths of the first transistor device and the second transistor device are connected in parallel. The transistor arrangement also includes a first control pad connected to the control node of the first transistor device through a first resistor, and a second control pad connected to the control node of the second transistor device and connected to the first control pad through a second resistor.

[0008] Another example relates to a method. The method includes determining an on-resistance of a transistor device. The transistor device includes a first transistor device and a second transistor device, each including a load path and a control node, and each at least partially integrated in a semiconductor body, wherein the load paths of the first transistor device and the second transistor device are connected in parallel, a first control pad, which is connected to the control node of the first transistor device through a first resistor, and a second control pad, which is connected to the control node of the second transistor device and connected to the first control pad through a second resistor. Determining the on-resistance includes placing the semiconductor body on a conductive carrier, operating the first transistor device in an off state, operating the second transistor device in an on state, and measuring the resistance of a circuit path including the parallel connection of the load path and the carrier of the first and second transistor devices to obtain a first resistance, and calculating the on-resistance based on the first resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The following examples are explained with reference to the accompanying drawings. The accompanying drawings are used to illustrate certain principles and therefore only illustrate aspects necessary for understanding these principles. These drawings are not to scale. In the accompanying drawings, the same reference characters represent the same features.

[0010] Figure 1 schematically illustrates an example of a transistor arrangement comprising a first transistor device and a second transistor device, each transistor device being integrated in a semiconductor body;

[0011] Figure 2 The diagram shows Figure 1 Equivalent circuit diagram of a transistor device;

[0012] Figure 3 illustrates a wafer including a plurality of semiconductor bodies during a measurement process using a test apparatus;

[0013] Figure 4 illustrates in greater detail one semiconductor body of a wafer during a measurement process;

[0014] Figure 5-7 Shown according to Figure 2 Equivalent circuit diagrams to illustrate the different measurement steps;

[0015] Figures 8A-8B illustrates transistor cells of a first transistor device and a second transistor device according to an example;

[0016] Figures 9A-9B illustrates transistor cells of a first transistor device and a second transistor device according to another example;

[0017] Fig.10 shows a top view of a semiconductor body according to one example;

[0018] Fig.11 Shown according to Fig.10 Details of the top view;

[0019] Fig.12 The invention shows a region in which transistor cells of a first and a second transistor device are arranged adjacent to each other according to Fig.10 and 11 A vertical cross-sectional view of a semiconductor body;

[0020] Fig.13 The invention shows a region in which the control electrode of the transistor cell of the first transistor device is connected to the runner according to Fig.10 and 11 A vertical cross-sectional view of a semiconductor body;

[0021] Fig.14 The invention shows a method according to which the control electrode of the transistor cell of the second transistor device is connected to the control pad in the region where the control electrode of the transistor cell of the second transistor device is connected to the control pad. Fig.10 and 11 A vertical cross-sectional view of a semiconductor body;

[0022] Fig.15 illustrates one example for implementing a first resistor connected between a first control pad and a gate runner connected to a control electrode of a transistor cell of a first transistor device; and

[0023] Fig.16 An example for implementing a second resistor connected between a first control pad and a second control pad connected to a control electrode of a transistor cell of a second transistor device is illustrated. DETAILED DESCRIPTION

[0024] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings form part of the specification and are used for illustrative purposes to show examples of how the invention can be used and implemented. It should be understood that the features of the various embodiments described herein can be combined with each other unless specifically stated otherwise.

[0025] Figure 1 A transistor arrangement according to an example is schematically illustrated. The transistor arrangement comprises a first transistor device 1 and a second transistor device 2, each transistor device comprising a load path and a control node G1, G2. The first and second transistor devices 1, 2 are at least partially integrated in a (common) semiconductor body 100. "At least partially integrated" includes that at least the active device region of the transistor device is integrated in the semiconductor body 100. The transistor device may include further parts, such as electrodes, formed above the surface of the semiconductor body 100.

[0026] According to one example, the semiconductor body 100 includes a single crystalline semiconductor material. Examples of single crystalline semiconductor materials include silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), silicon germanium (SiGe), other III-V semiconductors, or germanium.

[0027] Figure 1 A semiconductor body 100 is schematically illustrated, in which the first and second transistor devices 1, 2 are at least partially integrated. The first and second transistor devices 1, 2 are represented by circuit symbols. For illustration purposes only, Figure 1 The circuit symbol illustrated in is the circuit symbol of an N-type enhancement type (normally closed) MOSFET. However, this is only an example. The transistor devices 1, 2 are not limited to being implemented as N-type normally open MOSFETs. Instead, the first and second transistor devices 1, 2 can be implemented as P-type devices or can also be implemented as normally closed devices. According to an example, the first and second transistor devices 1, 2 are transistor devices of the same type.

[0028] refer to Figure 1 The transistor device further comprises a first control pad 41 connected to the control node G1 of the first transistor device 1 via the first resistor 31, and a second control pad 42 connected to the control node G2 of the second transistor device 2. In addition, the second control pad 42 is connected to the first control pad 41 via the second resistor 32. The first and second resistors 31, 32 are formed by Figure 1 The circuit symbol in is shown.

[0029] refer to Figure 1 The transistor device comprises a first surface 101 and a second surface 102. The second surface 102 is opposite to the first surface 101 in a vertical direction z of the semiconductor body 100. The vertical direction is a direction perpendicular to the first and second surfaces 101, 102. According to an example, the first and second control pads 41, 42 are arranged on the first surface 101, such as Figure 1 As shown in the picture. Figure 1 An insulating layer that may be arranged between the control pads 41 , 42 and the semiconductor body 100 is not shown in FIG.

[0030] According to an example, the load path of the first and second transistor devices 1,2 is a circuit path connected between the first load electrode 43 and the second load electrode 44. Each of the first and second load electrodes 43,44 is common to the first and second transistor devices 1,2.

[0031] According to one example, the first and second transistor devices 1, 2 are vertical transistor devices. In this example, Figure 1As illustrated, a first load electrode 43 is formed over a first surface 101 of the semiconductor body 100 , and a second load electrode 44 is formed over a second surface 102 of the semiconductor body 100 .

[0032] Each of the first and second control pads 41, 42 and the first and second load electrodes 43, 44 includes a conductive material. Examples of the conductive material include metals such as aluminum (Al) or copper (Cu), or alloys such as AlCu.

[0033] As further explained herein below, each of the first and second control pads 41, 42 is configured to be contacted by a probe of a test device during a test process (measurement process). Therefore, each of the first and second control pads 41, 42 has a sufficiently large size to be contacted by a probe. According to an example, each of the first and second control pads 41, 42 is a planar control pad.

[0034] Furthermore, according to one example, in the completed transistor device, the first control pad 41 is configured to have a connector, such as a bonding wire or a clip, connected thereto. In this example, the size of the first control pad 41 is large enough to allow a connector to be connected thereto.

[0035] According to an example, the size of the first control pad 41 is larger than the size of the second control pad. According to an example, the size of the first control pad 41 is 1E5 square micrometers (μm 2 ) and 1E6μm 2 (=1 square millimeter (mm 2 )), and the size of the second control pad 42 is 1E4 square micrometers (μm 2 ) and 1E5 square micrometers (μm 2 According to an example, the size of the first control pad 41 is at least 10 times the size of the second control pad 42.

[0036] Referring to the above, the first and second transistor devices 1, 2 may be implemented as MOSFETs. In this example, the control nodes G1, G2 of the first and second transistor devices 1, 2 are gate nodes, and the load paths are drain-source paths, each extending between the drain node and the source node of the respective transistor device. In this example, the first and second control pads 41, 42 are gate pads, the first load electrode 43 is a source electrode or source pad, and the second load electrode 44 is a drain electrode.

[0037] Although the first and second transistor devices 1, 2 are not limited to being implemented as gate-controlled transistor devices, such as MOSFETs, the first and second control nodes G1, G2 are referred to as gate nodes, the first and second control pads 41, 42 are referred to as gate pads, the first load electrode 43 is referred to as the source electrode 43, and the second load electrode 44 is referred to as the drain electrode.

[0038] Figure 2 The diagram shows Figure 1 , which has first and second transistor devices 1 , 2 , first and second gate pads 41 , 42 , a source electrode 43 and a drain electrode 44 .

[0039] The manufacture of transistor devices typically involves the manufacture of a plurality of transistor devices using the same manufacturing process at the same time. The individual transistor devices are part of a wafer which is separated at the end of the manufacturing process in order to provide a plurality of individual semiconductor devices which can ultimately be packaged. An essential characteristic of a transistor device is the on-resistance, which is the resistance of the transistor device in the on-state. It is desirable to measure the on-resistance of transistor devices formed on the same wafer and to measure it on the wafer level, i.e. at the end of the manufacturing process and before the wafer is separated. In this case, transistor devices which do not meet predetermined requirements regarding the on-resistance can be discarded without incurring further costs, such as packaging.

[0040] Figure 3 Schematically illustrates a wafer 1 comprising a plurality of semiconductor bodies 100, each semiconductor body 100 having a Figure 1 and 2 A transistor device of the type shown is shown. The semiconductor body 100 is only Figure 3 For example, the contact pads are not shown. In addition, Figure 3 A test apparatus is schematically illustrated, the test apparatus being configured to evaluate individual transistor devices at the wafer level.

[0041] refer to Figure 3 , the kerf regions 110 are arranged between the semiconductor bodies 100 on the wafer 1. At the end of the manufacturing process, the wafer 1 is separated along the kerf regions 110, which are partially removed when the wafer 1 is separated.

[0042] The test device comprises a conductive carrier 200 on top of which the wafer 1 is arranged such that the second load electrodes 44 of the individual transistor devices are in contact with the carrier 200. Figure 4 In the figure, Figure 4 A more detailed diagram is given based on Figure 3 The conductive carrier 200 is also referred to as a chuck hereinafter.

[0043] Wafer 1 can be fixed in a suitable position on the top of chuck 200 in various ways. According to one example, chuck 200 includes a through hole (not shown) and is connected to a vacuum pump (also not shown). The vacuum pump is configured to generate a vacuum between wafer 1 and chuck 200 through the through hole so as to fix wafer 1 in a suitable position on the top of chuck 200.

[0044] refer to Figure 3 and Figure 4 , the test device further includes an evaluation device 500, which includes probes (needles) 501, 502, 503, which are configured to be connected to the gate pads 41, 42 and the source electrode 43 during the test process (evaluation process). During the test process, the first probe 501 is configured to contact the first gate pad 41, the second probe 502 is configured to contact the second gate pad 42, and the third probe 503 is configured to contact the source electrode 43. In addition, the evaluation device 500 is connected to the chuck 200 at a position not covered by the wafer 1. The electrical contact 504 between the chuck 200 and the evaluation device 500 is hereinafter referred to as the chuck contact 504, and is only Figure 3 Schematically illustrated in FIG.

[0045] Refer to the above, Figure 1 and 4 The first and second transistor devices 1 , 2 illustrated in are vertical transistor devices, which are transistor devices in which first and second load electrodes are formed on opposite surfaces 101 , 102 of a semiconductor body 100 .

[0046] Basically, you can use Figure 3 The type of test equipment shown measures the on-resistance of a vertical transistor device by operating the transistor device in an on-state, driving current through the load path (drain-source path) of the transistor device, and measuring the voltage drop across the load path. Figure 3 and Figure 4 As can be seen in Figure 1, only one of the two load path electrodes is directly accessible. The second load electrode is covered by the chuck. Therefore, the traditional method of measuring the voltage across the load path includes measuring the voltage between the accessible load electrode and the chuck, and calculating the on-resistance based on the measured voltage and the current flowing through the load path.

[0047] As long as the contact resistance between the load electrode adjacent to the chuck and the resistance of the chuck itself is low compared to the on-resistance, the conventional method provides acceptable results. However, if the sum of the contact resistance and the chuck resistance is in the same range as the on-resistance, the result obtained by measuring the on-resistance in the conventional manner is too inaccurate.

[0048] The transistor device with the first and second transistor devices explained above makes it possible to measure the on-resistance Ron of the transistor device in a more accurate manner, wherein the load paths of the first and second transistor devices are connected in parallel and each transistor device includes a control node G1, G2 connected to the corresponding gate pad 41, 42. The on-resistance Ron of the transistor device is the on-resistance of the transistor device when both transistor devices are in the on-state. During normal operation of the transistor device, that is, during operation of the transistor device outside the test equipment, the two transistor devices operate synchronously. That is, the two transistor devices 1, 2 are turned on or off synchronously. Therefore, both transistor devices 1, 2 contribute to the conductivity of the transistor device in the on-state.

[0049] Reference below Figure 5-7 Various ways are explained for determining the on-resistance Ron of a transistor arrangement comprising a first and a second transistor device 1, 2. Each of these figures shows an equivalent circuit diagram of a transistor arrangement during different measurement processes.

[0050] According to an example, determining the on-resistance Ron of the transistor device includes operating the first transistor device 1 in an off state (blocking state), operating the second transistor device 2 in an on state (conducting state), and measuring the resistance of a load path including the parallel connection of the first and second transistor devices 1, 2 and a circuit path of the chuck 200 to obtain a first resistance R1. Determining the on-resistance Ron of the transistor device also includes calculating the on-resistance Ron based on the first resistance R1.

[0051] The first transistor device 1 is turned on or off depending on the first drive voltage Vdrv1 received between the first gate pad 41 and the source electrode 43, wherein when the first drive voltage Vdrv1 is higher than the threshold voltage of the first transistor device 1, the first transistor device 1 is in the on state. When the first drive voltage Vdrv1 is lower than the threshold voltage, the first transistor device 1 is in the off state. According to an example, operating the first transistor device in the off state 1 includes applying the first drive voltage Vdrv1 having a cut-off level to the first gate pad 41 through the first probe 501. For example, the first drive voltage Vdrv1 is a voltage between the probe 501 and the ground node. For example, the first drive voltage Vdrv1 is provided by the voltage source 521 of the evaluation device 500. For example, in order to apply the first drive voltage Vdrv1 between the first gate pad 41 and the source electrode 43, the source electrode 43 is also connected to the ground node. For measurement purposes during measurement, the connection to the ground node may be provided by one of the probes connected to the source electrode 43, or may be provided by a separate probe connecting the source electrode 43 to the ground node.

[0052] The second transistor device 2 is turned on or off depending on the driving voltage Vdrv2 received between the second gate pad 42 and the source electrode 43, wherein when the driving voltage Vdrv2 is higher than the threshold voltage of the second transistor device, the second transistor device 2 is in the on state. When the driving voltage Vdrv2 is lower than the threshold voltage, the second transistor device 2 is in the off state. According to an example, the first and second transistor devices 1, 2 have substantially the same threshold voltage.

[0053] It should be noted that the second gate pad 42 is only used for testing purposes. In the completed transistor device, only the first gate pad 41 is used to drive the first and second transistor devices 1, 2. In the normal operation mode, the second gate pad 42 simply acts as a connector between the second resistor 32 and the gate node G2 of the second transistor device 2. In the normal operation mode, the first and second transistor devices 1, 2 receive the same drive voltage from the first gate pad 41. For example, the normal operation mode is the operation mode of the transistor device outside the test equipment and after the transistor device has been packaged.

[0054] According to an example, operating the second transistor device 2 in the on state includes applying a second driving voltage Vdrv2 having an on level to the second gate pad 42 through the second probe 502. For example, the second driving voltage Vdrv2 is a voltage between the second gate pad 42 and the ground node. For example, the second driving voltage Vdrv2 is provided by the voltage source 522 of the evaluation device 500.

[0055] refer to Figure 5 And as explained before, the second resistor 32 is connected between the first and second gate pads 41, 42. Figure 5 In the illustrated measurement process, the second resistor 32 absorbs the difference between the first and second driving voltages Vdrv1 , Vdrv2 applied to the first and second gate pads 41 , 42 .

[0056] according to Figure 5 In the illustrated example, measuring the first resistance R1 includes driving a predetermined measurement current Im1 by a current source 511 of the evaluation device 500 through a load path including the parallel connection of the first and second transistor devices 1 , 2 and a circuit path of the chuck 200 . Figure 5 Driving the measurement current Im1 includes driving the measurement current through a circuit path including the load path and the chuck 200 connected in parallel via the chuck contact 504 and the third probe 503 . Figure 5In the illustrated equivalent circuit diagram, resistor 201 represents the contact resistance between drain electrode 44 and chuck 200, and the internal resistance of chuck 200 between drain electrode 44 and chuck contact 504. The resistance R201 of this resistor is hereinafter referred to as the contact and chuck resistance. Other resistances in the evaluation circuit, such as the resistance of the third probe 503, can either be ignored or can be considered to be represented by resistor 201.

[0057] Measuring the first resistance R1 also includes measuring a voltage Vm1 between the chuck contact 504 and the source electrode 43 by means of a voltage sensor 513 of the evaluation device 500. According to one example, the voltage is measured between the chuck contact 504 and another probe 505 that is in contact with the source electrode 43 and is located at a position spaced apart from the third probe carrying the measurement current Im. The first resistance is given by the quotient of the measurement voltage Vm1 and the measurement current Im,

[0058]

[0059] and is calculated by the evaluation device 500 based on, for example, the measured voltage Vm1 and the measured current Im1.

[0060] When the first transistor device 1 is in the off state and the second transistor device is in the on state, the resistance of the parallel-connected load path is substantially equal to the on-resistance Ron2 of the second transistor device 2, which is the resistance of the second transistor device 2 in the on state. The on-resistance Ron2 of the second transistor device 2 is hereinafter referred to as the second on-resistance.

[0061] exist Figure 5 In the illustrated measurement process, the measured first resistance R1 is substantially equal to the second on-resistance Ron2 plus the contact and chuck resistance R201.

[0062] R1=Ron2+R201 (2).

[0063] According to an example, the size of the second transistor device 2 is much smaller than the size of the first transistor device 1. For example, the size of the second transistor device 2 is the area of ​​the active device area of ​​the second transistor device in the semiconductor body 100. For example, the size of the first transistor device is the area of ​​the active device area of ​​the first transistor device 1 in the semiconductor body 100. The on-resistance of vertical transistor devices such as the first and second transistor devices 1, 2 is at least approximately inversely proportional to the area of ​​their active device areas. This is well known and therefore no further explanation is needed in this regard.

[0064] Assuming that the second transistor device 2 is much smaller than the first transistor device 1, the second on-resistance Ron2 is much higher than the first on-resistance Ron1, which is the resistance of the first transistor device 1 in the on state. For example, if m defines the ratio between the size A1 of the first transistor device 1 and the size A2 of the second transistor device 2, m=A1 / A2, then the second on-resistance Ron2 depends on the first on-resistance Ron1 and the size ratio m, as follows:

[0065] Ron2=m·Ron1 (3).

[0066] According to one example, the size ratio m is at least 100, so that the second on-resistance Ron2 is at least 100 times the first on-resistance Ron1 (and the size of the first transistor 1 is at least 100 times the size of the second transistor 2). According to one example, the size ratio m is at least 1000 (1E3) or at least 10000 (1E4).

[0067] The on-resistance Ron of the transistor arrangement is the resistance of the load path connected in parallel when both transistor devices 1, 2 are in the on-state and is given by

[0068]

[0069] Considering equation (3), the on-resistance Ron depends on the first or second on-resistance Ron1, Ron2 as follows:

[0070]

[0071] The on-resistance Ron of the transistor device is lower than the smaller of the first and second on-resistances Ron1, Ron2. Assuming that the contact and chuck resistance R201 is of the same order of magnitude as the on-resistance Ron of the transistor device, and assuming that the second on-resistance Ron2 is much higher than the first on-resistance Ron1, and therefore much higher than the on-resistance Ron of the transistor device, the contact and chuck resistance R201 is much lower than the second on-resistance Ron2. In this case, the contact and chuck resistance R201 is negligible in equation (2), so the measured first resistance R1 is substantially equal to the second on-resistance Ron2,

[0072] R1≈Ron2 (6).

[0073] Referring to the above, when both transistor devices are in the on-state, the on-resistance Ron of the transistor arrangement is given by the resistance of the load path of the parallel connection of the first and second transistor devices. Based on the first measurement resistor R1, the known size ratio m and considering equations (3), (4) and (5), the on-resistance Ron of the transistor arrangement can be calculated by the evaluation device 500 as follows:

[0074]

[0075] As can be seen from equation (6), the on-resistance Ron of the transistor arrangement having the first and second transistor devices 1, 2 can be obtained by measuring the first resistor R1 and calculating the on-resistance Ron by taking into account the first resistor R1 and the size ratio m.

[0076] In addition to the first resistor R1, a more accurate on-resistance Ron of the transistor device can also be obtained by measuring the second resistor R2. An example for measuring the second resistor R2 is as follows: Figure 6 As shown. Figure 6 Measuring the second resistance R2 includes operating the first transistor device 1 in an on state, operating the second transistor device 2 in an off state, and measuring the resistance of a load path including the parallel connection of the first and second transistor devices 1 , 2 and a circuit path of the chuck 200 .

[0077] Operating the first transistor device 1 in an on-state may include applying a drive voltage Vdrv1 having an on-level to the first gate pad 41, the on-level being configured to turn on the first transistor device 1. Operating the second transistor device 2 in an off-state may include applying a second drive voltage Vdrv2 having an off-level to the second gate pad 42, the off-level being configured to turn off the second transistor device 2. In this operating state of the transistor device, the second resistor 32 absorbs the difference between the first and second drive voltages Vdrv1, Vdrv2. By driving a measurement current Im2 through a circuit path including a load path and the chuck 200 connected in parallel by a current source 511, and measuring a voltage Vm2 across the second path using a voltage sensor 513, a voltage Vm2 can be measured with reference to FIG. Figure 5 The second resistance R2 is measured in the same way as explained for the first resistance. The second resistance R2 is given by the quotient of the measured voltage Vm2 and the measured current Im2,

[0078]

[0079] Referring to equation (2), the first resistance R1 is at least approximately given by the second on-resistance Ron2 plus the chuck and contact resistance R201. Figure 6 The second resistance R2 obtained in the illustrated measurement process is at least approximately given by the first on-resistance Ron1 plus the chuck and contact resistance R201,

[0080] R2=Ron1+R201 (9).

[0081] Based on equations (2) and (8), the following relationship applies between the first and second on-resistances Ron1, Ron2 and the first and second measuring resistances R1, R2,

[0082] R1-R2=Ron2-Ron1 (10).

[0083] Based on the relationship according to equation (10), considering the relationship between the first and second on-resistances Ron1, Ron2 according to equation (3), and considering equation (4), the on-resistance Ron depends on the measured first and second resistances R1, R2 and the size ratio as follows:

[0084]

[0085] According to another example, the on-resistance Ron is obtained based on one of the measured first and second resistances R1, R2 and the measured third resistance R3. Measuring the third resistance R3 includes: operating the first transistor device 1 and the second transistor device 2 in an on state, driving the measurement current Im3 through a circuit path including a load path connected in parallel of the first and second transistor devices 1, 2, and measuring a voltage Vm3 ( Figure 7 ). Operating the first and second transistor devices 1, 2 in the on state includes applying a first drive voltage Vdrv1 having an on level to the first gate pad 41. In this example, based on the first drive voltage Vdrv1 received at the first gate pad 41, both the first and second transistor devices 1, 2 are operated in the on state.

[0086] The third resistor R3 is given by the quotient of the measurement voltage Im3 and the measurement current Vm3,

[0087]

[0088] The third resistor R3 is equal to the on-resistance Ron of the transistor device plus the contact and chuck resistance R201,

[0089]

[0090] According to one example, the on-resistance Ron is obtained based on measuring the first and third resistors R1, R3. In this example, considering equations (3) and (4), the on-resistance Ron depends on the first and third resistors R1, R3 and the size ratio m, as follows:

[0091]

[0092] According to another example, the on-resistance Ron is obtained based on measuring the second and third resistors R2, R3. In this example, considering equations (3) and (4), the on-resistance Ron depends on the second and third resistors R2, R3 and the size ratio m, as follows:

[0093] Ron=(R2-R3)·m (14).

[0094] According to another example, the on-resistance Ron is obtained based on the first, second and third resistors R1, R2, R3. In this example, a more accurate result of the on-resistance Ron that is independent of the size ratio can be obtained. Considering equations (6), (9) and (12), it can be shown that the on-resistance Ron is given by the first and second resistors R1, R2 and the contact and chuck resistance R201 as follows:

[0095]

[0096] The contact and chuck resistance R201 depends on the three measured resistances R1, R2, R3 as follows:

[0097]

[0098] Therefore, considering equations (15a) and (15b), based on the three measured resistances R1, R2, R3, an accurate value of the on-resistance Ron can be obtained that is independent of the size ratio m.

[0099] Referring to the above, the contact and chuck resistance R201 depends on the contact resistance between the drain electrode 44 of the transistor device and the chuck 200, and on the resistance of the chuck 200 itself, where the contact resistance may be dominant. The contact and chuck resistance R201 is an indicator of how well the wafer 1 is placed on the chuck 200 and in contact with the chuck 200. According to an example, the method includes obtaining the contact and chuck resistance R201 based on at least two of the three measured resistances R1, R2, R3.

[0100] Referring to equation (15b), based on the resistances measured by R1, R2, R3, an accurate value of the contact and chuck resistance R201 can be obtained. In addition, based on considering equation (3), using only two of the three measured resistances R1, R2, R3, a very good approximation of the contact and chuck resistance R201 can be obtained. For example, based on the first and second resistances R1, R2 and the size ratio m, the contact and chuck resistance R201 is given by

[0101]

[0102] The obtained value of the contact and chuck resistance R201 can be used to decide whether to realign the wafer 1 on the chuck 200. According to one example, the obtained contact and chuck resistance R201 is compared with a threshold value, and when the obtained contact and chuck resistance R201 is above the threshold value, the wafer is realigned.

[0103] Each of the first and second transistor devices 1 , 2 may include a plurality of transistor cells 10 , 20 . Figures 8A-9B Different examples of transistor cells 10, 20 are illustrated in FIG. Fig. 8A and 8B The diagram illustrates transistor cells 10, 20 of first and second transistor devices 1, 2 according to an example, and Figures 9A-9B Transistor cells 10, 20 of a first and a second transistor device 1, 2 according to another example are illustrated. According to an example, the transistor cell 10 of the first transistor device 1 and the transistor cell 20 of the second transistor device 2 are implemented in the same way.

[0104] refer to Fig. 8A and 8B , each transistor cell 10, 20 comprises a source region 11, 21 of a first doping type, a body region 12, 22 of a second doping type complementary to the first doping type, and a control electrode 15, 25. The control electrode 15, 25 (hereinafter also referred to as the gate electrode 15, 25) is adjacent to the body region 12, 22, is dielectrically insulated from the body region 12, 22 by a gate dielectric 16, 26, and is arranged in a gate trench extending from a first surface 101 of the semiconductor body 100 into the semiconductor body 100.

[0105] refer to Fig. 8A and 8B , the source regions 11, 21 and the body regions 12, 22 of two adjacent transistor cells 10, 20 can be arranged in the mesa region between adjacent gate trenches. In this example, the body regions 12, 22 of the two adjacent transistor cells 10, 20 can be formed by a continuous (contiguous) doped region of the second doping type. In addition, two (other) adjacent transistor cells can share gate electrodes 15, 25. That is, the gate electrodes 15, 25 of the two adjacent transistor cells can be formed by a continuous electrode arranged in a gate trench. The gate electrode 21 includes a conductive material. Examples of conductive materials include doped polysilicon or metal. For example, the gate dielectric 22 includes an oxide.

[0106] In the following, the transistor cell 10 of the first transistor device 2 is also referred to as a first transistor cell. Equivalently, the transistor cell 20 of the second transistor device 2 is also referred to as a second transistor cell.

[0107] The source regions 11, 21 and the body regions 12, 22 of the transistor cells 10, 20 are connected to the source electrode 43. Fig. 8A and 8BIn the illustrated example, the connection between the source electrode 43 and the source and body regions 11, 21, 12, 22 comprises a conductive via 45 extending from the source electrode 43 through an insulating layer 61 formed on the first surface 101 of the semiconductor body 100 to the source and body regions 11, 21, 12, 22. Optionally, a body contact region that is more highly doped than the body regions 12, 22 is formed between the via 45 and the body regions 12, 22 to provide an ohmic contact between the via 45 and the body regions 12, 22. However, such a body contact region is not formed in the Fig. 8A and 8B Medium picture.

[0108] refer to Fig. 8A and 8B , each of the first and second transistor devices 1, 2 further comprises a drift region 14, 24 of the first doping type. The drift region 14, 24 adjoins the body region 12, 22 of the transistor cell 10, 20, thereby forming a PN junction between the body region 12, 22 of the second doping type and the drift region 14, 24 of the first doping type. In the vertical direction, the drift region 14 is arranged between the body region 12 and the drain region 13, 23. For example, the drain region 13, 23 is of the first doping type. According to an example, the drain regions 13, 23 of the first and second transistor devices 1, 2 are formed by one continuous doped semiconductor layer 110 of the semiconductor body 100.

[0109] According to one example, the semiconductor layer 110 forming the drain regions 13 , 23 is a semiconductor substrate, on top of which an epitaxial layer 120 is grown, in which further active device regions such as drift regions 14 , 24 , source regions 11 , 21 and body regions 12 , 22 are formed.

[0110] refer to Fig. 8A and 8B , the gate electrodes 15, 25 are spaced apart from each other in a first lateral direction x of the semiconductor body 100. The first lateral direction x is a direction substantially parallel to the first and second surfaces 101, 102. According to an example, the gate electrodes 15, 25 are implemented as strip electrodes (elongated electrodes). In this example, the gate electrodes 15, 25 are elongated in a second lateral direction y perpendicular to the first lateral direction x.

[0111] exist Fig. 8A and 8B In the illustrated example, the respective body regions 12 , 22 are formed along both opposite sidewalls of the gate trench. Fig. 9A and 9B Shown according to Fig. 8A and 8B Modification of the transistor units 10 , 20 .

[0112] exist Fig. 9A , 9B In the illustrated example, the body region 12, 22 is formed only along one of the two opposite sidewalls of each gate trench. Along the opposite sidewall, a body contact region 17, 27 is formed extending from the first surface 101 in the vertical direction z of the semiconductor body 100. Fig. 9A and 9B As shown, in the vertical direction z, the body contact regions 17, 27 may be spaced apart from the trench bottom of the corresponding gate trench. According to another example (not shown), the body contact regions 17, 27 extend beyond the trench bottom in the vertical direction z. Optionally, a JFET region 18, 28 of the second doping type adjoins the body contact regions 17, 27. The body contact regions 17, 27 adjoin the body region 12 of the corresponding transistor cell and connect the body region 12 to the source electrode 43. The optional JFET regions 18, 28 together with the adjoining portion of the drift region 14 form a JFET that pinches off and protects the gate dielectric 16, 26 from high electric fields when the transistor device is in the off state. This is well known and therefore no further explanation is needed in this regard.

[0113] Fig.10 4 shows a top view of a transistor device according to an example. As explained above, the transistor device comprises a first gate pad 41, a second gate pad 42 and a source electrode 43. In addition, according to Fig.10 The transistor device includes a gate runner 46. The gate runner 46 passes through the first resistor 31 (at Fig.10 4 (not visible in the figure) is connected to the gate pad 41. In addition, the gate runner 46 is connected to the gate electrode 15 of the transistor cell 10 of the first transistor device 1. The gate electrode 15 of the transistor cell 10 of the first transistor device 1 forms the gate node G1 of the first transistor device 1. Therefore, in accordance with Fig.10 In the transistor device of FIG. 4 , the first gate pad 41 is connected to the gate node G1 of the first transistor device through the first resistor 31 and the gate runner 46. An example for implementing the first resistor 31 between the first gate pad 41 and the gate runner 46 is further explained herein below.

[0114] according to Fig.10 In the illustrated example, the second gate pad 42 is arranged between the first gate pad 41 and the source electrode 43. The gate electrode 25 of the second transistor cell 20 forms the gate node G2 of the second transistor device 2. The second gate pad 42 is connected to the gate electrode 25 of the second transistor cell 20.

[0115] Fig.10The transistor cells 10, 20 are not shown. Examples for connecting the gate electrode 15 of the first transistor cell 10 to the gate runner 46 and for connecting the gate electrode 25 of the second transistor cell 22 to the second gate pad 42 are explained further herein below.

[0116] Fig.11 An enlarged view of the first and second gate pads 41 , 42 and adjacent sections of the source electrode 43 and the gate runner 46 are shown. Fig.11 The first and second transistor cells 10, 20 are not shown in the figure. However, for the purpose of illustration, the positions of some gate electrodes 15 of the first transistor cell 10 under the source electrode 43 and the positions of some gate electrodes 25 of the second transistor cell 20 under the source electrode 43 are shown in FIG. Fig.11 Indicated by bold lines.

[0117] For example, Fig.10 and 11 The transistor cells of the first and second transistor devices 1, 2 of the illustrated transistor arrangement may correspond to Fig. 8A and 8B The transistor units 10, 20 or according to Fig. 9A and 9B Thus, for example, a gate electrode 15 cut through some of the gate electrodes 15 of the first transistor cell 10 Fig.11 The illustrated vertical section AA may correspond to Fig. 8A and 9A The vertical cross section AA shown in the figure. In addition, for example, the gate electrodes 25 of the second transistor unit 20 are cut through Fig.11 The vertical section BB shown may correspond to Figure 8B and 9B The vertical section BB is shown.

[0118] Figure 12-16 Picture shows Fig.11 The transistor device shown in the figure is Fig.11 Vertical cross-sectional views in additional vertical sections are shown.

[0119] Fig.12 The diagram shows Fig.11 A vertical cross-sectional view of a transistor device in section CC, which cuts through a portion of a gate electrode 15 of a first transistor cell 10 and an adjacent gate electrode 25 of a second transistor cell 20. Fig.11 and 12 In the illustrated example, the longitudinal direction of each of these gate electrodes 15 , 25 corresponds to the second lateral direction y explained before.

[0120] exist Fig.11 In the illustrated example, each gate electrode 25 of the second transistor cell 20 is adjacent to the gate electrode 15 of the first transistor cell 10. Fig.12 The doped regions corresponding to the body regions 12 , 22 of the first and second transistor cells 10 , 20 are arranged between adjacent gate electrodes 15 , 25 .

[0121] Each gate electrode 15 of the first transistor cell 10 is connected to the gate runner 46 at least at one longitudinal end. This includes that the gate electrode 15 may be connected to the gate runner 46 at only one of its two longitudinal ends, or may be connected to the gate runner 46 at both of its longitudinal ends. For example, those gate electrodes 15 of the first transistor cell 10 having one longitudinal end adjacent to the gate electrode 25 of the second transistor cell 20 may be connected to the gate runner 46 at only the opposite longitudinal end (at Fig.11 ) connected to the gate runner 46.

[0122] exist Fig.11 In the illustrated example, the gate runner 46 includes a gate runner portion arranged between the first gate pad 41 and the first transistor cell 10. In this example, the gate electrode 15 arranged adjacent to the first gate pad 41 may be connected to the gate runner 46 at both longitudinal ends. However, the portion of the gate runner 46 arranged between the first gate pad 41 and the first transistor cell 10 is optional and may be omitted. In this case, the electrode 15 arranged adjacent to the first gate pad 41 is connected to the gate runner 46 only at one longitudinal end, i.e., longitudinally and away from the first gate pad 41.

[0123] Fig.13 An example for connecting the gate electrode 15 of the first transistor cell 10 to the gate runner 46 is shown. Fig.11 A vertical cross-sectional view of the transistor arrangement in section DD is shown. Section DD cuts through a portion of the gate electrode 15, a portion of the gate runner 46 and a portion of the source electrode 43 of the first transistor cell 10. Fig.13 In the illustrated example, the gate electrode 15 is connected to the gate runner 46 via a conductive via 54 extending from the gate runner 46 through the insulating layer 61 to the gate electrode 15. To this end, the gate electrode 15 extends below the gate runner 46 in the second lateral direction y.

[0124] by Fig.13The illustrated manner of connecting the gate electrode 15 to the gate runner 46 is only an example. Any other electrical connector extending from the gate runner 46 to the gate electrode 15 in the insulating layer 61 may also be used. In order to connect the gate electrode 15 to the gate runner 46, the gate electrode 15 does not necessarily need to extend under the gate runner 46 in the second lateral direction y. Instead, the electrical connector between the gate runner 46 and the gate electrode 15 may extend to a certain extent in the second lateral direction y in order to connect the gate runner 46 to the gate electrode 15.

[0125] exist Fig.14 An example for connecting the gate electrode 25 of the second transistor unit 20 to the second gate pad 42 is shown in FIG. Fig.11 A vertical cross-sectional view of the transistor device in section EE is shown. Section EE cuts through a portion of the gate runner 25 of the second transistor cell 20, a portion of the second gate pad 42 and a portion of the source electrode 43. Fig.13 In the illustrated example, the gate electrode 25 is connected to the second gate pad 42 via a conductive via 54 extending from the second gate pad 42 through the insulating layer 61 to the gate electrode 25. To this end, the gate electrode 25 extends below the second gate pad 42 in the second lateral direction y.

[0126] by Fig.14 The illustrated manner of connecting the gate electrode 25 to the second gate pad 42 is only an example. Any other electrical connector extending from the second gate pad 42 to the gate electrode 25 in the insulating layer 61 may also be used. In order to connect the gate electrode 25 to the second gate pad 42, the gate electrode 25 does not have to extend below the second gate pad 42 in the second lateral direction y. Instead, the electrical connector between the second gate pad 25 and the gate electrode 25 may extend to a certain extent in the second lateral direction y in order to connect the second gate pad 45 to the gate electrode 25.

[0127] Fig.15 An example of the first resistor 31 connected between the first gate pad 41 and the gate runner 46 is shown. More specifically, Fig.15 A vertical cross-section in section FF is illustrated, which cuts through a portion of the transistor arrangement in which the first resistor 31 is implemented.

[0128] refer to Fig.15, the first resistor 31 includes a resistance layer 311 formed in the insulating layer 61 below the first gate pad 41 and the gate runner 46. For example, the resistance layer 311 is a doped polysilicon layer. The resistance layer 311 is connected to the first gate pad 41 through a first conductive via 313 and is connected to the gate runner 46 through a second conductive via 312. The first and second conductive vias 313, 312 are spaced apart from each other. By appropriately selecting the resistivity of the resistance layer 311, the distance between the first and second conductive vias 313, 312, and the distance between the first and second conductive vias 313, 312 and the distance between the first and second conductive vias perpendicular to the Fig.15 The size in the direction of the illustrated cross section can adjust the resistance of the first resistor 31. Basically, the higher the resistivity of the resistor layer 311, the higher the resistance; the larger the distance between the conductive vias 313 and 312, the higher the resistance; and the vias 313 and 312 are perpendicular to the Fig.15 The shorter the dimension in the direction of the illustrated cross section, the higher the resistance.

[0129] Fig.16 An example of a second resistor 32 connected between the first and second gate pads 41, 42 is shown. More specifically, Fig.16 A vertical cross-section in section GG is shown, which cuts through a portion of the transistor arrangement in which the second resistor 32 is implemented.

[0130] The second resistor 32 can be implemented similarly to the first resistor 31. That is, referring to Fig.16 , the second resistor 32 may include a resistive layer 321 formed in an insulating layer below the first and second gate pads 41, 42. For example, the resistive layer 321 is a doped polysilicon layer. The resistive layer 321 is connected to the first gate pad 41 through a first conductive via 322, and is connected to the second gate pad 42 through a second conductive via. Any of the above explanations about adjusting the resistance of the second resistor 32 by appropriately selecting the resistivity of the resistive layer 321, the distance between the conductive vias 322, 323, and their sizes are applicable to adjusting the resistance of the second resistor 32 accordingly.

[0131] Referring to the above, in the normal operation mode of the transistor device, the first and second transistor devices 1, 2 are driven by the same driving voltage applied between the first gate pad 41 and the source electrode 43. Therefore, after the wafer 1 is divided into individual transistor devices and before packaging, the bonding wire, the clip, etc. are connected only to the first gate pad 41 to provide an external path to the first gate pad 41. Referring to the above, in the normal operation mode, the driving voltage applied to the first gate pad 41 is provided to the gate node G1 of the first transistor device 1 through the first resistor 31, and is provided to the gate node G2 of the second transistor device 2 through the second resistor 32. Referring to the above, the second resistor 32 makes it possible to apply different driving voltages to the first and second gate pads 41, 42 during the measurement process (test process).

[0132] According to one example, in the completed transistor device, a first connector, such as a bonding wire or a clip, is connected to the first gate pad 41. The first connector connected to the first gate pad 41 is electrically coupled to the second gate pad 42 through the first resistor 31, so that the first connector is used to control both the first transistor device 1 and the second transistor device 2. Therefore, in order to control the operation of the second transistor device 2, in addition to the first connector, no additional connector directly connected to the second gate pad 42 is required in the transistor device. Therefore, in the completed transistor device, one or more connectors may be directly connected only to the first gate pad 41, while the second gate pad 42 has no connector, such as a clip or a bonding wire, directly connected thereto.

[0133] According to an example, the second resistance R32 of the second resistor 32 is adapted to the first resistance R31 of the first resistor 31. According to an example, the second resistance R32 is greater than the first resistance R31. Each of the first and second transistor devices 1, 2 explained previously in this document includes a respective capacitance (gate-source capacitance) C1, C2 between the respective gate node G1, G2 and the source electrode 43. This capacitance C1, C2 forms an RC element in combination with the respective resistors R1, R2, which affects the switching speed of the respective transistor devices 1, 2. The RC constant of the RC element of the first transistor device 1 is given by the capacitance C1 multiplied by the first resistance R31, and the RC constant of the RC element of the second transistor device 2 is given by the capacitance C2 multiplied by the second resistance R32. Basically, the lower the RC constant, the higher the switching speed.

[0134] According to an example, the first and second resistors are adapted to each other such that the first and second transistor devices 1, 2 have at least approximately the same RC constant such that the first and second transistor devices 1, 2 are switched on and off at least approximately synchronously. According to an example, this is achieved by adapting the first and second resistors 31, 32 to each other such that the second resistor R32 is proportional to the first resistor R31, wherein the ratio between the first and second capacitors C1, C2 is the proportionality factor,

[0135]

[0136] Basically, the larger the size of the transistor device, the higher the capacitance. In addition, the capacitance is at least approximately proportional to the size of the corresponding transistor device. With this in mind and considering equation (17), according to one example, the second resistor R32 is proportional to the first resistor R31, where the size ratio m is the proportionality factor,

[0137] R32 = m·R31 (18).

[0138] Some aspects explained above are briefly summarized below with reference to numbered examples.

[0139] Example 1. A transistor arrangement comprising: a first transistor device and a second transistor device, each comprising a load path and a control node, and each at least partially integrated in a semiconductor body, wherein the load paths of the first transistor device and the second transistor device are connected in parallel; a first control pad connected to the control node of the first transistor device through a first resistor; and a second control pad connected to the control node of the second transistor device and connected to the first control pad through a second resistor.

[0140] Example 2. The transistor device according to Example 1, wherein the load path of the first transistor device is a circuit path between a first load electrode arranged above a first surface of the semiconductor body and a second load electrode arranged above a second surface opposite to the first surface of the semiconductor body; and wherein the load path of the second transistor device is a circuit path between the first load electrode and the second load electrode.

[0141] Example 3. The transistor device according to Example 1 or 2, wherein the first transistor device comprises a plurality of first transistor cells, each of the first transistor cells comprising a control electrode, wherein the second transistor device comprises a plurality of second transistor cells, each of the second transistor cells comprising a control electrode, wherein a control node of the first transistor device is formed by the control electrodes of the first transistor cells, and wherein a control node of the second transistor device is formed by the control electrodes of the second transistor cells.

[0142] Example 4. The transistor arrangement according to example 3, wherein a control electrode of the first transistor cell is connected to a conductive gate runner formed over the first surface of the semiconductor body, and wherein the gate runner is connected to the first control pad via a first resistor.

[0143] Example 5. The transistor device according to any of Examples 2 to 4, wherein the first and second control pads are formed over the first surface of the semiconductor body.

[0144] Example 6. The transistor device according to Example 5, wherein the first resistor is formed in an insulating layer formed over the first surface of the semiconductor body.

[0145] Example 7. The transistor device of Example 6, wherein the first resistor comprises a doped polysilicon layer.

[0146] Example 8. The transistor device according to any of Examples 5 to 7, wherein the second resistor is formed in an insulating layer formed over the first surface of the semiconductor body.

[0147] Example 9. The transistor device of Example 8, wherein the second resistor comprises a doped polysilicon layer.

[0148] Example 10. The transistor arrangement of any of the preceding examples, wherein a ratio between the resistance of the second resistor and the resistance of the first resistor is at least approximately equal to a ratio between a size of the first transistor device and a size of the second transistor device.

[0149] Example 11. The transistor device according to any of the preceding examples, wherein a ratio between a size of the first transistor device and a size of the second transistor device is at least 100, at least 1000 or at least 10000.

[0150] Example 12. The transistor arrangement according to any of the preceding examples, wherein each of the first and second transistor devices is a MOSFET.

[0151] Example 13. A method comprising: determining an on-resistance of a transistor device, wherein the transistor device comprises: a first transistor device and a second transistor device, each comprising a load path and a control node, and each being at least partially integrated in a semiconductor body, wherein the load paths of the first transistor device and the second transistor device are connected in parallel; a first control pad connected to the control node of the first transistor device through a first resistor; a second control pad connected to the control node of the second transistor device and connected to the first control pad through a second resistor, and wherein determining the on-resistance comprises: placing the semiconductor body on a conductive carrier; operating the first transistor device in an off state, operating the second transistor device in an on state, and measuring a resistance of a circuit path including the parallel-connected load path of the first and second transistor devices and the carrier to obtain a first resistance; and calculating the on-resistance based on the first resistance.

[0152] Example 14. The method of Example 13, wherein operating the first transistor device in an off state comprises applying a first drive voltage having an off level to the first control pad, and wherein operating the second transistor device in an on state comprises applying a second drive voltage having an on level to the second control pad.

[0153] Example 15. The method of example 13 or 14, wherein calculating the on-resistance based on the first resistance comprises multiplying the first resistance by a size factor that depends on a ratio between a size of the second transistor device and a size of the first transistor device.

[0154] Example 16. The method of Example 15, wherein calculating the on-resistance comprises calculating: Here, R1 represents a first resistor, and m represents a ratio between a size of the second transistor and a size of the first transistor.

[0155] Example 17. The method according to Example 13 or 14, further comprising: operating the first transistor device in an on state, operating the second transistor device in an off state, and measuring the resistance of a circuit path including a load path and a carrier connected in parallel of the first and second transistor devices to obtain a second resistance; and further calculating the on resistance based on the second resistance.

[0156] Example 18. The method of Example 17, wherein calculating the on-resistance comprises calculating: Here, R1 represents a first resistor, R2 represents a second resistor, and m represents a ratio between a size of the second transistor and a size of the first transistor.

[0157] Example 19. The method according to Example 18 further includes: operating each of the first transistor device and the second transistor device in an on state, and measuring a resistance of a circuit path including a load path and a carrier connected in parallel of the first and second transistor devices to obtain a third resistance; and further calculating the on resistance based on the third resistance.

[0158] Example 20. The method according to Example 13 or 14, further comprising: operating each of the first transistor device and the second transistor device in an on state, and measuring a resistance of a circuit path including a load path and a carrier connected in parallel of the first and second transistor devices to obtain a third resistance; and further calculating the on resistance based on the third resistance.

[0159] Example 21. The method of Example 20, wherein calculating the on-resistance comprises calculating: Here, R1 represents a first resistor, R2 represents a second resistor, and m represents a ratio between a size of the first transistor and a size of the second transistor.

[0160] Example 22. The method according to Example 19 further includes: operating the first transistor device in an on state, operating the second transistor device in an off state, and measuring the resistance of a circuit path including a load path and a carrier connected in parallel of the first and second transistor devices to obtain a second resistance; and further calculating the on resistance based on the second resistance.

[0161] Example 23. The method of any of Examples 13 to 21, wherein the semiconductor body is part of a wafer including a plurality of semiconductor bodies.

[0162] Example 24. The method of any one of Examples 13 to 22, further comprising: obtaining a contact resistance and a carrier resistance based on at least two measured resistances.

[0163] Example 25. The method of Example 24, further comprising: comparing the obtained contact and carrier resistance to a threshold value, and realigning the wafer on the carrier when the obtained contact and carrier resistance is greater than the threshold value.

Claims

1. A transistor device comprising: A first transistor device (1) and a second transistor device (2), each comprising a load path and a control node (G1, G2), and each at least partially integrated in a semiconductor body (100), wherein the load paths of the first transistor device (1) and the second transistor device (2) are connected in parallel; a first control pad (41) connected to a control node (G1) of a first transistor device (1) via a first resistor (31); and A second control pad (42) connected to the control node (G2) of the second transistor device (2) and connected to the first control pad (41) through a second resistor (32).

2. The transistor device according to claim 1, wherein the load path of the first transistor device (1) is a circuit path between a first load electrode (43) arranged above a first surface (101) of the semiconductor body (100) and a second load electrode (44) arranged above a second surface (102) opposite to the first surface (101) of the semiconductor body (100); and The load path of the second transistor device (1) is a circuit path between the first load electrode (43) and the second load electrode (44).

3. The transistor device according to claim 1 or 2, The first transistor device (1) comprises a plurality of first transistor units (10), each of the first transistor units comprises a control electrode (15), The second transistor device (2) comprises a plurality of second transistor units (20), each second transistor unit comprising a control electrode (25), wherein the control node (G1) of the first transistor device (1) is formed by the control electrode (15) of the first transistor unit (10), and The control node (G2) of the second transistor device (2) is formed by the control electrode (25) of the second transistor unit (20).

4. The transistor device according to claim 3, wherein a control electrode (15) of the first transistor unit (10) is connected to a conductive gate runner (46) formed above a first surface (101) of the semiconductor body (100), and The gate runner (46) is connected to the first control pad (41) through the first resistor (31).

5. The transistor arrangement according to any one of claims 2 to 4, Wherein first and second control pads (41, 42) are formed above a first surface (101) of a semiconductor body (100).

6. The transistor device according to claim 5, The first resistor (31) is formed in an insulating layer (61) formed above a first surface (101) of a semiconductor body (100).

7. The transistor device according to claim 6, The first resistor (31) comprises a doped polysilicon layer (311).

8. The transistor arrangement according to any one of claims 5 to 7, The second resistor (32) is formed in an insulating layer (61) formed above a first surface (101) of a semiconductor body (100).

9. The transistor device according to claim 8, The second resistor (32) includes a doped polysilicon layer (321).

10. A transistor arrangement according to any one of the preceding claims, The ratio between the resistances of the second resistor (32) and the first resistor (31) is at least approximately equal to the ratio between the size of the first transistor device (1) and the size of the second transistor device (2).

11. A transistor arrangement according to any one of the preceding claims, The ratio between the size of the first transistor device (1) and the size of the second transistor device (2) is at least 100, at least 1000 or at least 10000.

12. A transistor arrangement according to any one of the preceding claims, Each of the first and second transistor devices (1, 2) is a MOSFET.

13. A method comprising: Determine the on-resistance of the transistor device, The transistor device comprises: A first transistor device (1) and a second transistor device (2), each comprising a load path and a control node (G1, G2), and each at least partially integrated in a semiconductor body (100), wherein the load paths of the first transistor device (1) and the second transistor device (2) are connected in parallel; a first control pad (41) connected to a control node (G1) of a first transistor device (1) via a first resistor (31); a second control pad (42) connected to the control node (G2) of the second transistor device (2) and to the first control pad (41) through a second resistor (32), and Determining the on-resistance includes: placing a semiconductor body (100) on a conductive carrier (200); operating the first transistor device (1) in an off state, operating the second transistor device (2) in an on state, and measuring the resistance of a circuit path including a load path connected in parallel of the first and second transistor devices (1, 2) and a carrier (200) to obtain a first resistance; and The on-resistance is calculated based on the first resistor (R1).

14. The method according to claim 13, The operation of operating the first transistor device (1) in an off state comprises applying a first driving voltage (Vdrv1) having an off level to the first control pad (41), and Wherein operating the second transistor device (2) in a conductive state includes applying a second driving voltage (Vdrv2) having a conductive level to a second control pad (42).

15. The method according to claim 13 or 14, Calculating the on-resistance based on the first resistance (R1) comprises multiplying the first resistance by a size factor (m), the size factor depending on the ratio between the size of the second transistor device (2) and the size of the first transistor device (1).

16. The method according to claim 15, The calculation of on-resistance includes the calculation of: Wherein R1 represents the first resistor, and m represents the ratio between the size of the second transistor (2) and the size of the first transistor (1).

17. The method according to claim 13 or 14, further comprising: operating the first transistor device (1) in an on state, operating the second transistor device (2) in an off state, and measuring the resistance of a circuit path including a load path connected in parallel of the first and second transistor devices (1, 2) and a carrier (200) to obtain a second resistance (R2); and The on-resistance is further calculated based on the second resistor (R2).

18. The method according to claim 17, The calculation of on-resistance includes the calculation of: Wherein R1 represents the first resistor, R2 represents the second resistor, and m represents the ratio between the size of the second transistor (2) and the size of the first transistor (1).

19. The method according to claim 18, Also includes: operating each of the first transistor device (1) and the second transistor device in an on state, and measuring a resistance of a circuit path including a load path connected in parallel of the first and second transistor devices (1, 2) and a carrier (200) to obtain a third resistance (R3); and The on-resistance (Ron) is further calculated based on the third resistor (R3).

20. The method according to claim 13 or 14, further comprising: operating each of the first transistor device (1) and the second transistor device in an on state, and measuring a resistance of a circuit path including a load path connected in parallel of the first and second transistor devices (1, 2) and a carrier (200) to obtain a third resistance (R3); and The on-resistance (Ron) is further calculated based on the third resistor (R3).

21. The method according to claim 20, The calculation of on-resistance includes the calculation of: Wherein R1 represents the first resistor, R2 represents the second resistor, and m represents the ratio between the size of the first transistor (1) and the size of the second transistor (2).

22. The method of claim 19, further comprising: operating the first transistor device (1) in an on state, operating the second transistor device (2) in an off state, and measuring the resistance of a circuit path including a load path connected in parallel of the first and second transistor devices (1, 2) and a carrier (200) to obtain a second resistance (R2); and The on-resistance (Ron) is further calculated based on the second resistor (R2).

23. The method according to any one of claims 13 to 21, The semiconductor body (100) is part of a wafer (1) comprising a plurality of semiconductor bodies (100).

24. The method according to any one of claims 13 to 22, further comprising: A contact and carrier resistance (R201) is obtained based on at least two measured resistances (R1, R2, R3).

25. The method according to claim 24, further comprising: The obtained contact and carrier resistance (R201) is compared with a threshold value, and when the obtained contact and carrier resistance (R201) is greater than the threshold value, the wafer (1) on the carrier (200) is realigned.

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