Array substrate, preparation method thereof and display panel

Abstract

The invention provides an array substrate, a preparation method thereof and a display panel. The array substrate comprises a substrate, a first oxide active layer, a second oxide active layer, a switch transistor and a driving transistor, the first oxide active layer is located on one side of the substrate, and the first oxide active layer comprises a first part; the second oxide active layer is located on one side, far away from the substrate, of the first oxide active layer, and the second oxide active layer comprises a first active part; the switching transistor is located on the substrate and comprises a first part; the driving transistor is located on the substrate, the driving transistor comprises a driving active layer, the driving active layer comprises a first active part, and the carrier concentration in the first active part is larger than that in the first part.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] Indium Gallium Zinc Oxide (IGZO) thin film transistors have the advantages of high mobility, low power consumption, and large-area uniform film formation, and are therefore widely used in large-size organic light-emitting diode (OLED) display panels. However, IGZO thin film transistors are difficult to simultaneously meet the different requirements of large-size OLED display panels for switching transistors and driving transistors, such as requiring low leakage current for switching transistors and high on-state current for driving transistors.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art. Summary of the invention

[0004] In one aspect, an array substrate is provided, comprising a substrate, a first oxide active layer, a second oxide active layer, a switching transistor and a driving transistor; the first oxide active layer is located on one side of the substrate, and the first oxide active layer comprises a first portion; the second oxide active layer is located on a side of the first oxide active layer away from the substrate, and the second oxide active layer comprises a first active portion; the switching transistor is located on the substrate, and the switching transistor comprises the first portion; the driving transistor is located on the substrate, and the driving transistor comprises a driving active layer, and the driving active layer comprises the first active portion, wherein a carrier concentration in the first active portion is greater than a carrier concentration in the first portion.

[0005] According to some exemplary embodiments, the array substrate also includes a third oxide active layer and a first capacitor; the third oxide active layer is located on a side of the second oxide active layer away from the substrate, and the third oxide active layer includes a first conductive portion; the first capacitor is located on the substrate, the first capacitor includes a first electrode plate, the first electrode plate includes the first conductive portion, wherein the carrier concentration in the first conductive portion is greater than the carrier concentration in the first active portion.

[0006] According to some exemplary embodiments, the first oxide active layer further includes a second portion, the driving active layer further includes the second portion, and the first active portion is located on a side of the second portion away from the substrate.

[0007] According to some exemplary embodiments, the third oxide active layer also includes a second conductive portion and a third conductive portion, the driving active layer also includes the second conductive portion and the third conductive portion, and the second conductive portion and the third conductive portion are located on the side of the first active portion away from the substrate; the driving transistor also includes a first source and a first drain; the first source is connected to the second conductive portion; the first drain is connected to the third conductive portion.

[0008] According to some exemplary embodiments, the first oxide active layer also includes a third portion, the first electrode plate also includes the third portion, and the first conductive portion is located on a side of the third portion away from the substrate; and / or the second oxide active layer also includes a second active portion, the first electrode plate also includes the second active portion, and the first conductive portion is located on a side of the second active portion away from the substrate.

[0009] According to some exemplary embodiments, a ratio of a carrier concentration in the first conductive portion to a carrier concentration in the first portion is greater than or equal to 4.

[0010] According to some exemplary embodiments, a ratio of a carrier concentration in the first conductive portion to a carrier concentration in the first active portion is greater than or equal to 2.

[0011] According to some exemplary embodiments, the array substrate also includes a gate insulating layer and a first metal layer; the gate insulating layer is located on a side of the first oxide active layer, the second oxide active layer and the third oxide active layer away from the substrate; the first metal layer is located on a side of the gate insulating layer away from the substrate, and the first metal layer includes a first electrode, a second electrode and a third electrode; the driving transistor includes the first electrode, the switching transistor includes the second electrode, and the first capacitor includes the third electrode.

[0012] According to some exemplary embodiments, the array substrate further includes an interlayer insulating layer, the interlayer insulating layer is located on a side of the first metal layer away from the substrate, and a material of the interlayer insulating layer is the same as a material of the gate insulating layer.

[0013] According to some exemplary embodiments, the array substrate further includes a light-shielding metal layer, and the orthographic projections of the first oxide active layer, the second oxide active layer, and the third oxide active layer on the substrate are located within the orthographic projection of the light-shielding metal layer on the substrate.

[0014] In another aspect, a display panel is provided, comprising the array substrate as described above.

[0015] On the other hand, a method for preparing an array substrate is provided, the method comprising: forming a first oxide active layer on one side of a substrate, the first oxide active layer including a first part; forming a second oxide active layer on a side of the first oxide active layer away from the substrate, the second oxide active layer including a first active part, the carrier concentration in the second oxide active layer being greater than the carrier concentration in the first oxide active layer; and forming a switching transistor and a driving transistor on the substrate, the switching transistor including the first part, the driving transistor including a driving active layer, and the driving active layer including the first active part.

[0016] According to some exemplary embodiments, the method for preparing the array substrate also includes: forming a third oxide active layer on a side of the second oxide active layer away from the substrate, the third oxide active layer including a first conductive portion, and a carrier concentration in the third oxide active layer being greater than a carrier concentration in the second oxide active layer; and forming a first capacitor on the substrate, the first capacitor including a first electrode plate, and the first electrode plate including the first conductive portion.

[0017] According to some exemplary embodiments, oxygen and argon are introduced during the formation of the first oxide active layer, wherein the oxygen content is greater than or equal to 50% and less than or equal to 60%; and oxygen and argon are introduced during the formation of the second oxide active layer, wherein the oxygen content is greater than or equal to 20% and less than or equal to 35%.

[0018] According to some exemplary embodiments, oxygen and argon are introduced during the process of forming the third oxide active layer, wherein the content of oxygen is greater than or equal to 5% and less than or equal to 10%. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Other objects and advantages of the present disclosure will be apparent from the following description of the present disclosure with reference to the accompanying drawings, and will help to have a comprehensive understanding of the present disclosure.

[0020] Figure 1a A schematic plan view of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0021] Figure 1b Schematically shows the Figure 1a The cross-sectional schematic diagram of the array substrate along the AA direction is shown.

[0022] Figure 1c An equivalent circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure is schematically shown.

[0023] Figure 2A flow chart of a method for preparing an array substrate according to some embodiments of the present disclosure is schematically shown.

[0024] Figure 3a to Figure 3g The schematic diagram schematically shows the structures of various components in the process flow of preparing an array substrate according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0025] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of various exemplary embodiments. However, it is apparent that various exemplary embodiments may be implemented without these specific details or with one or more equivalent arrangements. In addition, various exemplary embodiments may be different, but not necessarily exclusive. For example, the specific shapes, configurations, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0026] In the accompanying drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. Thus, the size and relative size of the individual elements are not necessarily limited to the size and relative size shown in the drawings. When the exemplary embodiments may be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0027] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element may be directly on, directly connected to, or directly coupled to another element, or there may be intermediate elements. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly coupled to" another element, there are no intermediate elements. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", or "on" versus "directly on", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection.

[0028] It should be understood that, although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the exemplary embodiment, the first element may be named as the second element, and similarly, the second element may be named as the first element.

[0029] In the related art, it is difficult for IGZO thin-film transistors to simultaneously meet the different requirements of large-size OLED display panels for switch transistors and drive transistors, such as requiring low leakage current for switch transistors and high on-state current for drive transistors. Therefore, in order to solve at least one aspect of the above technical problems, the embodiments of the present disclosure provide an array substrate and a preparation method thereof, and a display panel, which are conducive to reducing the leakage current of the switch transistor and increasing the on-state current of the drive transistor.

[0030] Figure 1a is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 1b is based on Figure 1a The cross-sectional schematic diagram of the array substrate along the AA direction is shown. Figure 1c is an equivalent circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure.

[0031] Reference Figure 1a to Figure 1c In the array substrate, a plurality of pixel driving circuits PX are provided. The pixel driving circuits PX may include a plurality of components such as a switching transistor S1 and a driving transistor D1.

[0032] In some embodiments of the present disclosure, Figure 1b As shown, the array substrate includes a substrate 10, a first oxide active layer 30, a second oxide active layer 40, a switch transistor S1, and a drive transistor D1. The first oxide active layer 30 is located on one side of the substrate 10, and the first oxide active layer 30 includes a first portion 301. The second oxide active layer 40 is located on a side of the first oxide active layer 30 away from the substrate 10, and the second oxide active layer 40 includes a first active portion 401. The switch transistor S1 is located on the substrate 10, and the switch transistor S1 includes the first portion 301. The drive transistor D1 is located on the substrate 10, and the drive transistor D1 includes a drive active layer, and the drive active layer includes a first active portion 401, and the carrier concentration in the first active portion 401 is greater than the carrier concentration in the first portion 301.

[0033] It should be noted that in the display panel, the array substrate is mainly used to control the switch of each pixel to ensure the accurate display of the image. Among them, the switching transistor S1 is mainly used to control the on and off of the signal, and the leakage current of the switching transistor S1 needs to be kept low to improve the stability of the display panel and prevent the display panel from flickering. The driving transistor D1 is mainly used to control the magnitude of the current, for example, by controlling the magnitude of the current flowing through the vLED to adjust the luminous brightness of the OLED. The on-state current of the driving transistor D1 needs to be kept high to increase the switching speed and reduce the switching loss, so that the driving transistor D1 can respond quickly and work efficiently.

[0034] It can be understood that in this embodiment, by making the switch transistor S1 include the first part 301 of the first oxide active layer 30, the driving transistor D1 includes the first active part 401 of the second oxide active layer 40, and the carrier concentration in the first active part 401 is greater than the carrier concentration in the first part 301, that is, by reducing the carrier concentration in the first part 301 in the switch transistor S1, the conductivity of the first part 301 can be made worse, so as to reduce the leakage current of the switch transistor S1, improve the stability of the display panel, and prevent the display panel from flickering. By making the carrier concentration in the first active part 401 in the driving transistor D1 greater than the carrier concentration in the first part 301, the on-state current of the driving transistor D1 can be increased, so that the driving transistor D1 can respond quickly and work efficiently, so that the different requirements of the switch transistor S1 and the driving transistor D1 can be met at the same time.

[0035] It should be noted that the switching transistor S1 and the driving transistor D1 may be powered on respectively to perform a photoelectric test to measure the corresponding carrier concentration.

[0036] Continue to refer to Figure 1b In some embodiments of the present disclosure, the array substrate further includes a third oxide active layer 50 and a first capacitor C1. The third oxide active layer 50 is located on a side of the second oxide active layer 40 away from the substrate 10, and the third oxide active layer 50 includes a first conductive portion 501. The first capacitor C1 is located on the substrate 10, and the first capacitor C1 includes a first electrode plate, and the first electrode plate includes a first conductive portion 501, and the carrier concentration in the first conductive portion 501 is greater than the carrier concentration in the first active portion 401. The carrier concentration in the first conductive portion 501 can also be measured by energizing the first capacitor C1 and performing a photoelectric test.

[0037] It should be noted that the pixel driving circuit PX also includes a first capacitor C1. The first capacitor C1 is mainly used to maintain the stability of the data signal, thereby ensuring that the data signal voltage remains unchanged during the refresh cycle to ensure the continuity and stability of the display screen. Specifically, the first capacitor C1 writes the data signal voltage through the switching transistor S1 during the programming phase, and maintains the voltage during the driving phase, thereby controlling the gate voltage of the driving transistor D1, and then controlling the current flowing through the OLED to adjust the luminous brightness of the OLED.

[0038] It can be understood that, in the present embodiment, by making the first electrode plate of the first capacitor C1 include the first conductive part 501 of the third oxide active layer 50, the carrier concentration in the first conductive part 501 is greater than the carrier concentration in the first active part 401, that is, the carrier concentration in the first conductive part 501 is greater, so that the conductivity of the first electrode plate is better and closer to the metal property, the contact resistance of the first electrode plate is reduced, and the resistance when the current passes through is reduced, which is beneficial to increase the capacitance value to provide more energy and make the current pulse on the load longer or larger.

[0039] In some embodiments of the present disclosure, the ratio of the carrier concentration in the first conductive portion 501 to the carrier concentration in the first portion 301 is greater than or equal to 4. For example, the ratio of the carrier concentration in the first conductive portion 501 to the carrier concentration in the first portion 301 is any one of 4, 4.5, 5, 5.5, and 6.

[0040] In some embodiments of the present disclosure, the ratio of the carrier concentration in the first conductive portion 501 to the carrier concentration in the first active portion 401 is greater than or equal to 2. For example, the ratio of the carrier concentration in the first conductive portion 501 to the carrier concentration in the first active portion 401 is any value of 2, 2.2, 2.5, 3, or 3.5.

[0041] Next, refer to Figure 1c , exemplarily, the pixel driving circuit PX may be a 2T1C structure. It should be noted that the 2T1C structure is used as an example to illustrate the pixel driving circuit PX included in the array substrate according to the embodiment of the present disclosure, but the pixel driving circuit included in the array substrate according to the embodiment of the present disclosure is not limited to the 2T1C structure.

[0042] like Figure 1b and Figure 1c As shown, the gate electrode (e.g., the second electrode 702) of the switch transistor S1 is connected to the scan signal line GL, the second source electrode 903 of the switch transistor S1 is connected to the data line DL, and the second drain electrode 904 of the switch transistor S1 is connected to the gate electrode (e.g., the first electrode 701) of the drive transistor D1. For example, the second drain electrode 904 of the switch transistor S1 and the gate electrode of the drive transistor D1 may both be electrically connected to the node G. The switch transistor S1 is used to control the writing of the voltage signal from the data line DL to the pixel drive circuit PX.

[0043] The gate of the driving transistor D1 is electrically connected to the node G, the first drain 902 of the driving transistor D1 is connected to the first power signal VDD, and the first source 901 of the driving transistor D1 can be connected to the anode of the light emitting element L, so that a driving current can be generated according to the voltage signal to drive the light emitting element L to emit light. For example, the light emitting element L can be an organic light emitting diode (OLED).

[0044] The two ends of the storage capacitor C1 are respectively connected to the gate electrode and the first source electrode 901 of the driving transistor D1, and are used to store the voltage signal input from the data line DL. For example, one end of the storage capacitor C1 is electrically connected to the node G, and the other end of the storage capacitor C1 is electrically connected to the node S. That is, one end of the storage capacitor C1, the second drain electrode 904 of the switching transistor S1, and the gate electrode of the driving transistor D1 are all electrically connected to the node G, and the other end of the storage capacitor C1, the first source electrode 901 of the driving transistor D1, and the anode of the light-emitting element L are all electrically connected to the node S.

[0045] The anode of the light emitting element L is electrically connected to the node S, and the cathode of the light emitting element L is electrically connected to the low voltage level signal VSS. The first power signal VDD and the low voltage level signal VSS are both DC voltage signals for providing the necessary voltage for driving the light emitting element L to emit light.

[0046] Continue to refer to Figure 1b In some embodiments of the present disclosure, the first oxide active layer 30 further includes a second portion 302, the driving active layer further includes the second portion 302, and the first active portion 401 is located on a side of the second portion 302 away from the substrate 10. That is, the first oxide active layer 30 includes the first portion 301 and the second portion 302, the first portion 301 is the active layer of the switching transistor S1, the second portion 302 is located in the driving transistor D1, and the second portion 302 and the first portion 301 have the same material and component, that is, the second portion 302 and the first portion 301 can be prepared by the same process.

[0047] It can be understood that in this embodiment, by providing the second portion 302 on the side of the first active portion 401 in the driving transistor D1 close to the substrate 10, the protection capability of the first active portion 401 can be improved to block the invasion of foreign impurities, so that the driving transistor D1 can maintain good performance and reliability.

[0048] In some embodiments of the present disclosure, the third oxide active layer 50 further includes a second conductive portion 502 and a third conductive portion 503, and the driving active layer further includes a second conductive portion 502 and a third conductive portion 503, and the second conductive portion 502 and the third conductive portion 503 are located on the side of the first active portion 401 away from the substrate 10. The driving transistor D1 further includes a first source 901 and a first drain 902. The first source 901 is connected to the second conductive portion 502, and the first drain 902 is connected to the third conductive portion 503. That is, the third oxide active layer 50 includes the first conductive portion 501, the second conductive portion 502, and the third conductive portion 503, the first conductive portion 501 is located in the first capacitor C1, the second conductive portion 502 and the third conductive portion 503 are located in the driving transistor D1, the first source 901 is connected to the first active portion 401 through the second conductive portion 502, and the first drain 902 is connected to the first active portion 401 through the third conductive portion 503. The second conductive part 502 , the third conductive part 503 and the first conductive part 501 have the same materials and components, that is, the second conductive part 502 , the third conductive part 503 and the first conductive part 501 can be manufactured by the same process.

[0049] It can be understood that, in the present embodiment, the first source 901 and the first drain 902 are connected to the first active part 401 through the second conductive part 502 and the third conductive part 503 respectively. Since the materials and components of the second conductive part 502, the third conductive part 503 and the first conductive part 501 are the same, the conductivity of the second conductive part 502 and the third conductive part 503 is better than that of the first active part 401, so the contact impedance between the first source 901 and the first drain 902 and the first active part 401 is reduced, which can reduce signal loss.

[0050] In some embodiments of the present disclosure, the first oxide active layer 30 further includes the third portion 303, the first electrode plate further includes the third portion 303, and the first conductive portion 501 is located on a side of the third portion 303 away from the substrate 10; and / or, the second oxide active layer 40 further includes the second active portion 402, the first electrode plate further includes the second active portion 402, and the first conductive portion 501 is located on a side of the second active portion 402 away from the substrate 10. That is, the first electrode plate may include only the third portion 303 and the first conductive portion 501, or the first electrode plate may include only the second active portion 402 and the first conductive portion 501, or the first electrode plate may include the third portion 303, the second active portion 402, and the first conductive portion 501 (such as Figure 1b As shown in FIG. 4 , the second active portion 402 is located between the third portion 303 and the first conductive portion 501 .

[0051] Specifically, the first oxide active layer 30 also includes a third portion 303, which can be disposed in the first capacitor C1, and the third portion 303 has the same material and component as the second portion 302 and the first portion 301, that is, the third portion 303 can be prepared by the same process as the second portion 302 and the first portion 301. The second oxide active layer 40 includes a first active portion 401 and a second active portion 402, the first active portion 401 being the active layer of the driving transistor D1, the second active portion 402 being disposed in the first capacitor C1, and the second active portion 402 has the same material and component as the first active portion 401, that is, the second active portion 402 and the first active portion 401 can be prepared by the same process.

[0052] It can be understood that in this embodiment, by providing the third part 303 and / or the second active part 402 on the side of the first conductive part 501 close to the substrate 10, the first electrode plate can be raised and the distance d between the first electrode plate and the second electrode plate (i.e., the third electrode 703) can be reduced to increase the capacitance value of the first capacitor C1.

[0053] Continue to refer to Figure 1b In some embodiments of the present disclosure, the array substrate further includes a gate insulating layer 60 and a first metal layer 70. The gate insulating layer 60 is located on the side of the first oxide active layer 30, the second oxide active layer 40 and the third oxide active layer 50 away from the substrate 10. The first metal layer 70 is located on the side of the gate insulating layer 60 away from the substrate 10, and the first metal layer 70 includes a first electrode 701, a second electrode 702 and a third electrode 703. The driving transistor D1 includes a first electrode 701, the switching transistor S1 includes a second electrode 702, and the first capacitor C1 includes a third electrode 703. Specifically, the first electrode 701 is the gate of the driving transistor D1, the second electrode 702 is the gate of the switching transistor S1, and the third electrode 703 is the second plate of the first capacitor C1. That is, the gate of the driving transistor D1, the gate of the switching transistor S1 and the second plate of the first capacitor C1 can be prepared by the same process, which can improve the preparation efficiency of the array substrate.

[0054] In some embodiments of the present disclosure, the array substrate further includes an interlayer insulating layer 80 , which is located on a side of the first metal layer 70 away from the substrate 10 , and the material of the interlayer insulating layer 80 is the same as that of the gate insulating layer 60 .

[0055] It can be understood that, in this embodiment, since the material of the interlayer insulating layer 80 is the same as that of the gate insulating layer 60 (for example, both are silicon oxide), the same etching process can be used to form vias on the interlayer insulating layer 80 and the gate insulating layer 60 to achieve the connection between the first source 901 and the first drain 902 of the driving transistor D1 and the first active portion 401, and the connection between the second source 903 and the second drain 904 of the switching transistor S1 and the first portion 301. Therefore, a process of etching the gate insulating layer 60 alone can be saved, saving the process takt. In addition, in the driving transistor D1, the second conductive portion 502 and the third conductive portion 503 of the third oxide active layer 50 can also serve as an etching barrier layer for the gate insulating layer 60 to avoid damaging the first active portion 401 of the second oxide active layer 40 during the etching of the gate insulating layer 60.

[0056] In some embodiments of the present disclosure, the array substrate further includes a shading metal layer 20 , and the orthographic projections of the first oxide active layer 30 , the second oxide active layer 40 , and the third oxide active layer 50 on the substrate 10 are located within the orthographic projection of the shading metal layer 20 on the substrate 10 .

[0057] It is understandable that the oxide active layer (such as the IGZO active layer) is prone to generate photogenerated carriers under light, and these carriers may recombine with free electrons, thereby affecting the conductive performance of the device. In this embodiment, by providing a light-shielding metal layer 20, the light-shielding metal layer 20 includes a first light-shielding portion 201, a second light-shielding portion 202, and a third light-shielding portion 203, the driving transistor D1, the first capacitor C1, and the oxide active layer in the switch transistor S1 can be shielded from light, and the carrier recombination caused by light can be reduced, thereby improving the conductive performance of the device.

[0058] In some embodiments of the present disclosure, the array substrate also includes a buffer layer 11 and a passivation layer 12, the buffer layer 11 is located between the light-shielding metal layer 20 and the first oxide active layer 30, and the passivation layer 12 is located on the side of the first source 901, the first drain 902, the second source 903 and the second drain 904 away from the substrate 10.

[0059] Figure 2 is a flow chart of a method for preparing an array substrate according to some embodiments of the present disclosure.

[0060] like Figure 2 As shown, the method for preparing the array substrate includes steps S1 to S3.

[0061] In step S1 , a first oxide active layer is formed on one side of a substrate, and the first oxide active layer includes a first portion.

[0062] In step S2 , a second oxide active layer is formed on a side of the first oxide active layer away from the substrate, the second oxide active layer includes a first active portion, and a carrier concentration in the second oxide active layer is greater than a carrier concentration in the first oxide active layer.

[0063] In step S3 , a switch transistor and a drive transistor are formed on a substrate, wherein the switch transistor includes a first portion, and the drive transistor includes a drive active layer, and the drive active layer includes a first active portion.

[0064] It can be understood that in this embodiment, by making the switch transistor include the first part of the first oxide active layer, the driving transistor includes the first active part of the second oxide active layer, and the carrier concentration in the second oxide active layer is greater than the carrier concentration in the first oxide active layer, that is, by reducing the carrier concentration in the first part of the switch transistor, the conductivity of the first part can be made worse, so as to reduce the leakage current of the switch transistor, improve the stability of the display panel, and prevent the display panel from flickering. By making the carrier concentration in the first active part of the driving transistor greater than the carrier concentration in the first part, the on-state current of the driving transistor can be increased, so that the driving transistor can respond quickly and work efficiently, so that different requirements of the switch transistor and the driving transistor can be met at the same time.

[0065] In some embodiments of the present disclosure, the method for preparing the array substrate also includes: forming a third oxide active layer on a side of the second oxide active layer away from the substrate, the third oxide active layer including a first conductive portion, the carrier concentration in the third oxide active layer being greater than the carrier concentration in the second oxide active layer; and forming a first capacitor on the substrate, the first capacitor including a first electrode plate, and the first electrode plate including a first conductive portion.

[0066] It can be understood that, in the present embodiment, by making the first plate of the first capacitor include the first conductive portion of the third oxide active layer, the carrier concentration in the third oxide active layer is made greater than the carrier concentration in the second oxide active layer, that is, the carrier concentration in the first conductive portion is greater, so that the conductivity of the first plate is better and closer to the metal property, the contact resistance of the first plate is reduced, and the resistance when the current passes through is reduced, which is beneficial to increase the capacitance value, so as to provide more energy and make the current pulse on the load longer or larger.

[0067] In some embodiments of the present disclosure, oxygen and argon are introduced during the process of forming the first oxide active layer, wherein the oxygen content is greater than or equal to 50% and less than or equal to 60%, for example, the oxygen content is any value of 50%, 52%, 54%, 56%, and 60%. Oxygen and argon are introduced during the process of forming the second oxide active layer, wherein the oxygen content is greater than or equal to 20% and less than or equal to 35%, for example, the oxygen content is any value of 20%, 24%, 26%, 30%, and 35%. It should be noted that the oxygen content refers to the ratio of the oxygen content introduced during the preparation of the oxide active layer to the sum of the oxygen and argon contents introduced.

[0068] In some embodiments of the present disclosure, the first oxide active layer and the second oxide active layer are, for example, both IGZO active layers. The preparation method of the IGZO active layer can adopt magnetron sputtering technology. First, oxide targets of indium, gallium and zinc (In2O3, Ga2O3, ZnO) are placed in a magnetron sputtering chamber, and the purity of these targets is, for example, 99.99%. Then oxygen (O2) and argon (Ar) are used as sputtering gases, and the proportion of oxygen will affect the crystallinity and electrical properties of the IGZO active layer. During the sputtering process, parameters such as sputtering pressure, power and target distance need to be controlled. For example, the sputtering pressure is set to 0.4Pa, the sputtering power is set to 70W, and radio frequency magnetron sputtering is performed at room temperature to deposit the IGZO active layer. By adjusting the sputtering time and power density, the thickness and uniformity of the IGZO active layer can be controlled. In order to form a specific pattern of the IGZO active layer, a patterning process can be performed in combination with mask technology to ensure that the IGZO active layer is formed only at the required position.

[0069] It should be noted that the conductivity of the IGZO active layer mainly depends on the presence of oxygen vacancies, which are defects formed by the absence of oxygen ions in the lattice position. Oxygen vacancies act as carrier donors in the IGZO active layer, providing free electrons, thereby improving the conductivity of the IGZO active layer. Specifically, when the oxygen content introduced is low, the indium ions lack oxygen ions to match them, and the atomic radius of indium is relatively large, and the ability to bind electrons is relatively weak, so electrons can easily escape, which is equivalent to increasing the carriers and improving the conductivity. As the oxygen content increases during the film formation process, the number of oxygen vacancies decreases, resulting in a decrease in the carrier concentration, which makes the conductivity of the IGZO active layer worse.

[0070] It can be understood that in this embodiment, by making the content of oxygen introduced during the formation of the second oxide active layer lower than the content of oxygen introduced during the formation of the first oxide active layer, the carrier concentration in the second oxide active layer can be made greater than the carrier concentration in the first oxide active layer. In this way, the conductivity of the first oxide active layer is made worse to reduce the leakage current of the switching transistor; the conductivity of the second oxide active layer is made better to increase the on-state current of the driving transistor, so that different requirements of the switching transistor and the driving transistor can be met at the same time.

[0071] In some embodiments of the present disclosure, oxygen and argon are introduced during the formation of the third oxide active layer, wherein the oxygen content is greater than or equal to 5% and less than or equal to 10%, for example, the oxygen content is any one of 5%, 6%, 7%, 8%, and 10%.

[0072] It can be understood that in this embodiment, by making the content of oxygen introduced during the formation of the third oxide active layer lower than the content of oxygen introduced during the formation of the second oxide active layer, the carrier concentration in the third oxide active layer can be greater than the carrier concentration in the second oxide active layer. That is, the carrier concentration in the third oxide active layer is greater, so that the conductivity of the first electrode plate is better, closer to the metal property, the contact resistance of the first electrode plate is reduced, and the resistance when the current passes through is reduced, which is conducive to increasing the capacitance value, so as to provide more energy and make the current pulse on the load longer or larger.

[0073] Figure 3a to Figure 3g It is a schematic diagram of the structure of each component in the process flow of preparing an array substrate according to some embodiments of the present disclosure.

[0074] Reference Figure 3a First, a light shielding metal layer 20 is formed on a substrate 10, and the light shielding metal layer 20 includes a first light shielding portion 201, a second light shielding portion 202, and a third light shielding portion 203. A buffer layer 11 is formed on the side of the light shielding metal layer 20 away from the substrate 10. A first oxide active material layer 3, a second oxide active material layer 4, and a third oxide active material layer 5 are sequentially formed on the side of the buffer layer 11 away from the substrate 10, wherein the content of oxygen introduced during the formation of the third oxide active material layer 5 is lower than the content of oxygen introduced during the formation of the second oxide active material layer 4, and the content of oxygen introduced during the formation of the second oxide active material layer 4 is lower than the content of oxygen introduced during the formation of the first oxide active material layer 3. Then, a first photoresist layer 100 is formed on the side of the third oxide active material layer 5 away from the substrate 10.

[0075] It should be noted that the first photoresist layer 100 can be formed by a halftone mask process. Specifically, a photoresist material layer is first formed on the side of the third oxide active material layer 5 away from the substrate 10, and then the photoresist material layer is patterned using the first mask 101 to form the first photoresist layer 100. Among them, the first mask 101 includes a transparent portion z1, a light shielding portion z2 and a semi-transparent portion z3, and the photoresist material layer corresponding to the area where the transparent portion z1 is located is completely removed, the photoresist material layer corresponding to the area where the light shielding portion z2 is located is completely retained, and the photoresist material layer corresponding to the area where the semi-transparent portion z3 is located is partially retained. The transmittance of the semi-transparent portion z3 can be adjusted to adjust the thickness of the photoresist material layer corresponding to the area where the semi-transparent portion z3 is located.

[0076] Next, refer to Figure 3b ,exist Figure 3a An etching process is performed on the basis of the first oxide active material layer 3, the second oxide active material layer 4 and the third oxide active material layer 5 to remove the portions not covered by the first photoresist layer 100 to form a first oxide active layer 30, a second oxide active material layer semi-finished product 4' and a third oxide active material layer semi-finished product 5'.

[0077] Next, refer to Figure 3c ,exist Figure 3b The first photoresist layer 100 is etched to a depth of x1 to form a first photoresist pattern 100', exposing a portion of the third oxide active material layer semi-finished product 5'. The exposed third oxide active material layer semi-finished product 5' is then removed to form a third oxide active pattern 5", exposing a portion of the second oxide active material layer semi-finished product 4'.

[0078] Next, refer to Figure 3d ,exist Figure 3c The first photoresist pattern 100' is removed on the basis of the first photoresist pattern 100'. Then, a second photoresist layer 200 is formed, and the second photoresist layer 200 covers the third oxide active pattern 5', the second oxide active material layer semi-finished product 4' and the first oxide active layer 30 in the area where the first light shielding portion 201 and the second light shielding portion 202 are located.

[0079] It should be noted that the second photoresist layer 200 can be formed by a mask process. Specifically, a photoresist material layer is first formed on the side of the third oxide active pattern 5″ away from the substrate 10, and then the photoresist material layer is patterned using the second mask 102 to form the second photoresist layer 200. The second mask 102 includes a light-transmitting portion z1 and a light-shielding portion z2, and the photoresist material layer corresponding to the area where the light-transmitting portion z1 is located is completely removed, and the photoresist material layer corresponding to the area where the light-shielding portion z2 is located is completely retained.

[0080] Next, refer to Figure 3e ,exist Figure 3d On the basis of the above, the third oxide active pattern 5 ″ and the portion of the second oxide active material layer semi-finished product 4 ′ not covered by the second photoresist layer 200 are removed to expose the first portion 301 of the first oxide active layer 30, so as to prepare the second oxide active layer 40 and the third oxide active layer 50. Then the second photoresist layer 200 is removed. The third oxide active layer 50 includes a first conductive portion 501, a second conductive portion 502 and a third conductive portion 503. The second oxide active layer 40 includes a first active portion 401 and a second active portion 402, the first active portion 401 is located on a side of the second conductive portion 502 and the third conductive portion 503 close to the substrate 10, and the second active portion 402 is located on a side of the first conductive portion 501 close to the substrate 10. The first oxide active layer 30 also includes a second portion 302 and a third portion 303, the second portion 302 is located on a side of the first active portion 401 close to the substrate 10, and the third portion 303 is located on a side of the second active portion 402 close to the substrate 10.

[0081] Next, refer to Figure 3f ,exist Figure 3e On the basis of the substrate 10, a gate insulating layer 60, a first metal layer 70 and an interlayer insulating layer 80 are formed. Then, a first source 901, a first drain 902, a second source 903 and a second drain 904 are formed on the side of the interlayer insulating layer 80 away from the substrate 10. Among them, the first metal layer 70 includes a first electrode 701, a second electrode 702 and a third electrode 703, the first electrode 701 is the gate of the driving transistor D1, the second electrode 702 is the gate of the switching transistor S1, and the third electrode 703 is the second plate of the first capacitor C1. The first plate of the first capacitor C1 includes the third portion 303 of the first oxide active layer 30, the second active portion 402 of the second oxide active layer 40 and the first conductive portion 501 of the third oxide active layer 50.

[0082] Next, refer to Figure 3g ,exist Figure 3f A passivation layer 12 is formed on the basis of the

[0083] The present disclosure also provides a display panel, including the array substrate as described above. The specific structure and preparation method of the array substrate can be found in Figure 1a to Figure 3g And related instructions will not be repeated here.

[0084] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. An array substrate, characterized in that: The array substrate comprises: substrate; A first oxide active layer, located on one side of the substrate, wherein the first oxide active layer includes a first portion; a second oxide active layer, located on a side of the first oxide active layer away from the substrate, the second oxide active layer comprising a first active portion; a switch transistor located on the substrate, the switch transistor comprising the first portion; and a driving transistor, located on the substrate, the driving transistor comprising a driving active layer, the driving active layer comprising the first active portion, Wherein, the carrier concentration in the first active portion is greater than the carrier concentration in the first portion.

2. The array substrate according to claim 1, characterized in that: The array substrate further includes: a third oxide active layer, located on a side of the second oxide active layer away from the substrate, the third oxide active layer comprising a first conductive portion; and A first capacitor is located on the substrate, the first capacitor includes a first electrode plate, and the first electrode plate includes the first conductive portion. Wherein, the carrier concentration in the first conductive portion is greater than the carrier concentration in the first active portion.

3. The array substrate according to claim 1 or 2, characterized in that: The first oxide active layer further includes a second portion, the driving active layer further includes the second portion, and the first active portion is located on a side of the second portion away from the substrate.

4. The array substrate according to claim 2, characterized in that: The third oxide active layer further includes a second conductive portion and a third conductive portion, the driving active layer further includes the second conductive portion and the third conductive portion, and the second conductive portion and the third conductive portion are located on a side of the first active portion away from the substrate; The driving transistor further comprises: A first source electrode connected to the second conductive portion; as well as The first drain is connected to the third conductive part.

5. The array substrate according to claim 2, characterized in that: The first oxide active layer further includes a third portion, the first electrode plate further includes the third portion, and the first conductive portion is located on a side of the third portion away from the substrate; and / or, The second oxide active layer further includes a second active portion, the first electrode plate further includes the second active portion, and the first conductive portion is located on a side of the second active portion away from the substrate.

6. The array substrate according to claim 2, characterized in that: A ratio of a carrier concentration in the first conductive portion to a carrier concentration in the first portion is greater than or equal to 4.

7. The array substrate according to claim 2, characterized in that: A ratio of a carrier concentration in the first conductive portion to a carrier concentration in the first active portion is greater than or equal to 2.

8. The array substrate according to any one of claims 2 to 7, characterized in that: The array substrate further includes: a gate insulating layer, located on a side of the first oxide active layer, the second oxide active layer, and the third oxide active layer away from the substrate; A first metal layer, located on a side of the gate insulating layer away from the substrate, the first metal layer comprising a first electrode, a second electrode and a third electrode; and The driving transistor includes the first electrode, the switching transistor includes the second electrode, and the first capacitor includes the third electrode.

9. The array substrate according to claim 8, characterized in that: The array substrate further includes an interlayer insulating layer, which is located on a side of the first metal layer away from the substrate, and a material of the interlayer insulating layer is the same as a material of the gate insulating layer.

10. The array substrate according to any one of claims 2 to 7, characterized in that: The array substrate further includes a light-shielding metal layer, and the orthographic projections of the first oxide active layer, the second oxide active layer, and the third oxide active layer on the substrate are located within the orthographic projection of the light-shielding metal layer on the substrate.

11. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1-10.

12. A method for preparing an array substrate, characterized in that: The method for preparing the array substrate comprises: forming a first oxide active layer on one side of the substrate, wherein the first oxide active layer includes a first portion; forming a second oxide active layer on a side of the first oxide active layer away from the substrate, the second oxide active layer comprising a first active portion, and a carrier concentration in the second oxide active layer being greater than a carrier concentration in the first oxide active layer; and A switching transistor and a driving transistor are formed on the substrate, the switching transistor including the first portion, the driving transistor including a driving active layer including the first active portion.

13. The method for preparing an array substrate according to claim 12, characterized in that: The method for preparing the array substrate further includes: forming a third oxide active layer on a side of the second oxide active layer away from the substrate, the third oxide active layer comprising a first conductive portion, and a carrier concentration in the third oxide active layer being greater than a carrier concentration in the second oxide active layer; and A first capacitor is formed on the substrate, wherein the first capacitor includes a first electrode plate, and the first electrode plate includes the first conductive portion.

14. The method for preparing an array substrate according to claim 12, wherein: In the process of forming the first oxide active layer, oxygen and argon are introduced, wherein the content of oxygen is greater than or equal to 50% and less than or equal to 60%; and Oxygen and argon are introduced during the process of forming the second oxide active layer, wherein the content of oxygen is greater than or equal to 20% and less than or equal to 35%.

15. The method for preparing an array substrate according to claim 13, characterized in that: Oxygen and argon are introduced during the process of forming the third oxide active layer, wherein the content of oxygen is greater than or equal to 5% and less than or equal to 10%.

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