Preparation method of array substrate, array substrate and display device

Abstract

The embodiment of the invention provides a preparation method of an array substrate, the array substrate and a display device. The preparation method of the array substrate comprises the following steps: providing a substrate; forming a first metal layer on one side of the substrate, patterning the first metal layer, and respectively forming a grid electrode and a soldering tin layer on the substrate; forming a first insulating material layer on one side of the grid electrode and the soldering tin layer on the substrate, and patterning the first insulating material layer to form a grid electrode insulating layer covering the grid electrode and a first insulating layer covering the soldering tin layer; and forming a second metal layer on the gate insulating layer and the first insulating layer at one side of the substrate, and patterning the second metal layer to form a source electrode, a drain electrode and a ground wire layer at one side of the first insulating layer far away from the substrate. According to the preparation method of the array substrate, the array substrate and the display device provided by the embodiment of the invention, waste pollution generated by a PCBA (Printed Circuit Board Assembly) is effectively reduced, the material and equipment cost is saved, the cost is effectively reduced, and the quality is improved.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular relates to a method for preparing an array substrate, an array substrate, and a display device. Background Art

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) is the most widely used and most popular display panel in the market. Its characteristics include low radiation, low space occupancy, beautiful appearance, and excellent picture quality. After decades of development, its technology maturity is also very high.

[0003] The structure of TFT-LCD displays currently on the market is usually composed of a panel, a printed circuit board assembly (PCBA), a flexible printed circuit (FPC), a backlight, etc. There are FPC and PCBA on the periphery of the panel, which are used to provide various display information to the display screen after power is turned on. However, as the size of the panel increases, the area of ​​PCBA and FPC will also increase, which will make the frame of the display thicker and the PCBA more prone to warping. At the same time, due to the selection of PCBA materials, which are mainly composed of glass fiber and epoxy resin, the actual production process causes great pollution to the environment, and its heat dissipation effect is also unsatisfactory. After long-term use, the PCBA board will age due to the influence of temperature and humidity, thus affecting the normal use of the display. Summary of the invention

[0004] In view of this, the embodiments of the present application provide a method for preparing an array substrate, an array substrate and a display device to solve the technical problems of PCBA warping in existing LCD displays, waste pollution caused by PCBA and PCBA aging affecting the normal use of the display.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing an array substrate, comprising the following steps:

[0006] providing a substrate;

[0007] forming a first metal layer on one side of the substrate, and patterning the first metal layer to form a gate and a solder layer respectively located on the substrate;

[0008] forming a first insulating material layer on a side of the substrate where the gate and the solder layer are located, and patterning the first insulating material layer to form a gate insulating layer covering the gate and a first insulating layer covering the solder layer;

[0009] forming a second metal layer on a side where the gate insulating layer and the first insulating layer are located on the substrate, and patterning the second metal layer to form a source electrode and a drain electrode located on a side of the gate insulating layer away from the substrate, and a ground layer located on a side of the first insulating layer away from the substrate;

[0010] A second insulating material layer is formed on the side of the substrate where the source, the drain and the ground layer are located, and the second insulating material layer is patterned to form a passivation layer covering the source, the drain and the gate insulating layer, and a second insulating layer covering the ground layer.

[0011] In some embodiments, after forming the gate insulating layer and the first insulating layer and before forming the second metal layer, the method further includes:

[0012] A silicon material layer is deposited on the side where the gate insulating layer and the first insulating layer are located on the substrate, the silicon material layer is patterned, and an active layer is formed on the side of the gate insulating layer away from the substrate, wherein the active layer is located between the gate insulating layer and the source and the drain.

[0013] In some embodiments, depositing a silicon material layer on a side of the gate insulating layer and the first insulating layer located on the substrate, and patterning the silicon material layer includes:

[0014] In the process of patterning the silicon material layer on the first insulating layer, no photoresist is applied on the silicon material layer on the first insulating layer, so that the silicon material layer on the first insulating layer is etched away;

[0015] Alternatively, the silicon material layer located on the first insulating layer is directly removed.

[0016] In some embodiments, the gate and the solder layer are configured to be spaced apart.

[0017] In some embodiments, it also includes:

[0018] A third metal layer is formed on a side of the substrate where the passivation layer and the second insulating layer are located, and the third metal layer is patterned to form a touch electrode layer located on a side of the passivation layer away from the substrate, and a power supply layer located on a side of the second insulating layer away from the substrate.

[0019] In some embodiments, the patterning process sequentially includes:

[0020] Coating photoresist, exposure, development, etching and photoresist stripping.

[0021] In some embodiments, patterning the first metal layer includes: performing light shielding on two portions of the first metal layer located on the substrate.

[0022] In some embodiments, patterning the first insulating material layer includes: performing light shielding processing on the first insulating material layer located above and around the gate and the solder layer, respectively.

[0023] In some embodiments, the patterning process of the second metal layer includes: performing shading process on the second metal layer located in the orthographic projections of the gate insulating layer and the solder layer respectively along the thickness direction of the array substrate, and leaving the middle portion of the second metal layer on the gate insulating layer blank and not performing shading process.

[0024] In some embodiments, the patterning process of the second insulating material layer includes: shading the second insulating material layer located above and around the gate insulating layer, and shading the second insulating material layer located within the orthographic projection of the first insulating layer in the thickness direction of the array substrate.

[0025] In some embodiments, the material of the substrate includes one of glass and plastic;

[0026] When the material of the substrate is glass, the substrate has the following performance parameters:

[0027] Thermal conductivity is 0.7~1.3W(m·k);

[0028] The thermal expansion coefficient is 3-4ppm / ℃;

[0029] The line width is 3 to 4 μm and the line spacing is 2 to 3 μm.

[0030] In a second aspect, an embodiment of the present application provides an array substrate, which is manufactured using the manufacturing method described in the first aspect.

[0031] In a third aspect, an embodiment of the present application provides a display device, comprising a housing and a main board, the display device further comprising the array substrate described in the second aspect, the main board and the array substrate being arranged in the housing, the array substrate being electrically connected to the main board.

[0032] The present application provides a method for preparing an array substrate, an array substrate and a display device, wherein the method for preparing the array substrate integrates the method for preparing a PCBA board and the method for preparing a TFT-LCD array substrate, that is, the two are manufactured at the same time, and a common substrate is used. Then, when the gate is deposited by the Array process, the deposition of the solder layer in the PCBA board is realized at the same time, and when the gate insulating layer is deposited, the insulating layer in the PCBA board is replaced with the same material at the same time; similarly, when the drain / source electrode is deposited, the deposition of the ground layer in the PCBA board can be realized, and so on, the number of metal layers and insulating layers that can be deposited in the PCBA can be determined according to the number of processes of the metal layer required by the Array and the number of depositions of the insulating layer / passivation layer. Compared with the traditional process of making a PCBA board alone, the process can be effectively reduced. Since the embodiment of the present application abandons the use of PCBA and FPC, most of the processes can be carried out on LCD equipment, and the materials used to make LCD can also be used to realize the functions of PCBA and FPC, achieving the effect of cost saving in terms of material and equipment requirements, and also reducing the thickness and weight of the overall module, improving the heat dissipation performance, and reducing the risk of PCBA warping. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 It is a structural schematic diagram of a PCBA board in the prior art;

[0035] Figure 2 is a schematic flow chart of a method for preparing an array substrate provided in an embodiment of the present application;

[0036] Figure 3 is a process structure schematic diagram of steps S100 and S200 in the method for preparing an array substrate provided in an embodiment of the present application;

[0037] Figure 4 is a process structure schematic diagram of step S300 in the method for preparing an array substrate provided in an embodiment of the present application;

[0038] Figure 5 is a process structure schematic diagram of step S400 in the method for preparing an array substrate provided in an embodiment of the present application;

[0039] Figure 6It is a schematic diagram of the process structure of S310 in the method for preparing an array substrate provided by the present application;

[0040] Figure 7 is a process structure schematic diagram of step S500 in the method for preparing an array substrate provided in an embodiment of the present application;

[0041] Figure 8 is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

[0042] Fig. 9 It is a schematic diagram of the structure of the display device provided in an embodiment of the present application.

[0043] Among them, the figure numbers are:

[0044] 001, metal structure layer; 002, insulation structure layer;

[0045] 10. Substrate;

[0046] 20. First metal layer; 21. Gate; 22. Solder layer;

[0047] 30. first insulating material layer; 31. gate insulating layer; 32. first insulating layer;

[0048] 40. Second metal layer; 41. Source; 42. Drain; 43. Ground layer;

[0049] 50. second insulating material layer; 51. passivation layer; 52. second insulating layer;

[0050] 60. silicon material layer; 61. active layer;

[0051] 70. Shell;

[0052] 80. Base. DETAILED DESCRIPTION

[0053] In the following description, specific details such as specific system structures, technologies, etc. are proposed for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the embodiments of the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from hindering the description of the embodiments of the present application.

[0054] It should also be understood that the term “and / or” used in the description of the embodiments of the present application and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0055] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0056] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present application.

[0057] In addition, in the description of the embodiments of the present application and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0058] References to "some embodiments" or "some embodiments" etc. described in the specification of the embodiments of the present application mean that one or more embodiments of the embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Thus, the statements "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in the different parts of this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways. "Multiple" refers to two or more.

[0059] With the advancement of display technology, the design accuracy of traditional PCBA is difficult to meet the more complex wiring requirements of higher density welding products. Purchasing high-precision PCBA from abroad further increases costs. Moreover, as the size of the panel increases, the area of ​​PCBA and FPC will also increase, which will make the frame of the display thicker and the PCBA more prone to warping. At the same time, since the material of PCBA is mainly composed of glass fiber and epoxy resin, it causes great pollution to the environment in the actual production process. At the same time, its heat dissipation effect is not satisfactory. After long-term use, the PCBA board will age due to the influence of temperature and humidity, thus affecting the normal use of the display.

[0060] The invention concept of this application is derived from the four-layer PCBA board. The basic structure of the existing PCBA board is as follows: Figure 1As shown, it usually includes a multi-layer metal structure layer 001, and an insulating structure layer 002 is set between the metal structure layers 001 to separate them. Since the PCBA board is also coated with a layer of metal film, and then exposed, developed, etched and other processes are carried out to achieve complex, multi-layer routing, the manufacturing process is similar to the manufacturing method of the TFT-LCD array substrate. Therefore, the preparation process of the PCBA board is integrated with the Array process of TFT-LCD, that is, the routing on the PCBA board is realized through the Array process and materials, thereby realizing the integrated design of PCBA, FPC and array substrate. Therefore, the embodiment of the present application provides a method for preparing an array substrate, an array substrate and a display device, which can well solve the above problems, replace the traditional PCBA, effectively reduce the waste pollution generated by PCBA, save material and equipment costs, and effectively improve the display quality.

[0061] It should be noted that the thickness direction of the array substrate mentioned in the embodiment of the present application is the Y direction in the figure, and the X direction is the length / width direction of the array substrate. The above is only for the convenience of understanding the technical solution of the embodiment of the present application, and should not be understood as limiting the scope of the embodiment of the present application.

[0062] A first aspect of the present application provides a method for preparing an array substrate, such as Figures 2 to 7 As shown, the following steps are included:

[0063] S100, providing a substrate 10;

[0064] S200, forming a first metal layer 20 on one side of the substrate 10, and patterning the first metal layer 20 to form a gate 21 and a solder layer 22 respectively located on the substrate 10;

[0065] S300, forming a first insulating material layer 30 on the side of the substrate 10 where the gate 21 and the solder layer 22 are located, and patterning the first insulating material layer 30 to form a gate insulating layer 32 covering the gate 21 and a first insulating layer 32 covering the solder layer 22;

[0066] S400, forming a second metal layer 40 on the side of the gate insulating layer 31 and the first insulating layer 32 located on the substrate 10, and patterning the second metal layer 40 to form a source 41 and a drain 42 located on the side of the gate insulating layer 31 away from the substrate 10, and a ground layer 43 located on the side of the first insulating layer 32 away from the substrate 10;

[0067] S500, forming a second insulating material layer 50 on one side of the substrate 10 where the source 41, the drain 42 and the ground layer 43 are located, and patterning the second insulating material layer 50 to form a passivation layer 51 covering the source 41, the drain 42 and the gate insulating layer 31, and a second insulating layer 52 covering the ground layer 43.

[0068] The method for preparing an array substrate provided in an embodiment of the present application performs an array process on the same substrate to form a layer structure of a PCBA board while manufacturing a TFT-LCD array substrate, and shares processes and materials, thereby effectively reducing the entire array substrate process and omitting the use of a PCBA board, thereby preventing the PCBA board from warping in the array substrate and avoiding environmental pollution caused by the selection of conventional PCBA materials (glass fiber and epoxy resin). Moreover, traditional PCBA materials will age after long-term use due to the influence of humidity and temperature, thereby affecting the normal use of the display. The present application avoids the above-mentioned situation by adopting the same process and materials as the LCD array substrate.

[0069] The array process is a critical link in the manufacturing process of TFT-LCD (Thin Film Transistor Liquid Crystal Display). The array process is mainly used to manufacture TFT-LCD array substrates, which are the core part responsible for controlling the switching of each pixel.

[0070] It should be noted that the first insulating material layer 30 is formed on the side where the gate 21 and the solder layer 22 are located on the substrate 10. The term "located" means that the first insulating material layer 30, the gate 21, and the solder layer 22 are located on the same side of the substrate. Specifically, part of the first insulating material layer 30 is located on the gate 21 and the solder layer 22, and part of it is directly located on the substrate 10.

[0071] In application, the preparation method of the array substrate provided in the embodiment of the present application integrates the preparation method of the PCBA board and the preparation method of the TFT-LCD array substrate, that is, the two are manufactured at the same time, the substrate is shared, and then when the gate is deposited by the Array process, the deposition of the solder layer in the PCBA board is realized at the same time, and when the gate insulation layer is deposited, the insulation layer in the PCBA board is replaced by the same material; similarly, when the drain / source is deposited, the deposition of the ground layer in the PCBA board can be realized, and so on, the number of metal layers and insulation layers that can be deposited in the PCBA can be determined according to the number of metal layer processes and insulation layer / passivation layer deposition times required by the Array. The conventional PCBA and FPC are abandoned, and most of the processes of the PCBA-related structures can be carried out on LCD equipment. At the same time, the LCD manufacturing materials can also be used to realize the functions of PCBA and FPC, achieving the effect of cost saving in terms of material and equipment requirements, and also reducing the thickness and weight of the overall module and improving the heat dissipation performance.

[0072] In some embodiments, in step S100, the material of the substrate includes one of glass and plastic. In a preferred embodiment, the material of the substrate is glass. When the material of the substrate is glass, the substrate has the following performance parameters:

[0073] Thermal conductivity is 0.7~1.3W(m·k);

[0074] The thermal expansion coefficient is 3-4ppm / ℃;

[0075] The line width is 3 to 4 μm and the line spacing is 2 to 3 μm.

[0076] In application, conventional PCB substrates are made of glass fiber and epoxy resin, and their comprehensive performance parameters are not as good as those of glass substrates. The specific parameters are compared in the following table:

[0077] Comparison table of characteristics of PCBA boards made of conventional PCB substrates and glass substrates

[0078] parameter Glass substrate Conventional PCB substrate Thermal conductivity 0.7~1.3W(m·k) 0.25W(m·k) Coefficient of thermal expansion 3~4ppm / ℃ 12~18ppm / ℃ Line Width 3~4μm 100μm Line spacing 2~3μm 100μm Material Cu, G-SiNx Cu, G-SiNx, glass fiber, epoxy resin

[0079] Note: Cu is copper, G-SiNx refers to a specific layer structure used in the TFT-LCD (Thin Film Transistor Liquid Crystal Display) Array process. Here "G" stands for "Gate" and "SiNx" stands for "Silicon Nitride".

[0080] From the table above, we can see that PCBA boards made of glass substrates have higher thermal conductivity and heat dissipation capacity, so components generate less heat when working on glass substrates, which improves product yield and service life. In addition, the mechanical properties of glass substrates are better, making the whole more stable and flatter, and PCBA with better precision can be obtained.

[0081] In the following embodiment, in step S200, Figure 2 and Figure 3 As shown, a first metal layer 20 is formed on one side of the substrate 10, and then the first metal layer 20 is patterned to form a gate 21 and a solder layer 22 respectively located on the substrate 10. In the application, the material of the first metal layer is selected from one of copper, molybdenum, and aluminum. In a preferred embodiment, the first metal layer is a copper layer, and a first metal film layer is formed on one side of the substrate by a sputtering process, wherein the sputtering process includes: bombarding a copper target material with high-energy particles in a vacuum, so that copper atoms are splashed out from the surface of the target material and deposited on the substrate to form a uniform thin film (first metal layer). In the application, the patterning of the first metal layer includes: shielding the two parts of the first metal layer spaced on the substrate, so that in the subsequent steps, a gate and a solder layer are formed. In some other embodiments, the patterning of the first metal layer includes: coating only the two parts of the first metal layer spaced on the substrate with a photoresist, so that in the subsequent steps, a gate and a solder layer are formed.

[0082] In application, after patterning the first metal layer 20, a gate electrode 21 and a solder layer 22 are formed on the substrate 10, wherein the solder layer 22 is used as a structural layer in the PCBA board. The spacing setting is conducive to ensuring that the two do not affect each other in the subsequent process, and ensuring the normal functions of the LCD array substrate, PCBA, and FPC.

[0083] In some embodiments, the patterning process includes: coating photoresist, exposure, development, etching and photoresist removal. Coating photoresist refers to coating a layer of photoresist (PR) material on the deposited thin film (first metal layer). PR is a light-sensitive polymer, which can be divided into positive photoresist and negative photoresist according to the reaction properties after exposure. Exposure is to transfer the pattern to the PR layer using a mask and an exposure machine. The ultraviolet light emitted by the exposure machine passes through the transparent area on the mask and irradiates the PR layer, causing the PR properties of these areas to change. Development is to treat the PR layer with a developer to remove the PR in the exposed area (for positive photoresist) or the unexposed area (for negative photoresist), thereby forming a patterned PR layer on the substrate. After the development is completed, the desired pattern is formed on the PR layer. Etching is to use chemical etching or dry etching (such as plasma etching) to remove the underlying material not protected by PR. The etching process etches away the underlying material according to the pattern of the PR layer, leaving the desired structure (gate). After etching is completed, photoresist removal uses solvents or other methods to remove the PR layer to facilitate subsequent processes. Photoresist removal can use wet or dry photoresist removal processes.

[0084] In applications, this series of steps usually needs to be repeated many times to complete the manufacturing of different layers of the entire TFT-LCD array substrate. For example, when making gate lines, it is necessary to first sputter the gate material, then perform PR coating, exposure, development, etching and photoresist removal; after that, for the source and drain materials, this series of steps also needs to be repeated.

[0085] In some embodiments, in step S300, Figure 2 and Figure 4 As shown, a first insulating material layer 30 is formed on one side of the substrate 10 where the gate 21 and the solder layer 22 are located, and then the first insulating material layer 30 is patterned to form a gate insulating layer 31 covering the gate 21 and a first insulating layer 32 covering the solder layer 22. In application, the material of the first insulating material layer includes but is not limited to SiO2 or SiN. By selecting SiO2 or SiN as the material of GI (gate insulating layer), and because GI has an insulating effect, it can be used as an insulating layer in the PCBA board to separate the solder layer and the ground layer. In this way, the process and technology of the gate insulating layer and the first insulating layer are shared, which effectively reduces the cost of materials and simplifies the process steps.

[0086] In the application, a first insulating material layer is formed on the side of the substrate where the gate and the solder layer are located. Since the gate insulating layer to be formed finally needs to isolate the gate, a first insulating material layer covering the substrate, the gate and the solder layer needs to be formed on the substrate. Figure 4As shown, finally, a gate insulating layer completely covering the exposed part of the gate and a first insulating layer completely covering the exposed part of the solder layer can be obtained. The first insulating material layer is also formed into a thin film on the substrate, the gate and the solder layer by a sputtering process.

[0087] In applications, such as Figure 4 As shown, the patterning process of the first insulating material layer 30 includes: performing a light shielding process on the first insulating material layer 30 located above and around the gate 21 and the solder layer 22. Such an operation can ensure that a gate insulating layer covering the gate and a first insulating layer covering the solder layer are finally formed. In other embodiments, only the first insulating material layer 30 located above and around the gate 21 and the solder layer 22 is coated with a photoresist so that it is not etched away in subsequent steps.

[0088] In some embodiments, in step S400, Figure 2 and Figure 5 As shown, a second metal layer 40 is formed on the side of the gate insulating layer 31 and the first insulating layer 32 located on the substrate 10, and then the second metal layer 40 is patterned to form a source 41 and a drain 42 located on the side of the gate insulating layer 31 away from the substrate 10, and a ground layer 43 located on the side of the first insulating layer 32 away from the substrate 10. The material of the second metal layer 40 is the same as that of the first metal layer 20, which is one of copper, aluminum or molybdenum, preferably copper.

[0089] In applications, such as Figure 5 As shown, the patterning process of the second metal layer 40 includes: coating the second metal layer 40 located in the orthographic projection of the gate insulating layer 31 and the solder layer 22 along the thickness direction of the array substrate with photoresist, and leaving the middle of the second metal layer 40 corresponding to the gate insulating layer 31 blank and not coated with photoresist. In this way, it is ensured that the source electrode 41, the drain electrode 42 and the ground layer 43 that are spaced from each other are formed.

[0090] It should be noted that the second metal layer 40 is formed on the side where the gate insulating layer 31 and the first insulating layer 32 are located on the substrate 10. That is, the formed second metal layer 40, the gate insulating layer 31, and the first insulating layer 32 are all located on the same side of the substrate. Specifically, part of the second metal layer 40 is disposed on the gate insulating layer 31 and the first insulating layer 32, and part of the second metal layer 40 is in direct contact with the substrate 10.

[0091] In application, the source and drain finally formed are located on the gate insulating layer and within the orthographic projection of the gate in the thickness direction of the array substrate, and the source and drain are spaced apart to ensure that they can remain independent of each other and do not affect normal operation.

[0092] In some embodiments, Figure 6 As shown, after step S300 and before step S400, the method further includes step S310, depositing a silicon material layer 60 on the side of the gate insulating layer 31 and the first insulating layer 32 located on the substrate 10, patterning the silicon material layer 60, and forming an active layer 61 on the side of the gate insulating layer 31 away from the substrate 10, wherein the active layer 61 is located between the gate insulating layer 31 and the source 41 and the drain 42. The silicon material layer 60 includes amorphous silicon or polycrystalline silicon, which serves as the active layer 61 of the array substrate. In applications, the active layer is the core part of the TFT and determines the conductive properties of the TFT. Under the action of the gate voltage, the carriers (electrons or holes) in the active layer flow between the source and the drain.

[0093] In the application, a silicon material layer 60 is deposited on the side of the gate insulating layer 31 and the first insulating layer 32 located on the substrate 10, and then the silicon material layer 60 is patterned, including:

[0094] During the process of patterning the silicon material layer 60 on the first insulating layer 32, the silicon material layer 60 on the first insulating layer 32 is not subjected to light shielding, so that the silicon material layer 60 on the first insulating layer 32 is etched away. In other embodiments, during the process of patterning the silicon material layer 60 on the first insulating layer 32, the silicon material layer 60 on the first insulating layer 32 is not coated with photoresist, so that the portion is etched away.

[0095] Because when the active layer is formed on the gate insulating layer, in order to ensure the simplicity and consistency of the process, a silicon material layer will be formed on the first insulating layer at the same time. However, this layer of structure is not needed in the production of PCBA boards, so it will not be shielded during the patterning process. In the subsequent exposure, etching and other steps, the silicon material layer on the first insulating layer will be etched away. In other words, it is only necessary to perform normal patterning on the part of the silicon material layer located on the gate insulating layer, and perform light shielding on the silicon material layer of the gate insulating layer, so as to ensure that in the subsequent steps, that part of the silicon material layer is not taken out, and finally form an active layer. In other embodiments, the silicon material layer located on the first insulating layer is directly removed.

[0096] In some embodiments, Figure 2 and Figure 7As shown, in step S500, a second insulating material layer 50 is formed on the side of the source 41, the drain 42 and the grounding layer 43 located on the substrate 10, and then the second insulating material layer 50 is patterned to form a passivation layer 51 covering the source 41, the drain 42 and the gate insulating layer 31, and a second insulating layer 52 covering the grounding layer 43. Among them, the passivation layer 51 is partially embedded in the gap between the source 41 and the drain 42, and the other part covers the source 41, the drain 42 and the gate insulating layer 31 and isolates them from the outside. The second insulating layer 52 completely covers the grounding layer 43.

[0097] It should be noted that the second insulating material layer 50 is formed on the side where the source 41, the drain 42 and the ground layer 43 are located on the substrate 10. This means that the formed second insulating material layer and the source 41, the drain 42 and the ground layer 43 are on the same side of the substrate 10. In some embodiments, part of the second insulating material layer 50 is located on the source 41, the drain 42 and the ground layer 43, and part of the second insulating material layer 50 is in direct contact with the substrate 10.

[0098] In application, the patterning process of the second insulating material layer 50 includes: coating the second insulating material layer 50 located above and around the gate insulating layer 31 with photoresist, so as to form a passivation layer 51 that finally covers the source 41, the drain 42 and the gate insulating layer 31; coating the second insulating material layer 50 located within the orthographic projection of the first insulating layer 32 along the thickness direction of the array substrate with photoresist, so as to form a second insulating layer 52 that has a structure similar to the first insulating layer 32 and covers the ground layer 43.

[0099] In some embodiments, the method for preparing the array substrate further includes step S600, forming a third metal layer (not shown in the figure) on the side of the passivation layer 51 and the second insulating layer 52 located on the substrate 10, and then patterning the third metal layer to form a touch electrode layer located on the side of the passivation layer 51 away from the substrate 10, and a power layer located on the side of the second insulating layer 52 away from the substrate 10. The third metal layer is similar to the first metal layer 20 and the second metal layer 40. In some embodiments, for touch products with built-in touch, there is a third metal layer above the passivation layer 51, so that the power layer can be deposited at the same time. The second passivation layer above the third metal layer is an insulating layer, and the third insulating layer for isolating the power layer is deposited at the same time.

[0100] In some embodiments, the process further includes S700, forming a third insulating material layer on the side of the touch electrode layer and the power layer located on the substrate 10, and then patterning the third insulating material layer to form an insulating layer covering the touch electrode layer and a third insulating layer located on the power layer. The third insulating material layer is similar to the first insulating material layer 30 and the second insulating material layer 50, and the related processes are the same.

[0101] In the application, the patterning process in steps S300, S310, S400, S500, S600 and step S700 is the same as that in step S200, and will not be described in detail here. In order to ensure the consistency of the entire Array process, when forming the first metal layer, the first insulating material layer, the silicon material layer, the second metal layer and the second insulating material layer, they are all formed by a sputtering process, and then patterned to finally obtain a corresponding layer structure.

[0102] In some embodiments, the method for preparing the array substrate further includes welding the electronic components, I / O interfaces, etc. required on the original PCBA board on the surface of the substrate, thereby finally realizing the integration of the array substrate and the PCBA.

[0103] A second aspect of an embodiment of the present application provides an array substrate, which is manufactured using the manufacturing method described in the first aspect.

[0104] In some embodiments, Figure 8 As shown, the array substrate includes TFTs and PCBAs that are spaced apart, and the TFTs and PCBAs share a substrate 10;

[0105] The TFT includes a substrate 10, a gate electrode 21, a gate insulating layer 31, an active layer 61, a source electrode 41, a drain electrode 42 and a passivation layer 51; the gate insulating layer 31 covers the gate electrode 21 and separates the gate electrode 21 from other structures; the active layer 61 is located on the gate insulating layer 31 and is located within the orthographic projection of the gate electrode 21 in the thickness direction of the array substrate; the source electrode 41 and the drain electrode 42 are respectively located on both sides of the active layer 61; the passivation layer 51 covers the source electrode 41, the drain electrode 42 and the gate insulating layer 31;

[0106] The PCBA includes a substrate 10, a solder layer 22, a first insulating layer 32, a ground layer 43 and a second insulating layer 52. The first insulating layer 32 completely covers the solder layer 22, the second insulating layer 52 completely covers the ground layer 43, and the second insulating layer 52 is located within the orthographic projection of the first insulating layer 32 in the thickness direction of the array substrate.

[0107] In some embodiments, the TFT further includes a touch electrode layer and an insulating layer covering the touch electrode layer, the touch electrode layer is located on one side of the passivation layer 51, and the PCBA further includes a power layer located on the second insulating layer 52 and a third insulating layer covering the power layer.

[0108] The array substrate provided in the embodiment of the present application eliminates the use of conventional PCBA boards, which naturally avoids the problem of PCBA warping, and can reduce the waste pollution generated by PCBA production, and prevent it from aging and affecting the normal use of the display. At the same time, the circuits of the PCBA are made on the glass substrate, and the materials used are all materials in the TFT-LCD production process, which saves material and equipment costs, and can also produce PCBAs with better precision.

[0109] A third aspect of the present application provides a display device, such as Fig. 9 As shown, the display device includes the array substrate, the housing 70 and the main board (not shown in the figure) described in the second aspect of the embodiment of the present application, the array substrate and the main board are arranged in the housing 70, and the array substrate is electrically connected to the main board. In some embodiments, the display device also includes a base 80, which is connected to the housing 70. It can stably support the entire display device.

[0110] The display device provided in the embodiment of the present application, the housing 70 is the external protection structure of the display device, which not only provides physical protection for the internal components to prevent the influence of the external environment on the electronic components, such as dust, moisture and accidental collision, but also plays a role in aesthetics and ergonomic design. The mainboard is the core control center of the display device, which contains circuits for processing image signals, power management, interface communication and other functions. It is responsible for receiving video signals from external devices (such as computers, TV boxes, etc.) and converting them into a format suitable for use by the display panel.

[0111] In application, the housing 70 is made of plastic or metal, or a combination of plastic and metal to achieve optimal performance and cost-effectiveness. The housing is provided with special slots, screw holes or other mechanical fixing devices to fix the array substrate and the motherboard to ensure that these key components remain stable during transportation and use. In other embodiments, the housing may also be provided with vents, buttons, interfaces, etc. to meet heat dissipation requirements and user operations.

[0112] In applications, the motherboard may be equipped with various chips, such as graphics processors, central processing units, memory modules, and other control chips, as well as interfaces for connecting external devices, such as HDMI, USB, etc. The array substrate is part of a flat panel display such as LCD or OLED, located on the back of the display panel, and is covered with thin film transistors and other tiny circuit structures. These TFTs are used to control the switching state of each pixel, thereby determining whether the pixel should be transparent (for LCD) or luminous (for OLED) to display images.

[0113] In application, the mainboard is connected to the array substrate through a flexible cable or a ribbon cable to transmit data signals from the mainboard to each TFT on the array substrate, thereby controlling the display content. At the same time, the power line also transmits the necessary power from the mainboard to the array substrate.

[0114] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0115] The above-described embodiments are only used to illustrate the technical solutions of the embodiments of the present application, rather than to limit them. Although the embodiments of the present application are described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the embodiments of the present application, and should all be included in the protection scope of the embodiments of the present application.

Claims

1. A method for preparing an array substrate, characterized in that: The following steps are involved: providing a substrate; forming a first metal layer on one side of the substrate, and patterning the first metal layer to form a gate and a solder layer respectively located on the substrate; forming a first insulating material layer on a side of the substrate where the gate and the solder layer are located, and patterning the first insulating material layer to form a gate insulating layer covering the gate and a first insulating layer covering the solder layer; forming a second metal layer on a side where the gate insulating layer and the first insulating layer are located on the substrate, and patterning the second metal layer to form a source electrode and a drain electrode located on a side of the gate insulating layer away from the substrate, and a ground layer located on a side of the first insulating layer away from the substrate; A second insulating material layer is formed on the side of the substrate where the source, the drain and the ground layer are located, and the second insulating material layer is patterned to form a passivation layer covering the source, the drain and the gate insulating layer, and a second insulating layer covering the ground layer.

2. The preparation method according to claim 1, characterized in that After forming the gate insulating layer and the first insulating layer and before forming the second metal layer, the method further includes: A silicon material layer is deposited on the side where the gate insulating layer and the first insulating layer are located on the substrate, the silicon material layer is patterned, and an active layer is formed on the side of the gate insulating layer away from the substrate, wherein the active layer is located between the gate insulating layer and the source and the drain.

3. The preparation method according to claim 2, characterized in that: Depositing a silicon material layer on the side of the gate insulating layer and the first insulating layer located on the substrate, and performing patterning on the silicon material layer, including: In the process of patterning the silicon material layer on the first insulating layer, no light shielding process is performed on the silicon material layer on the first insulating layer, so that the silicon material layer on the first insulating layer is etched away; Alternatively, the silicon material layer located on the first insulating layer is directly removed.

4. The preparation method according to claim 1, characterized in that: The gate electrode and the solder layer are arranged to be spaced apart.

5. The preparation method according to claim 1, characterized in that: Also includes: A third metal layer is formed on a side of the substrate where the passivation layer and the second insulating layer are located, and the third metal layer is patterned to form a touch electrode layer located on a side of the passivation layer away from the substrate, and a power layer located on a side of the second insulating layer away from the substrate.

6. The preparation method according to any one of claims 1 to 5, characterized in that: The patterning process sequentially comprises: Coating photoresist, exposure, development, etching and photoresist stripping.

7. The preparation method according to claim 6, characterized in that: The patterning process of the first metal layer includes: performing a light shielding process on two portions of the first metal layer located on the substrate; And / or, patterning the first insulating material layer includes: performing light shielding on the first insulating material layer located above and around the gate and the solder layer respectively; And / or, the patterning process of the second metal layer includes: performing a light shielding process on the second metal layer respectively located in the orthographic projection of the gate insulating layer and the solder layer along the thickness direction of the array substrate, and leaving a blank in the middle of the second metal layer on the gate insulating layer without performing the light shielding process; And / or, the patterning process of the second insulating material layer includes: shading the second insulating material layer located above and around the gate insulating layer, and shading the second insulating material layer located within the orthographic projection of the first insulating layer in the thickness direction of the array substrate.

8. The preparation method according to any one of claims 1 to 5, characterized in that: The material of the substrate includes one of glass and plastic; When the material of the substrate is glass, the substrate has the following performance parameters: Thermal conductivity is 0.7~1.3W(m·k); The thermal expansion coefficient is 3-4ppm / ℃; The line width is 3 to 4 μm and the line spacing is 2 to 3 μm.

9. An array substrate, characterized in that: The method is prepared according to any one of claims 1 to 8.

10. A display device, comprising a housing and a mainboard, characterized in that: The display device further comprises the array substrate according to claim 9, the main board and the array substrate are arranged in the housing, and the array substrate is electrically connected to the main board.

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