LED flip chip packaging test method and related equipment

Abstract

The invention provides a packaging test method of an LED flip chip and related equipment. The method comprises the following steps: acquiring wafer packaging parameters of the LED flip chip; determining a warping degree prediction model of wafer packaging parameters and a process parameter sensitivity sequence through multi-physics field coupling modeling; monitoring a warpage measurement distribution diagram of the wafer according to the warpage prediction model; determining wafer warpage compensation data according to the process parameter sensitivity sequence and the warpage measurement distribution diagram; comparing a three-dimensional deformation graph correspondingly generated by the wafer warping degree compensation data with a prediction result of the warping degree prediction model, and determining a comparison result; and performing welding spot defect high-resolution scanning on the wafer of the LED flip chip according to the comparison result, and identifying the welding spot defect of wafer packaging. Through the implementation of the scheme of the invention, accurate prediction, effective compensation and reliable detection of wafer buckling deformation in the packaging process of the LED flip chip can be realized, and the packaging quality is remarkably improved.

Description

Technical Field

[0001] The present application relates to the field of packaging and testing technology, and in particular to a packaging and testing method for LED flip chips and related equipment. Background Art

[0002] LED flip chip technology is widely used in the field of high-power LED modules due to its excellent heat dissipation performance and high-density packaging characteristics. However, in the packaging process of LED flip chips, due to the complexity of process parameters and differences in material properties, wafer warping often occurs, which directly affects the quality and reliability of solder joints.

[0003] Existing packaging test methods mainly rely on single optical or ultrasonic detection methods, which cannot accurately predict and compensate for the warpage deformation during the wafer packaging process, resulting in low accuracy and reliability of solder joint defect detection. Especially in the mass production of high-power LED modules, solder joint defects caused by wafer warpage often show complex three-dimensional features, and traditional detection methods are difficult to accurately identify and locate such complex defects. Summary of the invention

[0004] The present application provides a packaging and testing method for an LED flip chip and related equipment, which are used to solve the problem in the related art that it is difficult to accurately identify and locate solder joint defects caused by wafer warping.

[0005] The first aspect of the present application provides a packaging and testing method for an LED flip chip, the packaging and testing method for an LED flip chip comprising: Get the wafer packaging parameters of LED flip chip; Determine the warpage prediction model of the wafer packaging parameters and the process parameter sensitivity ranking through multi-physics field coupling modeling; Monitoring a warpage metric distribution map of a wafer according to the warpage prediction model; Determining wafer warpage compensation data according to the process parameter sensitivity ranking and the warpage metric distribution map; Comparing the three-dimensional deformation map generated corresponding to the wafer warpage compensation data with the prediction result of the warpage prediction model to determine the comparison result; The comparison result is used to perform a high-resolution scan of solder joint defects on the LED flip chip wafer to identify solder joint defects of the wafer package.

[0006] Optionally, in a first implementation of the first aspect of the present application, the step of determining the warpage prediction model of the wafer packaging parameters and the process parameter sensitivity ranking by multi-physics field coupling modeling includes: Generate an initial finite element model corresponding to the wafer packaging parameters through three-dimensional finite element meshing; According to the initial finite element model, a transient temperature field and a thermal stress field of the packaging process are coupled and solved to determine the stress distribution field of each area on the wafer surface and an initial warpage prediction curve; Determine a solder creep response model of the solder corresponding to the wafer packaging process according to the stress distribution field and the creep constitutive equation; Determining a set of process parameter influencing factors of the wafer packaging process according to the initial warpage prediction curve; Based on the process parameter influencing factor set and historical process data, a weight coefficient matrix of the process parameters and wafer warpage metrics is determined by a random forest regression model; The solder creep response model is sorted by parameter sensitivity through the weight coefficient matrix, and the warpage prediction model of the wafer packaging parameters and the process parameter sensitivity sorting are output.

[0007] Optionally, in a second implementation of the first aspect of the present application, the step of monitoring the warpage metric distribution map of the wafer according to the warpage prediction model includes: Acquiring temperature gradient data and strain timing data of each area on the wafer surface; generating predicted warpage distribution data matching the real-time process stage according to the temperature gradient data; Based on the strain time series data and the predicted warpage distribution data, a Kalman filter correction process is performed on the temperature drift error of the optical fiber sensor to determine the corrected temperature-strain field fusion data; Performing spatiotemporal alignment processing on the temperature-strain field fusion data and the predicted value of the warpage prediction model by using a dynamic time warping algorithm to generate a residual distribution matrix; A warpage distribution map of the wafer is determined according to the residual distribution matrix.

[0008] Optionally, in a third implementation of the first aspect of the present application, the step of determining wafer warpage compensation data according to the process parameter sensitivity ranking and the warpage measurement distribution map includes: Determine a process parameter priority weight table according to the process parameter sensitivity ranking and the weight coefficient matrix; Determine a set of spatial coordinates of each sensitive area on the surface of the wafer according to the warpage distribution map; Performing orthogonal experimental design optimization processing on the local temperature gradient compensation coefficient according to the spatial coordinate set and the process parameter priority weight table to generate a corresponding initial partition compensation curve; Performing multi-objective optimization processing on the initial partition compensation curve by using a non-dominated sorting genetic algorithm to generate an optimized curve compensation set; Performing time series dynamic alignment processing on the compensation parameters of each sensitive area according to the optimization curve compensation set to generate global temperature gradient compensation time series data; The warpage prediction model is weightedly fused with the global temperature gradient compensation timing data to determine wafer warpage compensation data.

[0009] Optionally, in a fourth implementation of the first aspect of the present application, the step of comparing the three-dimensional deformation map generated corresponding to the wafer warpage compensation data with the prediction result of the warpage prediction model and determining the comparison result includes: Iteratively registering the measured point cloud data of the three-dimensional deformation map with the predicted grid data of the warpage prediction model to generate a coordinate transformation matrix; Based on the coordinate transformation matrix, spatial interpolation alignment processing is performed on the measured point cloud data and the predicted grid data to generate a shape variable difference distribution matrix; According to the deformation difference distribution matrix, a spatial autocorrelation analysis process based on the Moran index is performed on the wafer surface to identify high autocorrelation abnormal areas; The Gaussian mixture model is used to perform multimodal clustering processing on the deformation difference values ​​of the high autocorrelation abnormal area to generate a corresponding comparison analysis report.

[0010] Optionally, in a fifth implementation of the first aspect of the present application, the step of performing a high-resolution scan of solder joint defects on the LED flip chip wafer based on the comparison result to identify solder joint defects of the wafer package includes: According to the high confidence probability areas marked in the comparison analysis report, adaptive scanning path planning processing is performed on the wafer surface to generate a partitioned scanning path sequence; Based on the partition scanning path sequence, a dynamic parameter matching process is performed on the scanning index of the high-resolution X-ray imaging device to determine a scanning parameter set corresponding to the defect type; According to the scanning parameter set, multi-angle tomographic projection data acquisition and processing are performed on the wafer solder joints, and three-dimensional defect data and defect morphology feature vectors are generated through an iterative reconstruction algorithm; The three-dimensional defect data and the defect morphology feature vector are input into a pre-trained neural network model to identify the solder joint defect type of the wafer package.

[0011] Optionally, in a sixth implementation of the first aspect of the present application, the method further includes: Dynamically correct the wafer packaging parameters according to the solder joint defect type and generate real-time process parameter adjustment instructions; Based on the process parameter sensitivity ranking and the real-time process parameter adjustment instructions, the compensation parameters and process boundary conditions are collaboratively optimized through a reinforcement learning algorithm, and an optimized process parameter configuration table is output; Performing process verification on the next batch of LED flip chips according to the process parameter configuration table, and collecting real-time data during the verification process through distributed optical fiber sensors; The real-time data is input into the warpage prediction model for iterative updating to generate updated model parameters for adaptive process drift compensation.

[0012] A second aspect of the present application provides a packaging and testing device for an LED flip chip, the packaging and testing device for an LED flip chip comprising: An acquisition module, used to acquire wafer packaging parameters of LED flip chips; A first determination module is used to determine the warpage prediction model of the wafer packaging parameters and the process parameter sensitivity ranking through multi-physics field coupling modeling; A monitoring module, used for monitoring a warpage metric distribution map of a wafer according to the warpage prediction model; A second determination module is used to determine wafer warpage compensation data according to the process parameter sensitivity ranking and the warpage measurement distribution map; A comparison module, used for comparing the three-dimensional deformation map generated corresponding to the wafer warpage compensation data with the prediction result of the warpage prediction model to determine the comparison result; The identification module is used to perform a high-resolution scan of solder joint defects on the wafer of the LED flip chip according to the comparison result, and identify the solder joint defects of the wafer package.

[0013] A third aspect of an embodiment of the present application provides an electronic device, comprising a memory and a processor, wherein the processor is used to execute a computer program stored in the memory, and when the processor executes the computer program, it implements each step of the LED flip chip packaging and testing method provided in the first aspect of the embodiment of the present application.

[0014] The fourth aspect of the embodiments of the present application provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, each step of the LED flip chip packaging and testing method provided in the first aspect of the embodiments of the present application is implemented.

[0015] In summary, according to the LED flip chip packaging test method and related equipment provided by the present application, the wafer packaging parameters of the LED flip chip are obtained; the warpage prediction model of the wafer packaging parameters and the process parameter sensitivity ranking are determined through multi-physical field coupling modeling; the warpage measurement distribution map of the wafer is monitored according to the warpage prediction model; the wafer warpage compensation data is determined according to the process parameter sensitivity ranking and the warpage measurement distribution map; the three-dimensional deformation map corresponding to the wafer warpage compensation data is compared with the prediction result of the warpage prediction model to determine the comparison result; the LED flip chip wafer is scanned with high resolution for solder joint defects through the comparison result to identify the solder joint defects of the wafer package. Through the implementation of the present application, the accurate prediction, effective compensation and reliable detection of wafer warpage deformation in the LED flip chip packaging process can be achieved, which significantly improves the packaging quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic flow chart of a packaging and testing method for an LED flip chip provided in an embodiment of the present application; Figure 2 A schematic diagram of a program module of a packaging and testing device for an LED flip chip provided in an embodiment of the present application; Figure 3 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to make the purpose, features, and advantages of the invention of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0018] In order to solve the problem in the related art that it is difficult to accurately identify and locate solder joint defects caused by wafer warpage, the present application embodiment provides a packaging test method for LED flip chips, such as Figure 1 The present invention provides a schematic flow chart of a packaging and testing method for an LED flip chip. The packaging and testing method for an LED flip chip includes the following steps: Step 110: Obtain wafer packaging parameters of LED flip chip.

[0019] Specifically, in this embodiment, wafer packaging parameters are the underlying data foundation of packaging testing, covering multi-dimensional information such as material properties, geometric structures, and process conditions, including but not limited to material property parameters (such as elastic modulus, thermal expansion coefficient, thermal conductivity of chips, solder, and substrates), geometric parameters (chip size, solder joint array spacing, substrate thickness), process parameters (reflow peak temperature, heating rate, pressure load), etc. They are obtained through process file analysis, real-time sensor acquisition (such as infrared thermometer monitoring temperature field distribution) and high-precision measurement equipment (white light interferometer to obtain solder layer thickness), and integrated into a structured database.

[0020] Step 120: Determine the warpage prediction model of wafer packaging parameters and the process parameter sensitivity ranking through multi-physics field coupling modeling.

[0021] Specifically, in this embodiment, multi-physics field coupling modeling is an advanced simulation technology that can simultaneously consider the interaction of multiple physical fields such as heat, mechanics, and electricity. In the packaging process of LED flip chips, the coupling of these physical fields has a significant effect on the warpage of the wafer. By establishing a warpage prediction model, the warpage of the wafer during the packaging process can be predicted in advance, thereby providing a basis for subsequent compensation and optimization. The process parameter sensitivity ranking is to determine which parameters have the most significant impact on the warpage by analyzing the degree of influence of different process parameters on the warpage. For example, changes in packaging temperature and pressure may have a greater impact on the warpage, while the impact of certain material characteristic parameters is relatively small. Through this sorting, key process parameters can be optimized in a targeted manner, thereby effectively controlling the warpage of the wafer.

[0022] In an optional implementation of the present embodiment, the steps of determining the warpage prediction model of wafer packaging parameters and the process parameter sensitivity ranking through multi-physical field coupling modeling include: generating an initial finite element model corresponding to the wafer packaging parameters through three-dimensional finite element meshing; coupling and solving the transient temperature field and thermal stress field of the packaging process according to the initial finite element model to determine the stress distribution field and the initial warpage prediction curve of each area on the wafer surface; determining the solder creep response model of the solder corresponding to the wafer packaging process according to the stress distribution field and the creep constitutive equation; determining the set of process parameter influencing factors of the wafer packaging process according to the initial warpage prediction curve; determining the weight coefficient matrix of process parameters and wafer warpage measurement through a random forest regression model based on the set of process parameter influencing factors and historical process data; and ranking the parameter sensitivity of the solder creep response model through the weight coefficient matrix, and outputting the warpage prediction model of the wafer packaging parameters and the process parameter sensitivity ranking.

[0023] Specifically, in this embodiment, in the process of generating an initial finite element model corresponding to wafer packaging parameters through three-dimensional finite element meshing, it is first necessary to establish a geometric model of the wafer, including the size, shape, material properties, etc. of the wafer, and use these parameters to generate a three-dimensional finite element mesh model. In the generated finite element model, it is necessary to define the physical properties of the material such as thermal conductivity and thermal expansion, and consider the material properties of the solder used in the packaging process. After completing the initial finite element model, the coupling solution stage of the transient temperature field and thermal stress field of the packaging process is entered. During the packaging process, the change of the heat source will cause the temperature difference between the wafer and the packaging material, thereby inducing thermal stress. Coupled simulation is performed by solving the heat conduction equation and the stress balance equation. While solving the temperature field, the distribution of the thermal stress field can be calculated by the thermal expansion equation. The evolution of the stress field is usually derived according to the elastic model of thermal stress, considering the influence of the elastic modulus, Poisson's ratio and thermal expansion coefficient of the material, and obtaining the thermal stress value of each grid point. The result of this process will reflect the stress distribution in different areas of the wafer surface and generate a preliminary warpage prediction curve. After obtaining the preliminary stress field distribution and warpage prediction curve, the creep response model of solder in the wafer packaging process is determined according to the creep constitutive equation. The solder material is subjected to temperature changes and stress during the packaging process, and its deformation behavior often exhibits creep characteristics. The creep constitutive equation usually takes a form similar to the following: , in, is the creep rate, is the stress, A is the material constant, n is the stress exponent, is the activation energy, R is the gas constant, T is the temperature, is the stress criterion, is a coefficient related to material properties, and m is a stress exponent. This equation reflects the deformation characteristics of solder under different temperature and stress conditions, and is used to predict the creep behavior of solder during the packaging process. According to the initial warpage prediction curve, the set of process parameter influencing factors of the packaging process is determined. These influencing factors mainly include factors such as temperature change rate, packaging time, selection of solder materials, and pressure application. Through statistical analysis and experimental data, the contribution of each process parameter to the wafer warpage can be obtained. Based on the set of process parameter influencing factors and historical process data, a random forest regression model is used to determine the weight coefficient matrix between process parameters and wafer warpage metrics. The random forest regression model constructs multiple regression trees and uses the evaluation of the impact of each tree on the process parameters to derive the weight coefficient of each process parameter on the wafer warpage. These weight coefficients reflect the sensitivity of different process parameters to warpage, thereby providing guidance for process optimization. In this model, the goal is to train the random forest regression model by minimizing the prediction error to obtain an accurate relationship between process parameters and warpage metrics. The sensitivity of the parameters of the solder creep response model is sorted according to the weight coefficient matrix. Through this sorting, the selection of solder materials and the design of the packaging process can be further optimized, thereby minimizing the possibility of wafer warpage and ensuring the success of the packaging process. Finally, the warpage prediction model of the wafer packaging parameters and the sensitivity sorting of the process parameters are output, providing reliable data support and theoretical basis for subsequent packaging optimization.

[0024] Step 130 : monitoring the warpage distribution map of the wafer according to the warpage prediction model.

[0025] Specifically, in this embodiment, the warpage metric distribution map is generated by a warpage prediction model to intuitively display the warpage of the wafer during the packaging process. The distribution map can show the degree of warpage in different areas of the wafer, helping engineers to quickly identify areas with higher warpage. By real-time monitoring of the warpage metric distribution map, problems that may occur in the packaging process, such as local stress concentration or uneven materials, can be discovered in a timely manner. This monitoring method has the characteristics of high precision and high efficiency, and can provide real-time feedback during the packaging process, thereby guiding the adjustment of process parameters. In addition, the warpage metric distribution map can also be used to evaluate the stability and consistency of the packaging process, providing data support for subsequent process optimization.

[0026] In an optional implementation of the present embodiment, the step of monitoring the warpage measurement distribution map of the wafer according to the warpage prediction model includes: acquiring temperature gradient data and strain timing data of each area on the wafer surface; generating predicted warpage distribution data matching the real-time process stage according to the temperature gradient data; performing Kalman filtering correction processing on the temperature drift error of the optical fiber sensor based on the strain timing data and the predicted warpage distribution data, and determining the corrected temperature-strain field fusion data; performing spatiotemporal alignment processing on the temperature-strain field fusion data and the predicted value of the warpage prediction model through a dynamic time warping algorithm, and generating a residual distribution matrix; and determining the warpage distribution map of the wafer according to the residual distribution matrix.

[0027] Specifically, in this embodiment, in the process of obtaining the temperature gradient data and strain timing data of each area on the wafer surface, it is first necessary to obtain the temperature data of each position on the wafer surface through a high-precision sensor or an optical fiber temperature sensor. Since the temperature distribution on the wafer surface is affected by factors such as the change of heat source and the thermal expansion characteristics of the material during the packaging process, the temperature gradient at each position shows a different change trend. In order to accurately capture this process, an optical fiber temperature sensor array is used. The optical fiber temperature sensor can be distributed along the surface of the wafer to record the temperature changes in each area in real time. At the same time, the timing data of the wafer surface strain can be obtained by a strain gauge or an optical fiber strain sensor. The optical fiber strain sensor can record the change of strain and reflect the deformation of the wafer caused by factors such as temperature and pressure during the packaging process.

[0028] Based on these acquired temperature gradient data, combined with the real-time process stage, the predicted warpage distribution data corresponding to each stage can be generated. It can be understood that the warpage prediction model is established by analyzing factors such as the thermal expansion coefficient of the wafer material, the wafer geometry, and the packaging process. Through the temperature gradient data, the temperature changes in different areas can be estimated, and the distribution of warpage can be inferred based on the thermal expansion characteristics of the material. Specifically, the following formula can be used to calculate the predicted warpage value: , in, is the warpage at position x at time t, is the thermal expansion coefficient of the material, is the temperature field, is the initial temperature, is the time element. This formula calculates the warpage caused by temperature changes in each area to obtain the predicted warpage distribution. Based on the strain time series data and the predicted warpage distribution data, it is necessary to correct the temperature drift error. Since the temperature sensor will be affected by environmental changes, resulting in drift errors in the temperature data, it can be corrected by the Kalman filter algorithm. Kalman filtering is an optimal recursive estimation algorithm that can dynamically correct the error based on the system's noise model and observation data. After the temperature-strain field data is corrected, the dynamic time warping algorithm can be used to perform spatiotemporal alignment of the temperature-strain field fusion data and the predicted value of the warpage prediction model. The dynamic time warping algorithm finds the best alignment by calculating the minimum distance between time series. The goal of the dynamic time warping algorithm is to minimize the "distance" between two time series by optimizing the path: , in, and are the elements of two time series, is the cost function of alignment, which represents the distance between sequence elements. Finally, the optimal alignment path is obtained by minimizing the cost. This algorithm can ensure the spatiotemporal alignment between the warpage prediction data and the temperature strain data, thereby improving the accuracy of the model.

[0029] Finally, the warpage distribution map of the wafer can be determined by analyzing the residual distribution matrix. The residual distribution matrix is ​​composed of the comparison results of the temperature strain field data and the warpage prediction model, reflecting the error between the predicted value and the actual observed value. The size and distribution of the residual can provide an intuitive analysis tool for the risk of wafer warpage and guide the optimization of the packaging process. By further processing the residual matrix, a warpage distribution map can be generated. This graph provides an important basis for warpage control in the packaging process, helps optimize the key parameters in the packaging process, and ensures the final product quality.

[0030] Step 140 : determining wafer warpage compensation data according to the process parameter sensitivity ranking and the warpage measurement distribution map.

[0031] Specifically, in this embodiment, after determining the process parameter sensitivity ranking and the warpage measurement distribution map, the wafer warpage compensation data can be further calculated. The generation of compensation data is based on the analysis of the warpage prediction model, and the warpage of the wafer is compensated by adjusting the key process parameters. For example, if the warpage of a certain area is high, the warpage can be reduced by increasing the packaging pressure of the area or adjusting the packaging temperature. The process parameter sensitivity ranking guides which parameters need to be adjusted first to achieve the best compensation effect. In this way, the warpage of the wafer can be accurately controlled to ensure that the packaged chip has good performance and reliability.

[0032] In an optional implementation of the present embodiment, the step of determining wafer warpage compensation data according to process parameter sensitivity ranking and warpage measurement distribution map includes: determining a process parameter priority weight table according to process parameter sensitivity ranking and a weight coefficient matrix; determining a spatial coordinate set of each sensitive area on the wafer surface according to the warpage distribution map; performing orthogonal experimental design optimization processing on the local temperature gradient compensation coefficient according to the spatial coordinate set and the process parameter priority weight table to generate a corresponding initial partition compensation curve; performing multi-objective optimization processing on the initial partition compensation curve through a non-dominated sorting genetic algorithm to generate an optimized curve compensation set; performing time series dynamic alignment processing on the compensation parameters of each sensitive area according to the optimized curve compensation set to generate global temperature gradient compensation timing data; weighted fusion of the warpage prediction model and the global temperature gradient compensation timing data to determine the wafer warpage compensation data.

[0033] Specifically, in the present embodiment, in the process of determining the process parameter priority weight table according to the process parameter sensitivity ranking and the weight coefficient matrix, it is first necessary to quantitatively analyze the influence of each process parameter in the warpage control. The process parameter sensitivity ranking analyzes the influence of each process parameter on the warpage change to obtain the contribution of each parameter. This analysis result can be used to construct a priority weight table to reflect the contribution of different process parameters to the warpage. Subsequently, the spatial coordinate set of each sensitive area on the wafer surface is determined based on the warpage distribution map. The warpage distribution map shows the warpage change at different positions on the wafer surface, where the area with a large warpage change is generally considered to be a sensitive area. By analyzing the warpage distribution map, it is possible to clarify which areas on the wafer surface are most sensitive to warpage control, and further obtain the spatial coordinate set of these areas. After obtaining the spatial coordinate set of the sensitive area, the orthogonal experimental design optimization of the local temperature gradient compensation coefficient is performed according to these coordinates and the process parameter priority weight table. Orthogonal experimental design is a multi-factor analysis method that allows the influence of each factor to be systematically evaluated and reduces the number of experiments by reasonably arranging experiments. In this optimization process, the compensation coefficient of each sensitive area is used as one factor of the experiment, and the process parameters are used as another factor. Through orthogonal experimental design, the local temperature gradient compensation coefficient under different process parameter combinations can be determined, and the initial partition compensation curve can be generated. The generation of the partition compensation curve depends on the relationship between the compensation coefficient and each process parameter, which can be determined by regression analysis or fitting method.

[0034] The initial partition compensation curve is optimized by multi-objective using the non-dominated sorting genetic algorithm. Genetic algorithm is an optimization method that simulates natural selection. It can search for the global optimal solution through selection, crossover and mutation operations. In this problem, the non-dominated sorting genetic algorithm is used to optimize multiple objectives, usually including reducing the warping degree and optimizing the compensation effect. In the genetic algorithm, each individual represents a solution, and its quality is measured by the evaluation function. The core idea of ​​non-dominated sorting is to select solutions that are superior in multiple objectives, rather than relying solely on a certain objective. During the optimization process, the genetic algorithm will continue to iterate to obtain the optimal compensation curve set. After optimizing the compensation curve set, it is necessary to dynamically align the compensation parameters of each sensitive area in time series. Since the compensation curves are generated at different time points and the change of warping degree is a dynamic process, it is necessary to align the compensation parameters in time series. This process is also performed by the dynamic time warping algorithm.

[0035] Finally, the warpage prediction model and the global temperature gradient compensation timing data are weighted and fused to determine the wafer warpage compensation data. The weighted fusion process gives different weights to the warpage prediction model and compensation timing data, and comprehensively considers their impact on warpage control. The weighted fusion formula can be expressed as: , in, is the warpage compensation data after weighted fusion, is the output of the warpage prediction model, is the global temperature gradient compensation timing data, and is the weight coefficient, which reflects the importance of the two in the final compensation. Through this weighted fusion, the warpage compensation data finally obtained can accurately reflect the warpage changes in various areas of the wafer surface, provide a reliable basis for optimizing the packaging process, and ensure that the quality of the final product meets the design requirements.

[0036] Step 150 : Compare the three-dimensional deformation map generated corresponding to the wafer warpage compensation data with the prediction result of the warpage prediction model to determine the comparison result.

[0037] Specifically, in this embodiment, a three-dimensional deformation map is generated based on the wafer warpage compensation data to show the deformation of the wafer after compensation. By comparing the three-dimensional deformation map with the prediction results of the warpage prediction model, the validity of the compensation data can be verified. If the comparison results show that the compensated warpage is consistent with the prediction results, it means that the compensation data is accurate; otherwise, the compensation data needs to be further adjusted. This comparison method can ensure the reliability of the compensation data, thereby providing an accurate reference for subsequent solder joint defect detection. In addition, the comparison results can also be used to evaluate the optimization effect of the packaging process and provide a basis for subsequent process improvements.

[0038] In an optional implementation of the present embodiment, the three-dimensional deformation map generated corresponding to the wafer warpage compensation data is compared with the prediction result of the warpage prediction model, and the steps of determining the comparison result include: iteratively aligning the measured point cloud data of the three-dimensional deformation map with the predicted grid data of the warpage prediction model to generate a coordinate transformation matrix; based on the coordinate transformation matrix, spatially interpolating and aligning the measured point cloud data with the predicted grid data to generate a deformation variable difference distribution matrix; according to the deformation variable difference distribution matrix, performing spatial autocorrelation analysis on the wafer surface based on the Moran index to identify high autocorrelation abnormal areas; performing multimodal clustering on the deformation difference values ​​of the high autocorrelation abnormal areas through a Gaussian mixture model to generate a corresponding comparison analysis report.

[0039] Specifically, in this embodiment, when iteratively registering the measured point cloud data of the three-dimensional deformation map with the predicted grid data of the warpage prediction model, it is first necessary to determine the spatial correspondence between the two. The point cloud data and the predicted grid data are obtained in different ways, wherein the point cloud data is the actual deformation data obtained by measurement technology, such as laser scanning or optical sensor, and the predicted grid data is based on the expected deformation result inferred by the finite element model or other theoretical model. Since the measurement and model prediction may have different coordinate systems and scale differences, it is necessary to achieve their spatial alignment through an iterative registration algorithm. The goal of iterative registration is to find a coordinate transformation matrix that can map the coordinates of the predicted grid data to the coordinate system of the measured point cloud data. The commonly used iterative registration method is to minimize the error between the two, and the coordinate transformation matrix is ​​repeatedly adjusted iteratively by the iterative nearest point algorithm to gradually minimize the Euclidean distance between the two. In each iteration, the corresponding points in the point cloud data and the predicted grid data are matched, the distance between them is calculated, and the error is reduced by updating the rotation and translation matrices, and finally a converged coordinate transformation matrix is ​​obtained. Based on the obtained coordinate transformation matrix, the measured point cloud data and the predicted grid data are spatially interpolated and aligned. The purpose of spatial interpolation is to ensure accurate data alignment while making up for the difference between the measured and predicted data to generate a shape variable difference distribution matrix. By applying the coordinate transformation matrix to the measured point cloud data and the predicted grid data, the corresponding data of the two in the same coordinate system can be obtained. Then, the difference between the predicted value and the actual value is calculated at each coordinate point using the interpolation method to obtain the shape variable difference distribution matrix. According to the shape variable difference distribution matrix, the wafer surface is subjected to spatial autocorrelation analysis based on the Moran's index. The Moran's index (Moran's I) is a method to measure the autocorrelation of spatial data, which can evaluate the correlation between adjacent points in spatial data. The calculation formula of the Moran's index is: , Where N is the total number of points, and are the deformation difference values ​​of the i-th and j-th points respectively, is the average value of the deformation difference of all points, is a spatial weight matrix, which indicates the spatial relative relationship between point i and point j. The value of Moran's index can be used to determine the autocorrelation of spatial data. If the Moran's index is close to 1, it indicates strong autocorrelation, and if it is close to -1, it indicates strong anti-autocorrelation, and if it is close to 0, it indicates no significant spatial autocorrelation. In the wafer surface deformation difference matrix, the Moran's index can be used to identify areas with significant spatial autocorrelation. These areas may be abnormal areas caused by some local process defects or external influencing factors in the packaging process.

[0040] After identifying abnormal areas with high autocorrelation, the deformation difference values ​​of these areas can be clustered multimodally using the Gaussian mixture model (GMM). The Gaussian mixture model is a clustering method based on a probability model. It assumes that the data is composed of multiple Gaussian distributions and can effectively capture the potential patterns of the data. In the deformation variable difference distribution matrix, there may be multiple patterns or clusters, and GMM fits these patterns through maximum likelihood estimation. By analyzing each cluster, areas with large deformation differences can be identified and associated with specific process problems. The probability density function of GMM can be expressed as: , in, is the probability density of data point x, is the mixing coefficient of the kth Gaussian distribution, The mean is The covariance is The Gaussian distribution of K is the number of Gaussian distributions. Through this model, high autocorrelation areas can be grouped and corresponding comparison analysis reports can be generated.

[0041] It should be noted that the report will mark the high autocorrelation abnormal areas on the wafer surface. These areas are identified by the spatial autocorrelation analysis of the Moran index, indicating that the deformation difference in these areas has obvious spatial dependence and may be affected by factors such as local process problems or material property inhomogeneity. The report will further show the relationship between key physical properties such as the thermal expansion coefficient and elastic modulus of the material and the deformation of the wafer surface, and analyze how these material properties affect the deformation in different areas. For example, in some areas of the wafer, the deformation may be abnormal due to excessive temperature gradient or significant difference in thermal expansion coefficient, which in turn affects the overall warpage. Secondly, the report will show the results of the comparative analysis, including cluster analysis based on the Gaussian mixture model (GMM). Specifically, the GMM model can divide the deformation difference into several different modes or clusters, each cluster representing a potential source of abnormality. The marked high confidence probability areas will also be listed in detail in the report. These high confidence probability areas are obtained through cluster analysis, indicating that the deformation difference in these areas has a higher confidence, which means that the deformation difference in these areas is more significant and stable.

[0042] Step 160: Perform a high-resolution scan of solder joint defects on the LED flip chip wafer based on the comparison results to identify solder joint defects of the wafer package.

[0043] Specifically, in this embodiment, high-resolution scanning is to perform detailed solder joint defect detection on the wafer through advanced detection equipment, such as a laser scanning microscope or an electron microscope. By comparing the results, it can be determined which areas need to be scanned in focus, thereby improving the efficiency and accuracy of the detection. The identification of solder joint defects is based on the analysis of the scanned image. Through image processing and pattern recognition technology, solder joint defects such as solder joint unevenness, solder joint missing or solder joint cracks can be automatically identified. This detection method has the characteristics of high resolution and high sensitivity, and can effectively identify tiny solder joint defects, ensuring that the packaged chip has good reliability and performance.

[0044] In an optional implementation of the present embodiment, a high-resolution scan of solder joint defects on a wafer of an LED flip chip is performed through comparison results to identify solder joint defects in wafer packaging, including: performing adaptive scanning path planning processing on the wafer surface according to the high confidence probability area marked in the comparison analysis report to generate a partitioned scanning path sequence; based on the partitioned scanning path sequence, performing dynamic parameter matching processing on the scanning indicators of a high-resolution X-ray imaging device to determine a scanning parameter set corresponding to the defect type; performing multi-angle tomographic projection data acquisition processing on the wafer solder joints according to the scanning parameter set, and generating three-dimensional defect data and defect morphology feature vectors through an iterative reconstruction algorithm; and inputting the three-dimensional defect data and defect morphology feature vectors into a pre-trained neural network model to identify the solder joint defect type of the wafer package.

[0045] Specifically, in this embodiment, accurate scanning path design is performed based on the high autocorrelation abnormal areas identified in the report. The core goal of adaptive scanning path planning is to cover these abnormal areas as efficiently as possible, while avoiding repeated scanning of irrelevant areas, thereby improving scanning efficiency and imaging accuracy. To this end, a partition scanning strategy based on regional importance can be adopted. When designing the scanning path, the wafer surface is first spatially partitioned, the high confidence probability area is divided into multiple sub-areas, and an appropriate scanning density is assigned to each area. For the part marked as a high autocorrelation area, more scanning resources and high-density scanning paths should be arranged first, while the scanning frequency can be appropriately reduced for the low confidence area. In order to achieve adaptive path planning, an optimization algorithm can be used to minimize the scanning time while ensuring that all important areas are covered, and a partition scanning path sequence can be generated. After the partition scanning path sequence is generated, the scanning indicators of the high-resolution X-ray imaging device are dynamically matched based on the partition scanning path. The scanning parameters (such as the power, exposure time, resolution, etc. of the X-ray source) of the X-ray imaging device may vary in different scanning tasks. In order to ensure the accuracy and effectiveness of the scanning results, the scanning parameters must be dynamically adjusted according to the requirements of different types of defects and scanning areas. This process can be achieved by predicting the defect type and adjusting the scanning parameters based on historical data or real-time feedback information. For example, some defect types may require higher resolution, while others only require moderate exposure time and source power. When dynamically matching scanning parameters, machine learning algorithms are used to analyze the relationship between historical scanning data and defect types, so as to automatically select the appropriate set of scanning parameters.

[0046] After determining the appropriate set of scanning parameters, it is necessary to collect and process the multi-angle tomographic projection data of the wafer solder joints. The tomographic projection data collection is to irradiate the wafer surface with X-rays from multiple different angles and record the projection data at each angle, which includes the perspective information of the wafer surface and solder joints at different angles. By fusing the X-ray imaging data at different angles, more comprehensive information about the three-dimensional morphology of the solder joints can be obtained. The core of tomographic imaging is that it can obtain a more accurate three-dimensional structural image than single-angle imaging through the combination of multi-angle projection. The three-dimensional data is reconstructed using an iterative reconstruction algorithm based on the collected projection data. The iterative reconstruction algorithm is a process that gradually adjusts the three-dimensional data model through continuous optimization to make it best match the measured projection data. Through iterative reconstruction, the three-dimensional defect data of the solder joint can be obtained, and the morphological feature vectors of the defects can be further extracted. These vectors will be used for subsequent defect identification and classification. The obtained three-dimensional defect data and defect morphological feature vectors are input into the pre-trained neural network model to identify the type of solder joint defects. After being trained with a large amount of historical data, the neural network model can automatically identify different types of solder joint defects, such as voids, cracks, offsets, etc. Neural networks usually use deep learning architectures such as convolutional neural networks (CNN) to process images and three-dimensional data. They can extract high-level features from raw data through multi-layer neuron connections to achieve accurate defect classification. After inputting the three-dimensional defect data, the neural network calculates the output of each layer through the forward propagation algorithm and finally obtains the defect type prediction result. In this way, solder joint defects in wafer packaging can be accurately identified, providing an important basis for subsequent quality control and process optimization.

[0047] In an optional implementation of the present embodiment, the wafer packaging parameters are dynamically corrected according to the solder joint defect type, and real-time process parameter adjustment instructions are generated; based on the process parameter sensitivity ranking and the real-time process parameter adjustment instructions, the compensation parameters and process boundary conditions are collaboratively optimized through a reinforcement learning algorithm, and an optimized process parameter configuration table is output; the process of the next batch of LED flip chips is verified according to the process parameter configuration table, and real-time data in the verification process is collected through distributed optical fiber sensors; the real-time data is input into the warpage prediction model for iterative update processing, and updated model parameters for adaptive process drift compensation are generated.

[0048] Specifically, in this embodiment, the relevant parameters of the packaging process are adjusted according to the output results of the defect recognition model, that is, the type of solder joint defects. For example, if there are voids or cracks in the solder joint, it may be necessary to adjust parameters such as temperature gradient, pressure application or solder dosage to avoid further development of the defect. These adjustments need to be based on the analysis of the solder joint defect type, and the corresponding process modification plan is determined according to the specific manifestation of the defect. By comparing historical data and solder joint defect types, a dynamic correction mechanism can be constructed. When a certain defect type is detected, the system can automatically generate real-time process parameter adjustment instructions. The purpose of these adjustment instructions is to optimize the process parameters used in the current packaging process, reduce the possibility of defects, and ultimately improve the quality of the product. Based on the sensitivity ranking of process parameters and real-time process parameter adjustment instructions, the compensation parameters and process boundary conditions are coordinated and optimized by the reinforcement learning algorithm. Specifically, the reinforcement learning algorithm evaluates whether the process results after each adjustment are improved by defining a reward function, and performs real-time learning based on the influence of process parameters on warpage and defect incidence. The reinforcement learning model can continuously optimize the process parameters based on these feedbacks to improve the quality of the packaging process. Ultimately, the reinforcement learning model will output an optimized process parameter configuration table, clearly indicating the best process parameters to be used under specific conditions.

[0049] According to the process parameter configuration table, the process verification of the next batch of LED flip chips is carried out. During the verification process, distributed fiber optic sensors are used to collect data in the process in real time. These sensors can monitor physical quantities such as temperature, pressure and strain in the packaging process. These real-time data will be used as input for further iterative update and optimization of the model. By analyzing these real-time data, the actual deviations in the process can be understood in a timely manner, and these implementation data can be input into the warpage prediction model for iterative update processing. The warpage prediction model is a mathematical model built based on previous process data and warpage analysis results. It can predict the warpage behavior of wafers under different process conditions. When new real-time data is input into the model, the model will correct the original prediction parameters based on these data to improve its accuracy. The prediction model is based on certain process parameters (such as temperature, pressure, etc.), and the model parameters can be updated through the following iterative formula: , in, is the parameter in the kth iteration, is the learning rate, is the loss function with respect to the parameters The gradient of It is the loss function of the prediction model, which is usually measured by the difference between the warpage and the actual data. Through such an iterative update process, the model can continuously optimize its prediction ability based on new real-time data and generate more accurate adaptive process drift compensation to update the model parameters.

[0050] In each iteration of the process, the warpage prediction model is gradually adjusted based on actual process feedback data to cope with any drift that may occur during the process. Through continuous updating and optimization, the model can adapt to the dynamic changes in the packaging process, thereby providing more accurate warpage predictions, and based on real-time process parameter adjustment feedback, gradually improve the packaging process, and ultimately achieve effective control of wafer warpage.

[0051] According to a packaging and testing method for LED flip chips provided by the present application, wafer packaging parameters of LED flip chips are obtained; a warpage prediction model of wafer packaging parameters and a process parameter sensitivity ranking are determined through multi-physical field coupling modeling; a warpage measurement distribution diagram of the wafer is monitored according to the warpage prediction model; wafer warpage compensation data is determined according to the process parameter sensitivity ranking and the warpage measurement distribution diagram; a three-dimensional deformation diagram corresponding to the wafer warpage compensation data is compared with the prediction result of the warpage prediction model to determine the comparison result; a high-resolution scan of solder joint defects of LED flip chip wafers is performed through the comparison result to identify solder joint defects of wafer packaging. Through the implementation of the present application, accurate prediction, effective compensation and reliable detection of wafer warpage deformation during LED flip chip packaging can be achieved, significantly improving the packaging quality.

[0052] Figure 2 The present invention provides a packaging and testing device for an LED flip chip, which can be used to implement the packaging and testing method for the LED flip chip in the above-mentioned embodiment. Figure 2 As shown, the LED flip chip packaging and testing device mainly includes: An acquisition module 10 is used to acquire wafer packaging parameters of LED flip chips; A first determination module 20 is used to determine a warpage prediction model of wafer packaging parameters and a process parameter sensitivity ranking through multi-physics field coupling modeling; A monitoring module 30, for monitoring a warpage metric distribution map of a wafer according to a warpage prediction model; A second determination module 40 is used to determine the wafer warpage compensation data according to the process parameter sensitivity ranking and the warpage metric distribution map; A comparison module 50 is used to compare the three-dimensional deformation map generated corresponding to the wafer warpage compensation data with the prediction result of the warpage prediction model to determine the comparison result; The identification module 60 is used to perform high-resolution scanning of solder joint defects on the LED flip chip wafer based on the comparison results, and identify solder joint defects of the wafer package.

[0053] In an optional implementation of the present embodiment, the first determination module is specifically used to: generate an initial finite element model corresponding to wafer packaging parameters through three-dimensional finite element mesh division; couple and solve the transient temperature field and thermal stress field of the packaging process according to the initial finite element model to determine the stress distribution field and the initial warpage prediction curve of each area on the wafer surface; determine the solder creep response model of the solder corresponding to the wafer packaging process according to the stress distribution field and the creep constitutive equation; determine the set of process parameter influencing factors of the wafer packaging process according to the initial warpage prediction curve; determine the weight coefficient matrix of process parameters and wafer warpage measurement through a random forest regression model based on the set of process parameter influencing factors and historical process data; and rank the solder creep response model according to the parameter sensitivity through the weight coefficient matrix, and output the warpage prediction model of the wafer packaging parameters and the process parameter sensitivity ranking.

[0054] In an optional implementation of the present embodiment, the monitoring module is specifically used to: obtain temperature gradient data and strain timing data of each area on the wafer surface; generate predicted warpage distribution data matching the real-time process stage based on the temperature gradient data; perform Kalman filtering correction processing on the temperature drift error of the optical fiber sensor based on the strain timing data and the predicted warpage distribution data, and determine the corrected temperature-strain field fusion data; perform spatiotemporal alignment processing on the temperature-strain field fusion data and the predicted value of the warpage prediction model through a dynamic time warping algorithm, and generate a residual distribution matrix; and determine the warpage distribution map of the wafer based on the residual distribution matrix.

[0055] In an optional implementation of the present embodiment, the second determination module is specifically used to: determine a process parameter priority weight table according to the process parameter sensitivity ranking and the weight coefficient matrix; determine a spatial coordinate set of each sensitive area on the wafer surface according to the warpage distribution map; perform orthogonal experimental design optimization processing on the local temperature gradient compensation coefficient according to the spatial coordinate set and the process parameter priority weight table to generate a corresponding initial partition compensation curve; perform multi-objective optimization processing on the initial partition compensation curve through a non-dominated sorting genetic algorithm to generate an optimized curve compensation set; perform time series dynamic alignment processing on the compensation parameters of each sensitive area according to the optimized curve compensation set to generate global temperature gradient compensation timing data; weightedly fuse the warpage prediction model with the global temperature gradient compensation timing data to determine the wafer warpage compensation data.

[0056] In an optional implementation of the present embodiment, the comparison module is specifically used to: iteratively align the measured point cloud data of the three-dimensional deformation map with the predicted grid data of the warpage prediction model to generate a coordinate transformation matrix; based on the coordinate transformation matrix, perform spatial interpolation alignment processing on the measured point cloud data and the predicted grid data to generate a deformation variable difference distribution matrix; based on the deformation variable difference distribution matrix, perform spatial autocorrelation analysis processing on the wafer surface based on the Moran index to identify high autocorrelation abnormal areas; perform multimodal clustering processing on the deformation difference values ​​of the high autocorrelation abnormal areas through a Gaussian mixture model to generate a corresponding comparison analysis report.

[0057] In an optional implementation of the present embodiment, the identification module is specifically used to: perform adaptive scanning path planning processing on the wafer surface according to the high confidence probability area marked in the comparison analysis report, and generate a partitioned scanning path sequence; based on the partitioned scanning path sequence, perform dynamic parameter matching processing on the scanning indicators of the high-resolution X-ray imaging equipment to determine the scanning parameter set corresponding to the defect type; based on the scanning parameter set, perform multi-angle tomographic projection data acquisition processing on the wafer solder joints, and generate three-dimensional defect data and defect morphology feature vectors through an iterative reconstruction algorithm; input the three-dimensional defect data and defect morphology feature vectors into a pre-trained neural network model to identify the solder joint defect type of the wafer package.

[0058] In an optional implementation of this embodiment, the packaging test device also includes: a growth module. The generation module is used to: dynamically correct the wafer packaging parameters according to the type of solder joint defects, and generate real-time process parameter adjustment instructions; based on the process parameter sensitivity ranking and the real-time process parameter adjustment instructions, the compensation parameters and process boundary conditions are collaboratively optimized through the reinforcement learning algorithm, and the optimized process parameter configuration table is output; the next batch of LED flip chips are process verified according to the process parameter configuration table, and real-time data in the verification process is collected through distributed optical fiber sensors; the real-time data is input into the warpage prediction model for iterative update processing, and the updated model parameters of the adaptive process drift compensation are generated.

[0059] According to the LED flip chip packaging test device provided by the present application, the wafer packaging parameters of the LED flip chip are obtained; the warpage prediction model of the wafer packaging parameters and the process parameter sensitivity ranking are determined through multi-physical field coupling modeling; the warpage measurement distribution map of the wafer is monitored according to the warpage prediction model; the wafer warpage compensation data is determined according to the process parameter sensitivity ranking and the warpage measurement distribution map; the three-dimensional deformation map corresponding to the wafer warpage compensation data is compared with the prediction result of the warpage prediction model to determine the comparison result; the LED flip chip wafer is scanned for solder joint defects with high resolution through the comparison result to identify the solder joint defects of the wafer package. Through the implementation of the present application, the accurate prediction, effective compensation and reliable detection of wafer warpage deformation in the LED flip chip packaging process can be achieved, which significantly improves the packaging quality.

[0060] According to the application plan provided Figure 3 An electronic device provided in an embodiment of the present application. The electronic device can be used to implement the LED flip chip packaging test method in the aforementioned embodiment, mainly comprising: The memory 301, the processor 302, and the computer program 303 stored in the memory 301 and executable on the processor 302 are connected to the memory 301 and the processor 302 are connected via communication. When the processor 302 executes the computer program 303, the LED flip chip packaging test method in the above embodiment is implemented. The number of processors can be one or more.

[0061] The memory 301 may be a high-speed random access memory (RAM) memory, or a non-volatile memory (non-volatile memory), such as a disk memory. The memory 301 is used to store executable program codes, and the processor 302 is coupled to the memory 301 .

[0062] Furthermore, the present application also provides a computer-readable storage medium, which may be provided in the electronic device in the above embodiments. Figure 3 Memory in the illustrated embodiment.

[0063] The computer readable storage medium stores a computer program, and when the program is executed by the processor, the packaging and testing method of the LED flip chip in the aforementioned embodiment is implemented. Furthermore, the computer storable medium can also be a U disk, a mobile hard disk, a read-only memory (ROM), a RAM, a magnetic disk or an optical disk, and other media that can store program codes.

[0064] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0065] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0066] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A packaging and testing method for LED flip chips, characterized in that: include: Get the wafer packaging parameters of LED flip chip; Determine the warpage prediction model of the wafer packaging parameters and the process parameter sensitivity ranking through multi-physics field coupling modeling; Monitoring a warpage metric distribution map of a wafer according to the warpage prediction model; Determining wafer warpage compensation data according to the process parameter sensitivity ranking and the warpage metric distribution map; Comparing the three-dimensional deformation map generated corresponding to the wafer warpage compensation data with the prediction result of the warpage prediction model to determine the comparison result; The comparison result is used to perform a high-resolution scan of solder joint defects on the LED flip chip wafer to identify solder joint defects of the wafer package.

2. The LED flip chip packaging and testing method according to claim 1, characterized in that: The step of determining the warpage prediction model of the wafer packaging parameters and the process parameter sensitivity ranking by multi-physics field coupling modeling includes: Generate an initial finite element model corresponding to the wafer packaging parameters through three-dimensional finite element meshing; According to the initial finite element model, a transient temperature field and a thermal stress field of the packaging process are coupled and solved to determine the stress distribution field of each area on the wafer surface and an initial warpage prediction curve; Determine a solder creep response model of the solder corresponding to the wafer packaging process according to the stress distribution field and the creep constitutive equation; Determining a set of process parameter influencing factors of the wafer packaging process according to the initial warpage prediction curve; Based on the process parameter influencing factor set and historical process data, a weight coefficient matrix of the process parameters and wafer warpage metrics is determined by a random forest regression model; The solder creep response model is sorted by parameter sensitivity through the weight coefficient matrix, and the warpage prediction model of the wafer packaging parameters and the process parameter sensitivity sorting are output.

3. The LED flip chip packaging and testing method according to claim 2, characterized in that: The step of monitoring the warpage metric distribution map of the wafer according to the warpage prediction model comprises: Acquiring temperature gradient data and strain timing data of each area on the wafer surface; generating predicted warpage distribution data matching the real-time process stage according to the temperature gradient data; Based on the strain time series data and the predicted warpage distribution data, a Kalman filter correction process is performed on the temperature drift error of the optical fiber sensor to determine the corrected temperature-strain field fusion data; Performing spatiotemporal alignment processing on the temperature-strain field fusion data and the predicted value of the warpage prediction model by using a dynamic time warping algorithm to generate a residual distribution matrix; A warpage distribution map of the wafer is determined according to the residual distribution matrix.

4. The LED flip chip packaging and testing method according to claim 3, characterized in that: The step of determining wafer warpage compensation data according to the process parameter sensitivity ranking and the warpage metric distribution map comprises: Determine a process parameter priority weight table according to the process parameter sensitivity ranking and the weight coefficient matrix; Determine a set of spatial coordinates of each sensitive area on the surface of the wafer according to the warpage distribution map; Performing orthogonal experimental design optimization processing on the local temperature gradient compensation coefficient according to the spatial coordinate set and the process parameter priority weight table to generate a corresponding initial partition compensation curve; Performing multi-objective optimization processing on the initial partition compensation curve by using a non-dominated sorting genetic algorithm to generate an optimized curve compensation set; Performing time series dynamic alignment processing on the compensation parameters of each sensitive area according to the optimization curve compensation set to generate global temperature gradient compensation time series data; The warpage prediction model is weightedly fused with the global temperature gradient compensation timing data to determine wafer warpage compensation data.

5. The LED flip chip packaging and testing method according to claim 1, characterized in that: The step of comparing the three-dimensional deformation map generated corresponding to the wafer warpage compensation data with the prediction result of the warpage prediction model and determining the comparison result includes: Iteratively registering the measured point cloud data of the three-dimensional deformation map with the predicted grid data of the warpage prediction model to generate a coordinate transformation matrix; Based on the coordinate transformation matrix, spatial interpolation alignment processing is performed on the measured point cloud data and the predicted grid data to generate a shape variable difference distribution matrix; According to the deformation difference distribution matrix, a spatial autocorrelation analysis process based on the Moran index is performed on the wafer surface to identify high autocorrelation abnormal areas; The Gaussian mixture model is used to perform multimodal clustering processing on the deformation difference values ​​of the high autocorrelation abnormal area to generate a corresponding comparison analysis report.

6. The LED flip chip packaging and testing method according to claim 5, characterized in that: The step of performing high-resolution scanning of solder joint defects on the LED flip chip wafer based on the comparison result to identify solder joint defects of the wafer package includes: According to the high confidence probability areas marked in the comparison analysis report, adaptive scanning path planning processing is performed on the wafer surface to generate a partitioned scanning path sequence; Based on the partition scanning path sequence, a dynamic parameter matching process is performed on the scanning index of the high-resolution X-ray imaging device to determine a scanning parameter set corresponding to the defect type; According to the scanning parameter set, multi-angle tomographic projection data acquisition and processing are performed on the wafer solder joints, and three-dimensional defect data and defect morphology feature vectors are generated through an iterative reconstruction algorithm; The three-dimensional defect data and the defect morphology feature vector are input into a pre-trained neural network model to identify the solder joint defect type of the wafer package.

7. The LED flip chip packaging and testing method according to claim 6, characterized in that: The method further comprises: Dynamically correct the wafer packaging parameters according to the solder joint defect type and generate real-time process parameter adjustment instructions; Based on the process parameter sensitivity ranking and the real-time process parameter adjustment instructions, the compensation parameters and process boundary conditions are collaboratively optimized through a reinforcement learning algorithm, and an optimized process parameter configuration table is output; Performing process verification on the next batch of LED flip chips according to the process parameter configuration table, and collecting real-time data during the verification process through distributed optical fiber sensors; The real-time data is input into the warpage prediction model for iterative updating to generate updated model parameters for adaptive process drift compensation.

8. A packaging and testing device for LED flip chips, characterized in that: The LED flip chip packaging and testing device comprises: An acquisition module, used to acquire wafer packaging parameters of LED flip chips; A first determination module is used to determine the warpage prediction model of the wafer packaging parameters and the process parameter sensitivity ranking through multi-physics field coupling modeling; A monitoring module, used for monitoring a warpage metric distribution map of a wafer according to the warpage prediction model; A second determination module is used to determine wafer warpage compensation data according to the process parameter sensitivity ranking and the warpage measurement distribution map; A comparison module, used for comparing the three-dimensional deformation map generated corresponding to the wafer warpage compensation data with the prediction result of the warpage prediction model to determine the comparison result; The identification module is used to perform a high-resolution scan of solder joint defects on the wafer of the LED flip chip according to the comparison result, and identify the solder joint defects of the wafer package.

9. An electronic device, characterized in that: The device comprises a memory and a processor, wherein: The processor is used to execute the computer program stored in the memory; When the processor executes the computer program, the steps in the LED flip chip packaging and testing method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps in the LED flip chip packaging and testing method according to any one of claims 1 to 7 are implemented.

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