Memristor-based majority gate logic circuit, control method, device and application

Abstract

The present invention discloses a majority gate logic circuit, a control method, a device and an application based on a memristor, belonging to the technical field of microelectronic devices; it includes two identical memristors M1 and M2 whose resistors and negative electrodes are both connected to one end of the resistor. The present invention makes full use of the resistance state characteristics of the memristor. By setting the resistance state of the memristor M1 to the resistance state corresponding to the logic value c on the basis that the initial resistance state of the memristor M2 is in the high resistance state, the positive electrode of the memristor M1, the positive electrode of the memristor M2, and the input voltage at the other end of the resistor correspond to the voltage -V(b)-V p related to the logic value b, the voltage V(a) related to the logic value a, and the voltage -V(b) related to the logic value b, thereby realizing the majority gate logic operation of the logic values a, b, and c. The present invention only needs to use two memristors to realize the majority gate logic operation, reducing the circuit area overhead.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic devices, and more specifically, relates to a majority gate logic circuit, a control method, a device and an application based on a memristor. Background Art

[0002] The XOR-Majority Graph (XMG) is a combinatorial logic paradigm constructed based on three-input majority gate logic (Majority, MAJ) and XOR logic. Among them, the majority gate realizes the fault-tolerant decision-making function by outputting the majority value of the input signals (MAJ(a, b, c)=ab + ac + bc), and the XOR gate performs linear operations through a parity check mechanism ( ). The two constitute a complete logic basis and can iteratively implement any Boolean function. XMG deeply integrates the two types of logics through topological optimization and shows significant advantages in fields such as arithmetic operations, fault-tolerant computing, and cryptography. In particular, in the design of adders, XMG can use majority gates to implement the core logic of carry generation and cooperate with XOR gates to complete the sum-bit calculation. This characteristic makes XMG an ideal choice for constructing energy-efficient arithmetic units such as full adders and multipliers. The key and difficulty in implementing XMG lies in implementing majority gate logic. Therefore, it is of great significance to study a majority gate logic circuit.

[0003] Currently, existing majority gate logic circuits are mostly implemented based on traditional CMOS technology, but such technologies have obvious problems. First, traditional CMOS circuits require multiple different logic gates and levels to implement the XOR-majority graph, resulting in complex circuit design, large power consumption, and large area. Second, in order to implement the two logics of XOR logic gates and majority logic gates separately, it is usually necessary to design independent circuit units, which will generate redundancy and reduce resource utilization. Therefore, how to reduce circuit complexity, eliminate redundancy, and improve performance has become the main challenge in the current technology.

[0004] Memristors, with their non-volatile resistance state storage and threshold regulation characteristics, provide a subversive solution for the efficient implementation of majority logic gates (MAJ). However, existing majority gate logic circuits based on memristors consist of three memristors and a fixed-value resistor, with a large number of memristors and a large circuit area overhead. Summary of the Invention

[0005] Aiming at the above defects or improvement requirements of the prior art, the present invention provides a control method and device for a majority gate logic circuit and an adder circuit based on a memristor, which are used to solve the technical problem of large circuit area overhead of existing majority gate logic circuits based on memristors.

[0006] To achieve the above object, in a first aspect, the present invention provides a memristor-based majority gate logic circuit for performing majority gate logic operations on logic values a, b, and c, including: a resistor and two identical memristors M1 and M2; the negative electrodes of the memristor M1 and the memristor M2 are both connected to one end of the resistor;

[0007] Before the majority gate logic circuit performs majority gate logic operations on logic values a, b, and c, the resistance state of the memristor M2 is in a high resistance state;

[0008] When the majority gate logic circuit performs majority gate logic operations on logic values a, b, and c, the resistance state of the memristor M1 is the resistance state corresponding to the logic value c, and the positive electrode of the memristor M1 is used to connect to the voltage -V(b)-V p , the positive electrode of the memristor M2 is used to connect to the voltage V(a), the other end of the resistor is used to connect to the voltage -V(b), and the final resistance state of the memristor M2 is the result of the majority gate logic operation of the logic values a, b, and c;

[0009] Among them, the high resistance state of the memristor corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1"; when b is 1, V(b) is V p ; when b is 0, V(b) is a voltage with an amplitude of 0; when a is 1, V(a) is V p ; when a is 0, V(a) is a voltage with an amplitude of 0; the voltage V p satisfies: V set / 2 < V p < V set , and V p < 2|V reset | / 3; V set is the threshold for the memristor to change from the high resistance state to the low resistance state; V reset is the threshold for the memristor to change from the low resistance state to the high resistance state; the resistance value of the resistor ; R H and R L are respectively the high resistance state resistance value and the low resistance state resistance value of the memristor.

[0010] In a second aspect, the present invention provides a control method for the above majority gate logic circuit, including:

[0011] When performing majority gate logic operations on logic values a, b, and c, set the resistance state of the memristor M1 to the resistance state corresponding to the logic value c, connect the voltage -V(b)-V p to the positive electrode of the memristor M1, connect the voltage V(a) to the positive electrode of the memristor M2, connect the voltage -V(b) to the end of the resistor not connected to the memristor, and use the final resistance state of the memristor M2 as the result of the majority gate logic operation of the logic values a, b, and c;

[0012] Among them, before performing the majority gate logic operation on the logical values a, b, and c, the resistance state of the memristor M2 is in a high resistance state.

[0013] In a third aspect, the present invention provides a majority gate logic operation device, including: a controller and the majority gate logic circuit provided in the first aspect of the present invention;

[0014] The controller is used to execute the control method of the majority gate logic circuit provided in the second aspect of the present invention.

[0015] In a fourth aspect, the present invention provides a control method for an adder circuit; wherein, the adder circuit includes: a resistor and four identical memristors M1, M2, M3, and M4; the negative electrodes of the four memristors are all connected to one end of the resistor; the resistance value of the resistor ; R H and R L are respectively the high resistance state resistance value and the low resistance state resistance value of the memristor;

[0016] The control method includes performing an addition operation on the adder circuit to implement 1-bit addends a, b, and carry input c:

[0017] S1. Set the memristor M1 to the resistance state corresponding to c. At this time, the resistance states of the memristors M2, M3, and M4 are all in the high resistance state;

[0018] S2. Make the positive electrodes of the memristors M3 and M4 in a floating state. Connect a voltage -V(b)-V p to the positive electrode of the memristor M1, connect a voltage V(a) to the positive electrode of the memristor M2, and connect a voltage -V(b) to the end of the resistor not connected to the memristor, so as to obtain the majority gate logic operation result of a, b, and c corresponding to its resistance state in the memristor M2 and use it as the carry result of the addition operation;

[0019] Make the positive electrodes of the memristors M2 and M4 in a floating state. Connect a voltage V(a)-2V p to the positive electrode of the memristor M1, connect a voltage with an amplitude of 0 to the positive electrode of the memristor M3, and connect a voltage -V(a)-V p to the end of the resistor not connected to the memristor, so as to obtain the exclusive OR logic operation result of a and c corresponding to its resistance state in the memristor M3;

[0020] After obtaining the exclusive OR logic operation result of a and c, make the positive electrodes of the memristors M1 and M2 in a floating state. Connect a voltage V(b)-2V p to the positive electrode of the memristor M3, connect a voltage with an amplitude of 0 to the positive electrode of the memristor M4, and connect a voltage -V(b)-V p, so as to obtain the XOR logic operation result of a, b, and c corresponding to its resistance state in the memristor M4, and use it as the summation result of the addition operation;

[0021] Among them, the high resistance state of the memristor corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1"; when b is 1, V(b) is V p ; when b is 0, V(b) is a voltage with an amplitude of 0; when a is 1, V(a) is V p ; when a is 0, V(a) is a voltage with an amplitude of 0; the voltage V p satisfies: V set / 2 < V p < V set , and V p < 2|V reset | / 3; V set is the threshold value for the memristor to change from the high resistance state to the low resistance state; V reset is the threshold value for the memristor to change from the low resistance state to the high resistance state.

[0022] In a fifth aspect, the present invention provides a control method for an adder circuit, which is used to implement the addition operation of n-bit numbers a n ......a2a1, b n ......b2b1 and a 1-bit carry input c1; n ≥ 2; the adder circuit includes: a resistor and four identical memristors M1, M2, M3, M4; the negative electrodes of the four memristors are all connected to one end of the resistor; the resistance value of the resistor ; R H and R L are respectively the high resistance state resistance value and the low resistance state resistance value of the memristor;

[0023] The control method includes: sequentially executing n rounds of addition sub-processes; among them, in the i-th round of addition sub-process, a i is used as a, b i is used as b, c i is used as c, and the control method provided in the fourth aspect above is executed on the adder circuit to obtain the carry result c i+1 and the summation result s i of the i-th round of addition operation; i = 1, 2,..., n.

[0024] In a sixth aspect, the present invention provides an addition operation device, including: an adder circuit and a controller;

[0025] The adder circuit includes: a resistor and four identical memristors M1, M2, M3, M4; the negative electrodes of the four memristors are all connected to one end of the resistor; the resistance value of the resistor ; R H and R LThey are the high resistance state resistance value and the low resistance state resistance value of the memristor respectively;

[0026] The controller is used to execute the control method of the fourth aspect or the fifth aspect above.

[0027] In a seventh aspect, the present invention provides a control method for an adder circuit, which is used to implement the addition operation of an n-bit number a n ......a2a1, b n ......b2b1 and a 1-bit carry input c1; n≥2; the adder circuit includes: a resistor and 2n + 2 identical memristors; the negative electrodes of the 2n + 2 memristors are all connected to one end of the resistor; the resistance value of the resistor ; R H and R L They are the high resistance state resistance value and the low resistance state resistance value of the memristor respectively;

[0028] The control method includes: selecting one memristor from the 2n + 2 memristors as the memristor M3, and sequentially executing n rounds of addition sub-processes;

[0029] Among them, in the i-th round of addition sub-process, i = 1, 2,..., n:

[0030] When i = 1, select one memristor from the remaining unselected memristors as the memristor M1 in the current round of addition sub-process, and set it to the resistance state corresponding to c1; when i≥2, use the memristor M2 in the previous round of addition sub-process as the memristor M1 in the current round of addition sub-process;

[0031] Select two memristors from the remaining unselected memristors as M2 and M4 in the current round of addition sub-process respectively; the memristor M3 and the memristors M1, M2, and M4 in the current round of addition sub-process form a sub-adder circuit in the current round; among them, the resistance states of the memristor M3 and the memristors M2 and M4 in the current round of addition sub-process are all in the high resistance state;

[0032] Take a i as a, b i as b, c i as c, and execute S2 in the control method provided in the fourth aspect above on the sub-adder circuit in the current round to obtain the carry result c i+1 and the sum result s i ;

[0033] In each round of addition sub-process, the positive electrodes of the remaining memristors except the memristor M3 and the memristors M1, M2, and M4 in the current round of addition sub-process are all in a floating state;

[0034] After n rounds of addition sub-processes, s n......s2s1 and c n+1 That is the result of the required addition operation.

[0035] In an eighth aspect, the present invention provides an addition operation device, including: an addition circuit and a controller; the addition circuit includes: a resistor and 2n + 2 identical memristors; the negative electrodes of the 2n + 2 memristors are all connected to one end of the resistor; the resistance value of the resistor ; R H and R L are respectively the high-resistance state resistance value and the low-resistance state resistance value of the memristor; n≥2;

[0036] The controller is used to execute the control method provided in the seventh aspect above.

[0037] In a ninth aspect, the present invention provides a control method for an addition circuit, which is used to implement the addition operation of n-bit numbers a n ......a2a1, b n ......b2b1 and a 1-bit carry input c1; n≥2; the addition circuit includes: n parallel branches, and switch modules m1, m2,..., m for controlling the connection or disconnection between adjacent two branches n-1 ; the i-th switch module m i is used to control the connection or disconnection between the i-th branch and the (i + 1)-th branch; i = 1, 2,..., n - 1; the i-th branch includes: the i-th resistor R i and three memristors whose negative electrodes are all connected to one end of the resistor R i ; the n-th branch includes: the n-th resistor R n and four memristors whose negative electrodes are all connected to one end of the resistor R n ; all the memristors in the addition circuit are the same, all the resistors are the same, and the resistance value is ; R H and R L are respectively the high-resistance state resistance value and the low-resistance state resistance value of the memristor;

[0038] The control method includes:

[0039] S1. Sequentially execute n - 1 rounds of carry calculation sub-processes; in the i-th round of carry calculation sub-process: control the i-th switch module m i to conduct to connect the i-th branch and the (i + 1)-th branch, and the rest of the switch modules are all disconnected;

[0040] When i = 1, select a memristor from the i-th branch as the memristor M1 in the i-th round of carry calculation sub-process, and set it to the resistance state corresponding to c1; when i≥2, use the memristor M2 in the previous round of carry calculation sub-process as the memristor M1 in the current round of carry calculation sub-process;

[0041] Select a memristor from the i+1 branches as the memristor M2 in the i-th round of carry calculation sub-process, at which time the resistance state of the memristor M2 is a high resistance state; make the positive electrodes of other memristors except the memristors M1 and M2 in the current round of carry calculation sub-process in a floating state;

[0042] The positive electrode of the memristor M1 is connected to the voltage -V(b i )-V p , the positive electrode of the memristor M2 is connected to the voltage V(a i ), in the resistor R i or R i+1 The voltage -V(b i ), so that the corresponding resistance state a is obtained in the memristor M2 in the current round of carry calculation subprocess. i , b i 、c i The result of the majority gate logic operation is used as the carry result of the i-th round of addition operation;

[0043] S2, disconnect all switch modules so that all branches are disconnected; execute the nth round of carry calculation subprocess, and execute n rounds of sum calculation subprocess in parallel;

[0044] The above-mentioned execution of the n-th round carry calculation sub-process includes:

[0045] The memristor M2 in the previous round of carry calculation sub-process is used as the memristor M1 in the current round of carry calculation sub-process, and a memristor that has not been selected is selected from the nth branch as the memristor M2 in the nth round of carry calculation sub-process. At this time, the resistance state of the memristor M2 is a high resistance state; the positive electrodes of the other memristors in the nth branch except the memristors M1 and M2 in the current round of carry calculation sub-process are all in a floating state;

[0046] The positive electrode of the memristor M1 is connected to the voltage -V(b n )-V p , the positive electrode of the memristor M2 is connected to the voltage V(a n ), in the resistor R n The voltage -V(b n ), so that the corresponding resistance state a is obtained in the memristor M2 in the current round of carry calculation subprocess. n , b n 、c n The result of the majority gate logic operation is used as the carry result of the nth round of addition operation;

[0047] The above-mentioned parallel execution of the n-round summation calculation sub-process includes:

[0048] For the j-th branch, use the memristor selected as the memristor M1 in the j-th round carry calculation sub-process as the memristor M j1 ; and select two unselected memristors from the j-th branch as the memristors M j3 and M j4 ; j = 1, 2,..., n;

[0049] Make the positive pole of each memristor M j4 in a floating state, and parallelly connect the corresponding voltage V(a j1 ) - 2V j to the positive pole of each memristor M p . Parallelly connect a voltage with an amplitude of 0 to the positive pole of each memristor M j3 . Parallelly connect the corresponding voltage -V(a j ) - V j to the end of each resistor R p that is not connected to the memristor, so as to parallelly obtain the XOR logic operation result of a j3 and c j corresponding to its resistance state in each memristor M j ;

[0050] Make the positive pole of each memristor M j1 in a floating state. After obtaining the XOR logic operation result of a j and c j , parallelly connect the corresponding voltage V(b j3 ) - 2V j to the positive pole of each memristor M p . Parallelly connect a voltage with an amplitude of 0 to the positive pole of each memristor M j4 . Parallelly connect the corresponding voltage -V(b j ) - V j to the end of each resistor R p that is not connected to the memristor, so as to parallelly obtain the XOR logic operation result of a j4 , b j , and c j corresponding to its resistance state in each memristor M j , and use it as the summation result of the addition operation;

[0051] Among them, the high resistance state of the memristor corresponds to the logical value "0", and the low resistance state corresponds to the logical value "1"; when b j is 1, V(b j ) is V p ; when b j is 0, V(b j) is a voltage with an amplitude of 0; when a j is 1, V(a j ) is V p ; when a j is 0, V(a j ) is a voltage with an amplitude of 0; the voltage V p satisfies: V set / 2 < V p < V set , and V p < 2|V reset | / 3; V set is the threshold for the memristor to change from the high resistance state to the low resistance state; V reset is the threshold for the memristor to change from the low resistance state to the high resistance state.

[0052] In a tenth aspect, the present invention provides an addition operation device, including: an addition circuit and a controller; the addition circuit includes: n parallel branches, and switch modules m1, m2,..., m n-1 for controlling the connection or disconnection between adjacent two branches; n ≥ 2; the i-th switch module m i is used to control the connection or disconnection between the i-th branch and the (i + 1)-th branch; i = 1, 2,..., n - 1; the i-th branch includes: the i-th resistor R i and three memristors whose negative electrodes are both connected to one end of the resistor R i ; the n-th branch includes: the n-th resistor R n and four memristors whose negative electrodes are both connected to one end of the resistor R n ; all the memristors in the addition circuit are the same, all the resistors are the same, and the resistance value is ; R H and R L are respectively the high resistance state resistance value and the low resistance state resistance value of the memristor;

[0053] The controller is used to execute the control method provided in the ninth aspect.

[0054] In an eleventh aspect, the present invention provides a control system, including: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, it executes the control methods provided in the second aspect, the fourth aspect, the fifth aspect, the seventh aspect or the ninth aspect of the present invention.

[0055] In a twelfth aspect, the present invention further provides a computer-readable storage medium, the computer-readable storage medium includes a stored computer program, wherein when the computer program is run by a processor, it controls the device where the storage medium is located to execute the control methods provided in the second aspect, the fourth aspect, the fifth aspect, the seventh aspect or the ninth aspect of the present invention.

[0056] In a thirteenth aspect, the invention also provides a computer program product, including a computer program / instructions, which, when executed by a processor, implement the control method provided in the second, fourth, fifth, seventh, or ninth aspect of the invention.

[0057] Generally speaking, through the above technical solutions conceived by the present invention, the following beneficial effects can be achieved:

[0058] 1. The invention provides a majority gate logic circuit based on memristors and a corresponding device, including two identical memristors M1 and M2 whose resistors and negative electrodes are both connected to one end of the resistor; the invention makes full use of the resistance state characteristics of the memristors. Based on the initial resistance state of the memristor M2 being in a high resistance state, the resistance state of the memristor M1 is set to the resistance state corresponding to the logic value c, and the positive electrode of the memristor M1, the positive electrode of the memristor M2, and the input voltage at the other end of the resistor correspond to the voltage -V(b)-V p , the voltage V(a) related to the logic value a, and the voltage -V(b) related to the logic value b, where V set / 2 < V p < V set , and to ensure that the memristor M1 is not reset, it is necessary to satisfy V p < 2|V reset | / 3; based on the above design, when at least two of a, b, and c are logic "1", the voltage across the memristor M2 is greater than or equal to 2V p , and 2V p > V set , so the memristor M2 undergoes a set process, and the stored logic result in the memristor M2 is "1"; on the contrary, when at most one of a, b, and c is logic "1", the voltage across the memristor M2 is less than or equal to V p , and V p < V set , so the memristor M2 maintains the high resistance state unchanged, and the stored logic result is "0"; thus, the majority gate logic operation of the logic values a, b, and c is realized; the invention only needs to use two memristors to realize the majority gate logic operation, reducing the circuit area overhead.

[0059] 2. For the majority gate logic circuit based on memristors and the corresponding device provided by the invention, the characteristics of the memristors enable the circuit to have stronger fault tolerance and still maintain high stability when some components fail.

[0060] 3. The fourth aspect of the present invention provides a control method for an addition circuit. The addition circuit includes a resistor and four identical memristors M1, M2, M3, and M4 whose negative electrodes are all connected to one end of the resistor. Based on the initial resistance states of the memristors M2, M3, and M4 being in the high-resistance state, the resistance state of the memristor M1 is set to the resistance state corresponding to the logical value c. The memristors M1 and M2 are selected to perform a majority gate logic operation on the logical values a, b, and c. The memristors M1 and M3 are selected to perform an exclusive OR logic operation on the logical values a and c. The memristors M3 and M4 are selected to perform an exclusive OR logic operation on the exclusive OR logic operation result of a and c and the logical value b. Throughout the process, the circuit elements for implementing the majority gate logic operation and the process for implementing the exclusive OR logic operation adopt a unified circuit structure, and the internal circuit elements can be partially reused. There is no need to separately design independent majority gate logic operation circuit units and exclusive OR logic operation circuit units, avoiding redundancy, reducing the circuit complexity, reducing the circuit area overhead, and improving the circuit compactness and resource utilization rate.

[0061] 4. The fifth aspect of the present invention provides a control method for an addition circuit, which is used to implement the addition operation of n-bit numbers a n ......a2a1, b n ......b2b1 and the 1-bit carry input c1. The entire operation process reuses the same addition circuit, and only four identical memristors whose negative electrodes are all connected to one end of the resistor are required to implement the addition operation of multi-bit numbers, reducing the circuit complexity, reducing the circuit area overhead, and improving the circuit compactness and resource utilization rate.

[0062] 5. The seventh aspect of the present invention provides a control method for an addition circuit. The addition circuit used includes a resistor and 2n + 2 identical memristors. During the process of implementing the addition operation of n-bit numbers a n ......a2a1, b n ......b2b1 and the 1-bit carry input c1, the carry result calculated by the addition sub-process is stored in the corresponding memristor in the form of a resistance state for direct use in the next round of addition sub-process without additional read and write operations, reducing the operation complexity.

[0063] 6. The ninth aspect of the present invention provides a control method for an addition circuit. The addition circuit used includes n parallel branches and a switch module for controlling the connection or disconnection between adjacent two branches. The i-th branch includes: the i-th resistor R i and three memristors whose negative electrodes are all connected to one end of the resistor R i The n-th branch includes: the n-th resistor R n and three memristors whose negative electrodes are all connected to one end of the resistor R nFour memristors connected to one end; in the whole operation process, the carry calculation sub-process of the first n - 1 rounds is performed serially first; then the carry calculation sub-process of the nth round is executed, and the sum calculation sub-process of n rounds is executed in parallel. This method fully combines serial and parallel methods, and can further improve the calculation efficiency when n takes a relatively large value. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 FIG. is a schematic diagram of a majority gate logic circuit based on memristors provided by an embodiment of the present invention.

[0065] Figure 2 FIG. is a schematic diagram of an adder circuit provided by an embodiment of the fifth aspect of the present invention.

[0066] Figure 3 FIG. is a schematic diagram of an adder circuit provided by an embodiment of the seventh aspect of the present invention.

[0067] Figure 4 FIG. is a schematic diagram of an adder circuit provided by an embodiment of the ninth aspect of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0068] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0069] To achieve the above objective, in the first aspect, the present invention provides a majority gate logic circuit based on memristors for performing majority gate logic operations on logical values a, b, and c, including: a resistor and two identical memristors M1 and M2; the negative electrodes of the memristor M1 and the memristor M2 are both connected to one end of the resistor;

[0070] Before the majority gate logic circuit performs majority gate logic operations on logical values a, b, and c, the resistance state of the memristor M2 is in a high resistance state;

[0071] When the majority gate logic circuit performs majority gate logic operations on logical values a, b, and c, the resistance state of the memristor M1 is the resistance state corresponding to the logical value c, and the positive electrode of the memristor M1 is used to connect to the voltage -V(b) - V p , the positive electrode of the memristor M2 is used to connect to the voltage V(a), the other end of the resistor is used to connect to the voltage -V(b), and the final resistance state of the memristor M2 is the result of the majority gate logic operation of the logical values a, b, and c;

[0072] Among them, the high resistance state of the memristor corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1"; when b is 1, V(b) is V p ; when b is 0, V(b) is a voltage with an amplitude of 0; when a is 1, V(a) is V p ; when a is 0, V(a) is a voltage with an amplitude of 0; the voltage V p satisfies: V set / 2 < V p < V set , and V p < 2|V reset | / 3; V set is the threshold value for the memristor to change from the high resistance state to the low resistance state; V reset is the threshold value for the memristor to change from the low resistance state to the high resistance state; the resistance value of the resistor , so as to clearly distinguish the low resistance state, high resistance state of the memristor and the resistance value of the resistor; R H and R L are respectively the high resistance state resistance value and the low resistance state resistance value of the memristor.

[0073] Preferably, in an alternative embodiment, the switching ratios of the memristors M1 and M2 are both greater than or equal to 100. The switching ratio of the memristor directly affects the resistance state change window of the memristors in the output column. The larger the switching ratio, the larger the resistance state change window of the memristors in the output column. When the switching ratio is greater than or equal to 100, the memristors in the output column can more accurately achieve the resistance state change, thereby further improving the calculation accuracy.

[0074] In a second aspect, the present invention provides a control method for the above-mentioned majority gate logic circuit, including:

[0075] When performing a majority gate logic operation on the logic values a, b, and c, set the resistance state of the memristor M1 to the resistance state corresponding to the logic value c, connect the voltage -V(b)-V p to the positive electrode of the memristor M1, connect the voltage V(a) to the positive electrode of the memristor M2, connect the voltage -V(b) to the end of the resistor not connected to the memristor, and use the final resistance state of the memristor M2 as the result of the majority gate logic operation of the logic values a, b, and c;

[0076] Among them, before performing the majority gate logic operation on the logic values a, b, and c, the resistance state of the memristor M2 is in the high resistance state.

[0077] The related technical solutions are the same as those of the majority gate logic circuit provided in the first aspect of the present invention, and will not be elaborated here.

[0078] In a third aspect, the present invention provides a majority gate logic operation device, including: a controller and the majority gate logic circuit provided in the first aspect of the present invention;

[0079] The controller is used to execute the control method of the majority gate logic circuit provided in the second aspect of the present invention.

[0080] The related technical solutions are the same as the majority gate logic circuit provided in the first aspect of the present invention and the control method provided in the second aspect, which will not be elaborated here.

[0081] In order to further illustrate the memristor-based majority gate logic circuit and control method provided by the present invention, a specific embodiment will be described in detail below:

[0082] This embodiment provides a memristor-based majority gate logic circuit for performing majority gate logic operations on logic values a, b, and c. As Figure 1 shown, it includes: a resistor and two identical memristors M1 and M2; the negative electrodes of the memristors M1 and M2 are both connected to one end of the resistor; the positive electrodes of the memristors M1 and M2 are controlled through control terminals T1 and T2, and the other end of the resistor (the end not connected to the memristor) is controlled through the control terminal T3;

[0083] The memristor includes two resistance states, namely the high resistance state (High Resistance State, HRS) and the low resistance state (Low Resistance State, LRS). By applying a port voltage with a specific direction and magnitude, the memristor can transition between the two resistance states. Among them, by applying a positive voltage greater than V set , the memristor can be set from the high resistance state to the low resistance state; on the contrary, by applying a negative voltage less than V reset , the memristor can transition from the low resistance state to the high resistance state. V set is the threshold for the memristor to transition from the high resistance state to the low resistance state; V reset is the threshold for the memristor to transition from the low resistance state to the high resistance state.

[0084] The resistance value of the resistor ; R H and R L are respectively the high resistance state resistance value and the low resistance state resistance value of the memristor. Considering that the memristor switching ratio directly affects the resistance state change window of the memristors in the output column, the larger the switching ratio, the larger the resistance state change window of the memristors in the output column. When the switching ratio is greater than or equal to 100, the memristors in the output column can more accurately achieve resistance state changes, thereby further improving the calculation accuracy. Preferably, the switching ratio of the memristor is greater than or equal to 100; in this embodiment, the high resistance R H of the memristor = 100 KΩ, and the low resistance R L = 1 KΩ.

[0085] Before the majority gate logic circuit performs the majority gate logic operation on the logic values a, b, and c, the resistance state of the memristor M2 is in a high resistance state;

[0086] When the majority gate logic circuit performs the majority gate logic operation on the logic values a, b, and c:

[0087] The input resistance state of the memristor M1 is determined by the logic value c and has a resistance state corresponding to the logic value c; the high resistance state of the memristor corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1";

[0088] The input voltage of the control terminal T1 is determined by the logic value b and is -V(b) - V p , that is, -V(b) - V is connected to the positive electrode of the memristor M1 p ; specifically, when b is 1, V(b) is V p ; when b is 0, V(b) is a voltage with an amplitude of 0;

[0089] The input voltage of the control terminal T2 is determined by the logic value a and is V(a), that is, the voltage V(a) is connected to the positive electrode of the memristor M2; specifically, when a is 1, V(a) is V p ; when a is 0, V(a) is a voltage with an amplitude of 0;

[0090] The input voltage of the control terminal T3 is determined by the logic value b and is -V(b), that is, the voltage -V(b) is connected to the positive electrode of the memristor M2;

[0091] The final resistance state of the memristor M2 is the result of the majority gate logic operation of the logic values a, b, and c; when the final resistance state of the memristor M2 is in a high resistance state, the corresponding majority gate logic operation result is the logic value "0"; when the final resistance state of the memristor M2 is in a low resistance state, the corresponding majority gate logic operation result is the logic value "1";

[0092] Among them, the voltage V p satisfies: V set / 2 < V p < V set , and to ensure that the memristor M1 is not reset, it is necessary to satisfy V p < 2|V reset | / 3; V set is the threshold for the memristor to change from a high resistance state to a low resistance state; V reset is the threshold for the memristor to change from a low resistance state to a high resistance state; preferably, in order to have a large margin for both the logic output of "1" and the logic output of "0", V p = 0.6V set .

[0093] It should be noted that the resistance value of the resistor It plays a role in voltage division. Thus, when the memristor M1 is in the low-resistance state, the negative voltage of the memristor M2 is approximately equal to the voltage at the T1 port; when the memristor M1 is in the high-resistance state, the negative voltage of the memristor M2 is approximately equal to the voltage at the T3 port. Based on the above design, when at least two of a, b, and c are logic "1", the voltage across the memristor M2 is greater than or equal to 2V p , and 2V p >V set . Therefore, the memristor M2 undergoes the set process, and the stored logic result in the memristor M2 is "1"; on the contrary, when at most one of a, b, and c is logic "1", the voltage across the memristor M2 is less than or equal to V p , and V p <V set . Therefore, the memristor M2 maintains the high-resistance state unchanged, and the stored logic result is "0"; thus, the majority gate logic operation of the logic values a, b, and c is realized.

[0094] Majority gate logic and exclusive-or logic are the core of the majority exclusive-or graph. The two form a complete logic basis. By combining majority gate logic and exclusive-or logic, any Boolean function can be realized, and different arithmetic operations can be achieved. The majority exclusive-or graph can use majority gate logic to implement the core logic of carry generation and cooperate with exclusive-or gate logic to complete the sum bit calculation. This characteristic makes the majority exclusive-or graph an ideal choice for constructing high-energy-efficient arithmetic units such as adders and multipliers.

[0095] Among many arithmetic operations, the adder is the most basic arithmetic unit in digital circuit design. Its performance directly affects the efficiency and power consumption of data processing. Therefore, here mainly the adder is taken as an example for introduction. In the design of existing adder circuits, it is usually necessary to separately design independent circuit units for majority gate logic operations and exclusive-or logic operations, which requires a large number of components and many iterative operation steps, thus generating a large amount of redundancy and reducing resource utilization.

[0096] To solve the above problems, the present invention provides the application of the implementation method of the majority gate logic provided by the present invention in the process of realizing adder operations, specifically as follows:

[0097] In a fourth aspect, the present invention provides a control method for an adder circuit; wherein, the adder circuit includes: a resistor and four identical memristors M1, M2, M3, and M4; the negative electrodes of the four memristors are all connected to one end of the resistor; the resistance value of the resistor ; R H and R L are respectively the high-resistance state resistance value and the low-resistance state resistance value of the memristor;

[0098] The control method includes performing an addition operation on the adder circuit to implement 1-bit addends a, b, and carry input c:

[0099] S1. Set the memristor M1 to a resistance state corresponding to c. At this time, the resistance states of the memristors M2, M3, and M4 are all in the high-resistance state;

[0100] S2. Make the positive electrodes of the memristors M3 and M4 in a floating state. Connect -V(b)-V to the positive electrode of the memristor M1, p connect the voltage V(a) to the positive electrode of the memristor M2, and connect the voltage -V(b) to the end of the resistor not connected to the memristor, so as to obtain the majority gate logic operation result of a, b, and c corresponding to its resistance state in the memristor M2, and use it as the carry result of the addition operation;

[0101] Make the positive electrodes of the memristors M2 and M4 in a floating state. Connect the voltage V(a)-2V to the positive electrode of the memristor M1, p connect the voltage with an amplitude of 0 to the positive electrode of the memristor M3, and connect the voltage -V(a)-V to the end of the resistor not connected to the memristor, p so as to obtain the exclusive-OR logic operation result of a and c corresponding to its resistance state in the memristor M3 ;

[0102] After obtaining the exclusive-OR logic operation result make the positive electrodes of the memristors M1 and M2 in a floating state. Connect the voltage V(b)-2V to the positive electrode of the memristor M3, p connect the voltage with an amplitude of 0 to the positive electrode of the memristor M4, and connect the voltage -V(b)-V to the end of the resistor not connected to the memristor, p so as to obtain the exclusive-OR logic operation result of a, b, and c corresponding to its resistance state in the memristor M4 and use it as the sum result of the addition operation;

[0103] Among them, the high-resistance state of the memristor corresponds to the logic value "0", and the low-resistance state corresponds to the logic value "1"; when b is 1, V(b) is V p ; when b is 0, V(b) is the voltage with an amplitude of 0; when a is 1, V(a) is V p ; when a is 0, V(a) is the voltage with an amplitude of 0; V set / 2 < V p < V set and V p < 2|V reset | / 3; V set is the threshold for the memristor to change from the high-resistance state to the low-resistance state; V reset is the threshold for the memristor to change from the low-resistance state to the high-resistance state. Preferably, in order to make both the logic output of "1" and the logic output of "0" have a large margin, V p = 0.6V set .

[0104] It should be noted that for the majority gate logic operation of a, b, and c, the exclusive OR logic operation of a and c, and the exclusive OR logic operation of the exclusive OR result of a and c and the logical value b in S2, the execution order only needs to ensure that the exclusive OR logic operation of the logical values a and c is executed before the exclusive OR logic operation of the exclusive OR result of a and c and the logical value b. The majority gate logic operation of a, b, and c can be executed before the exclusive OR logic operation of the logical values a and c, or after the exclusive OR logic operation of the logical values a and c and before the exclusive OR logic operation of the exclusive OR result of a and c and the logical value b, or after the exclusive OR logic operation of the exclusive OR result of a and c and the logical value b. There is no limitation here.

[0105] Considering that the switching ratio of the memristor directly affects the resistance state change window of the memristors in the output column, the larger the switching ratio, the larger the resistance state change window of the memristors in the output column. When the switching ratio is greater than or equal to 100, the memristors in the output column can more accurately achieve the resistance state change, thereby further improving the calculation accuracy. Preferably, the switching ratio of the memristor is greater than or equal to 100; in an alternative embodiment, the high resistance R of the memristor H = 100 KΩ, and the low resistance R L = 1 KΩ.

[0106] It should be noted that based on 1-bit addition, the present invention can further expand the method of multi-bit addition operation in various ways. The following provides several typical ways:

[0107] In a fifth aspect, the present invention provides a control method for an addition circuit, which is used to implement the addition operation of n-bit numbers a n ......a2a1, b n ......b2b1 and the 1-bit carry input c1; n≥2; the addition circuit includes: a resistor and four identical memristors M1, M2, M3, M4; the negative electrodes of the four memristors are all connected to one end of the resistor; the resistance value of the resistor ; R H and R L are respectively the high resistance state resistance value and the low resistance state resistance value of the memristor;

[0108] The control method includes: sequentially executing n rounds of addition sub-processes; among them, as Figure 2 shown, in the i-th round of addition sub-process, take a i as a, b i as b, c i as c, and execute the control method provided in the fourth aspect for the addition circuit to obtain the carry result c i+1 and the sum result s i; i = 1, 2, ..., n.

[0109] The specific operation is shown in Table 1.

[0110]

[0111] Through the above operations, the function of the full adder is realized. Among them, the 1-bit carry input c1 is determined by the user and can be logical "1" or logical "0".

[0112] Considering that the switching ratio of the memristor directly affects the resistance state change window of the memristors in the output column, the larger the switching ratio, the larger the resistance state change window of the memristors in the output column. When the switching ratio is greater than or equal to 100, the memristors in the output column can more accurately achieve the resistance state change, thereby further improving the calculation accuracy. Preferably, the switching ratio of the memristor is greater than or equal to 100; in an alternative embodiment, the high resistance R of the memristor H = 100 KΩ, and the low resistance R L = 1 KΩ.

[0113] The related technical solutions are the same as the control methods provided in the fourth aspect of the present invention and will not be elaborated here.

[0114] In a sixth aspect, the present invention provides an addition operation device, including: an addition circuit and a controller;

[0115] The addition circuit includes: a resistor and four identical memristors M1, M2, M3, and M4; the negative electrodes of the four memristors are all connected to one end of the resistor; the resistance value of the resistor ; R H and R L are respectively the high resistance state resistance value and the low resistance state resistance value of the memristor;

[0116] The controller is used to execute the control method in the above fourth aspect or fifth aspect.

[0117] Considering that the switching ratio of the memristor directly affects the resistance state change window of the memristors in the output column, the larger the switching ratio, the larger the resistance state change window of the memristors in the output column. When the switching ratio is greater than or equal to 100, the memristors in the output column can more accurately achieve the resistance state change, thereby further improving the calculation accuracy. Preferably, the switching ratio of the memristor is greater than or equal to 100; in an alternative embodiment, the high resistance R of the memristor H = 100 KΩ, and the low resistance R L = 1 KΩ.

[0118] The related technical solutions are the same as the control methods provided in the fourth and fifth aspects of the present invention and will not be elaborated here.

[0119] Seventh aspect, the present invention provides a control method for an addition circuit, which is used to implement the addition operation of an n-bit number a n ......a2a1, b n ......b2b1 and a 1-bit carry input c1; n≥2; the addition circuit includes: a resistor and 2n + 2 identical memristors; the negative electrodes of the 2n + 2 memristors are all connected to one end of the resistor; the resistance value of the resistor ; R H and R L are respectively the high-resistance state resistance value and the low-resistance state resistance value of the memristor;

[0120] The control method includes: selecting one memristor from the 2n + 2 memristors as memristor M3, and sequentially executing n rounds of addition sub-processes;

[0121] Wherein, in the i-th round of addition sub-process, i = 1, 2,..., n:

[0122] When i = 1, select one memristor from the remaining unselected memristors as memristor M1 in the current round of addition sub-process, and set it to the resistance state corresponding to c1; when i≥2, use the memristor M2 in the previous round of addition sub-process as memristor M1 in the current round of addition sub-process;

[0123] Select two memristors from the remaining unselected memristors as M2 and M4 in the current round of addition sub-process respectively; memristor M3 and memristors M1, M2 and M4 in the current round of addition sub-process form a sub-addition circuit in the current round; wherein, the resistance states of memristor M3 and memristors M2, M4 in the current round of addition sub-process are both in the high-resistance state;

[0124] Take a i as a, b i as b, c i as c, and execute S2 in the control method provided in the fourth aspect above on the sub-addition circuit in the current round to obtain the carry result c i+1 and the sum result s i ;

[0125] In each round of addition sub-process, the positive electrodes of the remaining memristors except memristor M3 and memristors M1, M2 and M4 in the current round of addition sub-process are all in a floating state;

[0126] After n rounds of addition sub-processes, s n ......s2s1 and c n+1 are the results of the required addition operation.

[0127] Such as Figure 3The figure shows an example schematic diagram of the addition circuit provided by the seventh aspect of the present invention.

[0128] Considering that the switching ratio of the memristor directly affects the resistance state change window of the memristors in the output column, the larger the switching ratio, the larger the resistance state change window of the memristors in the output column. When the switching ratio is greater than or equal to 100, the memristors in the output column can more accurately achieve the resistance state change, thereby further improving the calculation accuracy. Preferably, the switching ratio of the memristor is greater than or equal to 100; in an alternative embodiment, the high resistance R of the memristor H = 100 KΩ, and the low resistance R L = 1 KΩ.

[0129] The related technical solutions are the same as the control method provided by the fourth aspect of the present invention, and will not be elaborated here.

[0130] In the eighth aspect, the present invention provides an addition operation device, including: an addition circuit and a controller; the addition circuit includes: a resistor and 2n + 2 identical memristors; the negative electrodes of the 2n + 2 memristors are all connected to one end of the resistor; the resistance value of the resistor ; R H and R L are respectively the high resistance state resistance value and the low resistance state resistance value of the memristor; n ≥ 2;

[0131] The controller is configured to execute the control method provided by the seventh aspect above.

[0132] The related technical solutions are the same as the method provided by the seventh aspect of the present invention, and will not be elaborated here.

[0133] In the ninth aspect, the present invention provides a control method for an addition circuit, which is used to implement the addition operation of n-bit numbers a n ......a2a1, b n ......b2b1 and 1-bit carry input c1; n ≥ 2; the addition circuit includes: n parallel branches, and switch modules m1, m2,..., m n-1 for controlling the connection or disconnection between adjacent two branches; the i-th switch module m i is used to control the connection or disconnection between the i-th branch and the (i + 1)-th branch; i = 1, 2,..., n - 1; the i-th branch includes: the i-th resistor R i and three memristors whose negative electrodes are all connected to one end of the resistor R i ; the n-th branch includes: the n-th resistor R n and four memristors whose negative electrodes are all connected to one end of the resistor R n ; all the memristors in the addition circuit are the same, all the resistors are the same, and the resistance value is ; R H and RL They are respectively the high resistance state resistance value and the low resistance state resistance value of the memristor;

[0134] The control method includes:

[0135] S1. Sequentially execute n - 1 rounds of carry calculation sub - processes; in the i - th round of carry calculation sub - process: control the i - th switch module m i To conduct and connect the i - th branch and the (i + 1) - th branch, and all other switch modules are disconnected;

[0136] When i = 1, select a memristor from the i - th branch as the memristor M1 in the i - th round of carry calculation sub - process, and set its resistance state corresponding to c1; when i≥2, use the memristor M2 in the previous round of carry calculation sub - process as the memristor M1 in the current round of carry calculation sub - process;

[0137] Select a memristor from the (i + 1) branches as the memristor M2 in the i - th round of carry calculation sub - process. At this time, the resistance state of this memristor M2 is the high - resistance state; make the positive electrodes of other memristors except the memristors M1 and M2 in the current round of carry calculation sub - process float;

[0138] Connect the voltage - V(b i ) - V to the positive electrode of the memristor M1 in the current round of carry calculation sub - process, p Connect the voltage V(a i ) to the positive electrode of the memristor M2 in the current round of carry calculation sub - process, and connect the voltage - V(b i ) or - V(b i+1 ) to the end of the resistor R i that is not connected to the memristor. Thus, obtain the majority - gate logic operation result of a i , b i , c i corresponding to its resistance state in the memristor M2 in the current round of carry calculation sub - process, and use it as the carry result of the i - th round of addition operation;

[0139] S2. Disconnect all switch modules so that all branches are not connected; execute the n - th round of carry calculation sub - process and execute n rounds of summation calculation sub - processes in parallel;

[0140] Among them, the above - mentioned execution of the n - th round of carry calculation sub - process includes:

[0141] Take the memristor M2 in the carry calculation sub-process of the previous round as the memristor M1 in the carry calculation sub-process of the current round, and select an unselected memristor from the nth branch as the memristor M2 in the carry calculation sub-process of the nth round. At this time, the resistance state of this memristor M2 is in the high resistance state; make the positive poles of the other memristors in the nth branch except the memristors M1 and M2 in the carry calculation sub-process of the current round in a floating state;

[0142] Connect the voltage -V(b n ) - V p to the positive pole of the memristor M1 in the carry calculation sub-process of the current round, connect the voltage V(a n ) to the positive pole of the memristor M2 in the carry calculation sub-process of the current round, and connect the voltage -V(b n ) to the end of the resistor R n that is not connected to the memristor, so as to obtain the majority gate logic operation result of a n , b n , c n corresponding to its resistance state in the memristor M2 in the carry calculation sub-process of the current round, and use it as the carry result of the nth round addition operation;

[0143] The above parallel execution of the n-round summation calculation sub-process includes:

[0144] For the jth branch, take the memristor selected as the memristor M1 in the carry calculation sub-process of the jth round as the memristor M j1 ; and select two unselected memristors from the jth branch as the memristors M j3 , M j4 ; j = 1, 2,..., n;

[0145] Make the positive pole of each memristor M j4 in a floating state, and parallelly connect the corresponding voltage V(a j1 ) - 2V j to the positive pole of each memristor M p (that is, parallelly connect V(a1) - 2V 11 , V(a2) - 2V 21 ,..., V(a n1 ) - 2V p to the positive poles of M p , M n ,..., M p one by one), parallelly connect the voltage with an amplitude of 0 to the positive pole of each memristor M j3 (that is, parallelly connect the voltage with an amplitude of 0 to the positive poles of M 13 , M 23 ,..., M n3 ), and parallelly connect each resistor Rj One end of the unconnected memristor is connected to the corresponding voltage -V(a j ) - V p (that is, parallelly connect to R1, R2,..., R n One end of the unconnected memristor is respectively connected to the voltage -V(a1) - V p , -V(a2) - V p ,..., -V(a n ) - V p ), so as to parallelly obtain the exclusive - OR logic operation result of a j3 and c j corresponding to its resistance state in each memristor M j (that is, parallelly obtain the exclusive - OR logic operation result of a1, c1 corresponding to its resistance state in M 13 , M 23 ,..., M n3 respectively, the exclusive - OR logic operation result of a2, c2,..., a n and c n corresponding to its resistance state);

[0146] Make the positive electrode of each memristor M j1 in a floating state. After obtaining the exclusive - OR logic operation result of a j and c j , parallelly connect the corresponding voltage V(b j3 ) - 2V j to the positive electrode of each memristor M p (that is, parallelly connect V(b1) - 2V 13 , V(b2) - 2V 23 ,..., V(b n3 ) - 2V p to the positive electrodes of M p , M n ) - 2V p respectively), parallelly connect a voltage with an amplitude of 0 to the positive electrode of each memristor M j4 (that is, parallelly connect a voltage with an amplitude of 0 to the positive electrodes of M 14 , M 24 ,..., M n4 ), parallelly connect the corresponding voltage -V(b j ) - V j to one end of the unconnected memristor of each resistor R p (that is, parallelly connect the voltage -V(b1) - V n , -V(b2) - V p ,...,-V(b p ,...,-V(bn ) - V p ), so as to obtain the XOR logic operation result of a, b, and c corresponding to its resistance state in each memristor M in parallel (that is, the XOR logic operation results of a1, b1, c1 corresponding to their resistance states are obtained one - to - one in M j4 , M j , b j , c j , and so on, and the XOR logic operation results of a, b, c corresponding to their resistance states are obtained one - to - one in M 14 , M 24 ,..., M n4 ; that is, the XOR logic operation results of a1, b1, c1 corresponding to their resistance states are obtained one - to - one, the XOR logic operation results of a2, b2, c2,..., a n , b n , c n corresponding to their resistance states), and it is used as the summation result of the addition operation;

[0147] Among them, the high - resistance state of the memristor corresponds to the logic value "0", and the low - resistance state corresponds to the logic value "1"; when b j is 1, V(b j ) is V p ; when b j is 0, V(b j ) is a voltage with an amplitude of 0; when a j is 1, V(a j ) is V p ; when a j is 0, V(a j ) is a voltage with an amplitude of 0; the voltage V p satisfies: V set / 2 < V p < V set , and V p < 2|V reset | / 3; V set is the threshold for the memristor to change from the high - resistance state to the low - resistance state; V reset is the threshold for the memristor to change from the low - resistance state to the high - resistance state. Preferably, in order to make both the logic output of "1" and the logic output of "0" have a large margin, V p = 0.6V set .

[0148] Considering that the switching ratio of the memristor directly affects the resistance state change window of the memristors in the output column, the larger the switching ratio, the larger the resistance state change window of the memristors in the output column. When the switching ratio is greater than or equal to 100, the memristors in the output column can more accurately achieve the resistance state change, thereby further improving the calculation accuracy. Preferably, the switching ratio of the memristor is greater than or equal to 100; in an alternative embodiment, the high - resistance R H of the memristor is 100KΩ, and the low - resistance R L is 1KΩ.

[0149] It should be noted that the execution order of the above-mentioned carry calculation sub-process in the nth round and the parallel execution of the summation calculation sub-process in n rounds is not limited. The carry calculation sub-process in the nth round can be carried out before the parallel execution of the summation calculation sub-process in n rounds, or after the parallel execution of the summation calculation sub-process in n rounds.

[0150] It should be noted that the above switch module can be any existing switch module, which is not limited here. It can be a switch connected between two adjacent branches, or a switch can be set on each branch respectively (the switches on two adjacent branches form a switch module).

[0151] As Figure 4 shown is a schematic example of the adder circuit provided in the ninth aspect of the present invention. In this schematic example, a switch module includes two switches, which are respectively arranged on two adjacent branches.

[0152] In a tenth aspect, the present invention provides an addition operation device, including: an adder circuit and a controller; the adder circuit includes: n parallel branches, and switch modules m1, m2,..., m that control the connection or disconnection between two adjacent branches n-1 ; n≥2; the ith switch module m i is used to control the connection or disconnection between the ith branch and the (i + 1)th branch; i = 1, 2,..., n - 1; the ith branch includes: the ith resistor R i and three memristors whose negative electrodes are both connected to one end of the resistor R i ; the nth branch includes: the nth resistor R n and four memristors whose negative electrodes are both connected to one end of the resistor R n ; all the memristors in the adder circuit are the same, all the resistors are the same, and the resistance value is ; R H and R L are respectively the high-resistance state resistance value and the low-resistance state resistance value of the memristor;

[0153] The controller is used to execute the control method provided in the ninth aspect.

[0154] The related technical solutions are the same as the control method provided in the ninth aspect of the present invention, which will not be elaborated here.

[0155] In summary, the present invention efficiently implements majority gate logic operations and exclusive - OR logic operations based on the non - linear and memory characteristics of memristors, and further realizes addition operations; the present invention does not require separately designing independent majority gate logic operation circuit units and exclusive - OR logic operation circuit units, avoiding redundancy. By designing a unified circuit structure, majority gate logic and exclusive - OR logic can be calculated through the same steps, which not only reduces the circuit complexity but also improves resource utilization. Compared with traditional CMOS circuits, the memristor - based circuit can significantly reduce power consumption and area, further improving the overall performance of the circuit.

[0156] Based on this, the solution of the present invention has significant advantages. First, the unified circuit structure eliminates redundant design, improving the compactness and resource utilization of the circuit. Second, the memristor circuit can efficiently complete majority gate logic operations and exclusive - OR logic operations under the conditions of low power consumption and small area, and is particularly suitable for large - scale parallel computing tasks. Finally, the characteristics of memristors enable the circuit to have stronger fault - tolerance ability and still maintain high stability when some components fail. Therefore, the present invention not only solves the redundancy and efficiency problems in the prior art but also has high application prospects, especially in the fields of integrated circuits and high - efficiency computing.

[0157] In the eleventh aspect, the present invention provides a control system, including: a memory and a processor, where the memory stores a computer program, and when the processor executes the computer program, it executes the control method provided in the second, fourth, fifth, seventh, or ninth aspect of the present invention.

[0158] The related technical solutions are the same as the control methods provided in the second, fourth, fifth, seventh, and ninth aspects of the present invention, and will not be elaborated here.

[0159] In the twelfth aspect, the present invention further provides a computer - readable storage medium, where the computer - readable storage medium includes a stored computer program, and when the computer program is run by a processor, it controls the device where the storage medium is located to execute the control method provided in the second, fourth, fifth, seventh, or ninth aspect of the present invention.

[0160] The related technical solutions are the same as the control methods provided in the second, fourth, fifth, seventh, and ninth aspects of the present invention, and will not be elaborated here.

[0161] In the thirteenth aspect, the invention further provides a computer program product, including computer programs / instructions, and when the computer programs / instructions are executed by a processor, they implement the control method provided in the second, fourth, fifth, seventh, or ninth aspect of the present invention.

[0162] The related technical solutions are the same as the control methods provided in the second, fourth, fifth, seventh, and ninth aspects of the present invention, and will not be elaborated here.

[0163] Those skilled in the art can easily understand that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A majority gate logic circuit based on a memristor, characterized in that: Used to perform majority gate logic operations on logic values ​​a, b, c, including: a resistor and two identical memristors M1 and M2; the negative electrodes of the memristors M1 and M2 are both connected to one end of the resistor; Before the majority gate logic circuit performs majority gate logic operation on the logic values ​​a, b, and c, the resistance state of the memristor M2 is a high resistance state; When the majority gate logic circuit performs majority gate logic operations on logic values ​​a, b, and c, the resistance state of the memristor M1 is the resistance state corresponding to the logic value c, and the positive electrode of the memristor M1 is used to access the voltage -V(b)-V p , the positive electrode of the memristor M2 is used to access the voltage V(a), and the other end of the resistor is used to access the voltage -V(b). The final resistance state of the memristor M2 is the result of the majority gate logic operation of the logic values ​​a, b, and c; The high resistance state of the memristor corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1". When b is 1, V(b) is V p ; When b is 0, V(b) is a voltage with an amplitude of 0; when a is 1, V(a) is V p ; When a is 0, V(a) is a voltage with an amplitude of 0; voltage V p Satisfaction: V set / 2 < V p < V set , and V p < 2 |V reset | / 3;V set V is the threshold value of the memristor changing from high resistance state to low resistance state; reset is the threshold value of the memristor from low resistance state to high resistance state; the resistance value of the resistor ; R H and R L are the high-resistance state resistance and low-resistance state resistance of the memristor respectively.

2. A control method for a majority gate logic circuit, characterized in that: The majority gate logic circuit is the majority gate logic circuit according to claim 1; the control method comprises: When performing majority gate logic operation on logic values ​​a, b, and c, the resistance state of the memristor M1 in the majority gate logic circuit is set to the resistance state corresponding to the logic value c, and a voltage -V(b)-V is connected to the positive electrode of the memristor M1. p , the positive electrode of the memristor M2 in the majority gate logic circuit is connected to the voltage V(a), and the end of the resistor in the majority gate logic circuit that is not connected to the memristor is connected to the voltage -V(b), and the final resistance state of the memristor M2 is used as the majority gate logic operation result of the logic values ​​a, b, c; Before performing majority gate logic operation on the logic values ​​a, b, and c, the resistance state of the memristor M2 is a high resistance state.

3. A majority gate logic operation device, characterized in that: include: A controller and a majority gate logic circuit as claimed in claim 1; The controller is used to execute the control method described in claim 2.

4. A control method for an adding circuit, characterized in that: The adding circuit comprises: a resistor and four identical memristors M1, M2, M3, and M4; the negative electrodes of the four memristors are all connected to one end of the resistor; the resistance value of the resistor ; R H and R L are the high-resistance resistance value and the low-resistance resistance value of the memristor respectively; The control method includes performing an addition operation on the adding circuit to implement 1-bit addends a, b and carry input c: S1, setting the memristor M1 to a resistance state corresponding to c, at which point the resistance states of the memristors M2, M3, and M4 are all high resistance states; S2, make the positive electrodes of memristors M3 and M4 float, and connect -V(b)-V to the positive electrode of memristor M1 p , a voltage V(a) is connected to the positive electrode of the memristor M2, and a voltage -V(b) is connected to the end of the resistor that is not connected to the memristor, so that the majority gate logic operation results of a, b, and c corresponding to its resistance state are obtained in the memristor M2, and used as the carry result of the addition operation; Make the positive electrodes of memristors M2 and M4 float, and connect the positive electrode of memristor M1 to voltage V(a)-2V p , a voltage with an amplitude of 0 is connected to the positive electrode of the memristor M3, and a voltage of -V(a)-V is connected to the end of the resistor that is not connected to the memristor p , thereby obtaining the XOR logic operation result of a and c corresponding to its resistance state in the memristor M3; After obtaining the XOR logic operation result of a and c, the positive electrodes of the memristors M1 and M2 are placed in a floating state, and the positive electrode of the memristor M3 is connected to a voltage V(b)-2V. p , a voltage with an amplitude of 0 is connected to the positive electrode of the memristor M4, and a voltage of -V(b)-V is connected to the end of the resistor that is not connected to the memristor p , thereby obtaining the XOR logic operation result of a, b, c corresponding to its resistance state in the memristor M4, and using it as the summation result of the addition operation; The high resistance state of the memristor corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1". When b is 1, V(b) is V p ; When b is 0, V(b) is a voltage with an amplitude of 0; when a is 1, V(a) is V p ; When a is 0, V(a) is a voltage with an amplitude of 0; voltage V p Satisfaction: V set / 2 < V p < V set , and V p < 2 |V reset | / 3;V set V is the threshold value of the memristor changing from high resistance state to low resistance state; reset is the threshold value at which the memristor changes from a low-resistance state to a high-resistance state.

5. A control method for an adding circuit, characterized in that: Used to implement n-bit number a n ......a2a1, b n ......addition operation of b2b1 and 1-bit carry input c1; n≥2; the addition circuit comprises: a resistor and four identical memristors M1, M2, M3, M4; the negative electrodes of the four memristors are connected to one end of the resistor; the resistance value of the resistor ; R H and R L are the high-resistance resistance value and the low-resistance resistance value of the memristor respectively; The control method comprises: executing n rounds of addition sub-processes in sequence; wherein, in the i-th round of addition sub-process, a i As a, b i As b, c i As c, and the control method of claim 4 is executed on the adding circuit to obtain the carry result c of the i-th round of addition operation i+1 and sum result i ; i=1,2,...,n.

6. An addition operation device, characterized in that: include: Adding circuits and controllers; The adding circuit comprises: a resistor and four identical memristors M1, M2, M3, and M4; the negative electrodes of the four memristors are all connected to one end of the resistor; the resistance value of the resistor ; R H and R L are the high-resistance resistance value and the low-resistance resistance value of the memristor respectively; The controller is used to execute the control method described in claim 4 or 5.

7. A control method for an adding circuit, characterized in that: Used to implement n-bit number a n ......a2a1, b n ......addition operation of b2b1 and 1-bit carry input c1; n≥2; the addition circuit comprises: a resistor and 2n+2 identical memristors; the negative electrodes of the 2n+2 memristors are connected to one end of the resistor; the resistance value of the resistor ; R H and R L are the high-resistance resistance value and the low-resistance resistance value of the memristor respectively; The control method comprises: selecting a memristor from 2n+2 memristors as the memristor M3, and sequentially executing n rounds of addition sub-processes; Where, in the i-th round of addition subprocess, i=1,2,...,n: When i=1, a memristor is selected from the remaining unselected memristors as the memristor M1 in the current round of addition sub-process, and is set to the resistance state corresponding to c1; when i≥2, the memristor M2 in the previous round of addition sub-process is used as the memristor M1 in the current round of addition sub-process; Select two memristors from the remaining unselected memristors as M2 and M4 in the current round of addition sub-process respectively; memristor M3 and memristors M1, M2 and M4 in the current round of addition sub-process constitute a sub-addition circuit in the current round; wherein the resistance state of memristor M3 and memristors M2 and M4 in the current round of addition sub-process are all high resistance state; A i As a, b i As b, c i As c, and executing S2 in the control method of claim 4 on the sub-addition circuit in the current round, obtaining the carry result c of the addition operation in the i-th round i+1 and sum result i ; In each round of addition sub-process, the positive electrodes of the remaining memristors except the memristor M3 and the memristors M1, M2 and M4 in the current round of addition sub-process are in a floating state; After n rounds of addition sub-process, s n ...s2s1 and c n+1 This is the result of the addition operation.

8. An addition operation device, characterized in that: include: Adding circuits and controllers; The adding circuit comprises: a resistor and 2n+2 identical memristors; the negative electrodes of the 2n+2 memristors are all connected to one end of the resistor; the resistance value of the resistor ; R H and R L are the high-resistance resistance and low-resistance resistance of the memristor respectively; n≥2; The controller is used to execute the control method described in claim 7.

9. A control method for an adding circuit, characterized in that: Used to implement n-bit number a n ......a2a1, b n ...addition operation of b2b1 and 1-bit carry input c1; n≥2; the addition circuit comprises: n parallel branches, and switch modules m1, m2, ..., m for controlling the connection or disconnection between two adjacent branches n-1 ; The i-th switch module m i Used to control the connection or disconnection between the i-th branch and the i+1-th branch; i=1,2,...,n-1; the i-th branch includes: the i-th resistor R i and the negative electrode are connected to the resistor R i Three memristors connected at one end; the nth branch includes: the nth resistor R n and the negative electrode are connected to the resistor R n Four memristors connected at one end of the summing circuit; all memristors in the summing circuit are the same, all resistors are the same, and the resistance is ; R H and R L are the high-resistance resistance value and the low-resistance resistance value of the memristor respectively; The control method comprises: S1, execute n-1 rounds of carry calculation sub-processes in sequence; in the i-th round of carry calculation sub-process: control the i-th switch module m i The switch modules are turned on to connect the i-th branch with the i+1-th branch, and the other switch modules are disconnected; When i=1, a memristor is selected from the i-th branch as the memristor M1 in the i-th round of carry calculation sub-process, and is set to the resistance state corresponding to c1; when i≥2, the memristor M2 in the previous round of carry calculation sub-process is used as the memristor M1 in the current round of carry calculation sub-process; A memristor is selected from the i+1th branch as the memristor M2 in the i-th round of carry calculation sub-process, and the resistance state of the memristor M2 is a high resistance state at this time; the positive electrodes of other memristors except the memristors M1 and M2 in the current round of carry calculation sub-process are all in a floating state; The positive electrode of the memristor M1 is connected to the voltage -V(b i )-V p , the positive electrode of the memristor M2 is connected to the voltage V(a i ), in the resistor R i or R i+1 The voltage -V(b i ), so that the corresponding resistance state a is obtained in the memristor M2 in the current round of carry calculation subprocess. i , b i 、c i The result of the majority gate logic operation is used as the carry result of the i-th round of addition operation; S2, disconnect all switch modules so that all branches are disconnected; execute the nth round of carry calculation subprocess, and execute n rounds of sum calculation subprocess in parallel; The performing of the n-th round carry calculation subprocess includes: The memristor M2 in the previous round of carry calculation sub-process is used as the memristor M1 in the current round of carry calculation sub-process, and a memristor that has not been selected is selected from the nth branch as the memristor M2 in the nth round of carry calculation sub-process. At this time, the resistance state of the memristor M2 is a high resistance state; the positive electrodes of the other memristors in the nth branch except the memristors M1 and M2 in the current round of carry calculation sub-process are all in a floating state; The positive electrode of the memristor M1 is connected to the voltage -V(b n )-V p , the positive electrode of the memristor M2 is connected to the voltage V(a n ), in the resistor R n The voltage -V(b n ), so that the corresponding resistance state a is obtained in the memristor M2 in the current round of carry calculation subprocess. n , b n 、c n The result of the majority gate logic operation is used as the carry result of the nth round of addition operation; The parallel execution of n rounds of summation calculation subprocesses includes: For the j-th branch, the memristor selected as memristor M1 in the j-th round of carry calculation subprocess is used as memristor M j1 ; and select two unselected memristors from the jth branch as memristors M j3 、M j4 ; j = 1, 2, ..., n; Each memristor M j4 The positive electrode is in a floating state, and in parallel in each memristor M j1 The positive electrode is connected to the corresponding voltage V(a j )-2V p , in parallel in each memristor M j3 The positive terminal is connected to a voltage with an amplitude of 0, and each resistor R j The end not connected to the memristor is connected to the corresponding voltage -V(a j )-V p , so that in parallel in each memristor M j3 The corresponding a in its resistance state is obtained j 、c j The XOR logic operation result of Each memristor M j1 The positive electrode is in a floating state, and the a j 、c j After the XOR logic operation result, each memristor M j3 The positive electrode is connected to the corresponding voltage V(b j )-2V p , in parallel in each memristor M j4 The positive terminal is connected to a voltage with an amplitude of 0, and each resistor R j The end not connected to the memristor is connected to the corresponding voltage -V(b j )-V p , so that in parallel in each memristor M j4 The corresponding a in its resistance state is obtained j 、b j 、c j The XOR logic operation result is used as the sum result of the addition operation; The high resistance state of the memristor corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1". j When V(b j ) is V p When b j When V(b j ) is a voltage with an amplitude of 0; when a j When V(a j ) is V p ;when a j When V(a j ) is a voltage with an amplitude of 0; voltage V p Satisfaction: V set / 2 < V p < V set , and V p < 2 |V reset | / 3;V set V is the threshold value of the memristor changing from high resistance state to low resistance state; reset is the threshold value at which the memristor changes from a low-resistance state to a high-resistance state.

10. An addition operation device, characterized in that: include: Adding circuits and controllers; The adding circuit comprises: n parallel branches and switch modules m1, m2, ..., m3 for controlling the connection or disconnection between two adjacent branches. n-1 ; n≥2; the i-th switch module m i Used to control the connection or disconnection between the i-th branch and the i+1-th branch; i=1,2,...,n-1; the i-th branch includes: the i-th resistor R i and the negative electrode are connected to the resistor R i Three memristors connected at one end; the nth branch includes: the nth resistor R n and the negative electrode are connected to the resistor R n Four memristors connected at one end of the summing circuit; all memristors in the summing circuit are the same, all resistors are the same, and the resistance is ; R H and R L are the high-resistance resistance value and the low-resistance resistance value of the memristor respectively; The controller is used to execute the control method described in claim 9.

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