Manufacturing method of super-junction MOS (Metal Oxide Semiconductor) device
By using the epitaxial filling process to form a reverse cladding method during the manufacturing process of super junction MOS devices, the stress defect problem caused by the epitaxial layer is solved, and shallower deep trenches and better pressure resistance are achieved.
Patent Information
- Application Number
- CN202510098883.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2025-04-25
AI Technical Summary
When manufacturing super junction MOS devices, the epitaxial layer is prone to completely reverse the mask, resulting in stress defects in subsequent processes.
After defining a super junction pattern on the first conductive type epitaxial layer and etching to form a deep trench, the hard mask layer is removed, and then filling the deep trench into the deep trench through the epitaxial filling process to form a second conductive type epitaxial layer so that it is reversed on the first conductive type epitaxial layer to form a second conductive type epitaxial backclosure.
This method can expand the depletion zone longitudinally, form shallower deep grooves under the same pressure resistance, avoiding the problem of stress defects in subsequent processes.
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Figure CN119894027A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a method for manufacturing a super junction MOS device. Background Art
[0002] In order to solve the problem of increased on-resistance due to increased rated voltage, super junction MOS devices arrange multiple vertical PN junction structures between the drain and source terminals to achieve low on-resistance while maintaining high voltage. The existence of super junctions has greatly broken through the theoretical limits of silicon, and the higher the rated voltage, the more obvious the reduction in on-resistance.
[0003] Related technical solutions When manufacturing a super junction structure, a first conductive type epitaxial layer is usually etched based on a pattern on a mask to form a groove, and then a second conductive type epitaxial layer is epitaxially grown in the groove through an epitaxial doping process without removing the mask.
[0004] However, in the process of epitaxial growth to form the second conductive type epitaxial layer in the related technology, the epitaxial layer is likely to completely wrap around the mask. Since the mask and the epitaxial layer are made of different materials, the related technology is likely to cause stress defects in subsequent processes. Summary of the invention
[0005] The present application provides a method for manufacturing a super junction MOS device, which can solve the problem that related technologies easily lead to stress defects in subsequent processes.
[0006] In order to solve the technical problem in the background technology, the present application provides a method for manufacturing a super junction MOS device, and the method for manufacturing a super junction MOS device comprises the following steps:
[0007] Providing a semiconductor base layer, the semiconductor base layer comprising a base layer and a first conductivity type epitaxial layer;
[0008] defining a super junction pattern on the first conductive type epitaxial layer through a hard mask layer;
[0009] Etching the epitaxial layer based on the super junction pattern to form a deep trench in the first conductivity type epitaxial layer;
[0010] removing the hard mask layer;
[0011] Filling the deep trench with a second conductive type epitaxial layer through an epitaxial filling process, wherein the second conductive type epitaxial layer fills the deep trench and exceeds the deep trench, and is reversely wrapped on the first conductive type epitaxial layer to form a second conductive type epitaxial reverse wrapping layer;
[0012] Forming a trench gate, wherein the trench gate extends downward from the second conductive type epitaxial reverse cladding layer to the first conductive type epitaxial layer;
[0013] Implanting second conductivity type impurities into the second conductivity type epitaxial reverse cladding layer, so that the second conductivity type epitaxial reverse cladding layer forms a second conductivity type body region;
[0014] The source and drain of the super junction MOS device are fabricated in the second conductive type body region.
[0015] Optionally, after the step of filling the deep trench with a second conductive type epitaxial layer by an epitaxial filling process, the second conductive type epitaxial layer fully fills the deep trench and exceeds the deep trench, and reversely wraps the first conductive type epitaxial layer to form a second conductive type epitaxial reverse cladding layer, the following steps are further performed before the step of forming a trench gate, the trench gate extending downward from the second conductive type epitaxial reverse cladding layer to the first conductive type epitaxial layer:
[0016] The second conductivity type epitaxial anti-cladding layer is thinned by a chemical mechanical polishing process.
[0017] Optionally, after the step of thinning the second conductivity type epitaxial reverse cladding layer by chemical mechanical polishing is completed, the thickness of the remaining second conductivity type epitaxial reverse cladding layer is 2um to 3um.
[0018] Optionally, in the step of etching the epitaxial layer based on the super junction pattern to form a deep trench in the first conductive type epitaxial layer, the depth of the deep trench is 30 um to 50 um.
[0019] Optionally, the step of forming a trench gate, wherein the trench gate extends downward from the second conductive type epitaxial reverse cladding layer to the first conductive type epitaxial layer, comprises:
[0020] Etching the second conductivity type epitaxial reverse cladding layer and the first conductivity type epitaxial layer from the second conductivity type epitaxial reverse cladding layer in the first conductivity type epitaxial layer region to form a gate trench;
[0021] forming a gate oxide layer on an inner surface of the gate trench;
[0022] The gate trench with the gate oxide layer is filled with gate polysilicon.
[0023] Optionally, the step of implanting second conductivity type impurities into the second conductivity type epitaxial reverse cladding layer so that the second conductivity type epitaxial reverse cladding layer forms a second conductivity type body region includes:
[0024] The dose of the second conductivity type epitaxial anti-cladding layer is 1E13 atoms / cm 2 To 2E14 atoms / cm 2 The second conductivity type impurities are formed so that the second conductivity type epitaxial anti-cladding layer forms a second conductivity type body region.
[0025] Optionally, the step of implanting second conductivity type impurities into the second conductivity type epitaxial reverse cladding layer so that the second conductivity type epitaxial reverse cladding layer forms a second conductivity type body region includes:
[0026] The second conductivity type impurities are implanted into the second conductivity type epitaxial reverse cladding layer at an energy of 80 KeV to 200 KeV, so that the second conductivity type epitaxial reverse cladding layer forms a second conductivity type body region.
[0027] The technical solution of the present application includes at least the following advantages: the hard mask layer on the N-type epitaxial layer is removed before the deep trench is filled with a P-type epitaxial layer through an epitaxial filling process, and after the P-type epitaxial layer fills the deep trench, it exceeds the deep trench and is reversed to form a P-type epitaxial reverse layer on the N-type epitaxial layer. The P-type epitaxial reverse layer can vertically expand the depletion region, thereby forming a shallower deep trench under the same withstand voltage, avoiding the problem of stress defects in subsequent processes. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0029] Figure 1 A flow chart of a method for manufacturing a super junction MOS device provided in an embodiment of the present application is shown;
[0030] Figure 2 A schematic diagram of the cross-sectional structure of the device after step S2 is completed is shown;
[0031] Figure 3 A schematic diagram of the cross-sectional structure of the device after step S3 is completed is shown;
[0032] Figure 4 A schematic diagram of the cross-sectional structure of the device after step S5 is completed is shown;
[0033] Figure 5 A schematic diagram of the cross-sectional structure of the device after step S6 is completed is shown;
[0034] Figure 6shows a schematic diagram of a cross-sectional structure of the device after step S7 is completed;
[0035] Figure 7 FIG. 4 is a schematic diagram showing a cross-sectional structure of the device after step S8 is completed. DETAILED DESCRIPTION
[0036] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0037] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0038] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0039] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0040] The following embodiments are explained by assuming that the first conductivity type is N type and the second conductivity type is P type. In other embodiments, the first conductivity type may be P type and the second conductivity type may be N type.
[0041] Figure 1 A flow chart of a method for manufacturing a super junction MOS device according to an embodiment of the present application is shown. Figure 1 It can be seen that the manufacturing method of the super junction MOS device includes the following steps:
[0042] Step S1: providing a semiconductor base layer, wherein the semiconductor base layer comprises a base layer and an N-type epitaxial layer.
[0043] Step S2: defining a super junction pattern on the N-type epitaxial layer through a hard mask layer.
[0044] Reference Figure 2 , which shows a schematic diagram of the cross-sectional structure of the device after step S2 is completed, from Figure 2 As can be seen in FIG. 1 , the base layer 110 is covered with an N-type epitaxial layer 120 , and the N-type epitaxial layer 120 is covered with a hard mask layer 130 with a super junction pattern.
[0045] Step S3: etching the epitaxial layer based on the super junction pattern to form a deep trench in the N-type epitaxial layer.
[0046] Exemplarily, the depth of the deep trench is 30um to 50um.
[0047] Figure 3 The schematic diagram of the cross-sectional structure of the device after step S3 is completed is shown. Figure 3 As can be seen in FIG. 1 , a deep trench 200 is formed in the N-type epitaxial layer 120 , and the deep trench 200 extends downward from the upper surface of the N-type epitaxial layer 120 .
[0048] Step S4: removing the hard mask layer.
[0049] Step S5: Filling the deep trench with a P-type epitaxial layer through an epitaxial filling process, wherein the P-type epitaxial layer completely fills the deep trench and exceeds the deep trench, and is inverted to form a P-type epitaxial inverted layer on the N-type epitaxial layer.
[0050] Reference Figure 4 , which shows a schematic diagram of the cross-sectional structure of the device after step S5 is completed, from Figure 4 It can be seen that the P-type epitaxial layer 140 fills the deep trench 200 and exceeds the deep trench 200 , and is reversely wrapped on the N-type epitaxial layer 120 to form a P-type epitaxial reverse cladding layer 300 .
[0051] For example, after completing step S5, the P-type epitaxial anti-cladding layer may be thinned by a chemical mechanical polishing process, and the thickness of the thinned P-type epitaxial anti-cladding layer is 2 um to 3 um.
[0052] Step S6: forming a trench gate, wherein the trench gate extends downward from the P-type epitaxial anti-cladding layer to the N-type epitaxial layer.
[0053] Exemplarily, step S6 may be implemented through the following steps S61 to S63.
[0054] Step S61: etching the P-type epitaxial reverse cladding layer and the N-type epitaxial layer from the P-type epitaxial reverse cladding layer in the N-type epitaxial layer region to form a gate trench.
[0055] Step S62: forming a gate oxide layer on the inner surface of the gate trench.
[0056] Step S63: filling the gate trench with the gate oxide layer with gate polysilicon.
[0057] Reference Figure 5 , which shows a schematic diagram of the cross-sectional structure of the device after step S6 is completed. Figure 5 It can be seen from the figure that the trench gate 400 formed by the manufacturing extends downward from the P-type epitaxial anti-cladding layer 300 to the N-type epitaxial layer 120 .
[0058] The lower surface of the gate polysilicon is flush with the lower surface of the P-type epitaxial reverse cladding layer 300 .
[0059] Step S7: injecting P-type impurities into the P-type epitaxial anti-cladding layer, so that the P-type epitaxial anti-cladding layer forms a P-type body region.
[0060] Figure 6 The schematic diagram of the cross-sectional structure of the device after step S7 is completed is shown. Figure 6 It can be seen from the figure that after the P-type impurities are injected, the P-type epitaxial anti-cladding layer 300 forms a P-type body region P-Body.
[0061] For example, the P-type epitaxial anti-cladding layer may be implanted with a dose of 1E13 atoms / cm at an energy of 80 KeV to 200 KeV. 2 To 2E14 atoms / cm 2 The P-type impurities make the P-type epitaxial anti-cladding layer form a P-type body region.
[0062] Step S8: fabricating the source and drain of the super junction MOS device in the P-type body region.
[0063] Exemplarily, N-type impurities may be injected into the P-type body region P-Body to form N-type source and drain electrodes 310 on the upper surface of the P-type body region P-Body. Then, an isolation layer is formed on the N-type source and drain electrodes, and a metal layer is formed on the isolation layer, and the metal layer contacts the N-type source and drain electrodes through contact holes.
[0064] Figure 7 The schematic diagram of the cross-sectional structure of the device after step S8 is completed is shown. Figure 7 It can be seen that an N-type source and drain 310 is formed on the upper surface of the P-type body region P-Body, an isolation layer 500 is formed on the N-type source and drain 310, a metal layer 600 is formed on the isolation layer 500, and the metal layer 600 contacts the N-type source and drain 310 through a contact hole 700.
[0065] The present application removes the hard mask layer on the N-type epitaxial layer before filling the deep trench to form a P-type epitaxial layer through an epitaxial filling process, and after the P-type epitaxial layer fills the deep trench, it exceeds the deep trench and is reversed on the N-type epitaxial layer to form a P-type epitaxial reverse layer. The P-type epitaxial reverse layer can vertically expand the depletion region, thereby forming a shallower deep trench under the same withstand voltage, avoiding the problem of stress defects in subsequent processes.
[0066] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A method for manufacturing a super junction MOS device, characterized in that: The manufacturing method of the super junction MOS device comprises the following steps: Providing a semiconductor base layer, the semiconductor base layer comprising a base layer and a first conductivity type epitaxial layer; defining a super junction pattern on the first conductive type epitaxial layer through a hard mask layer; Etching the epitaxial layer based on the super junction pattern to form a deep trench in the first conductivity type epitaxial layer; removing the hard mask layer; Filling the deep trench with a second conductive type epitaxial layer through an epitaxial filling process, wherein the second conductive type epitaxial layer fills the deep trench and exceeds the deep trench, and is reversely wrapped on the first conductive type epitaxial layer to form a second conductive type epitaxial reverse wrapping layer; Forming a trench gate, wherein the trench gate extends downward from the second conductive type epitaxial reverse cladding layer to the first conductive type epitaxial layer; Implanting second conductivity type impurities into the second conductivity type epitaxial reverse cladding layer, so that the second conductivity type epitaxial reverse cladding layer forms a second conductivity type body region; The source and drain of the super junction MOS device are fabricated in the second conductive type body region.
2. The method for manufacturing a super junction MOS device according to claim 1, wherein: After the step of filling the deep trench with a second conductive type epitaxial layer by an epitaxial filling process, the second conductive type epitaxial layer fully fills the deep trench and exceeds the deep trench, and reversely wraps the first conductive type epitaxial layer to form a second conductive type epitaxial reverse cladding layer, the following steps are further performed before the step of forming a trench gate, the trench gate extending downward from the second conductive type epitaxial reverse cladding layer to the first conductive type epitaxial layer: The second conductivity type epitaxial anti-cladding layer is thinned by a chemical mechanical polishing process.
3. The method for manufacturing a super junction MOS device according to claim 2, characterized in that: After the step of thinning the second conductivity type epitaxial reverse cladding layer by chemical mechanical polishing is completed, the thickness of the remaining second conductivity type epitaxial reverse cladding layer is 2um to 3um.
4. The method for manufacturing a super junction MOS device according to claim 1, wherein: The step of forming a trench gate, wherein the trench gate extends downward from the second conductive type epitaxial reverse cladding layer to the first conductive type epitaxial layer, comprises: Etching the second conductivity type epitaxial reverse cladding layer and the first conductivity type epitaxial layer from the second conductivity type epitaxial reverse cladding layer in the first conductivity type epitaxial layer region to form a gate trench; forming a gate oxide layer on an inner surface of the gate trench; The gate trench with the gate oxide layer is filled with gate polysilicon.
5. The method for manufacturing a super junction MOS device according to claim 1, wherein: In the step of etching the epitaxial layer based on the super junction pattern to form a deep trench in the first conductive type epitaxial layer, the depth of the deep trench is 30 um to 50 um.
6. The method for manufacturing a super junction MOS device according to claim 1, wherein: The step of injecting second conductivity type impurities into the second conductivity type epitaxial reverse cladding layer so that the second conductivity type epitaxial reverse cladding layer forms a second conductivity type body region comprises: The dose of the second conductivity type epitaxial anti-cladding layer is 1E13 atoms / cm 2 To 2E14 atoms / cm 2 The second conductivity type impurities are formed so that the second conductivity type epitaxial anti-cladding layer forms a second conductivity type body region.
7. The method for manufacturing a super junction MOS device according to claim 1, wherein: The step of injecting second conductivity type impurities into the second conductivity type epitaxial reverse cladding layer so that the second conductivity type epitaxial reverse cladding layer forms a second conductivity type body region comprises: The second conductivity type impurities are implanted into the second conductivity type epitaxial reverse cladding layer at an energy of 80 KeV to 200 KeV, so that the second conductivity type epitaxial reverse cladding layer forms a second conductivity type body region.