High voltage MOS device embedded in advanced process
By setting an inverse adjustment zone opposite to the impurity type of the drift region at the gate longitudinal boundary position of the high-voltage MOS device, the bimodal characteristic problem in the device is solved, which improves low leakage performance and reduces power consumption.
Patent Information
- Application Number
- CN202510099387.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2025-04-25
AI Technical Summary
In the prior art, the production of high-voltage MOS devices embedded in advanced processes has problems with bimodal characteristics, resulting in reduced low leakage performance of the device and excessive power consumption.
An inverse adjustment region opposite to the impurity type of the first drift region and the second drift region is provided at both end boundary positions extending longitudinally in the gate to adjust the impurity concentration and enable the parasitic device to be turned on simultaneously to avoid the bimodal effect.
By setting the inverse adjustment zone, the bimodal effect can be effectively avoided, the device's low leakage performance and power consumption can be reduced.
Smart Images
Figure CN119894045A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a high-voltage MOS device embedded in an advanced process. Background Art
[0002] In semiconductor technology, even if the size of components continues to decrease, it is still hoped that the performance of transistors can be further improved, and it is also hoped that integrated circuit semiconductor devices that combine low, high, and medium voltage application ranges can be manufactured. For example, an integrated circuit (hereinafter referred to as a driver IC) for driving image sensors, LCDs, and printed heads, etc., is composed of a drive output unit of a high-voltage MOS transistor with a strong withstand voltage between the drain and the source that works at a power supply voltage above +V, and a logic unit of a control drive output unit of a low-voltage MOS transistor with a poor drain withstand voltage that can be used at a power supply voltage below several volts.
[0003] However, high-voltage MOS devices embedded in advanced processes produced by related processes still have problems with dielectric current and double-peak characteristics, which directly reduce the low leakage performance of the device and cause excessive power consumption. Summary of the invention
[0004] The present application provides a high-voltage MOS device embedded in an advanced process, which can solve the problem of double-peak characteristics of the high-voltage MOS device embedded in the advanced process in the related art.
[0005] In order to solve the technical problem described in the background technology, the present application provides a high-voltage MOS device embedded in an advanced process, the high-voltage MOS device embedded in the advanced process includes a semiconductor base layer, a gate extending in a longitudinal direction is formed on the semiconductor base layer; after a voltage is applied to the gate, a channel region extending in a longitudinal direction is formed in the semiconductor base layer at a position corresponding to the gate, and the channel region has a first width in a transverse direction;
[0006] The semiconductor base layer also forms:
[0007] A first drift region, wherein the first drift region is located on a left side of the channel region in a lateral direction, and the first drift region overlaps with a side of the channel region that is close to the first drift region;
[0008] a second drift region, the second drift region being located on the right side of the channel region in a lateral direction, the second drift region overlapping a side close to the channel region; the second drift region and the first drift region being spaced apart by a second width;
[0009] An inversion adjustment region, wherein the inversion adjustment region is located at two end boundaries of the gate extending longitudinally, and an impurity type of the inversion adjustment region is opposite to an impurity type of the first drift region and the second drift region.
[0010] Optionally, the inversion adjustment region is located at a longitudinally extending boundary of the gate at a position spaced apart between the second drift region and the first drift region.
[0011] Optionally, a width of the inversion adjustment region is equal to a second width between the second drift region and the first drift region.
[0012] Optionally, the height of the inversion adjustment zone along the longitudinal extension is 0.2um to 0.6um.
[0013] Optionally, the inversion adjustment region extends longitudinally inwardly to a first height from the longitudinal extension boundary of the gate, and the inversion adjustment region extends longitudinally inwardly to a second height from the longitudinal extension boundary of the gate, and the second height is greater than the first height.
[0014] Optionally, the doping concentration of the inversion regulation region is 1*E+15e / cm 2 To 5*E+15e / cm 2 .
[0015] The technical solution of the present application includes at least the following advantages: by setting an inversion adjustment region with an impurity type opposite to that of the first drift region and the second drift region at the boundary positions of the two ends of the longitudinal extension of the gate, the impurity concentration at the longitudinal boundary position of the gate is adjusted, so that the parasitic devices at the longitudinal boundary position of the gate are turned on synchronously with the parasitic devices at other longitudinal positions of the gate, thereby avoiding the double peak effect. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0017] Figure 1 A schematic diagram of a top view of a high-voltage MOS device embedded in an advanced process provided by an embodiment of the present application is shown;
[0018] Figure 2 A schematic diagram of a top view of a high-voltage MOS device embedded in an advanced process provided by another embodiment of the present application is shown. DETAILED DESCRIPTION
[0019] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0020] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0021] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0022] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0023] Figure 1 FIG. 1 shows a schematic diagram of a top view of a high-voltage MOS device embedded in an advanced process according to an embodiment of the present application. Figure 1 As can be seen, the high-voltage MOS devices embedded in the advanced process include:
[0024] A semiconductor base layer, on which a gate 100 extending in a longitudinal direction is formed; after a voltage is applied to the gate 100, a channel region 200 extending in a longitudinal direction is formed in the semiconductor base layer at a position corresponding to the gate 100, and the channel region has a first width W1 in a transverse direction.
[0025] The semiconductor base layer also forms:
[0026] The first drift region 310 is located on the left side of the channel region 200 in the horizontal direction, and the first drift region 310 overlaps with the side close to the channel region 200. Exemplarily, the source 400 of the high-voltage MOS device is formed in the first drift region 310. Figure 1 In the illustrated embodiment, the source 400 and the gate 100 of the high voltage MOS device are laterally connected.
[0027] The second drift region 320 is located on the right side of the channel region 200 in the horizontal direction, and the second drift region 320 overlaps with the side of the channel region 200 that is close to the second drift region 320; the second drift region 320 is spaced apart from the first drift region 310 by a second width W2. Exemplarily, the drain 500 of the high-voltage MOS device is formed in the second drift region 320. Figure 1 In the illustrated embodiment, the drain 500 of the high voltage MOS device is laterally connected to the gate 100 .
[0028] In other embodiments, Figure 2 In the embodiment shown, the first drift region 310 overlaps with the side close to the channel region 200, the second drift region 320 overlaps with the side close to the channel region 200, and the source 400 and the drain 500 located in the second drift region 320 are spaced apart from the gate 100. The source 400, the drain 500 and the gate 100 form the active region of the high-voltage MOS device.
[0029] The inversion adjustment region 600 is located at the boundary positions of both ends of the longitudinal extension of the gate 100, and the impurity type of the inversion adjustment region 600 is opposite to the impurity type of the first drift region 310 and the second drift region 320. Exemplarily, the impurity type of the first drift region 310 and the second drift region 320 is N-type, and the impurity type of the inversion adjustment region 600 is P-type.
[0030] In the related art, impurity ions are easily precipitated at the boundary of the gate 100 due to processes such as thermal processes, which easily leads to a double peak phenomenon, which is specifically manifested as an uneven ID-VG curve and the parasitic devices at the longitudinal boundary of the gate are turned on earlier than the parasitic devices at other longitudinal positions of the gate.
[0031] In the present application, an inversion adjustment region with an impurity type opposite to that of the first drift region and the second drift region is arranged at the boundary positions of both ends of the longitudinal extension of the gate to adjust the impurity concentration at the longitudinal boundary position of the gate, so that the parasitic device at the longitudinal boundary position of the gate is turned on synchronously with the parasitic devices at other longitudinal positions of the gate, thereby avoiding the double peak effect.
[0032] Exemplarily, the inversion adjustment region 600 is located at the longitudinal extension boundary of the gate 100 at the interval between the second drift region 320 and the first drift region 310. The width of the inversion adjustment region 600 is equal to the second width W2 between the second drift region 320 and the first drift region 310. Since the ion precipitation problem at the longitudinal extension boundary position of the gate at the interval between the first drift region and the second drift region is serious, an inversion adjustment region is formed at this position, and the width of the inversion adjustment region is equal to the second width W2, which can well solve the problem of ion precipitation at this position and avoid the double peak effect.
[0033] Exemplarily, the height h of the inversion adjustment region 600 extending in the longitudinal direction is 0.2um to 0.6um. The height h of the inversion adjustment region 600 should not be too small or too large. If it is too small, the compensation effect will be reduced, and if it is too large, the threshold voltage of the device will be affected.
[0034] The inversion adjustment region 600 extends inwardly from the longitudinally extending boundary of the gate 100 to a first height in the longitudinal direction, and extends inwardly from the longitudinally extending boundary of the gate 100 to a second height in the longitudinal direction, and the second height is greater than the first height. The inversion adjustment region 600 extends inwardly from the longitudinally extending boundary of the gate 100 to a height greater than the inwardly extending height, thereby reducing the impact on the threshold voltage of the device.
[0035] For example, the doping concentration of the inversion adjustment region 600 is 1*E+15e / cm 2 To 5*E+15e / cm 2 .
[0036] The description is given with the impurity type of the inversion adjustment region 600 being P-type and the impurity type of the first drift region 310 and the second drift region 320 being N-type. When manufacturing the inversion adjustment region 600 in this embodiment, the inversion adjustment region 600 can be shielded in the N-type doping process after the gate 100 structure is formed, and the inversion adjustment region 600 is additionally implanted in the subsequent P-type doping process.
[0037] This embodiment uses an inversion adjustment region to adjust the work function of the polysilicon gate and eliminate the double peak phenomenon caused by edge parasitic devices. The manufacturing method can reduce the process difficulty of embedding high-voltage MOS devices at advanced process nodes, and the process accuracy can be controlled. The inversion adjustment region is formed only by modifying the layout, without increasing the device size and additional processes.
[0038] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A high voltage MOS device embedded in an advanced process, characterized in that: The high-voltage MOS device embedded in the advanced process includes a semiconductor base layer, on which a gate extending in a longitudinal direction is formed; after a voltage is applied to the gate, a channel region extending in a longitudinal direction is formed in the semiconductor base layer at a position corresponding to the gate, and the channel region has a first width in a transverse direction; The semiconductor base layer also forms: A first drift region, wherein the first drift region is located on a left side of the channel region in a lateral direction, and the first drift region overlaps with a side of the channel region that is close to the first drift region; a second drift region, the second drift region being located on the right side of the channel region in a lateral direction, the second drift region overlapping a side close to the channel region; the second drift region and the first drift region being spaced apart by a second width; An inversion adjustment region, wherein the inversion adjustment region is located at two end boundaries of the gate extending longitudinally, and an impurity type of the inversion adjustment region is opposite to an impurity type of the first drift region and the second drift region.
2. The high voltage MOS device embedded in the advanced process as claimed in claim 1, characterized in that: The inversion adjustment region is located at a longitudinal extension boundary of the gate at a position spaced apart between the second drift region and the first drift region.
3. The high voltage MOS device embedded in the advanced process as claimed in claim 2, characterized in that: The width of the inversion adjustment region is equal to a second width between the second drift region and the first drift region.
4. The high voltage MOS device embedded in an advanced process as claimed in claim 1, characterized in that: The height of the inversion adjustment zone along the longitudinal extension is 0.2um to 0.6um.
5. The high voltage MOS device embedded in the advanced process as claimed in claim 4, characterized in that: The inversion adjustment region extends longitudinally inwardly from the longitudinal extension boundary of the gate to a first height, and the inversion adjustment region extends longitudinally inwardly from the longitudinal extension boundary of the gate to a second height, and the second height is greater than the first height.
6. The high voltage MOS device embedded in an advanced process as claimed in claim 1, characterized in that: The doping concentration of the inversion regulation region is 1*E+15e / cm 2 To 5*E+15e / cm 2 .