Semiconductor element and manufacturing method thereof

Abstract

The invention discloses a semiconductor element and a manufacturing method thereof. The semiconductor element comprises a gate structure, a first epitaxial layer, a second epitaxial layer and a cover layer. The gate structure is disposed on a substrate. The first epitaxial layer is disposed in the substrate at two sides of the gate structure. The second epitaxial layer is disposed on the first epitaxial layer, wherein an included angle between a surface of the second epitaxial layer and a horizontal direction is 15-35 degrees. The cap layer is disposed on the second epitaxial layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a semiconductor element with an epitaxial layer having a surface with a specific tilt angle and a manufacturing method thereof. Background Art

[0002] As the line width of semiconductor manufacturing processes continues to shrink, more challenges and bottlenecks have emerged in semiconductor manufacturing processes. For example, in a MOS transistor with a cap layer formed on an epitaxial layer, when the cap layer is thick, short circuits are likely to occur between adjacent components, and when the cap layer is thin, the outer wall of the epitaxial layer may be removed during the cleaning process to form holes, causing the metal silicide to easily flow along the holes in the epitaxial layer during the subsequent self-aligned silicide process, causing the metal silicide to form outside the predetermined position.

[0003] Therefore, how to improve the structure and manufacturing method of semiconductor elements can reduce the probability of short circuits between elements on the one hand, and reduce the probability of unexpected flow of metal silicide on the other hand, which has become an important issue for related industries. Summary of the invention

[0004] An object of the present invention is to provide a semiconductor device and a method for manufacturing the same to solve the above-mentioned problem.

[0005] According to one embodiment of the present invention, a semiconductor element is provided, comprising a gate structure, a first epitaxial layer, a second epitaxial layer and a cap layer. The gate structure is disposed on a substrate. The first epitaxial layer is disposed in the substrate on two sides of the gate structure. The second epitaxial layer is disposed on the first epitaxial layer, wherein an angle between a surface of the second epitaxial layer and a horizontal direction is 15 degrees to 35 degrees. The cap layer is disposed on the second epitaxial layer.

[0006] According to another embodiment of the present invention, a method for manufacturing a semiconductor device is provided, comprising the following steps: forming a gate structure on a substrate; forming two grooves in the substrate on two sides of the gate structure; forming a first epitaxial layer in the two grooves; forming a second epitaxial layer on the first epitaxial layer, wherein an angle between a surface of the second epitaxial layer and a horizontal direction is 15 degrees to 35 degrees; forming a cap layer on the second epitaxial layer.

[0007] Compared with the prior art, the present invention has the angle between the surface of the second epitaxial layer and the horizontal direction within a specific range, which is beneficial to reducing the probability of forming holes on the side wall of the second epitaxial layer during the cleaning process without increasing the thickness of the cap layer. It is also beneficial to reducing the probability of short circuits between components caused by excessive thickness of the cap layer, and can reduce the probability of unexpected flow of metal silicide. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 It is a schematic cross-sectional view of the steps of manufacturing a semiconductor device according to one embodiment of the present invention.

[0009] Main component symbols

[0010] 1: Semiconductor components

[0011] 10: Base

[0012] 11: Top surface

[0013] 110: Gate structure

[0014] 112: Gate dielectric layer

[0015] 114: Gate material layer

[0016] 116: Mask layer

[0017] 122: First spacer

[0018] 124: Second spacer

[0019] 130: Lightly doped drain region

[0020] 140: Groove

[0021] 150: Buffer layer

[0022] 160: First epitaxial layer

[0023] 161: Top surface

[0024] 170: Second epitaxial layer

[0025] 171: Surface

[0026] 172: Bottom surface

[0027] 173: Top surface

[0028] 180: Covering layer

[0029] 181: Surface

[0030] 192a, 192b, 192c, 192d: Etching gas

[0031] 194a, 194b, 194c, 194d: Deposition material gas

[0032] A1, A2: Angle

[0033] D1: Horizontal direction

[0034] D2: Vertical direction

[0035] P0: Ion implantation process

[0036] P1, P2, P3, P4: Selective epitaxial growth process

[0037] t1, t2, W1: thickness

[0038] T1: Total thickness DETAILED DESCRIPTION

[0039] The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the accompanying drawings. In order to make the contents of the present invention clearer and easier to understand, the following drawings may be simplified schematic diagrams, and the elements therein may not be drawn to scale. In addition, the number and size of each element in the drawings are for illustration only and are not intended to limit the present invention. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, back, bottom, top, etc., are only for reference to the directions of the accompanying drawings. Therefore, the directional terms used are for illustration, not for limitation of the present invention. In addition, in the following embodiments, the same or similar elements will use the same or similar reference numerals.

[0040] The description below regarding “a first feature is formed on or above a second feature” may refer to “the first feature is in direct contact with the second feature” or “there are other features between the first feature and the second feature” such that the first feature and the second feature are not in direct contact with each other.

[0041] The present invention uses the terms "first", "second", etc. to describe elements, regions, layers, and / or sections, but it should be understood that these terms are only used to distinguish a certain element, region, layer, and / or section from another element, region, layer, and / or section, and they do not imply or represent any previous ordinal number of the element, nor do they represent the arrangement order of a certain element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, region, layer, and / or section discussed below may also be referred to as the second element, region, layer, and / or section. These terms in the claims may not be the same as those in the specification, but may be replaced by "first", "second", "third", etc. according to the order of the elements declared in the claims.

[0042] Please refer to Figures 1 to 6 , which is a schematic cross-sectional view of the steps of manufacturing a semiconductor device according to one embodiment of the present invention. In this embodiment, a semiconductor device 1 (see Figure 6 ) is used as an example for explanation of the PMOS transistor. Figure 1 As shown, first, a gate structure 110 is formed on a substrate 10. The substrate 10 may be a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate or a silicon on insulator (SOI) substrate. The substrate 10 may further include a well region (not shown in the figure). For example, the well region may be formed by an ion implantation process (not shown in the figure), and the doping of the well region may be adjusted depending on whether the semiconductor element 1 formed subsequently is suitable for an NMOS transistor or a PMOS transistor. In the present embodiment, the semiconductor element 1 is a PMOS transistor as an example, therefore, the well region may be an N-type well region, and the well region may be doped with N-type dopants, such as arsenic, phosphorus, etc.

[0043] The gate structure 110 includes, from bottom to top, a gate dielectric layer 112, a gate material layer 114, and a mask layer 116. In the present embodiment, the gate structure 110 can be manufactured by a gate first manufacturing process, a gate last manufacturing process of a high-k first manufacturing process, and a gate last manufacturing process of a high-k last manufacturing process according to the manufacturing process requirements. Taking the post-high-k dielectric layer fabrication process of the present embodiment as an example, a deposition process may be performed to sequentially form a gate dielectric material, a gate material, and a mask material on the substrate 10, and a pattern transfer process may be performed using a patterned photoresist (not shown) as a mask, and a portion of the mask material, a portion of the gate material, and a portion of the gate dielectric material may be removed by a single etching or a sequential etching process, and then the patterned photoresist may be stripped to form a gate structure 110 including a gate dielectric layer 112, a gate material layer 114, and a mask layer 116 on the top surface 11 of the substrate 10. The material of the gate dielectric layer 112 may include, but is not limited to, oxides and / or nitrides, and the oxide may include, for example, silicon dioxide (SiO 2 ), the nitride may include, for example, silicon nitride (SiN). The material of the gate material layer 114 may include, but is not limited to, a non-metallic conductive material, such as polysilicon. The material of the mask layer 116 may include, but is not limited to, silicon dioxide (SiO 2 ), silicon nitride (SiN), silicon carbide (SiC) and / or silicon oxynitride (SiON).

[0044] In addition, although the present embodiment takes a planar transistor as an example, in other variations, the method for manufacturing a semiconductor element of the present invention can also be applied to a non-planar transistor, such as a transistor having a fin structure. In this case, Figure 1 The indicated substrate 10 corresponds to the fin structure formed on the substrate 10 .

[0045] Next, a first spacer 122 may be selectively formed to surround the gate structure 110. The first spacer 122 may be, for example, an offset spacer. The material of the first spacer 122 may include oxide, such as silicon dioxide. Next, an ion implantation process P0 is performed to form two lightly doped drain regions 130 in the substrate 10 on both sides of the gate structure 110. The conductivity type of the two lightly doped drain regions 130 is the same and different from the conductivity type of the well region. In this embodiment, the well region is an N-type well region, and the conductivity type of the two lightly doped drain regions 130 is P-type. Therefore, the ion implantation process P0 is to implant P-type dopants into the substrate 10. P-type dopants may include, but are not limited to, boron (B), aluminum (Al), gallium (Ga), indium (In), etc. Next, a second spacer 124 is formed to surround the gate structure 110. The material of the second spacer 124 may include nitride, such as silicon nitride, silicon oxynitride, or silicon carbide nitride.

[0046] Then, if Figure 2 As shown, two grooves 140 are formed in the substrate 10 on two sides of the gate structure 110. For example, a dry etching and / or wet etching process can be performed, and the gate structure 110, the first spacer 122 and the second spacer 124 are used as etching masks, and a single or multiple etchings are performed downward along the second spacer 124 to remove a portion of the substrate 10 to form two grooves 140 in the substrate 10 on two sides of the gate structure 110.

[0047] Then, if Figure 3 As shown, the buffer layer 150 can be selectively formed in the two grooves 140. Specifically, a selective epitaxial growth process P1 can be performed, for example, a chemical vapor deposition system (not shown) can be used, and an etching gas 192a and a deposition material gas 194a are respectively introduced into the chemical vapor deposition system to form the buffer layer 150 in the two grooves 140. According to one embodiment, the material of the buffer layer 150 includes silicon germanium (SiGe), the etching gas 192a includes hydrogen chloride (HCl), and the deposition material gas 194a includes a silicon (Si) source gas, such as dichlorosilane (DCS), and may further include another deposition material gas (not separately labeled), for example, may include a germanium (Ge) source gas, but is not limited thereto, and the etching gas 192a and the deposition material gas 194a can be adjusted according to the composition of the buffer layer 150.

[0048] Then, if Figure 4As shown, a first epitaxial layer 160 is formed in the two grooves 140, wherein the first epitaxial layer 160 is disposed on the buffer layer 150. Specifically, a selective epitaxial growth process P2 may be performed, for example, a chemical vapor deposition system (not shown) may be used, and an etching gas 192b and a deposition material gas 194b are respectively introduced into the chemical vapor deposition system to form the first epitaxial layer 160 in the two grooves 140. According to one embodiment, the material of the first epitaxial layer 160 includes silicon germanium, the material of the buffer layer 150 includes silicon germanium (SiGe), and the concentration of germanium in the first epitaxial layer 160 is greater than the concentration of germanium in the buffer layer 150. The etching gas 192b includes hydrogen chloride, and the deposition material gas 194b includes a silicon source gas, such as dichlorosilane, and may further include another deposition material gas (not separately labeled), for example, may include a germanium source gas, but is not limited thereto, and the etching gas 192b and the deposition material gas 194b may be adjusted according to the composition of the first epitaxial layer 160.

[0049] Figure 4 In the embodiment, the buffer layer 150 is disposed between the substrate 10 and the first epitaxial layer 160, so that the first epitaxial layer 160 does not directly contact the substrate 10. The buffer layer 150 can relieve the stress between the substrate 10 and the first epitaxial layer 160. The top surface 161 of the first epitaxial layer 160 is flush with or substantially flush with the top surface 11 of the substrate 10. In other words, the first epitaxial layer 160 does not protrude from or substantially does not protrude from the top surface 11 of the substrate 10. Here, the top surface 11 of the substrate 10 refers to the surface of the substrate 10 where the groove 140 is not formed.

[0050] Then, if Figure 5 As shown, a second epitaxial layer 170 is formed on the first epitaxial layer 160. Specifically, a selective epitaxial growth process P3 may be performed, for example, a chemical vapor deposition system (not shown) may be used, and an etching gas 192c and a deposition material gas 194c are respectively introduced into the chemical vapor deposition system to form the second epitaxial layer 170 on the first epitaxial layer 160. According to one embodiment, the material of the first epitaxial layer 160 includes silicon germanium, the etching gas 192c includes hydrogen chloride gas, and the deposition material gas 194c includes a silicon source gas, such as dichlorosilane, and may further include another deposition material gas (not separately labeled), for example, may include a germanium source gas, but is not limited thereto, and the etching gas 192c and the deposition material gas 194c may be adjusted according to the composition of the first epitaxial layer 160. Figure 5 In the embodiment, the bottom surface 172 of the second epitaxial layer 170 is flush with or substantially flush with the top surface 11 of the substrate 10. In other words, the second epitaxial layer 170 protrudes from or substantially protrudes from the top surface 11 of the substrate 10, and the second epitaxial layer 170 has a trapezoidal cross section.

[0051] When the materials of the buffer layer 150, the first epitaxial layer 160, and the second epitaxial layer 170 all contain silicon germanium, the concentration of germanium in the buffer layer 150 is lower than the concentration of germanium in the first epitaxial layer 160, and the concentration of germanium in the second epitaxial layer 170 changes gradually from bottom to top along the vertical direction D2. For example, it may gradually decrease from bottom to top along the vertical direction D2, or it may gradually change from bottom to top along the vertical direction D2 from the same as the concentration of germanium in the first epitaxial layer 160 to 0.

[0052] Then, if Figure 6 As shown, a cap layer 180 is formed on the second epitaxial layer 170, and the cap layer 180 completely covers the second epitaxial layer 170. Specifically, a selective epitaxial growth process P4 can be performed, for example, a chemical vapor deposition system (not shown) can be used, and an etching gas 192d and a deposition material gas 194d are respectively introduced into the chemical vapor deposition system to form the cap layer 180 on the second epitaxial layer 170. According to one embodiment, the material of the cap layer 180 includes silicon, and the material of the cap layer 180 does not include germanium (that is, the concentration of germanium in the cap layer 180 is 0), the etching gas 192d includes hydrogen chloride gas, and the deposition material gas 194d includes silicon source gas, such as dichlorosilane, but is not limited thereto, and the etching gas 192d and the deposition material gas 194d can be adjusted according to the composition of the cap layer 180. In this way, the production of the semiconductor device 1 can be completed.

[0053] When forming the second epitaxial layer 170, the molar ratio of the etching gas 192c to the deposition material gas 194c may be greater than the molar ratio of the etching gas 192d to the deposition material gas 194d when forming the cap layer 180. As a result, it is beneficial to give the angle A1 between the surface 171 of the second epitaxial layer 170 and the horizontal direction D1 and the angle A2 between the surface 181 of the cap layer 180 and the horizontal direction D1 to fall within a specific range, or to make the surface 171 and the surface 181 grow into a specific crystal plane, which is beneficial to reduce the probability of short circuit between components and reduce the probability of unexpected flow of metal silicide. For example, when forming the second epitaxial layer 170, the molar ratio of the etching gas 192c to the deposition material gas 194c may be 1 to 2. When forming the cap layer 180, the molar ratio of the etching gas 192d to the deposition material gas 194d may be 0.45 to 0.55.

[0054] The present invention can perform a doping process in-situ while forming the first epitaxial layer 160 and perform an annealing process in combination, so as to inject dopants into the first epitaxial layer 160 to form source / drain regions (not separately labeled), or can perform an ion implantation process after the first epitaxial layer 160 is formed and perform an annealing process in combination to form source / drain regions in the first epitaxial layer 160, all of which are within the scope of the present invention.

[0055] Although not shown in the figure, the method for manufacturing a semiconductor device may also include other manufacturing processes for manufacturing transistors, such as sequentially forming a contact hole etching stop layer and an interlayer dielectric layer to cover the gate structure 110 and the cap layer 180, and performing a metal gate replacement (RMG) manufacturing process to replace the non-metallic conductive material of the gate structure 110 with a single-layer structure or a multi-layer structure containing a metal conductive material. The aforementioned single-layer structure may only include a low-resistance metal layer, and the material of the low-resistance metal layer may be selected from copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP) or a combination thereof. The aforementioned multi-layer structure may be formed by a low-resistance metal layer and a high dielectric constant dielectric layer and / or a barrier layer and / or a work function metal layer. The metal gate replacement manufacturing process is well known in the art and will not be described in detail here.

[0056] The above-mentioned film layers, such as the gate dielectric layer 112, the gate material layer 114, the mask layer 116, the first spacer 122, the second spacer 124, etc., can be formed by any suitable method, such as but not limited to molecular beam epitaxy (MBE), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer deposition (ALD), etc.

[0057] Please refer to Figure 6 , Figure 6 A cross-sectional view of a semiconductor device 1 according to an embodiment of the present invention is shown. Here, the semiconductor device 1 is taken as a PMOS transistor as an example.

[0058] The semiconductor device 1 comprises a gate structure 110, a first epitaxial layer 160, a second epitaxial layer 170 and a cap layer 180. The gate structure 110 is disposed on a substrate 10, the first epitaxial layer 160 is disposed in the substrate 10 on two sides of the gate structure 110, the second epitaxial layer 170 is disposed on the first epitaxial layer 160, and the cap layer 180 is disposed on the second epitaxial layer 170.

[0059] The semiconductor device 1 may further include a buffer layer 150, a first spacer 122, and a second spacer 124. The buffer layer 150 is disposed in the substrate 10 on both sides of the gate structure 110, the first spacer 122 surrounds the gate structure 110, and the second spacer 124 surrounds the first spacer 122. The gate structure 110 includes a gate dielectric layer 112, a gate material layer 114, and a mask layer 116 from bottom to top.

[0060] The angle A1 between the surface 171 of the second epitaxial layer 170 and the horizontal direction D1 is 15 degrees to 35 degrees. The material of the second epitaxial layer 170 may include silicon germanium, and the crystal plane of the surface 171 of the second epitaxial layer 170 may be (311). The thickness t1 of the second epitaxial layer 170 perpendicular to the horizontal direction D1 (i.e., parallel to the vertical direction D2) is 30 angstroms to 150 angstroms. This helps to reduce the probability of holes being formed on the sidewalls of the second epitaxial layer 170 during the cleaning process. The aforementioned range of thickness t1 may refer to the distance between the bottommost surface (i.e., bottom surface 172) and the topmost surface (i.e., top surface 173) of the second epitaxial layer 170 in the vertical direction D2. The second epitaxial layer 170 completely covers the first epitaxial layer 160 . The bottom surface 172 of the second epitaxial layer 170 is flush with or substantially flush with the top surface 11 of the substrate 10 . The second epitaxial layer 170 protrudes from or substantially protrudes from the top surface 11 of the substrate 10 , and has a trapezoidal cross section.

[0061] The angle A2 between the surface 181 of the cap layer 180 and the horizontal direction D1 is 0 to 5 degrees. The material of the cap layer 180 may include silicon, and the crystal plane of the surface 181 of the cap layer 180 may be (100). The thickness t2 of the cap layer 180 perpendicular to the horizontal direction D1 (i.e., parallel to the vertical direction D2) is 100 angstroms to 200 angstroms. The thickness t2 of the cap layer 180 in the peripheral region (not separately labeled) is greater than the thickness t2 of the cap layer 180 in the central region (not separately labeled), which can enhance the effect of preventing the metal silicide from flowing unexpectedly. The aforementioned range of thickness t2 may refer to the distance between the topmost surface (i.e., top surface 173) of the second epitaxial layer 170 and the topmost surface (i.e., surface 181) of the cap layer 180 in the vertical direction D2. The cap layer 180 completely covers the second epitaxial layer 170, and the sidewall (not separately labeled) of the cap layer 180 may be in direct contact with the second spacer 124.

[0062] The sum of the thicknesses T1 of the second epitaxial layer 170 and the cap layer 180 in the direction perpendicular to the horizontal direction D1 (i.e., T=t1+t2) is 130 angstroms to 350 angstroms. The thickness W1 of a sidewall (not separately labeled) of the second spacer 124 in the horizontal direction D1 may be 150 angstroms to 200 angstroms. The ratio (T1 / W1) of the sum of the thicknesses T1 of the second epitaxial layer 170 and the cap layer 180 in the direction perpendicular to the horizontal direction D1 to the thickness W1 of the sidewall of the second spacer 124 in the horizontal direction D1 may be 1 to 2. Thus, the effect of preventing the metal silicide from flowing unexpectedly may be enhanced.

[0063] Compared with the prior art, the present invention has the angle between the surface of the second epitaxial layer and the horizontal direction within a specific range, which is beneficial for reducing the probability of forming holes on the side wall of the second epitaxial layer during the cleaning process without increasing the thickness of the cap layer. It is also beneficial for reducing the probability of short circuits between components caused by excessive thickness of the cap layer, and can reduce the probability of unexpected flow of metal silicide.

[0064] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor device comprising: A gate structure is disposed on the substrate; A first epitaxial layer is disposed in the substrate on two sides of the gate structure; A second epitaxial layer is disposed on the first epitaxial layer, wherein an angle between a surface of the second epitaxial layer and a horizontal direction is 15 degrees to 35 degrees; and The cap layer is disposed on the second epitaxial layer. 2 . The semiconductor device as claimed in claim 1 , wherein an angle between a surface of the cap layer and the horizontal direction is 0 degrees to 5 degrees. 3 . The semiconductor device as claimed in claim 2 , wherein a material of the cap layer comprises silicon, and a crystal plane of the surface of the cap layer is (100). 4 . The semiconductor device as claimed in claim 1 , wherein a thickness of the second epitaxial layer in a direction perpendicular to the horizontal direction is 30 angstroms to 150 angstroms. 5 . The semiconductor device as claimed in claim 1 , wherein a thickness of the cap layer in a direction perpendicular to the horizontal direction is 100 angstroms to 200 angstroms. 6 . The semiconductor device as claimed in claim 1 , wherein a total thickness of the second epitaxial layer and the cap layer in a direction perpendicular to the horizontal direction is 130 angstroms to 350 angstroms.

7. The semiconductor device according to claim 1, further comprising: A spacer surrounds the gate structure. 8 . The semiconductor device as claimed in claim 7 , wherein a ratio of a sum of thicknesses of the second epitaxial layer and the cap layer in a direction perpendicular to the horizontal direction to a thickness of a sidewall of the spacer in the horizontal direction is 1 to 2. 9 . 9 . The semiconductor device as claimed in claim 7 , wherein a thickness of a sidewall of the spacer in the horizontal direction is 150 angstroms to 200 angstroms. 10 . The semiconductor device as claimed in claim 1 , wherein a material of the second epitaxial layer comprises silicon germanium, and a crystal plane of the surface of the second epitaxial layer is (311).

11. A method for manufacturing a semiconductor device, comprising: forming a gate structure on the substrate; forming two grooves in the substrate at two sides of the gate structure; forming a first epitaxial layer in the two grooves; forming a second epitaxial layer on the first epitaxial layer, wherein an angle between a surface of the second epitaxial layer and a horizontal direction is 15 degrees to 35 degrees; and A cap layer is formed on the second epitaxial layer. 12 . The method according to claim 11 , wherein an angle between the surface of the cover layer and the horizontal direction is 0 degrees to 5 degrees.

13. The method of claim 11, wherein forming the second epitaxial layer and forming the cap layer comprises introducing an etching gas and a deposition material gas, and when forming the second epitaxial layer, the molar ratio of the etching gas to the deposition material gas is greater than when forming the cap layer. 14 . The method of claim 13 , wherein a molar ratio of the etching gas to the deposition material gas is 1 to 2 when forming the second epitaxial layer. 15 . The method of claim 13 , wherein a molar ratio of the etching gas to the deposition material gas is 0.45 to 0.55 when forming the cap layer. 16 . The method of claim 11 , wherein a thickness of the second epitaxial layer in a direction perpendicular to the horizontal direction is 30 angstroms to 150 angstroms. 17 . The method according to claim 11 , wherein a thickness of the cap layer in a direction perpendicular to the horizontal direction is 100 angstroms to 200 angstroms.

18. The method of claim 11, further comprising: A spacer is formed to surround the gate structure. 19 . The method according to claim 18 , wherein a ratio of a sum of thicknesses of the second epitaxial layer and the cap layer in a direction perpendicular to the horizontal direction to a thickness of a sidewall of the spacer in the horizontal direction is 1 to 2. 20 . The method of claim 18 , wherein a thickness of a sidewall of the spacer in the horizontal direction is 150 angstroms to 200 angstroms.

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