Chip testing method and device, computer equipment and storage medium

Abstract

The invention relates to a chip testing method and device, computer equipment, a storage medium and a computer program product. The method comprises the following steps: receiving a test scene selection instruction, and analyzing the test scene selection instruction to obtain a target test scene selected by a tester; matching the target test scene with test scenes corresponding to a plurality of pre-stored chip netlists, wherein each pre-stored chip netlist is obtained by cutting a chip total netlist based on a test requirement of the corresponding test scene; taking a chip netlist corresponding to the successfully matched test scene as a target chip netlist matched with the target test scene; and testing in the target test scene based on the target chip netlist. The occupation amount of resources in the running process of the chip testing platform is reduced, and the testing time is shortened.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a chip testing method, apparatus, computer equipment, storage medium and computer program product. Background Art

[0002] The chip test platform includes an initialization component, a data generator, a chip netlist and a data collector. During the test process, all the codes of the chip test platform are first compiled to obtain an executable file, and then the executable file is executed. In this way, the chip test platform starts to run, the initialization component initializes the chip netlist, the data generator inputs data to the chip netlist, and the data collector collects output data from the chip netlist. Finally, based on the output data, it is determined whether the various functions of the chip netlist are normal. However, the chip netlist of the chip under test is very large, and the operation of the chip test platform will occupy a lot of processor resources, and the test time is also relatively long. Summary of the invention

[0003] Based on this, it is necessary to provide a chip testing method, apparatus, computer equipment, computer-readable storage medium and computer program product that can shorten the testing time in response to the above technical problems.

[0004] In a first aspect, the present application provides a chip testing method, comprising:

[0005] Receiving a test scenario selection instruction, parsing the test scenario selection instruction to obtain a target test scenario selected by a tester;

[0006] Matching the target test scenario with the test scenarios corresponding to the pre-stored plurality of chip netlists respectively, wherein each pre-stored chip netlist is obtained by reducing the chip total netlist based on the test requirements of the corresponding test scenario;

[0007] The chip netlist corresponding to the successfully matched test scenario is used as the target chip netlist matching the target test scenario; and the test under the target test scenario is performed based on the target chip netlist.

[0008] In a second aspect, the present application also provides a chip testing device, comprising:

[0009] A receiving module, used for receiving a test scenario selection instruction, parsing the test scenario selection instruction to obtain a target test scenario selected by a tester;

[0010] A matching module, used to match the target test scenario with the test scenarios corresponding to the pre-stored multiple chip netlists, each of which is obtained by reducing the chip total netlist based on the test requirements of the corresponding test scenario;

[0011] The test module is used to use the chip netlist corresponding to the successfully matched test scenario as the target chip netlist matching the target test scenario; and perform the test under the target test scenario based on the target chip netlist.

[0012] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0013] Receiving a test scenario selection instruction, parsing the test scenario selection instruction to obtain a target test scenario selected by a tester;

[0014] Matching the target test scenario with the test scenarios corresponding to the pre-stored plurality of chip netlists respectively, wherein each pre-stored chip netlist is obtained by reducing the chip total netlist based on the test requirements of the corresponding test scenario;

[0015] The chip netlist corresponding to the successfully matched test scenario is used as the target chip netlist matching the target test scenario; and the test under the target test scenario is performed based on the target chip netlist.

[0016] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the following steps are implemented:

[0017] Receiving a test scenario selection instruction, parsing the test scenario selection instruction to obtain a target test scenario selected by a tester;

[0018] Matching the target test scenario with the test scenarios corresponding to the pre-stored plurality of chip netlists respectively, wherein each pre-stored chip netlist is obtained by reducing the chip total netlist based on the test requirements of the corresponding test scenario;

[0019] The chip netlist corresponding to the successfully matched test scenario is used as the target chip netlist matching the target test scenario; and the test under the target test scenario is performed based on the target chip netlist.

[0020] In a fifth aspect, the present application further provides a computer program product, including a computer program, which implements the following steps when executed by a processor:

[0021] Receiving a test scenario selection instruction, parsing the test scenario selection instruction to obtain a target test scenario selected by a tester;

[0022] Matching the target test scenario with the test scenarios corresponding to the pre-stored plurality of chip netlists respectively, wherein each pre-stored chip netlist is obtained by reducing the chip total netlist based on the test requirements of the corresponding test scenario;

[0023] The chip netlist corresponding to the successfully matched test scenario is used as the target chip netlist matching the target test scenario; and the test under the target test scenario is performed based on the target chip netlist.

[0024] The above-mentioned chip testing method, device, computer equipment, storage medium and computer program product, after the chip testing platform receives the test scenario selection instruction, it first parses the test scenario selection instruction to obtain the target test scenario selected by the tester; then matches the target test scenario with the test scenarios corresponding to each of the pre-stored multiple chip netlists, wherein each pre-stored chip netlist is obtained by reducing the chip total netlist based on the test requirements of the corresponding test scenario; the chip netlist corresponding to the successfully matched test scenario is used as the target chip netlist that matches the target test scenario; and the test under the target test scenario is performed based on the target chip netlist. This method reduces the scale of the chip netlist, reduces the amount of resources occupied during the operation of the chip testing platform, and shortens the test time. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 A framework diagram of a chip testing platform in one embodiment;

[0027] Figure 2 A schematic diagram of a chip testing method according to an embodiment of the present invention;

[0028] Figure 3 A schematic diagram of a top-level instantiation process of a chip in one embodiment;

[0029] Figure 4 A schematic diagram of the top-level instantiation processing of a module in one embodiment;

[0030] Figure 5 A schematic diagram of a register simulation netlist in one embodiment;

[0031] Figure 6 A schematic diagram of an interconnection simulation netlist in one embodiment;

[0032] Figure 7 A schematic diagram of interface connections of a threaded netlist before deleting a main netlist in one embodiment;

[0033] Figure 8A schematic diagram of a signal connection interface recovery process in one embodiment;

[0034] Fig. 9 is a schematic diagram of a functional scan netlist in one embodiment;

[0035] Fig.10 The flowchart of performing functional scanning simulation on a target functional module in one embodiment is shown. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0037] The chip testing method provided in the embodiment of the present application can be applied to Figure 1 The chip test platform shown. Figure 1 The chip test platform shown includes: an initialization component, a data generator, a chip netlist and a data collector. The initialization component initializes and configures the chip netlist through a register access interface, the data generator inputs data to the chip netlist through a data input interface, and the data collector collects output data of the chip netlist through a data output interface. During the test process, all the codes of the chip test platform are first compiled to obtain an executable file, and then the executable file is executed, so that the chip test platform starts to run. However, the scale of the chip netlist of the chip under test is very large, and the operation of the chip test platform will occupy a lot of processor resources, and the test time is also relatively long.

[0038] To this end, the present application proposes that the tester can input a test scenario selection instruction to the chip test platform. After the chip test platform receives the test scenario selection instruction, it parses the test scenario selection instruction to obtain the target test scenario selected by the tester; then the target test scenario is matched with the test scenarios corresponding to the pre-stored multiple chip netlists, wherein each pre-stored chip netlist is obtained by reducing the total chip netlist based on the test requirements of the corresponding test scenario; the chip netlist corresponding to the successfully matched test scenario is used as the target chip netlist that matches the target test scenario; and the test under the target test scenario is performed based on the target chip netlist. This method reduces the scale of the chip netlist, reduces the amount of resources occupied during the operation of the chip test platform, and shortens the test time. The chip testing method provided by the present application is described in detail below in conjunction with specific embodiments.

[0039] In an exemplary embodiment, Figure 2 As shown, a chip testing method is provided, which is applied to Figure 1The chip testing platform in is taken as an example to illustrate, including the following steps 202 to 206.

[0040] in:

[0041] Step 202: receiving a test scenario selection instruction, parsing the test scenario selection instruction to obtain a target test scenario selected by a tester.

[0042] Among them, the chip testing platform can provide a visual interface, and the tester can trigger the test scenario selection instruction through the visual interface; the tester can also trigger the test scenario selection instruction through the command line of the chip testing platform, which is not limited to this in the embodiments of the present application.

[0043] Among them, the test scenario selection instruction carries the target test scenario selected by the tester, and the chip testing platform can parse the test scenario selection instruction to obtain the target test scenario selected by the tester.

[0044] Step 204 , matching the target test scenario with the test scenarios corresponding to the pre-stored plurality of chip netlists respectively, wherein each pre-stored chip netlist is obtained by reducing the chip total netlist based on the test requirements of the corresponding test scenario.

[0045] Among them, after parsing the target test scenario selected by the tester, the chip test platform can match the target test scenario with the test scenarios corresponding to each of the multiple pre-stored chip netlists.

[0046] Exemplarily, the pre-stored multiple chip netlists may include a register simulation netlist, an interconnection simulation netlist, and a function scan netlist, etc. The test scenario corresponding to the register simulation netlist is register timing simulation, the test scenario corresponding to the interconnection simulation netlist is interconnection function verification, and the test scenario corresponding to the function scan netlist is function scan simulation. The target test scenario may be matched with the three scenarios of register timing simulation, interconnection function verification, and function scan simulation, respectively, to determine a target chip netlist that matches the target test scenario.

[0047] Each pre-stored chip netlist is obtained by trimming the chip netlist based on the test requirements of the corresponding test scenario. For example, the register simulation netlist is obtained by trimming all the main netlists in the chip netlist, the interconnection simulation netlist is obtained by trimming the main netlists in some module netlists in the chip netlist, and the function scan netlist of function module A is obtained by trimming the main netlists in the module netlists corresponding to the other function modules except function module A in the chip netlist.

[0048] Step 206: Use the chip netlist corresponding to the successfully matched test scenario as the target chip netlist that matches the target test scenario; and perform the test under the target test scenario based on the target chip netlist.

[0049] Among them, after the chip testing platform finds a test scenario that successfully matches the target test scenario, it can use the chip netlist corresponding to the successfully matched test scenario as the target chip netlist that matches the target test scenario.

[0050] Exemplarily, assuming that after matching, the target test scenario is register timing simulation, the chip netlist corresponding to the pre-stored "register timing simulation" scenario can be used as the target chip netlist matching the target test scenario; assuming that after matching, the target test scenario is interconnection function verification, the chip netlist corresponding to the pre-stored "interconnection function verification" scenario can be used as the target chip netlist matching the target test scenario; assuming that after matching, the target test scenario is functional scan simulation of functional module A, the chip netlist corresponding to the pre-stored "functional scan simulation of functional module A" scenario can be used as the target chip netlist matching the target test scenario.

[0051] Among them, after determining the target chip netlist that matches the target test scenario, the chip test platform can perform testing under the target test scenario based on the target chip netlist.

[0052] In the above embodiment, after the chip test platform receives the test scenario selection instruction, it first parses the test scenario selection instruction to obtain the target test scenario selected by the tester; then the target test scenario is matched with the test scenarios corresponding to the pre-stored multiple chip netlists, wherein each pre-stored chip netlist is obtained by reducing the chip total netlist based on the test requirements of the corresponding test scenario; the chip netlist corresponding to the successfully matched test scenario is used as the target chip netlist that matches the target test scenario; and the test under the target test scenario is performed based on the target chip netlist. This method reduces the size of the chip netlist, reduces the amount of resources occupied during the operation of the chip test platform, and shortens the test time.

[0053] In some embodiments, the chip total netlist can be obtained in the following manner: based on the functional modules and registers included in the chip original netlist, the chip original netlist is instantiated at the top level of the chip to obtain the module netlist corresponding to each functional module and the first register netlist corresponding to the register; for each functional module, based on the main functional logic, register logic and threading logic in the module netlist corresponding to the current functional module, the module netlist corresponding to the current functional module is instantiated at the top level of the module to obtain the main netlist corresponding to the main functional logic, the second register netlist corresponding to the register logic and the threading netlist corresponding to the threading logic; the netlist obtained after the module top-level instantiation is used as the chip total netlist.

[0054] Among them, the chip original netlist contains multiple functional modules and registers. Based on the functional modules and registers contained in the chip original netlist, the chip original netlist can be instantiated at the top level of the chip to obtain the chip top-level netlist. The chip top-level netlist contains the module netlist corresponding to each functional module and the register netlist corresponding to the above-mentioned registers. For the convenience of distinction, in the embodiment of the present application, the register netlist obtained by the chip top-level instantiation processing is referred to as the first register netlist.

[0055] For example, see Figure 3 As shown, the original chip netlist contains n functional modules, namely module 1, module 2, ..., module n. The original chip netlist can be processed into a chip top-level instantiation to obtain a chip top-level netlist. The chip top-level netlist contains module netlist 1 corresponding to module 1, module netlist 2 corresponding to module 2, ..., module netlist n corresponding to module n, and the first register netlist.

[0056] Among them, the module netlist corresponding to each functional module includes the main functional logic, register logic and threading logic. For each functional module, the module netlist corresponding to the current functional module can be instantiated at the top level of the module based on the main functional logic, register logic and threading logic in the module netlist corresponding to the current functional module to obtain the main netlist corresponding to the main functional logic, the register netlist corresponding to the register logic and the threading netlist corresponding to the threading logic. For the convenience of distinction, in the embodiment of the present application, the register netlist obtained by the module top-level instantiation is referred to as the second register netlist. The above processing is performed on the module netlist corresponding to each functional module to obtain the total netlist of the chip.

[0057] Optionally, after obtaining the main netlist in each module netlist, the main netlist in each module netlist may be further split to obtain the threading netlist contained in each main netlist.

[0058] For example, see Figure 4 As shown, combined Figure 3 In the example, after obtaining module netlist 1 corresponding to module 1, module netlist 2 corresponding to module 2, ..., module netlist n corresponding to module n, and the first register netlist, for module netlist 1, based on the main function logic, register logic, and threading logic in module netlist 1, the module netlist 1 is instantiated at the top level of the module to obtain the main netlist corresponding to the above main function logic, the second register netlist corresponding to the above register logic, and the threading netlist corresponding to the above threading logic. The main netlist corresponding to the above main function logic is split to obtain the threading netlist contained in the main netlist corresponding to the above main function logic. The above processing is performed on module netlist 2, module netlist 3, ..., and module netlist n to obtain the total netlist of the chip.

[0059] In the above embodiment, a specific method for obtaining a chip total netlist is provided. First, based on the functional modules and registers included in the chip original netlist, the chip original netlist is instantiated at the top level of the chip; further, based on the main functional logic, register logic and threading logic in the module netlist corresponding to each functional module, the module netlist corresponding to each functional module is instantiated at the top level of the module to obtain the chip total netlist. Based on the test requirements of different test scenarios, the chip total netlist can be tailored to obtain chip netlists corresponding to different test scenarios. Based on the tailored chip netlist, tests are performed under corresponding test scenarios, thereby reducing the size of the netlist, reducing the resource occupancy during the operation of the chip test platform, and shortening the test time.

[0060] In some embodiments, the pre-stored multiple chip netlists include: a register simulation netlist, the test scenario corresponding to the register simulation netlist is a register timing simulation, and the register simulation netlist can be obtained by trimming the chip total netlist in the following way: deleting the main netlist in each module netlist in the chip total netlist to obtain the register simulation netlist.

[0061] Among them, the register netlists instantiated at each level of the chip are connected, that is, the first register netlist instantiated at the top level of the chip and the second register netlists in each module netlist instantiated at the top level of the module are connected. These register netlists together constitute the register network of the chip. The first register netlist is connected to the register access interface. Considering that the access to the register network is not blocked by the main netlist, therefore, see Figure 5 As shown in the figure, the main netlist in each module netlist in the chip total netlist can be deleted, and the obtained netlist can be used as a register simulation netlist to complete the test in the scenario of register timing simulation. Since the scale of all main netlists accounts for a large proportion of the scale of the chip total netlist, deleting all main netlists can greatly reduce the scale of the chip total netlist, reduce the resource usage during the operation of the chip test platform, and shorten the test time.

[0062] In the above embodiment, considering that the access to the register network is not blocked by the main netlist, the main netlist in each module netlist in the chip total netlist is deleted, and the obtained netlist is used as the register simulation netlist to complete the test in the scenario of register timing simulation. The register simulation netlist obtained in this way is very small in size, which reduces the resource usage of the chip test platform during the operation of the register timing simulation scenario and shortens the test time.

[0063] In some embodiments, the pre-stored multiple chip netlists include: an interconnection simulation netlist, the test scenario corresponding to the interconnection simulation netlist is interconnection function verification, and the interconnection simulation netlist can be obtained by trimming the chip total netlist in the following manner: deleting the main netlist in the module netlist between the two module netlists to be verified in the chip total netlist, and adding the threading netlists contained in the deleted main netlists, restoring the signal connection interfaces of the added threading netlists, and using the netlist obtained after the restoration as the interconnection simulation netlist.

[0064] Among them, considering that when verifying the interconnection function of two module netlists, the main netlist in the module netlist between the two module netlists has no effect on the interconnection function of the two module netlists, the main netlist in the module netlist between the two module netlists to be verified can be deleted.

[0065] However, after deleting the main netlist in the module netlist between the two module netlists to be verified, the threading netlist in the main netlist is also deleted, and the threading netlist in the main netlist needs to be restored. Specifically, the threading netlist included in each deleted main netlist can be added, and the signal connection interface of each added threading netlist can be restored. Among them, the signal connection interface includes an input signal interface, an output signal interface, a clock interface, and a reset interface. The netlist obtained after the restoration process can be used as an interconnection simulation netlist.

[0066] For example, see Figure 6 As shown, assuming that the original netlist of the chip contains four functional modules, namely module 1, module 2, module 3, and module 4, the two module netlists to be verified are module netlist 1 corresponding to module 1 and module netlist 4 corresponding to module 4. The main netlist in module netlist 2 and the main netlist in module netlist 3 can be deleted, and the threading netlist in the deleted main netlist can be added back. The signal connection interfaces of the two added threading netlists are restored, and the interconnection simulation netlist for interconnection function verification of module 1 and module 4 can be obtained. Module netlist 1 is connected to the data input interface, and module netlist 4 is connected to the data output interface.

[0067] For example, when restoring the signal connection interface of each added threading netlist, taking the module netlist 3 in the above example as an example, refer to Figure 7 As shown, the threading netlist in the module netlist 3, the main netlist and the threading netlist in the main netlist all have their own clock signal interface and reset signal interface, and the module netlist 3 has its own input signal interface and output signal interface. Specifically, the threading netlist in the main netlist is connected to the clock interface of clock 1, connected to the reset interface of reset 1, and also connected to the output signal interface, and the threading netlist in the module netlist 3 is connected to the input signal interface, see Figure 8As shown, after deleting the main netlist in module netlist 3, it is necessary to add back the threading netlist in the deleted main netlist, and connect the added threading netlist to clock 1, reset 1 and output signal interface.

[0068] In the above embodiment, considering that when the interconnection function verification is performed on two module netlists, the main netlist in the module netlist between the two module netlists has no effect on the interconnection function of the two module netlists, the main netlist in the module netlist between the two module netlists to be verified can be deleted, and the obtained netlist is used as the interconnection simulation netlist to complete the test in the interconnection function verification scenario. The interconnection simulation netlist obtained in this way is very small in scale, which reduces the resource occupation during the operation of the chip test platform in the interconnection function verification scenario and shortens the test time.

[0069] In some embodiments, the pre-stored multiple chip netlists include: functional scan netlists of different functional modules, and the functional scan netlists of different functional modules can be obtained by trimming the chip total netlist in the following manner: deleting the main netlists in the remaining module netlists except the target module netlist in the chip total netlist, and obtaining the functional scan netlist of the functional module corresponding to the target module netlist, wherein the target module netlist is any module netlist in the chip total netlist.

[0070] Among them, considering that when the module netlist corresponding to a certain functional module is subjected to functional scanning simulation, the main netlist in the module netlists corresponding to the other functional modules has no influence on the simulation process, therefore, in the chip total netlist, the main netlist in the module netlists other than the module netlist corresponding to the functional module can be deleted, and the obtained netlist is used as the functional scanning netlist of the functional module.

[0071] For example, see Fig. 9 As shown, the original chip netlist contains n functional modules, namely module 1, module 2, ..., module n. The original chip netlist can be processed by chip top-level instantiation to obtain the chip top-level netlist. The chip top-level netlist contains the module netlist corresponding to module 1, the module netlist corresponding to module 2, ..., the module netlist corresponding to module n. Assuming that the module netlist corresponding to module 1 is the target module netlist, the main netlist in the module netlist corresponding to module 2, the main netlist in the module netlist corresponding to module 3, ..., the main netlist in the module netlist corresponding to module n can be deleted to obtain the functional scan netlist of module 1. Each module netlist also includes a debug interface netlist. Each debug interface netlist is connected to the debug controller, and the debug controller is connected to the debug interface.

[0072] In the above embodiment, considering that when a module netlist corresponding to a certain functional module is subjected to functional scanning simulation, the main netlist in the module netlist corresponding to the other functional modules has no effect on the simulation process, the main netlist in the module netlists other than the module netlist corresponding to the functional module in the chip total netlist can be deleted, and the obtained netlist is used as the functional scanning netlist of the functional module for functional scanning simulation of the functional module. The functional scanning netlist obtained in this way is very small in scale, which reduces the occupation of resources during the operation of the chip test platform in the scenario of functional scanning simulation and shortens the test time.

[0073] In some embodiments, when the target test scenario is register timing simulation, the test in the scenario of register timing simulation can be performed in the following manner: the data to be written in the test case is transmitted to the second register netlist in each module netlist through the register access interface, the first register netlist and the threading netlist in each module netlist in turn, so as to instruct the second register netlist in each module netlist to write the received data to be written into the corresponding register; through the second register netlist in each module netlist, the written data in the corresponding register is read, and the written data is returned through the first register netlist and the register access interface in turn, and based on the data to be written and the written data, it is determined whether the first register netlist and each second register netlist are normal.

[0074] When the chip test platform determines that the target test scenario is register timing simulation, it can obtain test cases in the scenario of register timing simulation and combine them with Figure 5 The register simulation netlist shown transmits the data to be written in the test case to the second register netlist in each module netlist through the register access interface, the first register netlist and the threading netlist in each module netlist in turn, so as to instruct the second register netlist in each module netlist to write the received data to be written into the corresponding register.

[0075] After writing is completed, the written data in the corresponding register is read through the second register netlist in each module netlist, and the written data is returned in sequence through the first register netlist and the register access interface. After obtaining the written data, if the data to be written and the written data returned by each second register netlist are the same, then the register network is determined to be normal. If the data to be written and the written data returned by a second register netlist are inconsistent, then the register network is determined to be abnormal.

[0076] In the above embodiment, when the target test scenario is register timing simulation, the test in the register timing simulation scenario is performed based on the register simulation netlist. The register simulation netlist is obtained by trimming the total chip netlist based on the test requirements of the register timing simulation scenario. The netlist size is small, which reduces the resource occupancy of the chip test platform during the operation of the register timing simulation test scenario and shortens the test time.

[0077] In some embodiments, when the target test scenario is interconnection function verification, the test in this scenario can be performed in the following manner: through a data generator, input data in the test case is input into the first module netlist of the two module netlists to be verified, and the first main netlist in the first module netlist performs logic processing corresponding to the first main netlist on the input data, and the processing result is transmitted to the second module netlist in the two module netlists to be verified through a threading netlist in the module netlist between the two module netlists to be verified, and the second main netlist in the second module netlist performs logic processing corresponding to the second main netlist on the processing result; the processing result of the second main netlist is collected by a data collector, and based on the input data, it is determined whether the two module netlists to be verified are interconnected normally.

[0078] Among them, when the chip test platform determines that the target test scenario is the interconnection function verification, it can obtain the test case under the interconnection function verification scenario, and transmit the input data in the test case to the data generator. The data generator inputs the input data in the test case to the first module netlist in the two module netlists to be verified. The first module netlist performs logic processing corresponding to the first main netlist on the input data based on the received input data through the first main netlist in the first module netlist to obtain a first processing result. The first processing result is transmitted to the second module netlist in the two module netlists to be verified through the threading netlist in the module netlist between the two module netlists to be verified. The second module netlist performs logic processing corresponding to the second main netlist on the processing result based on the received first processing result through the second main netlist in the second module netlist to obtain a second processing result. The second processing result is compared with the reference processing result in the test case. When the two are consistent, it is determined that the interconnection between the two module netlists to be verified is normal. If they are inconsistent, it is determined that the interconnection between the two module netlists to be verified is abnormal.

[0079] In the above embodiment, when the target test scenario is interconnection function verification, the test in this scenario is performed based on the interconnection simulation netlist. The interconnection simulation netlist is obtained by reducing the total chip netlist based on the test requirements of the interconnection function verification scenario. The netlist size is small, which reduces the resource occupancy of the chip test platform during the operation of the interconnection function verification test scenario and shortens the test time.

[0080] In some embodiments, when the target test scenario is a functional scan simulation of a target functional module, the test in this scenario of functional scan simulation of the target functional module can be performed in the following manner: the input data in the test case is transmitted to the main netlist in the module netlist corresponding to the target functional module through the debug interface, the debug controller, and the debug interface netlist in the module netlist corresponding to the target functional module in sequence, so as to instruct the main netlist in the module netlist corresponding to the target functional module to process the input data to obtain a processing result; the processing result is returned through the debug interface netlist, the debug controller, and the debug interface in sequence, and based on the input data, the processing result and the test case, it is determined whether the connection between the debug controller and the debug interface netlist is normal.

[0081] Among them, when the chip testing platform determines that the target test scenario is the functional scan simulation of the target functional module, it can obtain the test case under the scenario of the functional scan simulation of the target functional module, and transmit the input data in the test case to the main netlist in the module netlist corresponding to the target functional module through the debug interface, the debug controller, and the debug interface netlist in the module netlist corresponding to the target functional module in sequence. The main netlist processes the input data to obtain a third processing result, and returns the third processing result through the debug interface netlist, the debug controller, and the debug interface in sequence. The third processing result is compared with the reference processing result in the test case. When the two are consistent, it is determined that the connection between the debug controller and the debug interface netlist is normal. If they are inconsistent, it is determined that the connection between the debug controller and the debug interface netlist is abnormal.

[0082] See also Fig.10 As shown, when the chip testing platform receives the test scenario selection instruction and determines that the target test scenario selected by the tester is the functional scan simulation of the target functional module, it first initializes the functional scan through the debug interface and the debug controller, and then selects the functional scan path according to the target functional module, and starts the functional scan based on the selected path. During the scanning process, the debug interface netlist in the module netlist corresponding to the target functional module is used to obtain the third processing result. After obtaining the third processing result, it can be determined that the functional scan simulation of the target functional module is completed.

[0083] In the above embodiment, when the target test scenario is the functional scan simulation of the target functional module, the test in this scenario of the functional scan simulation of the target functional module is performed based on the functional scan netlist corresponding to the target functional module. The functional scan netlist corresponding to the target functional module is obtained by reducing the total chip netlist based on the test requirements of the scenario of the functional scan simulation of the target functional module. The netlist size is small, which reduces the resource occupation of the chip test platform during the operation of the test scenario of the functional scan simulation of the target functional module and shortens the test time.

[0084] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0085] Based on the same inventive concept, the embodiment of the present application also provides a chip testing device for implementing the chip testing method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more chip testing device embodiments provided below can refer to the limitations on the chip testing method above, and will not be repeated here.

[0086] In an exemplary embodiment, a chip testing device is provided, comprising:

[0087] A receiving module, used for receiving a test scenario selection instruction, parsing the test scenario selection instruction to obtain a target test scenario selected by a tester;

[0088] A matching module, used to match the target test scenario with the test scenarios corresponding to the pre-stored multiple chip netlists, each of which is obtained by reducing the chip total netlist based on the test requirements of the corresponding test scenario;

[0089] The test module is used to use the chip netlist corresponding to the successfully matched test scenario as the target chip netlist matching the target test scenario; and perform the test under the target test scenario based on the target chip netlist.

[0090] In some embodiments, the chip testing device also includes a top-level instantiation module, which is used to perform top-level instantiation processing on the chip original netlist based on the functional modules and registers contained in the chip original netlist, so as to obtain the module netlist corresponding to each functional module and the first register netlist corresponding to the register; for each functional module, based on the main functional logic, register logic and threading logic in the module netlist corresponding to the current functional module, the module netlist corresponding to the current functional module is instantiated at the top-level to obtain the main netlist corresponding to the main functional logic, the second register netlist corresponding to the register logic and the threading netlist corresponding to the threading logic; the netlist obtained after the top-level instantiation processing of the module is used as the total netlist of the chip.

[0091] In some embodiments, the multiple chip netlists include: a register simulation netlist, the test scenario corresponding to the register simulation netlist is a register timing simulation, and the chip testing device also includes a trimming module for deleting the main netlist in each module netlist in the chip total netlist to obtain a register simulation netlist.

[0092] In some embodiments, the multiple chip netlists include: an interconnection simulation netlist, the test scenario corresponding to the interconnection simulation netlist is interconnection function verification, and a trimming module is also used to delete the main netlist in the module netlist between the two module netlists to be verified in the chip total netlist, and add the threading netlists contained in the deleted main netlists, restore the signal connection interfaces of the added threading netlists, and use the netlist obtained after the restoration as the interconnection simulation netlist.

[0093] In some embodiments, the multiple chip netlists include: functional scanning netlists of different functional modules, and a trimming module, which is also used to delete the main netlists in the remaining module netlists except the target module netlist in the chip total netlist to obtain the functional scanning netlist of the functional module corresponding to the target module netlist, and the target module netlist is any module netlist in the chip total netlist.

[0094] In some embodiments, the target test scenario is a register timing simulation, and the test module is specifically used to: transmit the data to be written in the test case to the second register netlist in each module netlist through the register access interface, the first register netlist, and the threading netlist in each module netlist, so as to instruct the second register netlist in each module netlist to write the received data to be written into the corresponding register; read the written data in the corresponding register through the second register netlist in each module netlist, return the written data through the first register netlist and the register access interface, and determine whether the first register netlist and each second register netlist are normal based on the data to be written and the written data.

[0095] In some embodiments, the target test scenario is interconnection function verification, and the test module is specifically used to: input the input data in the test case to the first module netlist of the two module netlists to be verified through a data generator, perform logic processing corresponding to the first main netlist on the input data through the first main netlist in the first module netlist, transmit the processing result to the second module netlist in the two module netlists to be verified through the threading netlist in the module netlist between the two module netlists to be verified, and perform logic processing corresponding to the second main netlist on the processing result through the second main netlist in the second module netlist; collect the processing result of the second main netlist through a data collector, and determine whether the two module netlists to be verified are interconnected normally based on the processing result of the second main netlist and the test case.

[0096] In some embodiments, the target test scenario is a functional scan simulation of a target functional module, and the test module is specifically used to: transmit the input data in the test case to the main netlist in the module netlist corresponding to the target functional module through the debug interface, the debug controller, and the debug interface netlist in the module netlist corresponding to the target functional module, so as to instruct the main netlist in the module netlist corresponding to the target functional module to process the input data to obtain a processing result; return the processing result through the debug interface netlist, the debug controller, and the debug interface, and determine whether the connection between the debug controller and the debug interface netlist is normal based on the processing result and the test case.

[0097] Each module in the above chip testing device can be implemented in whole or in part by software, hardware or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0098] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0099] Receiving a test scenario selection instruction, parsing the test scenario selection instruction to obtain a target test scenario selected by a tester;

[0100] Matching the target test scenario with the test scenarios corresponding to the pre-stored plurality of chip netlists respectively, wherein each pre-stored chip netlist is obtained by reducing the chip total netlist based on the test requirements of the corresponding test scenario;

[0101] The chip netlist corresponding to the successfully matched test scenario is used as the target chip netlist matching the target test scenario; and the test under the target test scenario is performed based on the target chip netlist.

[0102] In one embodiment, when the processor executes the computer program, the following steps are also implemented: based on the functional modules and registers included in the chip original netlist, the chip original netlist is instantiated at the top level of the chip to obtain the module netlist corresponding to each functional module and the first register netlist corresponding to the register; for each functional module, based on the main functional logic, register logic and threading logic in the module netlist corresponding to the current functional module, the module netlist corresponding to the current functional module is instantiated at the top level of the module to obtain the main netlist corresponding to the main functional logic, the second register netlist corresponding to the register logic and the threading netlist corresponding to the threading logic; the netlist obtained after the module top-level instantiation processing is used as the chip total netlist.

[0103] In one embodiment, the multiple chip netlists include: a register simulation netlist, the test scenario corresponding to the register simulation netlist is a register timing simulation, and the processor also implements the following steps when executing the computer program: deleting the main netlist in each module netlist in the chip total netlist to obtain a register simulation netlist.

[0104] In one embodiment, the multiple chip netlists include: an interconnection simulation netlist, the test scenario corresponding to the interconnection simulation netlist is interconnection function verification, and the processor also implements the following steps when executing the computer program: deleting the main netlist in the module netlist between the two module netlists to be verified in the chip total netlist, and adding the threading netlists contained in the deleted main netlists, restoring the signal connection interfaces of the added threading netlists, and using the netlist obtained after the restoration as the interconnection simulation netlist.

[0105] In one embodiment, the multiple chip netlists include: functional scan netlists of different functional modules. When the processor executes the computer program, the following steps are also implemented: the main netlists in the remaining module netlists except the target module netlist in the chip total netlist are deleted to obtain the functional scan netlist of the functional module corresponding to the target module netlist, and the target module netlist is any module netlist in the chip total netlist.

[0106] In one embodiment, the target test scenario is register timing simulation, and the processor also implements the following steps when executing the computer program: the data to be written in the test case is transmitted to the second register netlist in each module netlist through the register access interface, the first register netlist and the threading netlist in each module netlist in turn, so as to instruct the second register netlist in each module netlist to write the received data to be written into the corresponding register; the written data in the corresponding register is read through the second register netlist in each module netlist, and the written data is returned through the first register netlist and the register access interface in turn, and based on the data to be written and the written data, it is determined whether the first register netlist and each second register netlist are normal.

[0107] In one embodiment, the target test scenario is interconnection function verification, and the processor also implements the following steps when executing the computer program: through a data generator, input data in the test case is input to the first module netlist of the two module netlists to be verified, and the first main netlist in the first module netlist performs logic processing corresponding to the first main netlist on the input data, and transmits the processing result to the second module netlist in the two module netlists to be verified through a threading netlist in the module netlist between the two module netlists to be verified, and performs logic processing corresponding to the second main netlist on the processing result through the second main netlist in the second module netlist; the processing result of the second main netlist is collected through a data collector, and based on the processing result of the second main netlist and the test case, it is determined whether the two module netlists to be verified are interconnected normally.

[0108] In one embodiment, the target test scenario is a functional scan simulation of a target functional module, and the processor further implements the following steps when executing a computer program: the input data in the test case is transmitted to the main netlist in the module netlist corresponding to the target functional module through the debug interface, the debug controller, and the debug interface netlist in the module netlist corresponding to the target functional module in sequence, so as to instruct the main netlist in the module netlist corresponding to the target functional module to process the input data to obtain a processing result; the processing result is returned through the debug interface netlist, the debug controller, and the debug interface in sequence, and based on the processing result and the test case, it is determined whether the connection between the debug controller and the debug interface netlist is normal.

[0109] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0110] Receiving a test scenario selection instruction, parsing the test scenario selection instruction to obtain a target test scenario selected by a tester;

[0111] Matching the target test scenario with the test scenarios corresponding to the pre-stored plurality of chip netlists respectively, wherein each pre-stored chip netlist is obtained by reducing the chip total netlist based on the test requirements of the corresponding test scenario;

[0112] The chip netlist corresponding to the successfully matched test scenario is used as the target chip netlist matching the target test scenario; and the test under the target test scenario is performed based on the target chip netlist.

[0113] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: based on the functional modules and registers contained in the chip original netlist, the chip original netlist is instantiated at the top level of the chip to obtain the module netlist corresponding to each functional module and the first register netlist corresponding to the register; for each functional module, based on the main functional logic, register logic and threading logic in the module netlist corresponding to the current functional module, the module netlist corresponding to the current functional module is instantiated at the top level of the module to obtain the main netlist corresponding to the main functional logic, the second register netlist corresponding to the register logic and the threading netlist corresponding to the threading logic; the netlist obtained after the module top-level instantiation is used as the chip total netlist.

[0114] In one embodiment, the multiple chip netlists include: a register simulation netlist, the test scenario corresponding to the register simulation netlist is a register timing simulation, and when the computer program is executed by the processor, the following steps are also implemented: the main netlist in each module netlist in the chip total netlist is deleted to obtain a register simulation netlist.

[0115] In one embodiment, the multiple chip netlists include: an interconnection simulation netlist, the test scenario corresponding to the interconnection simulation netlist is interconnection function verification, and the computer program also implements the following steps when executed by the processor: deleting the main netlist in the module netlist between the two module netlists to be verified in the chip total netlist, and adding the threading netlists contained in the deleted main netlists, restoring the signal connection interfaces of the added threading netlists, and using the netlist obtained after the restoration as the interconnection simulation netlist.

[0116] In one embodiment, the multiple chip netlists include: functional scan netlists of different functional modules. When the computer program is executed by the processor, the following steps are also implemented: the main netlists in the remaining module netlists except the target module netlist in the chip total netlist are deleted to obtain the functional scan netlist of the functional module corresponding to the target module netlist, and the target module netlist is any module netlist in the chip total netlist.

[0117] In one embodiment, the target test scenario is register timing simulation, and the computer program also implements the following steps when executed by the processor: the data to be written in the test case is transmitted to the second register netlist in each module netlist through the register access interface, the first register netlist and the threading netlist in each module netlist, so as to instruct the second register netlist in each module netlist to write the received data to be written into the corresponding register; the written data in the corresponding register is read through the second register netlist in each module netlist, and the written data is returned through the first register netlist and the register access interface, and based on the data to be written and the written data, it is determined whether the first register netlist and each second register netlist are normal.

[0118] In one embodiment, the target test scenario is interconnection function verification, and the computer program also implements the following steps when executed by the processor: through a data generator, input data in the test case is input to the first module netlist of the two module netlists to be verified, and the first main netlist in the first module netlist performs logic processing corresponding to the first main netlist on the input data, and transmits the processing result to the second module netlist in the two module netlists to be verified through a threading netlist in the module netlist between the two module netlists to be verified, and performs logic processing corresponding to the second main netlist on the processing result through the second main netlist in the second module netlist; the processing result of the second main netlist is collected through a data collector, and based on the processing result of the second main netlist and the test case, it is determined whether the two module netlists to be verified are interconnected normally.

[0119] In one embodiment, the target test scenario is a functional scan simulation of a target functional module, and the following steps are also implemented when the computer program is executed by a processor: the input data in the test case is transmitted to the main netlist in the module netlist corresponding to the target functional module through the debug interface, the debug controller, and the debug interface netlist in the module netlist corresponding to the target functional module in sequence, so as to instruct the main netlist in the module netlist corresponding to the target functional module to process the input data to obtain a processing result; the processing result is returned through the debug interface netlist, the debug controller, and the debug interface in sequence, and based on the processing result and the test case, it is determined whether the connection between the debug controller and the debug interface netlist is normal.

[0120] In one embodiment, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the following steps:

[0121] Receiving a test scenario selection instruction, parsing the test scenario selection instruction to obtain a target test scenario selected by a tester;

[0122] Matching the target test scenario with the test scenarios corresponding to the pre-stored plurality of chip netlists respectively, wherein each pre-stored chip netlist is obtained by reducing the chip total netlist based on the test requirements of the corresponding test scenario;

[0123] The chip netlist corresponding to the successfully matched test scenario is used as the target chip netlist matching the target test scenario; and the test under the target test scenario is performed based on the target chip netlist.

[0124] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: based on the functional modules and registers contained in the chip original netlist, the chip original netlist is instantiated at the top level of the chip to obtain the module netlist corresponding to each functional module and the first register netlist corresponding to the register; for each functional module, based on the main functional logic, register logic and threading logic in the module netlist corresponding to the current functional module, the module netlist corresponding to the current functional module is instantiated at the top level of the module to obtain the main netlist corresponding to the main functional logic, the second register netlist corresponding to the register logic and the threading netlist corresponding to the threading logic; the netlist obtained after the module top-level instantiation is used as the chip total netlist.

[0125] In one embodiment, the multiple chip netlists include: a register simulation netlist, the test scenario corresponding to the register simulation netlist is a register timing simulation, and when the computer program is executed by the processor, the following steps are also implemented: the main netlist in each module netlist in the chip total netlist is deleted to obtain a register simulation netlist.

[0126] In one embodiment, the multiple chip netlists include: an interconnection simulation netlist, the test scenario corresponding to the interconnection simulation netlist is interconnection function verification, and the computer program also implements the following steps when executed by the processor: deleting the main netlist in the module netlist between the two module netlists to be verified in the chip total netlist, and adding the threading netlists contained in the deleted main netlists, restoring the signal connection interfaces of the added threading netlists, and using the netlist obtained after the restoration as the interconnection simulation netlist.

[0127] In one embodiment, the multiple chip netlists include: functional scan netlists of different functional modules. When the computer program is executed by the processor, the following steps are also implemented: the main netlists in the remaining module netlists except the target module netlist in the chip total netlist are deleted to obtain the functional scan netlist of the functional module corresponding to the target module netlist, and the target module netlist is any module netlist in the chip total netlist.

[0128] In one embodiment, the target test scenario is register timing simulation, and the computer program also implements the following steps when executed by the processor: the data to be written in the test case is transmitted to the second register netlist in each module netlist through the register access interface, the first register netlist and the threading netlist in each module netlist, so as to instruct the second register netlist in each module netlist to write the received data to be written into the corresponding register; the written data in the corresponding register is read through the second register netlist in each module netlist, and the written data is returned through the first register netlist and the register access interface, and based on the data to be written and the written data, it is determined whether the first register netlist and each second register netlist are normal.

[0129] In one embodiment, the target test scenario is interconnection function verification, and the computer program also implements the following steps when executed by the processor: through a data generator, input data in the test case is input to the first module netlist of the two module netlists to be verified, and the first main netlist in the first module netlist performs logic processing corresponding to the first main netlist on the input data, and transmits the processing result to the second module netlist in the two module netlists to be verified through a threading netlist in the module netlist between the two module netlists to be verified, and performs logic processing corresponding to the second main netlist on the processing result through the second main netlist in the second module netlist; the processing result of the second main netlist is collected through a data collector, and based on the processing result of the second main netlist and the test case, it is determined whether the two module netlists to be verified are interconnected normally.

[0130] In one embodiment, the target test scenario is a functional scan simulation of a target functional module, and the following steps are also implemented when the computer program is executed by a processor: the input data in the test case is transmitted to the main netlist in the module netlist corresponding to the target functional module through the debug interface, the debug controller, and the debug interface netlist in the module netlist corresponding to the target functional module in sequence, so as to instruct the main netlist in the module netlist corresponding to the target functional module to process the input data to obtain a processing result; the processing result is returned through the debug interface netlist, the debug controller, and the debug interface in sequence, and based on the processing result and the test case, it is determined whether the connection between the debug controller and the debug interface netlist is normal.

[0131] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0132] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0133] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A chip testing method, characterized in that: The method comprises: Receiving a test scenario selection instruction, parsing the test scenario selection instruction to obtain a target test scenario selected by a tester; Matching the target test scenario with the test scenarios corresponding to the pre-stored plurality of chip netlists respectively, wherein each pre-stored chip netlist is obtained by reducing the chip total netlist based on the test requirements of the corresponding test scenario; The chip netlist corresponding to the successfully matched test scenario is used as the target chip netlist matching the target test scenario; and the test under the target test scenario is performed based on the target chip netlist.

2. The method according to claim 1, characterized in that: The method further comprises: Based on the functional modules and registers included in the original chip netlist, the original chip netlist is instantiated at the top level of the chip to obtain a module netlist corresponding to each functional module and a first register netlist corresponding to the register; For each functional module, based on the main functional logic, register logic and threading logic in the module netlist corresponding to the current functional module, the module netlist corresponding to the current functional module is instantiated at the top level of the module to obtain a main netlist corresponding to the main functional logic, a second register netlist corresponding to the register logic and a threading netlist corresponding to the threading logic; The netlist obtained after instantiation of the top level of the module is used as the overall netlist of the chip.

3. The method according to claim 1, characterized in that The multiple chip netlists include: a register simulation netlist, the test scenario corresponding to the register simulation netlist is a register timing simulation, and the steps of obtaining the register simulation netlist include: The main netlist in each module netlist in the chip overall netlist is deleted to obtain a register simulation netlist.

4. The method according to claim 1, characterized in that: The multiple chip netlists include: an interconnection simulation netlist, the test scenario corresponding to the interconnection simulation netlist is interconnection function verification, and the steps of obtaining the interconnection simulation netlist include: In the chip total netlist, the main netlist in the module netlist between the two module netlists to be verified is deleted, and the threading netlists contained in the deleted main netlists are added, and the signal connection interfaces of the added threading netlists are restored, and the netlist obtained after the restoration is used as the interconnection simulation netlist.

5. The method according to claim 1, characterized in that The multiple chip netlists include: function scan netlists of different functional modules, and the steps of obtaining the function scan netlists include: Delete the main netlists in the remaining module netlists except the target module netlist in the chip total netlist to obtain the function scan netlist of the function module corresponding to the target module netlist, wherein the target module netlist is any module netlist in the chip total netlist.

6. The method according to claim 2, characterized in that The target test scenario is register timing simulation, and the test under the target test scenario is performed based on the target chip netlist, including: The data to be written in the test case is transmitted to the second register netlist in each module netlist through the register access interface, the first register netlist and the threading netlist in each module netlist in sequence, so as to instruct the second register netlist in each module netlist to write the received data to be written into the corresponding register; The written data in the corresponding register is read through the second register netlist in each module netlist, and the written data is returned in sequence through the first register netlist and the register access interface, and based on the data to be written and the written data, it is determined whether the first register netlist and each second register netlist are normal.

7. The method according to claim 1, characterized in that The target test scenario is interconnection function verification, and the test under the target test scenario based on the target chip netlist includes: Inputting input data in the test case to the first module netlist of the two module netlists to be verified through a data generator, performing logic processing corresponding to the first main netlist on the input data through a first main netlist in the first module netlist, transmitting the processing result to the second module netlist of the two module netlists to be verified through a threading netlist in the module netlist between the two module netlists to be verified, and performing logic processing corresponding to the second main netlist on the processing result through a second main netlist in the second module netlist; The processing result of the second main netlist is collected by a data collector, and based on the processing result of the second main netlist and the test case, it is determined whether the two module netlists to be verified are interconnected normally.

8. The method according to claim 1, characterized in that: The target test scenario is a functional scan simulation of a target functional module, and the test under the target test scenario is performed based on the target chip netlist, including: The input data in the test case is transmitted to the main netlist in the module netlist corresponding to the target functional module through the debug interface, the debug controller, and the debug interface netlist in the module netlist corresponding to the target functional module in sequence, so as to instruct the main netlist in the module netlist corresponding to the target functional module to process the input data and obtain a processing result; The processing result is returned in sequence through the debug interface netlist, the debug controller and the debug interface, and based on the processing result and the test case, it is determined whether the debug controller and the debug interface netlist are connected normally.

9. A chip testing device, characterized in that: The device comprises: A receiving module, used for receiving a test scenario selection instruction, parsing the test scenario selection instruction to obtain a target test scenario selected by a tester; A matching module, used to match the target test scenario with the test scenarios corresponding to the pre-stored multiple chip netlists, each of which is obtained by reducing the chip total netlist based on the test requirements of the corresponding test scenario; The test module is used to use the chip netlist corresponding to the successfully matched test scenario as the target chip netlist matching the target test scenario; and perform the test under the target test scenario based on the target chip netlist.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 8 are implemented.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

12. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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