Logic series estimation method and device, electronic equipment and storage medium

Abstract

The invention provides a logic series estimation method and device, electronic equipment and a storage medium, and relates to the technical field of digital circuits. The logic series estimation method comprises the following steps: acquiring a circuit netlist file describing a target logic path; replacing an arithmetic unit described in the circuit netlist file with a corresponding combinational logic unit to obtain an updated netlist file; wherein the combinational logic unit comprises at least two basic logic gate circuits; and determining the logic level of the target logic path based on the updated netlist file. The arithmetic unit is replaced by the corresponding combinational logic unit, so that the specific logic structure in the arithmetic unit can be considered when the logic series is calculated. Therefore, even if different logic paths pass through the arithmetic unit, the logic stages corresponding to the different logic paths can be calculated according to the combinational logic unit corresponding to the arithmetic unit, so that the accuracy of estimating the logic stages is improved.

Description

Technical Field

[0001] The present application relates to the technical field of digital circuits, and in particular to a logic level estimation method, device, electronic device and storage medium. Background Art

[0002] At present, when determining the number of logical levels of a logical path, it is usually necessary to first analyze all the computing units included in the logical path, and then determine the number of logical levels corresponding to each computing unit included in the logical path according to the pre-configured number of logical levels corresponding to each computing unit. Finally, the number of logical levels corresponding to all computing units included in the logical path is summed to obtain the total number of logical levels corresponding to the logical path. However, the results estimated in this way are often quite different from the actual results. Summary of the invention

[0003] The present application provides a logic level estimation method, device, electronic device and storage medium to improve the accuracy of estimating the logic level of a logic path.

[0004] In a first aspect, the present application provides a method for estimating a logic level, comprising: obtaining a circuit netlist file describing a target logic path, wherein the target logic path is a logic path of a logic level to be estimated; in the case where there are operation units in the circuit netlist file, replacing the operation units described in the circuit netlist file with corresponding combinational logic units to obtain an updated netlist file; wherein the combinational logic unit includes at least two levels of basic logic gate circuits; based on the updated netlist file, determining the logic level of the target logic path; wherein the logic level of the target logic path is related to the number of basic logic gate circuits included in the target logic path.

[0005] In the embodiment of the present application, by replacing the operation unit with its corresponding combinational logic unit, the specific logic structure inside the operation unit can be taken into account when calculating the logic level. Therefore, even if different logic paths pass through the operation unit, the logic levels corresponding to the different logic paths can be calculated respectively according to the combinational logic unit corresponding to the operation unit. Rather than directly and generally setting the logic level corresponding to the operation unit to a fixed value as in the prior art, the present solution can more accurately estimate the logic level of the logic path.

[0006] In combination with the technical solution provided in the first aspect above, in some possible implementations, replacing the operation units described in the circuit netlist file with corresponding combinational logic units to obtain an updated netlist file includes: determining all the operation units in the circuit netlist file; obtaining the combinational logic units corresponding to each of the operation units from a preset combinational logic unit library; and replacing each of the operation units with the combinational logic units corresponding to the operation unit to obtain the updated netlist file.

[0007] In an embodiment of the present application, by replacing all the operation units in the circuit netlist file with corresponding combinational logic units, when it is necessary to perform logic level estimation on multiple logic paths in the netlist file to be estimated respectively, there is no need to repeat the replacement process for each logic path included in the circuit netlist file, thereby reducing the amount of calculation.

[0008] In combination with the technical solution provided in the first aspect above, in some possible implementations, replacing the operation units described in the circuit netlist file with the corresponding operation unit netlist file to obtain an updated netlist file includes: determining all the operation units of the target logic path in the circuit netlist file; obtaining the combinational logic unit corresponding to each of the operation units from a preset combinational logic unit library; and replacing each of the operation units in the target logic path with the combinational logic unit corresponding to the operation unit to obtain the updated netlist file.

[0009] In an embodiment of the present application, by replacing all operation units of the target logic path in the circuit netlist file with corresponding combinational logic units, when only logical calculation estimation is required for the target logic path, the replacement operation of irrelevant operation units can be reduced, thereby reducing the workload and improving the estimation efficiency.

[0010] In combination with the technical solution provided in the first aspect above, in some possible implementations, if the combinational logic unit corresponding to the operation unit does not exist in the combinational logic unit library, the method also includes: obtaining the hardware description language file of the operation unit; synthesizing the hardware description language file of the operation unit to obtain the combinational logic unit corresponding to the operation unit; replacing the operation unit in the target logic path with the combinational logic unit corresponding to the operation unit to obtain the updated netlist file.

[0011] In the embodiment of the present application, the corresponding combinational logic unit is obtained through the hardware description language of the operation unit, so that the combinational logic unit corresponding to the operation unit can be obtained simply and conveniently.

[0012] In combination with the technical solution provided in the first aspect above, in some possible implementations, after obtaining the combinational logic unit corresponding to the operation unit based on the hardware description language file of the operation unit, the method also includes: storing the combinational logic unit corresponding to the operation unit in the combinational logic unit library.

[0013] In an embodiment of the present application, by storing the obtained combinational logic units in a combinational logic unit library, it is not necessary to obtain the hardware description language each time in the subsequent process, and the operation of the combinational logic unit corresponding to the operation unit can be obtained based on the hardware description language file, thereby improving the efficiency of obtaining the combinational logic unit corresponding to the operation unit.

[0014] In combination with the technical solution provided in the first aspect above, in some possible implementations, obtaining a circuit netlist file describing a target logic path includes: obtaining an RTL (register transfer level code) code to be estimated and an SDC (Synopsys Design Constraints, a file format for constraining digital circuit design) constraint file describing the target logic path; and compiling the circuit netlist file according to the RTL code and the SDC constraint file.

[0015] In combination with the technical solution provided in the first aspect above, in some possible implementations, determining the logic level of the target logic path based on the updated netlist file includes: judging whether any adjacent multiple basic logic gate circuits included in the multi-level basic logic gate circuits in the target logic path can be merged into one basic logic gate circuit; merging the multiple basic logic gate circuits that can be merged in the updated netlist file into one basic logic gate circuit; wherein the merged multiple basic logic gate circuits and the merged basic logic gate circuit implement the same function; and determining the logic level of the target logic path based on the updated netlist file after merging the multiple basic logic gate circuits.

[0016] In an embodiment of the present application, multiple basic logic gate circuits that can be merged are merged into one basic logic gate circuit, thereby simulating the operation of merging multiple logic gate circuits in the actual circuit design process, so that the estimation result of the logic level performed by this scheme is more in line with the actual situation, thereby improving the accuracy of the estimation result.

[0017] In combination with the technical solution provided in the first aspect above, in some possible implementations, based on the updated netlist file, determining the logic level of the target logic path includes: for the i-th basic logic gate circuit in the target logic path: taking the i-th basic logic gate circuit as the starting point, judging whether N consecutive basic logic gate circuits can be merged into one basic logic gate circuit; if they cannot be merged, reducing the value of N by 1, and judging again whether N consecutive basic logic gate circuits can be merged into one basic logic gate circuit; repeating this step until N consecutive basic logic gate circuits can be merged into one basic logic gate circuit, or the value of N is reduced by 1 and equal to 1; if the first N basic logic gate circuits can be merged into one basic logic gate circuit, If i+1 is less than M, then: the N basic logic gate circuits are merged into one basic logic gate circuit, and then the value of N is initialized. If i+N is less than M, the i+Nth basic logic gate circuit is used as the starting point, and the above judgment step is performed again; if i+N is equal to M, the merging process is terminated; M is the number of all basic logic gate circuits included in the target logic path before the merging operation is performed; if the value of N is equal to 1 after being subtracted by 1, then: the value of N is initialized. If i+1 is less than M, the i+1th basic logic gate circuit is used as the starting point, and the above judgment step is performed again; if i+1 is equal to M, the merging process is terminated; after the merging process is terminated, the logic level of the target logic path is determined based on the target logic path after the merging process is completed.

[0018] In the embodiment of the present application, by judging whether N consecutive basic logic gate circuits can be merged into one basic logic gate circuit, all N basic logic gate circuits that can be merged are merged into one basic logic gate circuit. This simulates the operation of merging multiple logic gate circuits in the actual circuit design process, so that the estimation result of the logic level performed by this solution is more in line with the actual situation, and the accuracy of the estimation result is improved.

[0019] In combination with the technical solution provided in the first aspect above, in some possible implementations, based on the updated netlist file, determining the logic level of the target logic path includes: judging whether the current starting basic logic gate circuit and the two consecutive basic logic gate circuits after the starting basic logic gate circuit can be merged into one basic logic gate circuit; wherein the starting basic logic gate circuit is: the basic logic gate circuit included in the target logic path described in the updated netlist file; if the current starting basic logic gate circuit and the two consecutive basic logic gate circuits after the starting basic logic gate circuit can be merged into one basic logic gate circuit, then: merge the current starting basic logic gate circuit and the two consecutive basic logic gate circuits after the starting basic logic gate circuit into one basic logic gate circuit, and use the third consecutive basic logic gate circuit after the starting basic logic gate circuit as the new starting basic logic gate circuit, and repeat the above operation; if the current starting basic logic gate circuit and the two consecutive basic logic gate circuits after the starting basic logic gate circuit can be merged into one basic logic gate circuit, then: merge the current starting basic logic gate circuit and the two consecutive basic logic gate circuits after the starting basic logic gate circuit into one basic logic gate circuit, and use the third consecutive basic logic gate circuit after the starting basic logic gate circuit as the new starting basic logic gate circuit, and repeat the above operation; If the two basic logic gate circuits cannot be merged into one basic logic gate circuit, then: determine whether the current starting basic logic gate circuit and a basic logic gate circuit that is continuous after the starting basic logic gate circuit can be merged into one basic logic gate circuit; if so, merge the current starting basic logic gate circuit and a basic logic gate circuit that is continuous after the starting basic logic gate circuit into one basic logic gate circuit, and use the second basic logic gate circuit that is continuous after the starting basic logic gate circuit as a new starting basic logic gate circuit, and repeat the above operation; if not, use the next basic logic gate circuit of the current starting basic logic gate circuit as a new starting basic logic gate circuit, and repeat the above operation; when the starting basic logic gate circuit is the last basic logic gate circuit of the target logic path, or the last basic logic gate circuit is merged into a new basic logic gate circuit, end the merging process, and determine the logic level of the target logic path based on the target logic path after the merging process is completed.

[0020] In an embodiment of the present application, by merging three consecutive basic logic gate circuits that can be merged and two consecutive basic logic gate circuits that can be merged into one basic logic gate circuit, the number of input pins of the merged basic logic gate circuit can be made less than or equal to 4, thereby making the merged basic logic gate circuit meet the process requirements and improving the practicality of the present solution.

[0021] In a second aspect, the present application provides a logic level estimation device, comprising: an acquisition module and a processing module. The acquisition module is used to acquire a circuit netlist file describing a target logic path, wherein the target logic path is a logic path of a logic level to be estimated; the processing module is used to replace the operation unit described in the circuit netlist file with a corresponding combinational logic unit when there is an operation unit in the circuit netlist file, so as to obtain an updated netlist file; wherein the combinational logic unit includes at least two levels of basic logic gate circuits; the processing module is also used to determine the logic level of the target logic path based on the updated netlist file; wherein the logic level of the target logic path is related to the number of basic logic gate circuits included in the target logic path.

[0022] In a third aspect, the present application provides an electronic device, comprising: a memory and a processor, the memory and the processor being connected; the memory being used to store programs; and the processor being used to call the programs stored in the memory to execute the method described in the first aspect above and / or in combination with any possible implementation of the first aspect above.

[0023] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a computer, the computer program executes the method described in the first aspect and / or in combination with any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 A schematic flow chart of a first logic level estimation method shown in an embodiment of the present application;

[0026] Figure 2 A schematic diagram of a flow chart of determining the number of logic levels of a target logic path based on an updated netlist file according to an embodiment of the present application;

[0027] Figure 3 A schematic flow chart of a second logic level estimation method shown in an embodiment of the present application;

[0028] Figure 4 A structural block diagram of a logic level estimation device shown in an embodiment of the present application;

[0029] Figure 5A structural block diagram of an electronic device shown in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0031] It should be noted that similar numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it is not necessary to further define and explain it in the subsequent drawings. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0032] The technical solution of the present application will be described in detail below with reference to the accompanying drawings.

[0033] See also Figure 1 , Figure 1 A flow chart of a logic level estimation method provided in this application is shown below. Figure 1 Describe the steps it involves.

[0034] S100: Obtain a circuit netlist file describing a target logic path.

[0035] The target logic path is a logic path of a logic level to be estimated.

[0036] A circuit netlist file that describes a target logic path, that is, the circuit netlist file includes content that describes the target logic path.

[0037] The target logic path is the path from the target input to the target output.

[0038] In one implementation, the circuit netlist file can be acquired in advance and stored in a local storage medium, and can be directly called when needed. Alternatively, the circuit netlist file can be acquired in real time when needed.

[0039] Optionally, the circuit netlist file may be an equivalent netlist, which is also called a process-independent (generic) netlist. It is a circuit netlist file converted by an HDL compiler (hardware description language compiler) from an RTL (Register Transfer Level) code. It is a form of circuit formed by combining process-independent gate-level gates.

[0040] Optionally, the circuit netlist file describing the target logic path may be obtained by: obtaining the RTL code and the SDC constraint file describing the target logic path, and then compiling the circuit netlist file according to the RTL code and the SDC constraint file.

[0041] The specific process of compiling the RTL code and the SDC constraint file into the circuit netlist file is well known to those skilled in the art and will not be described in detail here for the sake of brief description.

[0042] S200: When there are operation units in the circuit netlist file, replace the operation units described in the circuit netlist file with corresponding combinational logic units to obtain an updated netlist file.

[0043] Wherein, the combinational logic unit includes at least two basic logic gate circuits.

[0044] The basic logic gate circuit may be, for example, an AND gate circuit, an OR gate circuit, a NOT gate circuit, a NAND gate circuit, a NOR gate circuit, an XOR gate circuit, or an XNOR gate circuit. The basic logic gate circuit is not limited to the examples given here.

[0045] The operation unit may be, for example, an addition operation unit, a multiplication operation unit, a shift operation unit, etc., which require multiple basic logic gate circuits to implement. The operation unit is not limited to the operation units exemplified here.

[0046] Optionally, the combinational logic unit can reflect the combinational logic inside the operation unit. The combinational logic unit can be, for example, a circuit netlist file, a generic netlist file, etc., which can reflect the data of the combinational logic unit inside the operation unit, that is, describe the connection relationship, input data and output data of each basic logic gate circuit included in the operation unit. The specific data type of the combinational logic unit is not limited here.

[0047] Optionally, the combinational logic unit corresponding to the operation unit can be obtained in advance and directly called when needed. Alternatively, the combinational logic unit corresponding to the operation unit can also be obtained in real time when needed.

[0048] If the combinational logic unit corresponding to the operation unit is obtained in advance, it can be stored in a database or a lookup table. The specific storage method of the combinational logic unit corresponding to the operation unit is not limited to the method exemplified here.

[0049] In one implementation, the specific method of replacing the operation units described in the circuit netlist file with the corresponding combinational logic units to obtain the updated netlist file may be: first, all the operation units in the circuit netlist file are determined. Then, the combinational logic units corresponding to each operation unit are obtained from a preset combinational logic unit library. Finally, each operation unit is replaced with the combinational logic unit corresponding to the operation unit to obtain the updated netlist file.

[0050] By replacing all the operation units in the circuit netlist file with corresponding combinational logic units, when it is necessary to estimate the logic levels of multiple logic paths in the netlist file to be estimated, there is no need to repeat the replacement process for each logic path included in the circuit netlist file, thereby reducing the amount of calculation.

[0051] Optionally, each operation unit is replaced with a combinational logic unit corresponding to the operation unit, that is, the combinational logic unit corresponding to the operation unit is used to replace the operator of the operation unit in the circuit netlist file.

[0052] Optionally, if the operation unit does not exist in the circuit netlist file, this step may be skipped and S300 may be executed.

[0053] In one implementation, the operation unit described in the circuit netlist file is replaced with the corresponding operation unit netlist file, and the updated netlist file is obtained by first determining all the operation units of the target logic path in the circuit netlist file. Then, the combinational logic unit corresponding to each operation unit is obtained from a preset combinational logic unit library. Finally, each operation unit in the target logic path is replaced with the combinational logic unit corresponding to the operation unit to obtain the updated netlist file.

[0054] By replacing all the operation units of the target logic path in the circuit netlist file with corresponding combinational logic units, when only the target logic path needs to be estimated for logical calculation, the replacement operation of irrelevant operation units can be reduced, the workload is reduced, and the estimation efficiency is improved.

[0055] In one implementation, if the combinatorial logic unit corresponding to the operation unit does not exist in the combinatorial logic unit library, the hardware description language file of the operation unit can be obtained. Then the hardware description language file of the operation unit is synthesized to obtain the combinatorial logic unit corresponding to the operation unit. Finally, the operation unit in the target logic path is replaced with the combinatorial logic unit corresponding to the operation unit to obtain an updated netlist file.

[0056] Optionally, based on the hardware description language file of the operation unit, the method of obtaining the combinational logic unit corresponding to the operation unit can be to synthesize the hardware description language file of the operation unit to obtain the circuit netlist file of the operation unit. The circuit netlist file of the operation unit describes the corresponding combinational logic unit.

[0057] Among them, the specific method of synthesizing the hardware description language file to obtain the circuit netlist file is well known to those skilled in the art and will not be repeated here for the sake of brief description.

[0058] Optionally, after obtaining the combinatorial logic unit corresponding to the operation unit based on the hardware description language file of the operation unit, the combinatorial logic unit corresponding to the operation unit can also be stored in a combinatorial logic unit library. By storing the obtained combinatorial logic unit in the combinatorial logic unit library, in the subsequent process, it is not necessary to obtain the hardware description language every time and obtain the operation of the combinatorial logic unit corresponding to the operation unit based on the hardware description language file, thereby improving the efficiency of obtaining the combinatorial logic unit corresponding to the operation unit.

[0059] In one implementation, if the combinational logic unit corresponding to the operation unit does not exist in the combinational logic unit library, the combinational logic unit corresponding to the operation unit can also be obtained from a third-party device. Then, the operation unit in the target logic path is replaced with the combinational logic unit corresponding to the operation unit to obtain an updated netlist file.

[0060] Correspondingly, after the combinational logic unit corresponding to the operation unit is acquired, the combinational logic unit corresponding to the operation unit may also be stored in a combinational logic unit library.

[0061] S300: Determine the number of logic levels of the target logic path based on the updated netlist file.

[0062] The number of logic levels of the target logic path is related to the number of basic logic gate circuits included in the target logic path.

[0063] In one implementation, after obtaining the updated netlist file, the logic level of the target logic path can be directly calculated. That is, the number of basic logic gate circuits between the starting point (target input end) of the target logic path and the end point (target output end) of the target logic path is calculated. The number of basic logic gate circuits that exist is the logic level of the target logic path.

[0064] In one implementation, based on the updated netlist file, the method for determining the number of logic levels of the target logic path can be: first determine whether any adjacent multiple basic logic gate circuits included in the multi-level basic logic gate circuits in the target logic path can be merged into one basic logic gate circuit. Merge the multiple basic logic gate circuits that can be merged into one basic logic gate circuit; wherein the merged multiple basic logic gate circuits and the merged basic logic gate circuit implement the same function. Based on the updated netlist file after merging the multiple basic logic gate circuits, determine the number of logic levels of the target logic path.

[0065] The merged basic logic gate circuit is a basic logic gate circuit that can realize the function of the combined multiple basic logic gate circuits. Compared with the basic logic gate circuit before the merger, the merged basic logic gate circuit has 3 or more input terminals and / or 2 or more output terminals. In addition, when calculating the logic level, the logic level of the merged basic logic gate circuit is also 1.

[0066] For example, when calculating A&B&C ("&" indicates an AND operation), it may be implemented through two AND gate logic circuits, such as first calculating A&B, and then using the output of A&B and C as the input of the second AND gate logic circuit, and performing the AND calculation again to obtain the result of A&B&C. However, A&B&C can also be implemented through a three-input AND gate logic circuit, so the two AND gate logic circuits can be combined into a three-input AND gate logic circuit. The examples here are only for ease of understanding and should not be used as limitations on the present application.

[0067] Optionally, the specific number of basic logic gate circuits for judging whether they can be merged into one basic logic gate circuit can be set according to actual needs. For example, it can be judged whether any two adjacent basic logic gate circuits in the target logic path in the updated netlist file can be merged into one basic logic gate circuit; or it can be judged whether any three adjacent basic logic gate circuits in the target logic path in the updated netlist file can be merged into one basic logic gate circuit. The specific number of basic logic gate circuits for judging whether they can be merged into one basic logic gate circuit is not limited to the example given here.

[0068] Since the logic level corresponding to the merged basic logic gate circuit is also 1, the number of basic logic gate circuits included in the target logic path from the starting point to the end point after the basic logic gate circuits are merged is directly counted, and this number is the logic level of the target logic gate circuit.

[0069] In order to facilitate understanding of the determination of the logic level of the target logic path based on the updated netlist file after merging multiple basic logic gate circuits, the target logic path in the updated netlist file after merging multiple basic logic gate circuits includes a basic logic gate circuit, a basic logic gate circuit, a merged basic logic gate circuit, and a basic logic gate circuit from the starting point to the end point as an example. The logic level corresponding to the target logic path is 4. The examples here are only for ease of understanding and should not be used as a limitation to this application.

[0070] In one implementation, based on the updated netlist file, the specific method of determining the number of logic levels of the target logic path can be as follows: Figure 2 shown.

[0071] like Figure 2 As shown, for the i-th basic logic gate circuit in the target logic path: taking the i-th basic logic gate circuit as the starting point, determine whether N consecutive basic logic gate circuits can be merged into one basic logic gate circuit.

[0072] If the merger is not possible, reduce the value of N by 1, and determine again whether the consecutive N basic logic gate circuits can be merged into one basic logic gate circuit; repeat this step until the consecutive N basic logic gate circuits can be merged into one basic logic gate circuit, or the value of N is reduced by 1 and equal to 1.

[0073] If the first N basic logic gate circuits can be merged into one basic logic gate circuit, then: merge the N basic logic gate circuits into one basic logic gate circuit, and then initialize the value of N. If i+N is less than M, take the i+Nth basic logic gate circuit as the starting point and perform the above judgment steps again. If i+N is equal to M, end the merging process; M is the number of all basic logic gate circuits included in the target logic path.

[0074] If the value of N minus 1 is equal to 1, then: initialize the value of N. If i+1 is less than M, take the i+1th basic logic gate circuit as the starting point and perform the above judgment steps again; if i+1 is equal to M, end the merging process.

[0075] After the merging process is finished, the logic level of the target logic path is determined based on the target logic path after the merging process is completed.

[0076] Initializing N means updating the value of N to the initial value. The merged basic logic gate circuits will not be merged again.

[0077] Optionally, when the i-th basic logic gate circuit is used as the starting point, but the number of consecutive basic logic gate circuits is less than N but greater than 1, the value of N is modified to the number of consecutive basic logic gate circuits.

[0078] Among them, the specific implementation method of merging the N basic logic gate circuits into one basic logic gate circuit is consistent with the method of merging multiple basic logic gate circuits that can be merged into one basic logic gate circuit in the previous text. For the sake of brief description, it will not be repeated here.

[0079] For ease of understanding, an example is given in which the initial value of N is 3 and the initial value of M is 5.

[0080] First, starting from the first basic logic gate circuit of the target logic path, determine whether three consecutive basic logic gate circuits (that is, the first basic logic gate circuit, the second basic logic gate circuit, and the third basic logic gate circuit of the target logic path) can be merged into one basic logic gate circuit.

[0081] If three consecutive basic logic gate circuits cannot be merged, reduce the value of N by 1, and now N=2, and again determine whether two consecutive basic logic gate circuits (i.e., the first basic logic gate circuit and the second basic logic gate circuit of the target logic path) can be merged into one basic logic gate circuit.

[0082] If two consecutive basic logic gate circuits cannot be combined, the value of N is reduced by 1, and N=1 at this time, so the value of N is initialized (N=3). Taking the second basic logic gate circuit as the starting point, the above judgment steps are performed again.

[0083] If the previous three consecutive basic logic gate circuits can be merged into one basic logic gate circuit, then the fourth (i.e. 1+3) basic logic gate circuit of the target logic path (the fourth basic logic gate circuit of the target logic path that has not been merged) is used as the starting point to determine whether the three consecutive basic logic gate circuits (i.e. the fourth basic logic gate circuit, the fifth basic logic gate circuit, and the sixth basic logic gate circuit of the target logic path that has not been merged) can be merged into one basic logic gate circuit. However, since there are only the fourth basic logic gate circuit and the fifth basic logic gate circuit, and there is no sixth basic logic gate circuit, the value of N is modified to 2, that is, the fourth (i.e. 1+3) basic logic gate circuit of the target logic path is used as the starting point to determine whether the three consecutive basic logic gate circuits (i.e. the fourth basic logic gate circuit and the fifth basic logic gate circuit of the target logic path that has not been merged) can be merged into one basic logic gate circuit, and the previous judgment process is repeated.

[0084] The examples given here are only for ease of understanding and should not be construed as limiting the present application.

[0085] In one implementation, based on the updated netlist file, the method of determining the logic level of the target logic path may be: first determine whether the current starting point basic logic gate circuit and two consecutive basic logic gate circuits after the starting point basic logic gate circuit can be merged into one basic logic gate circuit. The starting point basic logic gate circuit is: the basic logic gate circuit included in the target logic path described in the updated netlist file.

[0086] If the current starting basic logic gate circuit and the two consecutive basic logic gate circuits after the starting basic logic gate circuit can be merged into one basic logic gate circuit, then: merge the current starting basic logic gate circuit and the two consecutive basic logic gate circuits after the starting basic logic gate circuit into one basic logic gate circuit, and use the third consecutive basic logic gate circuit after the starting basic logic gate circuit as the new starting basic logic gate circuit, and repeat the above operation.

[0087] If the current starting point basic logic gate circuit and the two consecutive basic logic gate circuits after the starting point basic logic gate circuit cannot be merged into one basic logic gate circuit, then: determine whether the current starting point basic logic gate circuit and a consecutive basic logic gate circuit after the starting point basic logic gate circuit can be merged into one basic logic gate circuit; if so, merge the current starting point basic logic gate circuit and a consecutive basic logic gate circuit after the starting point basic logic gate circuit into one basic logic gate circuit, and use the second consecutive basic logic gate circuit after the starting point basic logic gate circuit as the new starting point basic logic gate circuit, and repeat the above operation; if not, use the next basic logic gate circuit of the current starting point basic logic gate circuit as the new starting point basic logic gate circuit, and repeat the above operation.

[0088] When the starting basic logic gate circuit is the last basic logic gate circuit of the target logic path, or the last basic logic gate circuit is merged into one basic logic gate circuit, the merging process is ended, and the logic level of the target logic path is determined based on the target logic path after the merging process is completed.

[0089] Among them, the specific implementation method of merging the current starting basic logic gate circuit with the two consecutive basic logic gate circuits after the starting basic logic gate circuit into one basic logic gate circuit, and the specific implementation method of merging the current starting basic logic gate circuit with one consecutive basic logic gate circuit after the starting basic logic gate circuit into one basic logic gate circuit are consistent with the previous method of merging multiple basic logic gate circuits that can be merged into one basic logic gate circuit, and for the sake of brief description, they will not be repeated here.

[0090] The merged basic logic gate circuits will not be merged again.

[0091] Optionally, when the starting basic logic gate circuit is the second to last basic logic gate circuit in the target logic path, since there are no longer two consecutive basic logic gate circuits (not two basic logic gate circuits obtained by merging) thereafter, it is only necessary to determine whether the current starting basic logic gate circuit and one consecutive basic logic gate circuit after the starting basic logic gate circuit are merged into one basic logic gate circuit.

[0092] Optionally, the first basic logic gate circuit in the target logic path (that is, the basic logic gate circuit closest to the target input terminal) can be used as the initial starting point basic logic gate circuit.

[0093] For ease of understanding, the following description will be made by taking an example where a target logic path includes five basic logic gate circuits.

[0094] First, the first basic logic gate circuit in the target logic path is taken as the starting basic logic gate circuit, and it is determined whether the current starting basic logic gate circuit and the two consecutive basic logic gate circuits (the second basic logic gate circuit and the third basic logic gate circuit) after the starting basic logic gate circuit can be merged into one basic logic gate circuit.

[0095] If the first basic logic gate circuit, the second basic logic gate circuit, and the third basic logic gate circuit can be merged into one basic logic gate circuit, then the merger is performed. Then, the fourth basic logic gate circuit (the fourth basic logic gate circuit in the target logic path that has not been merged) is used as the starting basic logic gate circuit, and it is determined whether the fourth basic logic gate circuit and the fifth basic logic gate circuit can be merged into one basic logic gate circuit.

[0096] If the fourth basic logic gate circuit and the fifth basic logic gate circuit can be combined into one basic logic gate circuit, then the fourth basic logic gate circuit and the fifth basic logic gate circuit are combined into one basic logic gate circuit.

[0097] If the 4th basic logic gate circuit and the 5th basic logic gate circuit cannot be merged into one basic logic gate circuit, the 5th basic logic gate circuit (the 5th basic logic gate circuit in the target logic path that has not been merged) is used as the starting basic logic gate circuit. Since the 5th basic logic gate circuit is the last basic logic gate circuit in the target logic path, the merging process is terminated.

[0098] If the first basic logic gate circuit, the second basic logic gate circuit, and the third basic logic gate circuit cannot be combined into one basic logic gate circuit, then it is determined whether the first basic logic gate circuit and the second basic logic gate circuit can be combined into one basic logic gate circuit.

[0099] If the first basic logic gate circuit and the second basic logic gate circuit can be merged into one basic logic gate circuit, then merge them. Then take the third basic logic gate circuit (the third basic logic gate circuit in the target logic path that has not been merged) as the starting basic logic gate circuit, and determine whether the third basic logic gate circuit, the fourth basic logic gate circuit, and the fifth basic logic gate circuit can be merged into one basic logic gate circuit. Repeat the above determination process until the merging process is completed.

[0100] If the first basic logic gate circuit and the second basic logic gate circuit cannot be merged into one basic logic gate circuit, the second basic logic gate circuit is used as the starting basic logic gate circuit, and it is determined whether the second basic logic gate circuit, the third basic logic gate circuit, and the fourth basic logic gate circuit can be merged into one basic logic gate circuit. The above determination process is repeated until the merging process is completed.

[0101] The examples given here are only for ease of understanding and should not be construed as limiting the present application.

[0102] In one implementation, if the operation unit does not exist in the circuit netlist file, the logic level of the target logic path is determined according to the circuit netlist file.

[0103] The specific method of determining the number of logic levels of the target logic path according to the circuit netlist file is the same as the method of determining the number of logic levels of the target logic path based on the updated netlist file, and will not be repeated here for the sake of brief description.

[0104] In order to facilitate understanding of the above logic level estimation method, an example will be given below to illustrate.

[0105] like Figure 3 As shown, first obtain the RTL code and SDC constraint file describing the target logic path. Then compile and obtain the circuit netlist file (generic netlist) according to the RTL code and SDC constraint file.

[0106] Then, all operation units in the circuit netlist file are determined, and the combinational logic unit corresponding to each operation unit is obtained from the preset combinational logic unit library. Each operation unit is replaced with the combinational logic unit corresponding to the operation unit to obtain an updated netlist file.

[0107] It is determined whether the current starting basic logic gate circuit and two consecutive basic logic gate circuits after the starting basic logic gate circuit can be merged into one basic logic gate circuit. The starting basic logic gate circuit is the basic logic gate circuit included in the target logic path described in the updated netlist file.

[0108] If the current starting basic logic gate circuit and the two consecutive basic logic gate circuits after the starting basic logic gate circuit can be merged into one basic logic gate circuit, then: merge the current starting basic logic gate circuit and the two consecutive basic logic gate circuits after the starting basic logic gate circuit into one basic logic gate circuit, and use the third consecutive basic logic gate circuit after the starting basic logic gate circuit as the new starting basic logic gate circuit, and repeat the above operation.

[0109] If the current starting point basic logic gate circuit and the two consecutive basic logic gate circuits after the starting point basic logic gate circuit cannot be merged into one basic logic gate circuit, then: determine whether the current starting point basic logic gate circuit and a consecutive basic logic gate circuit after the starting point basic logic gate circuit can be merged into one basic logic gate circuit; if so, merge the current starting point basic logic gate circuit and a consecutive basic logic gate circuit after the starting point basic logic gate circuit into one basic logic gate circuit, and use the second consecutive basic logic gate circuit after the starting point basic logic gate circuit as the new starting point basic logic gate circuit, and repeat the above operation; if not, use the next basic logic gate circuit of the current starting point basic logic gate circuit as the new starting point basic logic gate circuit, and repeat the above operation.

[0110] When the starting basic logic gate circuit is the last basic logic gate circuit of the target logic path, or the last basic logic gate circuit is merged into one basic logic gate circuit, the merging process is ended, and the logic level of the target logic path is determined based on the target logic path after the merging process is completed.

[0111] Based on the same technical concept, the present application also provides a logic level estimation device, such as Figure 4 The logic level estimation device 100 includes an acquisition module 110 and a processing module 120 .

[0112] The acquisition module 110 is used to acquire a circuit netlist file describing a target logic path, where the target logic path is a logic path of a logic level to be estimated.

[0113] The processing module 120 is used to replace the operation unit described in the circuit netlist file with the corresponding combinational logic unit when there is an operation unit in the circuit netlist file, so as to obtain an updated netlist file; wherein the combinational logic unit includes at least two basic logic gate circuits.

[0114] The processing module 120 is further configured to determine the number of logic levels of the target logic path based on the updated netlist file; wherein the number of logic levels of the target logic path is related to the number of basic logic gate circuits included in the target logic path.

[0115] The processing module 120 is specifically used to determine all the operation units in the circuit netlist file; obtain the combinational logic unit corresponding to each of the operation units from a preset combinational logic unit library; and replace each of the operation units with the combinational logic unit corresponding to the operation unit to obtain the updated netlist file.

[0116] The processing module 120 is specifically used to determine all the operation units of the target logic path in the circuit netlist file; obtain the combinational logic unit corresponding to each of the operation units from a preset combinational logic unit library; and replace each of the operation units in the target logic path with the combinational logic unit corresponding to the operation unit to obtain the updated netlist file.

[0117] The processing module 120 is specifically used to obtain the hardware description language file of the operation unit; synthesize the hardware description language file of the operation unit to obtain the combinational logic unit corresponding to the operation unit; replace the operation unit in the target logic path with the combinational logic unit corresponding to the operation unit to obtain the updated netlist file.

[0118] After obtaining the combinational logic unit corresponding to the operation unit based on the hardware description language file of the operation unit, the processing module 120 is further used to store the combinational logic unit corresponding to the operation unit into the combinational logic unit library.

[0119] The acquisition module 110 is specifically used to acquire the RTL code and the SDC constraint file describing the target logic path; and compile the circuit netlist file according to the RTL code and the SDC constraint file.

[0120] The processing module 120 is specifically used to determine whether any adjacent multiple basic logic gate circuits included in the multi-level basic logic gate circuits in the target logic path can be merged into one basic logic gate circuit; merge the multiple basic logic gate circuits that can be merged into the one basic logic gate circuit; wherein the merged multiple basic logic gate circuits and the merged basic logic gate circuit realize the same function; and determine the logic level of the target logic path based on the updated netlist file after the multiple basic logic gate circuits are merged.

[0121] The processing module 120 is specifically used for: for the i-th basic logic gate circuit in the target logic path: taking the i-th basic logic gate circuit as the starting point, determining whether N consecutive basic logic gate circuits can be merged into one basic logic gate circuit; if they cannot be merged, reducing the value of N by 1, and determining again whether N consecutive basic logic gate circuits can be merged into one basic logic gate circuit; repeating this step until N consecutive basic logic gate circuits can be merged into one basic logic gate circuit, or the value of N is reduced by 1 and equal to 1; if the first N basic logic gate circuits can be merged into one basic logic gate circuit, then: merging the N basic logic gate circuits into one basic logic gate circuits, and then initialize the value of N. If i+N is less than M, then take the i+Nth basic logic gate circuit as the starting point and perform the above-mentioned judgment steps again; if i+N is equal to M, end the merging process; M is the number of all basic logic gate circuits included in the target logic path before the merging operation is performed; if the value of N is equal to 1 after subtracting 1, then: initialize the value of N. If i+1 is less than M, then take the i+1th basic logic gate circuit as the starting point and perform the above-mentioned judgment steps again; if i+1 is equal to M, end the merging process; after the merging process is ended, determine the logic level of the target logic path based on the target logic path after the merging process is completed.

[0122] The processing module 120 is specifically used to determine whether the current starting point basic logic gate circuit and the two consecutive basic logic gate circuits after the starting point basic logic gate circuit can be merged into one basic logic gate circuit; wherein the starting point basic logic gate circuit is: the basic logic gate circuit included in the target logic path described in the updated netlist file; if the current starting point basic logic gate circuit and the two consecutive basic logic gate circuits after the starting point basic logic gate circuit can be merged into one basic logic gate circuit, then: merge the current starting point basic logic gate circuit and the two consecutive basic logic gate circuits after the starting point basic logic gate circuit into one basic logic gate circuit, and use the third consecutive basic logic gate circuit after the starting point basic logic gate circuit as the new starting point basic logic gate circuit, and repeat the above operation; if the current starting point basic logic gate circuit and the two consecutive basic logic gate circuits after the starting point basic logic gate circuit cannot be merged into one basic logic gate circuit basic logic gate circuit, then: determine whether the current starting basic logic gate circuit and a basic logic gate circuit that is continuous after the starting basic logic gate circuit can be merged into one basic logic gate circuit; if so, merge the current starting basic logic gate circuit and a basic logic gate circuit that is continuous after the starting basic logic gate circuit into one basic logic gate circuit, and use the second basic logic gate circuit that is continuous after the starting basic logic gate circuit as the new starting basic logic gate circuit, and repeat the above operation; if not, use the next basic logic gate circuit of the current starting basic logic gate circuit as the new starting basic logic gate circuit, and repeat the above operation; when the starting basic logic gate circuit is the last basic logic gate circuit of the target logic path, or the last basic logic gate circuit is merged into one basic logic gate circuit, end the merging process, and determine the logic level of the target logic path based on the target logic path after completing the merging process.

[0123] The logic level estimation device 100 provided in the embodiment of the present application has the same implementation principle and technical effects as those of the aforementioned logic level estimation method embodiment. For the sake of brief description, for matters not mentioned in the device embodiment, reference may be made to the corresponding contents in the aforementioned logic level estimation method embodiment.

[0124] See also Figure 5 , which is an electronic device 200 provided in an embodiment of the present application. The electronic device 200 includes: a processor 210 and a memory 220.

[0125] The memory 220 and the processor 210 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other via one or more communication buses or signal lines. The memory 220 is used to store computer programs, such as storing Figure 4 The software function module shown in is the logic level estimation device 100. The logic level estimation device 100 includes at least one software function module that can be stored in the memory 220 in the form of software or firmware or fixed in the operating system (OS) of the electronic device 200. The processor 210 is used to execute the executable module stored in the memory 220, such as the software function module or computer program included in the logic level estimation device 100. At this time, the processor 210 is used to obtain a circuit netlist file describing a target logic path, and the target logic path is a logic path of the logic level to be estimated; when there is an operation unit in the circuit netlist file, the operation unit described in the circuit netlist file is replaced with a corresponding combinational logic unit to obtain an updated netlist file; wherein the operation unit includes at least two basic logic gate circuits; based on the updated netlist file, the logic level of the target logic path is determined; wherein the logic level of the target logic path is related to the number of basic logic gate circuits included in the target logic path.

[0126] Among them, the memory 220 can be, but is not limited to, RAM (Random Access Memory), ROM (Read Only Memory), PROM (Programmable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electric Erasable Programmable Read-Only Memory), etc.

[0127] The processor 210 may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a CPU (Central Processing Unit), an NP (Network Processor), etc.; it may also be a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The various methods, steps and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. A general-purpose processor may be a microprocessor or the processor 210 may also be any conventional processor, etc.

[0128] The electronic device 200 mentioned above includes but is not limited to a personal computer, a server, etc.

[0129] The embodiment of the present application also provides a computer-readable storage medium (hereinafter referred to as storage medium), on which a computer program is stored, and when the computer program is run by a computer such as the above-mentioned electronic device 200, the above-mentioned logic level estimation method is executed. The computer-readable storage medium includes: a U disk, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk, and other media that can store program codes.

[0130] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for estimating a logic level, characterized in that: include: Obtaining a circuit netlist file describing a target logic path, wherein the target logic path is a logic path of a logic level to be estimated; In the case where there are operation units in the circuit netlist file, the operation units described in the circuit netlist file are replaced with corresponding combinational logic units to obtain an updated netlist file; wherein the combinational logic unit includes at least two levels of basic logic gate circuits; Based on the updated netlist file, the number of logic levels of the target logic path is determined; wherein the number of logic levels of the target logic path is related to the number of basic logic gate circuits included in the target logic path.

2. The method according to claim 1, characterized in that The step of replacing the operation units described in the circuit netlist file with corresponding combinational logic units to obtain an updated netlist file includes: Determine all the computing units in the circuit netlist file; Acquire the combinational logic unit corresponding to each of the operation units from a preset combinational logic unit library; Each of the operation units is replaced with a combinational logic unit corresponding to the operation unit to obtain the updated netlist file.

3. The method according to claim 2, characterized in that If the combinational logic unit library does not contain a combinational logic unit corresponding to the operation unit, the method further includes: Obtaining a hardware description language file of the computing unit; Synthesizing the hardware description language file of the operation unit to obtain a combinational logic unit corresponding to the operation unit; The operation unit in the target logic path is replaced with a combinational logic unit corresponding to the operation unit to obtain the updated netlist file.

4. The method according to claim 3, characterized in that After obtaining a combinational logic unit corresponding to the operation unit based on a hardware description language file of the operation unit, the method further includes: The combinational logic unit corresponding to the operation unit is stored in the combinational logic unit library.

5. The method according to claim 1, characterized in that The step of obtaining a circuit netlist file describing a target logic path includes: Obtaining RTL code and SDC constraint files describing the target logic path; The circuit netlist file is obtained by compiling the RTL code and the SDC constraint file.

6. The method according to any one of claims 1 to 5, characterized in that: Determining the number of logic levels of a target logic path based on the updated netlist file includes: Determine whether any adjacent multiple basic logic gate circuits included in the multi-level basic logic gate circuits in the target logic path can be merged into one basic logic gate circuit; Merge the multiple basic logic gate circuits that can be merged in the updated netlist file into one basic logic gate circuit; wherein the multiple merged basic logic gate circuits and the merged basic logic gate circuit realize the same function; The number of logic levels of the target logic path is determined based on the updated netlist file after merging the plurality of basic logic gate circuits.

7. The method according to any one of claims 1 to 5, characterized in that: Determining the number of logic levels of a target logic path based on the updated netlist file includes: For the i-th basic logic gate circuit in the target logic path: Taking the i-th basic logic gate circuit as a starting point, determining whether N consecutive basic logic gate circuits can be combined into one basic logic gate circuit; If it cannot be merged, the value of N is reduced by 1, and it is determined again whether the continuous N basic logic gate circuits can be merged into one basic logic gate circuit; this step is repeated until the continuous N basic logic gate circuits can be merged into one basic logic gate circuit, or the value of N is reduced by 1 and equal to 1; If the first N basic logic gate circuits can be merged into one basic logic gate circuit, then: merge the N basic logic gate circuits into one basic logic gate circuit, and then initialize the value of N. If i+N is less than M, take the i+Nth basic logic gate circuit as the starting point and perform the above judgment steps again; if i+N is equal to M, end the merging process; M is the number of all basic logic gate circuits included in the target logic path before the merging operation is performed; If the value of N minus 1 is equal to 1, then: initialize the value of N. If i+1 is less than M, take the i+1th basic logic gate circuit as the starting point and perform the above judgment steps again; if i+1 is equal to M, end the merging process; After the merging process is finished, the logic level of the target logic path is determined based on the target logic path after the merging process is completed.

8. The method according to any one of claims 1 to 5, characterized in that: Determining the number of logic levels of a target logic path based on the updated netlist file includes: Determine whether the current starting point basic logic gate circuit and two consecutive basic logic gate circuits after the starting point basic logic gate circuit can be merged into one basic logic gate circuit; wherein the starting point basic logic gate circuit is: the basic logic gate circuit included in the target logic path described in the updated netlist file; If the current starting point basic logic gate circuit and the two consecutive basic logic gate circuits after the starting point basic logic gate circuit can be merged into one basic logic gate circuit, then: merge the current starting point basic logic gate circuit and the two consecutive basic logic gate circuits after the starting point basic logic gate circuit into one basic logic gate circuit, and use the third consecutive basic logic gate circuit after the starting point basic logic gate circuit as a new starting point basic logic gate circuit, and repeat the above operation; If the current starting point basic logic gate circuit and the two consecutive basic logic gate circuits after the starting point basic logic gate circuit cannot be merged into one basic logic gate circuit, then: determine whether the current starting point basic logic gate circuit and a consecutive basic logic gate circuit after the starting point basic logic gate circuit can be merged into one basic logic gate circuit; if yes, merge the current starting point basic logic gate circuit and a consecutive basic logic gate circuit after the starting point basic logic gate circuit into one basic logic gate circuit, and use the second consecutive basic logic gate circuit after the starting point basic logic gate circuit as the new starting point basic logic gate circuit, and repeat the above operation; if not, use the next basic logic gate circuit of the current starting point basic logic gate circuit as the new starting point basic logic gate circuit, and repeat the above operation; When the starting basic logic gate circuit is the last basic logic gate circuit of the target logic path, or the last basic logic gate circuit is merged into a new basic logic gate circuit, the merging process is terminated, and the logic level of the target logic path is determined based on the target logic path after the merging process is completed.

9. A logic level estimation device, characterized in that: include: An acquisition module, used to acquire a circuit netlist file describing a target logic path, wherein the target logic path is a logic path of a logic level to be estimated; A processing module, configured to replace the operation unit described in the circuit netlist file with a corresponding combinational logic unit when there is an operation unit in the circuit netlist file, so as to obtain an updated netlist file; wherein the combinational logic unit includes at least two levels of basic logic gate circuits; The processing module is further used to determine the number of logic levels of the target logic path based on the updated netlist file; wherein the number of logic levels of the target logic path is related to the number of basic logic gate circuits included in the target logic path.

10. An electronic device, characterized in that: include: A memory and a processor, wherein the memory and the processor are connected; The memory is used to store programs; The processor is used to call the program stored in the memory to execute the method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a computer, the method according to any one of claims 1 to 8 is executed.

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