PFC circuit control method, controller, chip and circuit

Abstract

The invention relates to the field of switching power supply control, in particular to a PFC circuit control method, a controller, a chip and a circuit. The control method of the PFC circuit comprises the steps that the PFC circuit is set to be in a CRM and DCM combined working mode in a power frequency half-sine wave, a maximum expected switching period and a minimum expected switching period corresponding to basic conduction time based on a PFC circuit switching device are adopted, and the maximum expected switching period is larger than the minimum expected switching period. The previous switching period corresponding to the PFC circuit switching device is compared with the maximum expected switching period and the minimum expected switching period, and the time of the current switching period corresponding to the PFC circuit switching device is adjusted by increasing or reducing the trough number of the inductance current interruption time, so that the fluctuation range of the switching frequency is adjusted and controlled, and the working efficiency of the system is improved. Meanwhile, during trough switching, the conduction time of the current switching period of the PFC circuit switching device is adjusted, and the THD performance of the system is enhanced.

Description

Technical Field

[0001] The present invention relates to the field of switching power supply control, and in particular to a control method, a controller, a chip and a circuit for a PFC circuit. Background Art

[0002] With the rapid development of power electronics technology, switching power supplies are widely used in electronic equipment with the characteristics of small size, light weight and high efficiency. They are an indispensable power supply mode for the rapid development of today's electronic information industry. However, these advantages are also accompanied by some negative effects, especially the harmonic pollution and reactive power increase of the power grid caused by the distortion of non-sinusoidal current waveform. At present, according to industry standards, capacitive load electrical equipment with power greater than 75W must add power factor correction (PFC) circuits to correct the power factor of the electrical equipment, so that the AC line current tracks the instantaneous change trajectory of the voltage waveform, and keeps the current and voltage in phase so that the system presents a pure resistive characteristic, thereby reducing the harmonic pollution and reactive power of the power grid caused by the distortion of non-sinusoidal current waveform, and improving the overall efficiency of the power system.

[0003] The BOOST PFC circuit is a commonly used topology used to improve the power factor of the power supply and reduce harmonic distortion. It has been widely used in small and medium power applications due to its simple structure and convenient control. In particular, the constant on-time control method and the critical conduction mode (CRM) working mode perform particularly well in small and medium power applications. However, within the half-wave of the power frequency, the BOOST PFC circuit maintains a single CRM working mode, which will cause a large fluctuation range of the switching frequency, thereby affecting the system efficiency. Therefore, how to adjust the range of the switching frequency and improve its working efficiency is a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a control method, a controller, a chip and a circuit of a PFC circuit.

[0005] This application adopts the following technical solutions: A control method for a PFC circuit, comprising: Acquire a maximum expected switching period and a minimum expected switching period based on a basic on-time of a switching device of a PFC circuit, wherein the maximum expected switching period is greater than the minimum expected switching period; Obtaining the last switching cycle of the PFC circuit and the number of valleys of the inductor current discontinuous time in the last switching cycle, and comparing the last switching cycle with the maximum expected switching cycle and the minimum expected switching cycle; When the previous switching cycle is greater than the maximum expected switching cycle, controlling the current switching cycle corresponding to the PFC circuit switch device to reduce the number of valleys of the inductor current discontinuous time; When the previous switching cycle is less than the minimum expected switching cycle, the current switching cycle corresponding to the PFC circuit switching device is controlled to increase the number of valleys of the inductor current discontinuous time, wherein when the number of valleys of the inductor current discontinuous time is one, the PFC circuit enters the CRM mode, and when the number of valleys of the inductor current discontinuous time is greater than one, the PFC circuit enters the DCM mode.

[0006] Optionally, the maximum expected switching period T is obtained. ref_sub and the minimum expected switching period T ref_add The steps include: Obtain the basic on-time of the PFC circuit switch device; The bus voltage value and the instantaneous value of the input voltage are obtained, and the real-time switching cycle of the PFC circuit in the CRM mode is obtained based on the basic on-time of the switching device of the PFC circuit, the bus voltage value, and the instantaneous value of the input voltage. The expression of the real-time switching cycle of the PFC circuit in the CRM mode is: , , Among them, V ac is the instantaneous value of the input voltage, V bus is the bus voltage value, T on_base is the basic conduction time of the PFC circuit switch device, T dem is the inductor demagnetization time, T CRM is the real-time switching cycle of the PFC circuit in CRM mode; An inverse relationship between the minimum expected switching period and the real-time switching period of the PFC circuit in the CRM mode is established based on the real-time switching period of the PFC circuit in the CRM mode to obtain the minimum expected switching period; A first offset is obtained, and based on the first offset and the minimum expected switching period, the minimum expected switching period and the first offset are added to obtain the maximum expected switching period.

[0007] Optionally, an expression for establishing an inverse relationship between the minimum expected switching period and the real-time switching period of the PFC circuit in the CRM mode is: , T ref_add ≥T ref_min , Where k is a negative number, b is a positive number, T ref_min Allow the minimum switching cycle for the system.

[0008] Optionally, the method further includes adjusting the minimum expected switching period and the maximum expected switching period, wherein when the input voltage slope is less than 0, a second offset is superimposed on the minimum expected switching period and the maximum expected switching period to obtain a second minimum expected switching period and a second maximum expected switching period, which are respectively used as the minimum expected switching period of the switching device of the PFC circuit and the maximum expected switching period of the switching device.

[0009] Optionally, the method further includes pre-compensating the on-time of the PFC circuit switch device at the valley switching moment to obtain the on-time of the current switching cycle of the PFC circuit switch device, wherein the step of obtaining the on-time of the current switching cycle of the PFC circuit switch device includes: Obtain the last switching cycle corresponding to the PFC circuit switch device, the total time of inductor excitation and demagnetization in the last switching cycle of the PFC circuit, the valley cycle of the PFC circuit, and the basic on-time of the PFC circuit switch device; Based on the number of valleys of the inductor current discontinuous time that is reduced or increased in the current switching cycle, the current switching cycle on time of the PFC circuit switch device is calculated.

[0010] Optionally, when the number of valleys of the current switching cycle that reduces the discontinuous time is one, the expression for calculating the on-time of the current switching cycle of the PFC circuit switch device is: , Among them, T on is the current switching cycle conduction time of the PFC circuit switch device, T on_base is the basic conduction time of the PFC circuit switch device, T sw is the previous switching cycle corresponding to the PFC circuit switch device, T power is the total time of inductor excitation and demagnetization in the previous switching cycle of the PFC circuit, T zcd It is the valley period of the PFC circuit inductor current discontinuity time; When the number of valleys of the intermittent time added in the current switching cycle is one, the expression for calculating the conduction time of the current switching cycle of the PFC circuit switch device is: , Among them, T on is the current switching cycle conduction time of the PFC circuit switch device, T on_base is the basic conduction time of the PFC circuit switch device, T sw is the previous switching cycle corresponding to the PFC circuit switch device, T power is the total time of inductor excitation and demagnetization in the previous switching cycle of the PFC circuit, T zcd It is the valley period of the PFC circuit inductor current discontinuity time.

[0011] The present invention further provides a PFC circuit controller using the above-mentioned PFC circuit control method, comprising: an acquisition unit, configured to acquire a maximum expected switching cycle and a minimum expected switching cycle, wherein the maximum expected switching cycle is greater than the minimum expected switching cycle, and the maximum expected switching cycle and the minimum expected switching cycle are acquired based on a basic on-time of a switching device of a PFC circuit; and acquire a previous switching cycle of the PFC circuit and the number of valleys of the discontinuous time of the inductor current in the previous switching cycle; The comparison and adjustment unit is used to compare the size of the previous switching cycle with the maximum expected switching cycle and the minimum expected switching cycle according to the information acquired by the acquisition unit; when the previous switching cycle is greater than the maximum expected switching cycle, control the current switching cycle corresponding to the PFC circuit switch device to reduce the number of valleys of the inductor current discontinuous time, wherein when the number of valleys of the inductor current discontinuous time is one, the PFC circuit enters the CRM mode, and when the number of valleys of the inductor current discontinuous time is greater than one, the PFC circuit enters the DCM mode; when the previous switching cycle is less than the minimum expected switching cycle, control the current switching cycle corresponding to the PFC circuit switch device to increase the number of valleys of the inductor current discontinuous time.

[0012] Optionally, the PFC circuit controller further includes: The on-time adjustment unit pre-compensates the on-time of the PFC circuit switch device at the valley switching moment to obtain the on-time of the current switching cycle of the PFC circuit switch device.

[0013] The present invention also provides a chip, comprising the above-mentioned PFC circuit controller.

[0014] The present invention also provides a circuit, including a PFC circuit and the above-mentioned PFC circuit controller.

[0015] In summary, the advantages and beneficial effects of the present invention are: The present invention provides a control method, controller, chip and circuit of a PFC circuit. The control method of the PFC circuit includes obtaining a maximum expected switching cycle and a minimum expected switching cycle based on a basic conduction time of a switch device of the PFC circuit, wherein the maximum expected switching cycle is greater than the minimum expected switching cycle; obtaining the number of valleys of the discontinuous time of the inductor current in the previous switching cycle and the previous switching cycle of the PFC circuit, and comparing the size of the previous switching cycle with the maximum expected switching cycle and the minimum expected switching cycle; when the previous switching cycle is greater than the maximum expected switching cycle, controlling the current switching cycle corresponding to the switch device of the PFC circuit to reduce the number of valleys of the discontinuous time of the inductor current, wherein when the number of valleys of the discontinuous time of the inductor current is one, the PFC circuit enters a CRM mode, and when the number of valleys of the discontinuous time of the inductor current is greater than one, the PFC circuit enters a DCM mode; when the previous switching cycle is less than the minimum expected switching cycle, controlling the current switching cycle corresponding to the switch device of the PFC circuit to increase the number of valleys of the discontinuous time of the inductor current.

[0016] The PFC circuit is set to work in a combination of CRM and DCM within a half-wave of a power frequency sine wave, the maximum expected switching period and the minimum expected switching period are obtained, the previous switching period corresponding to the PFC circuit switching device is compared with the maximum expected switching period and the minimum expected switching period, and the time of the current switching period corresponding to the PFC circuit switching device is adjusted by increasing or decreasing the number of valleys of the inductor current discontinuity time, thereby regulating the fluctuation range of the switching frequency and improving the system working efficiency.

[0017] When the PFC circuit is in DCM mode, the inductor current will be discontinuous within one switching cycle. This discontinuous characteristic will cause higher harmonic distortion. At the same time, when the valley number switches, the current waveform will also be distorted, resulting in an increase in total harmonic distortion (THD). Therefore, when switching in the valley, the on-time of the current switching cycle of the PFC circuit switch device is adjusted to enhance the THD performance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work, but they should fall within the scope of protection of this application.

[0019] Figure 1 It is a schematic diagram of a traditional BOOST PFC circuit; Figure 2A schematic diagram showing the relationship between the instantaneous value of the input voltage, the basic on-time of the switching device, and the switching frequency of the switching device in the BOOST PFC circuit in the CRM mode; Figure 3 A schematic diagram of a process of a PFC circuit control method provided by an embodiment of the present invention; Figure 4a~4b A schematic diagram of the relationship between the corresponding instantaneous value of the input voltage and the switching frequency of the switching device in the CRM working mode and the DCM mode of a control method for a PFC circuit provided by an embodiment of the present invention; Figure 5 A schematic diagram of obtaining a basic on-time of a switching device in a control method of a PFC circuit provided by an embodiment of the present invention; Figure 6 A schematic diagram of obtaining a maximum expected switching period and a minimum expected switching period of a control method for a PFC circuit provided by an embodiment of the present invention; Figure 7 A schematic diagram of the linear relationship between the minimum expected switching period of a control method for a PFC circuit and the real-time switching period of the PFC circuit in a CRM mode provided by an embodiment of the present invention; Figure 8 A schematic diagram of the relationship between the maximum expected switching period, the minimum expected switching period and the instantaneous value of the input voltage in a control method for a PFC circuit provided by an embodiment of the present invention; Fig. 9 A schematic diagram of the relationship between a maximum expected switching period, a minimum expected switching period, and a current switching period corresponding to a PFC circuit switch device in a control method for a PFC circuit provided by an embodiment of the present invention; Fig.10 A schematic diagram of the relationship between a maximum expected switching period, a minimum expected switching period, and a current switching period corresponding to a PFC circuit switch device obtained by further adjusting a control method for a PFC circuit provided by an embodiment of the present invention; Fig.11 A schematic diagram of an inductor current waveform after compensating for the on-time of a switch device of a PFC circuit in a previous switching cycle of a control method for a PFC circuit provided by an embodiment of the present invention; Fig.12 A schematic diagram of obtaining the current switching cycle conduction time of a PFC circuit switch device according to a PFC circuit control method provided by an embodiment of the present invention; Fig.13 A schematic diagram of valley detection of a PFC circuit control method provided by an embodiment of the present invention; Fig.14 A schematic diagram of a PFC circuit principle provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] like Figure 1 As shown, it is a traditional BOOST PFC (boost power factor correction) circuit, including: a rectifier bridge composed of a first diode D1 to a fourth diode D4, a first inductor L1, a second inductor L2, a third inductor L3, a switch device Q, a fifth diode D5, a first capacitor C1, a second capacitor C2, a third capacitor C3, a resistor R, and an input voltage; One end of the first capacitor C1 is connected to the first inductor L1 and one end of the input voltage, the other end of the first capacitor C1 is connected to one end of the second inductor L2 and the other end of the input voltage, one end of the second capacitor C2 is connected to the anode of the first diode D1, the cathode of the fourth diode D4, and the other end of the first inductor L1, the other end of the second capacitor C2 is connected to the anode of the third diode D3, the cathode of the second diode D2, and the other end of the second inductor L2, the cathode of the first diode D1 is connected to the cathode of the third diode D3, one end of the third inductor L3, and one end of the third capacitor C3, the other end of the third inductor L3 is connected to the drain of the switching device Q and the anode of the fifth diode D5, the cathode of the fifth diode D5 is connected to one end of the fourth capacitor C4 and one end of the resistor R, the anode of the fourth diode D4 is connected to the anode of the second diode D2, the other end of the third capacitor C3, the source of the switching device Q, the other end of the fourth capacitor, and the other end of the resistor R.

[0021] The BOOST PFC circuit is in a single CRM mode within the half-wave of the power frequency. Figure 2 As shown, due to the conduction time T of the PFC circuit switch device Q on remains unchanged, when the input voltage V ac When the value is smaller, the growth rate of the forward excitation current of the third inductor L3 will be correspondingly slowed down, so that the forward excitation current of the third inductor L3 is relatively small, and the energy storage of the third inductor L3 will be reduced. Correspondingly, the energy that needs to be released in the demagnetization stage of the third inductor L3 will be correspondingly reduced, and the demagnetization time of the third inductor L3 will be shortened, resulting in a shorter switching cycle of the PFC circuit switch device Q, and finally resulting in an increase in the switching frequency f of the PFC circuit switch device Q, that is, Figure 2 As shown, the switching frequency f of the PFC circuit switching device and the input voltage V ac Inversely proportional, when the input voltage V ac When the input voltage V acWhen the waveform decreases, the switching frequency f waveform of the PFC circuit switching device Q will rise, and the variation range of the switching frequency f of the PFC circuit switching device Q will be relatively wide; moreover, the increase in the switching frequency f of the PFC circuit switching device Q will lead to an increase in the switching loss of the PFC circuit switching device Q, and since the variation range of the switching frequency f of the PFC circuit switching device Q is relatively wide, the design of the magnetic components and EMI filters in the PFC circuit will become more difficult.

[0022] In order to control the width of the variation range of the switching frequency f of the PFC circuit switch device Q, reduce the maximum switching frequency f of the PFC circuit switch device Q, and improve the working efficiency of the system, the embodiment of the present application provides a control method, a controller, a chip and a circuit of a PFC circuit, which control the switching frequency f range of the PFC circuit switch device Q and improve the efficiency of the PFC circuit.

[0023] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0024] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0026] The present invention provides a control method for a PFC circuit, such as Figure 3 As shown, including: Step S10, obtaining a maximum expected switching period and a minimum expected switching period based on a basic on-time of a switching device of a PFC circuit, wherein the maximum expected switching period is greater than the minimum expected switching period; Step S20, obtaining the last switching cycle of the PFC circuit and the number of valleys of the inductor current discontinuous time in the last switching cycle, and comparing the last switching cycle with the maximum expected switching cycle and the minimum expected switching cycle; Step S30, when the previous switching cycle is greater than the maximum expected switching cycle, controlling the current switching cycle corresponding to the PFC circuit switch device to reduce the number of valleys of the inductor current discontinuous time, wherein when the number of valleys of the inductor current discontinuous time is one, the PFC circuit enters the CRM mode, and when the number of valleys of the inductor current discontinuous time is greater than one, the PFC circuit enters the DCM mode; Step S40: When the previous switching cycle is less than the minimum expected switching cycle, control the current switching cycle corresponding to the PFC circuit switch device to increase the number of valleys of the inductor current discontinuous time.

[0027] Specifically, in an embodiment of the present invention, the PFC circuit is set to a multi-mode working state, and the multi-mode working state includes a discontinuous conduction mode (DCM) and a critical conduction mode (CRM), so as to avoid a single working mode causing the switching frequency of the PFC circuit to be too high.

[0028] In the embodiment of the present invention, when the number of valleys is one, the PFC circuit is set to a CRM working mode; when the number of valleys is greater than one, the PFC circuit is set to a DCM working mode.

[0029] Execute step S10 to obtain the maximum expected switching period T based on the basic on-time of the PFC circuit switch device. ref_sub and the minimum expected switching period T ref_add , the maximum expected switching period T ref_sub Greater than the minimum expected switching period T ref_add .

[0030] In the embodiment of the present invention, based on the basic on-time of the PFC circuit switch device, the maximum expected switching period T is obtained by calculation. ref_sub and the minimum expected switching period T ref_add , calculate and obtain the maximum expected switching period T ref_sub and the minimum expected switching period T ref_add The steps include: Step S11, obtaining the basic on-time T of the PFC circuit switch device on_base ; In the embodiment of the present invention, based on the bus voltage value V bus , bus voltage reference value V bus_ref The basic on-time T of the switching device of the PFC circuit is obtained by calculation on_base .

[0031] In the embodiment of the present invention, Figure 5As shown, the basic on-time T of the switching device of the PFC circuit is obtained. on_base The steps include: Step S111, obtaining the bus voltage value V bus , bus voltage reference value V bus_ref , based on the bus voltage value V bus , bus voltage reference value V bus_ref Perform voltage loop calculation to obtain compensation u t ; In the embodiment of the present invention, the bus voltage value V bus is the output voltage of the PFC circuit; the bus voltage reference value V bus_ref is the output target voltage of the PFC circuit.

[0032] In an embodiment of the present invention, the voltage loop calculation method includes one of a PI (proportional integral) controller and a PID (proportional integral differential) controller.

[0033] In other embodiments, the voltage loop calculation method adopts other suitable calculation methods.

[0034] Step S112, obtaining the input voltage peak value V of the PFC circuit acpk , based on the input voltage peak V acpk , the compensation amount u t Normalized compensation u t , obtain the normalized compensation amount, and eliminate the effect of the input voltage fluctuation of the PFC circuit on the compensation amount u t The impact of Use normalized compensation to ensure that the compensation u t It is not affected by the input voltage fluctuation of the PFC circuit, thereby improving the stability and accuracy of the system.

[0035] In the embodiment of the present invention, based on the input voltage peak value V acpk , the compensation amount u t , get the normalized compensation u' t The expression of the compensation amount u is: t Divide by the input voltage peak V acpk The square of u' t =u t / V 2 acpk , where u' t is the normalized compensation amount, u t is the compensation amount, V acpk is the peak value of the input voltage.

[0036] Step S113, multiplying the normalized compensation amount by the coefficient K to obtain the basic on-time T of the switch device of the PFC circuit on_base , where K is a constant.

[0037] The coefficient K is used to eliminate the influence of proportional conversion such as sampling circuit ratio and digital quantization.

[0038] Step S12, obtaining the bus voltage value V bus , Input voltage instantaneous value V ac , based on the basic on-time T of the PFC circuit switch device on_base , the bus voltage value V bus , the instantaneous value of the input voltage V ac , obtain the maximum expected switching period T ref_sub and the minimum expected switching period T ref_add .

[0039] In the embodiment of the present invention, Figure 6 As shown, the maximum expected switching period T is calculated and obtained. ref_sub and the minimum expected switching period T ref_add The steps include: Step S121, obtaining the bus voltage value V bus , Input voltage instantaneous value V ac , based on the basic on-time T of the PFC circuit switch device on_base , inductor energy relationship, and obtain the real-time switching period T of the PFC circuit in CRM mode. CRM ; In the embodiment of the present invention, the real-time switching period T of the PFC circuit in the CRM mode is obtained. CRM The expression is: , , Among them, V ac is the instantaneous value of the input voltage, V bus is the bus voltage value, T on_base is the basic conduction time of the PFC circuit switch device, T dem is the inductor demagnetization time, T CRM is the real-time switching cycle of the PFC circuit in CRM mode.

[0040] like Figure 2 As shown, when the PFC circuit adopts a fixed CRM mode, the switching frequency of the switching device of the PFC circuit increases as the instantaneous value of the input voltage decreases, that is, the real-time switching period T CRMTo reduce the switching frequency of the PFC circuit switch device, the switching cycle time must be increased. When the input voltage is small, the switching frequency of the PFC circuit switch device is reduced by increasing the switching cycle time. Therefore, based on the inverse ratio of the instantaneous value of the input voltage to the switching cycle, the maximum expected switching cycle T is calculated. ref_sub and the minimum expected switching period T ref_add On the basis of, the number of valleys of the inductor current discontinuity time is adjusted to achieve the purpose of reducing the switching frequency of the PFC circuit switching device when the instantaneous value of the input voltage decreases in one power frequency half-wave.

[0041] Step S122, according to the real-time switching period T of the PFC circuit in the CRM mode CRM Establish the minimum desired switching period T ref_add and the real-time switching cycle T of the PFC circuit in the CRM mode CRM The minimum expected switching period T is obtained. ref_add .

[0042] Since the minimum expected switching period T ref_add , the maximum expected switching period T ref_sub and the real-time switching cycle T of the PFC circuit in the CRM mode CRM have an inversely proportional relationship, therefore, by establishing the minimum desired switching period T ref_add and the real-time switching cycle T of the PFC circuit in the CRM mode CRM The inverse relationship between the switching frequency and the switching frequency of the PFC circuit switching device is achieved.

[0043] In the embodiment of the present invention, Figure 7 As shown, the minimum desired switching period T is established ref_add and the real-time switching cycle T of the PFC circuit in the CRM mode CRM The expression of the inverse relationship is: , T ref_add ≥T ref_min , Where k is a negative number, b is a positive number, T ref_min Allow the minimum switching cycle for the system.

[0044] In the embodiment of the present invention, the value of b is 1.5 times, 2 times, 2.5 times or other suitable values ​​of the minimum switching frequency expected by the system, and the value range of the minimum switching frequency expected by the system is 22kHz~25kHz, so as to avoid audible noise heard by human ears; The constant k is -0.8, -1, -1.5 or other suitable values. When the absolute value of k is relatively large, such as Figure 4b As shown, the minimum expected switching period T ref_add The bending slope of is relatively large, so that the switching frequency f of the PFC circuit switch device Q decreases faster. When the absolute value of k is relatively small, such as Figure 4a As shown, the minimum expected switching period T ref_add The bending slope of is relatively small, so that the switching frequency f of the PFC circuit switch device Q decreases slowly; The system allows a minimum switching period T ref_min That is, the maximum frequency allowed by the system, through the minimum switching period T allowed by the system ref_min (i.e. the maximum frequency allowed by the system) for the minimum expected switching period T ref_add Limiting.

[0045] In other embodiments, the expression for the inverse relationship between the minimum expected switching period and the real-time switching period of the PFC circuit in the CRM mode may be set according to actual requirements.

[0046] Step S123, obtaining a first offset ΔT ref , based on the first offset ΔT ref , the minimum expected switching period T ref_add , the minimum expected switching period T ref_add and the first offset ΔT ref Add together to obtain the maximum expected switching period T ref_sub .

[0047] In an embodiment of the present invention, the maximum expected switching period T is obtained ref_sub The expression is: , Among them, T ref_sub is the maximum expected switching period, T ref_add is the minimum expected switching period, ΔT ref is the first offset.

[0048] In the embodiment of the present invention, the first offset ΔT ref It can be 1.5us, 2us, 2.5us or other suitable values.

[0049] In the embodiment of the present invention, Figure 7 As shown, the minimum desired switching period T established ref_add and the real-time switching cycle T of the PFC circuit in the CRM mode CRM The inverse relationship between ) where k is a negative number. The larger the absolute value of k, the corresponding Figure 8 As shown, the minimum expected switching period T ref_add and the maximum expected switching period T ref_sub The higher the slope of the curve, the faster and more the number of valleys is inserted, and the faster the switching frequency of the PFC circuit switch device decreases, thereby achieving a decrease in the switching frequency of the PFC circuit switch device, achieving the purpose of regulating the fluctuation range of the PFC circuit switch device, and improving the system working efficiency. Among them, T ref is the current expected switching cycle.

[0050] The present invention sets the PFC circuit to a combined working mode of CRM and DCM within a power frequency sine half wave, obtains the maximum expected switching cycle and the minimum expected switching cycle, compares the previous switching cycle corresponding to the PFC circuit switch device with the maximum expected switching cycle and the minimum expected switching cycle, and adjusts the time of the current switching cycle corresponding to the PFC circuit switch device by increasing or decreasing the number of valleys of the inductor current discontinuous time, thereby regulating the fluctuation range of the switching frequency and reducing the maximum switching frequency f of the PFC circuit switch device Q, thereby solving the problem of Figure 2 The original input voltage V ac The waveform decreases, and the switching frequency f waveform of the PFC circuit switching device Q will rise (especially when the input voltage V ac The switching frequency is close to 0V, that is, the switching frequency is high, such as Figure 4a~Figure 4b As shown, the present invention continuously adjusts the number of valleys to reduce the upward (higher) switching frequency of the FC circuit switch device, thereby reducing the switching loss of the system and improving the system working efficiency. The present invention embodiment realizes that the switching frequency of the PFC circuit switch device bends downward as the input voltage decreases within a power frequency sinusoidal half wave.

[0051] In practical applications, such as Fig. 9 As shown, when the input voltage instantaneous value V ac When the input voltage slope is positive, the current switching period T is continuously reduced, the number of valleys of the PFC circuit is continuously reduced, and the frequency of the switching device of the PFC circuit is increased. At this time, the maximum expected switching period T ref_sub It is the main control line; when the input voltage instantaneous value V ac When the input voltage slope is negative, the current switching period T increases continuously, the number of valleys in the system increases continuously, and the frequency of the switching device of the PFC circuit decreases. At this time, the minimum expected switching period T ref_addThe inventors found that as the input voltage slope changes, the switching frequency of the PFC circuit switch device will present an asymmetric state, resulting in an asymmetric inductor current, which makes the THD performance worse. In addition, this asymmetric inductor current state changes with the first offset ΔT ref In order to improve the symmetry of the inductor current waveform, it is necessary to further adjust the minimum expected switching period T as the input voltage slope changes. ref_add and the maximum expected switching period T ref_sub .

[0052] In an embodiment of the present invention, the minimum expected switching period T is further adjusted. ref_add and the maximum expected switching period T ref_sub , further adjust the minimum expected switching period T ref_add and the maximum expected switching period T ref_sub The steps include: Get the input voltage slope Slope V ac , the second offset ΔT ref_bias , Based on the input voltage slope Slope V ac and the second offset ΔT ref_bias Regulate the maximum expected switching period T obtained in the previous step ref_sub and the minimum desired switching period T ref_add , obtaining a second minimum expected switching period and a second maximum expected switching period, wherein the second minimum expected switching period is used as the minimum expected switching period of the switching device, and the second maximum expected switching period is used as the maximum expected switching period of the switching device.

[0053] In the embodiment of the present invention, Fig.10 As shown in the figure, when the input voltage slope Slope V ac When it is less than 0, the minimum expected switching period T ref_add , the maximum expected switching period T ref_sub The second offset ΔT is superimposed ref_bias , obtain the second minimum expected switching period and the second maximum expected switching period, respectively as the minimum expected switching period T of the switching device ref_add and the maximum expected switching period T of the switching device ref_sub , where T is the current switching period.

[0054] In the embodiment of the present invention, the second offset ΔT ref_bias The value of is the first offset ΔT ref One half of .

[0055] In other embodiments, the second offset ΔT ref_bias The value of is determined according to the situation.

[0056] By the maximum expected switching period T ref_sub and the minimum desired switching period T ref_add Further regulation avoids switching back and forth in system control and improves the symmetry of the waveform, so that the system can obtain better THD performance.

[0057] In the embodiment of the present invention, the input voltage slope Slope V ac It is obtained based on the half-wave after input rectification.

[0058] Execute step S20 to obtain the last switching cycle of the lower PFC circuit and the number of valleys of the inductor current discontinuity time in the last switching cycle, and compare the last switching cycle with the maximum expected switching cycle T ref_sub , minimum expected switching period T ref_add size.

[0059] In an embodiment of the present invention, a timer is used to measure the time of the previous switching cycle. In other embodiments, a counter or other methods are used to measure the time of the previous switching cycle.

[0060] In the embodiment of the present invention, in the DCM mode, there are at least two valleys in each switching cycle. In one switching cycle, the drain-source voltage V DS The position where the voltage waveform reaches the lowest point is the trough, and one low point is recorded as a trough.

[0061] In the embodiment of the present invention, by detecting the drain-source voltage V of the PFC circuit switch device DS The number of valleys is determined by detecting the waveform of the PFC circuit or by detecting the zero crossing point ZCD of the auxiliary winding, and the PFC circuit switch device is a MOS tube.

[0062] Step S30 is executed, when the previous switching period is greater than the maximum expected switching period T ref_sub When the current switching cycle corresponding to the PFC circuit switching device is controlled to reduce the number of valleys of the inductor current discontinuous time, when the number of valleys of the inductor current discontinuous time is one, the PFC circuit enters the CRM mode, and when the number of valleys of the inductor current discontinuous time is greater than one, the PFC circuit enters the DCM mode.

[0063] In the embodiment of the present invention, by reducing the number of valleys of the inductor current discontinuous time in the current switching cycle, the time of the current switching cycle T is shortened, so that the switching cycle returns to the expected range. In the same total time, the number of switching times of the PFC circuit is increased accordingly, thereby improving the switching frequency of the switching device.

[0064] In an embodiment of the present invention, the number of valleys of the inductor current discontinuous time is reduced by one each time, so that the switching cycle returns to the desired range. In other embodiments, the number of valleys of the inductor current discontinuous time is reduced by two each time or other suitable valleys.

[0065] Execute step S40, when the previous switching period is less than the minimum expected switching period T ref_add When the current switching cycle corresponding to the PFC circuit switch device is controlled, the number of valleys of the inductor current discontinuous time is increased.

[0066] In the embodiment of the present invention, by increasing the number of valleys of the inductor current discontinuous time in the current switching cycle, the time of the current switching cycle is lengthened, so that the switching cycle returns to the expected range. In the same total time, the number of switching times of the PFC circuit is reduced accordingly, thereby reducing the switching frequency of the switching device.

[0067] In an embodiment of the present invention, the number of valleys of the inductor current discontinuous time increased in each current switching cycle is one. In other embodiments, the number of valleys of the inductor current discontinuous time increased in each current switching cycle is two or other suitable valleys.

[0068] By reducing the number of valleys of the discontinuous time of the inductor current in the current switching cycle, the time of the current switching cycle is reduced, and the switching frequency of the corresponding switching cycle is increased; by increasing the number of valleys of the discontinuous time of the current switching cycle, the time of the current switching cycle is increased, and the switching frequency of the corresponding switching cycle is reduced, it is achieved that when the instantaneous value of the input voltage is small, that is, when the input instantaneous power is small, the corresponding switching frequency is reduced, thereby reducing the switching loss, and realizing the regulation of the fluctuation range of the switching frequency of the switching device of the PFC circuit, thereby improving the working efficiency of the PFC circuit.

[0069] In the embodiment of the present invention, Figure 8 As shown, based on the maximum switching frequency allowed by the system, the minimum value T of the minimum expected switching period is obtained. ref_min , using the minimum value of the minimum expected switching period T ref_min For the minimum desired switching period T ref_add Amplitude limiting is performed to adjust the switching frequency of the PFC circuit switch device in the DCM mode to be less than or equal to the maximum allowed switching frequency, so as to avoid the system frequency being too low and generating audible noise to the human ear.

[0070] In the embodiment of the present invention, when the number of valleys is one, the PFC circuit is set to a CRM working mode; when the number of valleys is greater than one, the PFC circuit is set to a DCM working mode.

[0071] Because, if Fig.11 As shown, in the DCM mode, the inductor current of the PFC circuit will be discontinuous within a switching cycle. This discontinuous characteristic will cause higher harmonic distortion. At the same time, the current switching cycle corresponding to the switching device of the PFC circuit is based on the maximum expected switching cycle T ref_sub and the minimum expected switching period T ref_add The number of valleys of the inductor current in each switching cycle is continuously adjusted. That is, when switching at valleys, the current waveform will also be distorted, resulting in an increase in THD. Therefore, it is necessary to adjust the current switching cycle on time of the PFC circuit switch device during valley switching to enhance the THD performance of the system. off Increase or decrease the inductor current discontinuity time after one valley of the previous switching cycle.

[0072] Therefore, in an embodiment of the present invention, the control method of the PFC circuit further includes pre-compensating the on-time of the PFC circuit switch device at the valley switching moment to obtain the current switching cycle on-time T of the PFC circuit switch device. on .

[0073] In the embodiment of the present invention, Fig.12 As shown, the step of obtaining the current switching cycle on time of the PFC circuit switch device includes: Step S51, obtaining the previous switching cycle T corresponding to the switch device of the lower PFC circuit sw , the total time T of inductor excitation and demagnetization in the last switching cycle of the PFC circuit power , the valley period T of the PFC circuit inductor current discontinuity time zcd , the basic conduction time T of the PFC circuit switch device on_base ; Step S52, calculating the current switching cycle on time T of the PFC circuit switch device based on the number of valleys of the inductor current discontinuous time that is reduced or increased in the current switching cycle on .

[0074] In the embodiment of the present invention, Fig.13 As shown, the valley period T of the PFC circuit inductor current discontinuity time is obtained. zcd The steps include: Detect the trough point and obtain the trough point signal ZCD; The valley period is detected, and the time interval between two adjacent valley point signals ZCD is used as the valley period T of the PFC circuit inductor current discontinuity time. zcd .

[0075] In the embodiment of the present invention, when the drain-source voltage V DS Every time it reaches the lowest point, a valley point signal ZCD is generated.

[0076] In an embodiment of the present invention, an auxiliary winding is added to the inductor of the PFC circuit, and the induced voltage generated by the auxiliary winding is detected. DS When the lowest point is reached, a valley signal ZCD is generated; or the drain-source voltage V of the PFC circuit switch device is directly measured. DS , and generates a valley point signal ZCD when it reaches the lowest point.

[0077] In the embodiment of the present invention, a voltage zero-crossing signal is obtained and the time interval between two adjacent voltage zero-crossing signals is recorded as the valley period T of the PFC circuit inductor current discontinuity time. zcd , select the time interval between the second valley point signal and the third valley point signal as the valley period T of the PFC circuit inductor current discontinuity time zcd , in order to reduce the possibility of false detection.

[0078] In the embodiment of the present invention, the current switching cycle conduction time T of the switching device is calculated. on The steps include: When the number of inductor current valleys increases in the current switching cycle corresponding to the PFC circuit switching device, the on-time of the switching device is increased; When the current switching cycle corresponding to the PFC circuit switching device reduces the number of inductor current valleys, the on-time of the switching device is reduced.

[0079] In the embodiment of the present invention, when the number of valleys of the intermittent time added in the current switching cycle is one, the current switching cycle conduction time T of the switching device of the PFC circuit is calculated and obtained. on The expression is: , Among them, T on is the current switching cycle conduction time of the PFC circuit switch device, T on_base is the basic conduction time of the PFC circuit switch device, T sw is the previous switching cycle corresponding to the PFC circuit switch device, T power is the total time of inductor excitation and demagnetization in the previous switching cycle of the PFC circuit, T zcd It is the intermittent valley period of the inductor current in the PFC circuit; When the number of valleys of the intermittent time of the current switching cycle is reduced to one, the current switching cycle conduction time T of the switching device of the PFC circuit is calculated and obtained. on The expression is: , Among them, T on is the current switching cycle conduction time of the PFC circuit switch device, T on_base is the basic conduction time of the PFC circuit switch device, T sw is the previous switching cycle corresponding to the PFC circuit switch device, T power is the total time of inductor excitation and demagnetization in the previous switching cycle of the PFC circuit, T zcd It is the intermittent valley period of the inductor current in the PFC circuit.

[0080] In other embodiments, the current switching cycle on time of the PFC circuit switch device is calculated and obtained according to actual needs.

[0081] The present invention further provides a PFC circuit controller, including the above-mentioned control method of a PFC circuit, including: Sampling unit, used to obtain the instantaneous value of input voltage Vac and bus voltage value V bus , bus voltage reference value V bus_ref ; an acquisition unit, configured to acquire a maximum expected switching cycle and a minimum expected switching cycle, wherein the maximum expected switching cycle is greater than the minimum expected switching cycle, and the maximum expected switching cycle and the minimum expected switching cycle are acquired based on a basic on-time of a switching device of a PFC circuit; and acquire a previous switching cycle of a PFC circuit in a DCM mode and a number of valleys of an inductor current discontinuous time in the previous switching cycle; The comparison and adjustment unit is used to compare the size of the previous switching cycle with the maximum expected switching cycle and the minimum expected switching cycle according to the information acquired by the acquisition unit; when the previous switching cycle is greater than the maximum expected switching cycle, control the current switching cycle corresponding to the PFC circuit switch device to reduce the number of valleys of the inductor current discontinuous time, wherein when the number of valleys of the inductor current discontinuous time is one, the PFC circuit enters the CRM mode, and when the number of valleys of the inductor current discontinuous time is greater than one, the PFC circuit enters the DCM mode; when the previous switching cycle is less than the minimum expected switching cycle, control the current switching cycle corresponding to the PFC circuit switch device to increase the number of valleys of the inductor current discontinuous time.

[0082] In an embodiment of the present invention, the PFC circuit controller further includes: The on-time adjustment unit pre-compensates the on-time of the PFC circuit switch device at the valley switching moment to obtain the on-time of the current switching cycle of the PFC circuit switch device.

[0083] The present invention also provides a chip, comprising the PFC circuit controller as described above.

[0084] Specifically, the functions of each pin of the chip are: ZCD: trough detection, obtain trough point, obtain trough point signal; VAC: obtaining an input voltage sampling value, which is used as the input voltage instantaneous value; VBUS: Get the bus voltage value.

[0085] The control chip U receives the signals required for implementing the control method of the present application through the above pins, and controls the PFC circuit accordingly.

[0086] The present invention also provides a circuit, such as Fig.14 As shown, it includes a PFC circuit and the above-mentioned PFC circuit controller; One end of the first capacitor C1 is connected to the first inductor L1 and one end of the input voltage, and the other end of the first capacitor C1 is connected to one end of the second inductor L2 and the input voltage V ac The other end of the first inductor L1 is connected to the anode of the first diode D1, the cathode of the fourth diode D4, the anode of the sixth diode D6, and the other end of the first inductor L1. The other end of the second capacitor C2 is connected to the anode of the third diode D3, the cathode of the second diode D2, the anode of the seventh diode D7, and the other end of the second inductor L2. The cathode of the first diode D1 is connected to the cathode of the third diode D3, the first end of the common-mode inductor L, and one end of the third capacitor C3. The third end of the common-mode inductor L is connected to the drain of the switching device Q and the anode of the fifth diode D5. The cathode of the fifth diode D5 is connected to one end of the fourth capacitor C4 and the resistor R load The anode of the fourth diode D4 is connected to the anode of the second diode D2, the other end of the third capacitor C3, and the resistor R cs one end of the fourth capacitor C4, the other end of the resistor R load The other end of the first resistor R1 is connected to the other end of the second resistor R2 and the ground, and the other end of the first resistor R1 is connected to the other end of the second resistor R2 and the VBU interface of the PFC circuit controller. csThe other end of the seventh diode is connected to the source of the switch device Q and the VCS interface of the PFC circuit controller, and the cathode of the seventh diode is connected to the cathode of the sixth diode and the resistor R ac1 One end of the resistor R ac1 The other end of the resistor R ac2 One end of the resistor R is connected to the VAC interface of the PFC circuit controller; ac2 The other end of the common mode inductor L is connected to the ground, the gate of the switch device Q is connected to the Q interface of the PFC circuit controller, and the second end of the common mode inductor L is connected to the resistor R zcd1 The fourth end of the common mode inductor L is grounded, and the resistor R zcd1 The other end of the resistor R zcd2 One end of the PFC circuit controller is connected to the ZCD interface of the PFC circuit controller, and the resistor R zcd2 The other end is grounded.

[0087] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the claims attached to this application.

Claims

1. A control method for a PFC circuit, characterized in that: include: Acquire a maximum expected switching period and a minimum expected switching period based on a basic on-time of a switching device of a PFC circuit, wherein the maximum expected switching period is greater than the minimum expected switching period; Obtaining the last switching cycle of the PFC circuit and the number of valleys of the inductor current discontinuous time in the last switching cycle, and comparing the last switching cycle with the maximum expected switching cycle and the minimum expected switching cycle; When the previous switching cycle is greater than the maximum expected switching cycle, the current switching cycle corresponding to the PFC circuit switch device is controlled to reduce the number of valleys of the inductor current discontinuous time, wherein when the number of valleys of the inductor current discontinuous time is one, the PFC circuit enters the CRM mode, and when the number of valleys of the inductor current discontinuous time is greater than one, the PFC circuit enters the DCM mode; When the previous switching cycle is less than the minimum expected switching cycle, the current switching cycle corresponding to the PFC circuit switch device is controlled to increase the number of valleys of the inductor current discontinuous time.

2. The control method of the PFC circuit according to claim 1, characterized in that: Get the maximum expected switching period T ref_sub and the minimum expected switching period T ref_add The steps include: Obtain the basic on-time of the PFC circuit switch device; The bus voltage value and the instantaneous value of the input voltage are obtained, and the real-time switching cycle of the PFC circuit in the CRM mode is obtained based on the basic on-time of the switching device of the PFC circuit, the bus voltage value, and the instantaneous value of the input voltage. The expression of the real-time switching cycle of the PFC circuit in the CRM mode is: ， ， Among them, V ac is the instantaneous value of the input voltage, V bus is the bus voltage value, T on_base is the basic conduction time of the PFC circuit switch device, T dem is the inductor demagnetization time, T CRM is the real-time switching cycle of the PFC circuit in CRM mode; An inverse relationship between the minimum expected switching period and the real-time switching period of the PFC circuit in the CRM mode is established based on the real-time switching period of the PFC circuit in the CRM mode to obtain the minimum expected switching period; A first offset is obtained, and based on the first offset and the minimum expected switching period, the minimum expected switching period and the first offset are added to obtain the maximum expected switching period.

3. The control method of the PFC circuit according to claim 2, characterized in that: The expression for establishing the inverse relationship between the minimum expected switching period and the real-time switching period of the PFC circuit in the CRM mode is: ， T ref_add ≥T ref_min ， Where k is a negative number, b is a positive number, T ref_min Allow the minimum switching cycle for the system.

4. The control method of the PFC circuit according to claim 1, characterized in that: It also includes further adjusting the minimum expected switching period and the maximum expected switching period, wherein, when the input voltage slope is less than 0, a second offset is superimposed on the minimum expected switching period and the maximum expected switching period to obtain a second minimum expected switching period and a second maximum expected switching period, which are respectively used as the minimum expected switching period of the switching device of the PFC circuit and the maximum expected switching period of the switching device.

5. The control method of the PFC circuit according to claim 1, characterized in that: The method further includes pre-compensating the on-time of the PFC circuit switch device at the valley switching moment to obtain the switch cycle on-time of the PFC circuit switch device, wherein the step of obtaining the current switch cycle on-time of the PFC circuit switch device includes: Obtain the last switching cycle corresponding to the PFC circuit switch device, the total time of inductor excitation and demagnetization in the last switching cycle of the PFC circuit, the valley period of the PFC circuit inductor current discontinuity time, and the basic conduction time of the PFC circuit switch device; Based on the number of valleys of the inductor current discontinuous time that is reduced or increased in the current switching cycle, the current switching cycle on time of the PFC circuit switch device is calculated.

6. The control method of the PFC circuit according to claim 5, characterized in that: When the number of valleys of the current switching cycle that reduces the discontinuous time is one, the expression for calculating the on-time of the current switching cycle of the PFC circuit switch device is: ， Among them, T on is the current switching cycle conduction time of the PFC circuit switch device, T on_base is the basic conduction time of the PFC circuit switch device, T sw is the previous switching cycle corresponding to the PFC circuit switch device, T power is the total time of inductor excitation and demagnetization in the previous switching cycle of the PFC circuit, T zcd It is the valley period of the PFC circuit inductor current discontinuity time; When the number of valleys of the intermittent time added in the current switching cycle is one, the expression for calculating the conduction time of the current switching cycle of the PFC circuit switch device is: ， Among them, T on is the current switching cycle conduction time of the PFC circuit switch device, T on_base is the basic conduction time of the PFC circuit switch device, T sw is the previous switching cycle corresponding to the PFC circuit switch device, T power is the total time of inductor excitation and demagnetization in the previous switching cycle of the PFC circuit, T zcd It is the valley period of the PFC circuit inductor current discontinuity time.

7. A PFC circuit controller using the PFC circuit control method according to any one of claims 1 to 6, characterized in that: include: an acquisition unit, configured to acquire a maximum expected switching cycle and a minimum expected switching cycle, wherein the maximum expected switching cycle is greater than the minimum expected switching cycle, and the maximum expected switching cycle and the minimum expected switching cycle are acquired based on a basic on-time of a switching device of a PFC circuit; and acquire a previous switching cycle of the PFC circuit and the number of valleys of the discontinuous time of the inductor current in the previous switching cycle; The comparison and adjustment unit is used to compare the size of the previous switching cycle with the maximum expected switching cycle and the minimum expected switching cycle according to the information acquired by the acquisition unit; when the previous switching cycle is greater than the maximum expected switching cycle, control the current switching cycle corresponding to the PFC circuit switch device to reduce the number of valleys of the inductor current discontinuous time, wherein when the number of valleys of the inductor current discontinuous time is one, the PFC circuit enters the CRM mode, and when the number of valleys of the inductor current discontinuous time is greater than one, the PFC circuit enters the DCM mode; when the previous switching cycle is less than the minimum expected switching cycle, control the current switching cycle corresponding to the PFC circuit switch device to increase the number of valleys of the inductor current discontinuous time.

8. A PFC circuit controller according to claim 7, characterized in that: Also includes: The on-time adjustment unit pre-compensates the on-time of the PFC circuit switch device at the valley switching moment to obtain the on-time of the current switching cycle of the PFC circuit switch device.

9. A chip, characterized in that: Comprising a PFC circuit controller as claimed in claim 7.

10. A circuit, characterized in that: The invention comprises a PFC circuit and a PFC circuit controller as claimed in claim 7.

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