Double-feedback branch current compensation type charge pump circuit

Abstract

A double-feedback branch current compensation type charge pump circuit comprises a core circuit, a double-feedback branch and a bias circuit which are connected in sequence, an input node of the double-feedback branch is connected with the core circuit and used for detecting potential change of output voltage, a first output node of a first feedback branch in the double-feedback branch is connected with a grid electrode of the bias circuit, and a second output node of a second feedback branch in the double-feedback branch is connected with a grid electrode of the bias circuit. And a second output node of the second feedback branch is connected with the biasing circuit, and the upper and lower charging and discharging currents are subjected to staged current compensation through the biasing circuit according to the degree that the output voltage deviates from the central potential. The problem of mismatch of upper and lower charge and discharge currents when the output voltage deviates from the central potential is solved through the double feedback branches, the phase error output by the phase frequency detector can be converted into the difference of the charge and discharge currents, and the loop filter is charged and discharged to generate the control voltage of the voltage-controlled oscillator, so that the voltage-controlled oscillator can be controlled within a wide control voltage range. And relatively low charge and discharge mismatch is realized, relatively small ripples on output voltage are realized, and the jitter performance of an output clock of the phase-locked loop is optimized.

Description

Technical Field

[0001] The present invention relates to a technology in the field of phase-locked loop, in particular to a double-feedback branch current compensation type charge pump circuit. Background Art

[0002] Due to the channel length modulation effect of the charge pump, as the control voltage deviates more from the center potential, the mismatch between the upper and lower charging and discharging current sources also increases. Summary of the invention

[0003] In view of the fact that the current compensation of the prior art is insufficient when the output voltage deviates from the center potential to a large extent, the present invention proposes a dual-feedback branch current compensation type charge pump circuit, which solves the mismatch problem of the upper and lower charging and discharging currents when the output voltage deviates from the center potential through the dual feedback branches, can convert the phase error output by the frequency detector and phase detector into the difference between the charging and discharging currents, charge and discharge the loop filter to generate the control voltage of the voltage-controlled oscillator, thereby achieving lower charging and discharging current mismatch and smaller ripple on the output voltage within a wider control voltage range, and optimizing the jitter performance of the phase-locked loop output clock.

[0004] The present invention is achieved through the following technical solutions:

[0005] The present invention relates to a dual-feedback branch current compensation type charge pump circuit, comprising: a core circuit, a dual feedback branch and a bias circuit connected in sequence, wherein: an input node of the dual feedback branch is connected to the core circuit for detecting a potential change of an output voltage, a first output node of a first feedback branch in the dual feedback branch is connected to a gate of a bias circuit, and a second output node of a second feedback branch is connected to a bias circuit, and according to the degree to which the output voltage deviates from a central potential, current compensation is performed in stages on upper and lower charge and discharge currents through the bias circuit. Technical Effects

[0006] The present invention adopts a dual feedback branch to perform current compensation on the charge and discharge current of the charge pump, and divides the compensation process into two stages according to the degree to which the output voltage deviates from the center potential, and compensates the charge and discharge current in stages. When the output voltage deviates from the center potential to a small extent, part of the circuit of the feedback branch is in a shut-off state, and compensation is performed only through part of the feedback branch; when the output voltage deviates from the center potential to a large extent, part of the circuit of the feedback branch is turned on, increasing the degree of compensation for the charge and discharge current. Staged compensation not only saves the power consumption of the overall circuit, but also realizes more accurate current compensation. Compared with the prior art, the present invention realizes that the output voltage of the charge pump is within the range of 0.1-0.8V, and the maximum tran mismatch of the upper and lower charge and discharge currents is less than 300nA under the conditions that the power supply voltage is 0.9V and the charge pump current Icp is 65uA. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of a charge pump circuit of the present invention;

[0008] In the figure: the red line is the first feedback branch, and the blue line is the second feedback branch;

[0009] Figure 2 This is a schematic diagram of a rail-to-rail input operational amplifier;

[0010] Figure 3 It is a schematic diagram of the TRAN_mismatch simulation effect under the condition of TT_0.9V_27℃. DETAILED DESCRIPTION

[0011] like Figure 1 As shown, this embodiment relates to a dual-feedback branch current compensation type charge pump circuit, including: a first feedback branch, a second feedback branch, a core circuit and a bias circuit, wherein: the gate of the tenth PMOS tube M10 in the bias circuit is connected to the gate of the nineteenth PMOS tube M19 in the core circuit and the second output node of the second feedback branch, the gate of the eighth NMOS tube M8 in the bias circuit is connected to the gate of the twentieth NMOS tube M20 in the core circuit and the first output node of the first feedback branch, and the input node of the dual feedback branch is connected to the node of the left branch in the core circuit located between the first transmission gate TG1 and the third transmission gate TG3.

[0012] The bias circuit includes: six NMOS tubes M0-M3, M7, M8, five PMOS tubes M4-M6, M9, M10 and two resistors R1, R2, wherein: the bias current input terminal i_bias is connected to one end of the first resistor R1, the gate of the zeroth NMOS tube M0 and the gate of the seventh NMOS tube M7, the other end of the first resistor R1 is connected to the gate of the first NMOS tube M1, the gate of the second NMOS tube M2, the gate of the third NMOS tube M3 and the drain of the zeroth NMOS tube, the source of the zeroth NMOS tube is connected to the drain of the first NMOS tube M1, the drain of the second NMOS tube M2 is connected to the gate of the fourth PMOS tube, the gate of the ninth PMOS tube The gate of the S tube is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the gate of the fifth PMOS tube M5, the gate of the sixth PMOS tube M6 and the drain of the fourth PMOS tube M4, the source of the fourth PMOS tube M4 is connected to the drain of the fifth PMOS tube M5, the drain of the sixth PMOS tube M6 is connected to the drain of the seventh NMOS tube and the gate of the eighth NMOS tube M8, the drain of the third NMOS tube M3 is connected to the drain of the ninth PMOS tube M9 and the gate of the tenth PMOS tube, the source of the ninth PMOS tube M9 is connected to the drain of the tenth PMOS tube M10, and the source of the seventh NMOS tube M7 is connected to the drain of the eighth NMOS tube.

[0013] The core circuit includes: four transmission gates TG1, TG2, TG3, TG4, a rail-to-rail input operational amplifier, a third rail-to-rail input operational amplifier, a twentieth NMOS tube M20 and a nineteenth PMOS tube M19, wherein: the drain of the nineteenth NMOS tube is connected to the first transmission gate TG1 and one end of the second transmission gate TG2, the other end of the first transmission gate TG1 is connected to the output end and the reverse input end of the third rail-to-rail input operational amplifier OP3 and one end of the third transmission gate, the other end of the second transmission gate TG2 is connected to the positive input end and the output end VC of the third rail-to-rail input operational amplifier and one end of the fourth transmission gate TG4, and the other ends of the third transmission gate TG3 and the fourth transmission gate TG4 are connected to the drain of the twentieth NMOS tube. The forward control end of the first transmission gate TG1 is connected to the reverse control end of the second transmission gate TG2 and the switch signal input end UPB, the forward control end of the third transmission gate TG3 is connected to the reverse control end of the fourth transmission gate TG4 and the switch signal input end DNB, the switch signal input end UP is connected to the reverse control end of the first transmission gate TG1 and the forward control end of the second transmission gate TG2, and the switch signal input end DN is connected to the reverse control end of the third transmission gate TG3 and the forward control end of the fourth transmission gate TG4.

[0014] The first feedback branch includes: a first rail-to-rail input operational amplifier, two PMOS tubes M14 and M16, and two NMOS tubes M12 and M13, wherein: the second output node is connected to the gate of the fourteenth PMOS tube M14 and the drain of the sixteenth PMOS tube M16, the input node is connected to the gate of the sixteenth PMOS tube M16 and the positive input terminal of the first rail-to-rail input operational amplifier, the source of the fourteenth PMOS tube M14 is connected to the reverse input terminal and the output terminal of the first rail-to-rail input operational amplifier, the drain of the fourteenth PMOS tube M14 is connected to the gate and drain of the thirteenth NMOS tube M13 and the gate of the twelfth NMOS tube M12, and the drain of the twelfth NMOS tube M12 is connected to the first output node.

[0015] The second feedback branch includes: a second rail-to-rail input operational amplifier, two PMOS tubes M11 and M17, and two NMOS tubes M15 and M18, wherein: the first output node is connected to the gate of the eighteenth PMOS tube M18 and the drain of the fifteenth NMOS tube M15, the input node is connected to the gate of the fifteenth NMOS tube M15 and the positive input terminal of the second rail-to-rail input operational amplifier, the source of the eighteenth NMOS tube M18 is connected to the reverse input terminal and the output terminal of the second rail-to-rail input operational amplifier, the drain of the eighteenth NMOS tube M18 is connected to the gate and drain of the seventeenth PMOS tube M17 and the gate of the eleventh PMOS tube M11, and the drain of the eleventh PMOS tube M11 is connected to the second output node.

[0016] like Figure 2 As shown, the rail-to-rail input operational amplifier includes: a bias structure and a folded common-source amplifier circuit connected thereto, wherein: the gate and drain of the twenty-fifth PMOS tube M25 in the bias structure are connected to the gate of the twenty-sixth PMOS tube M26 and the gate of the thirty-eighth PMOS tube M38 in the folded common-source amplifier circuit, and the gate of the twenty-fourth NMOS tube M24 in the bias structure is connected to the gate of the thirty-first NMOS tube M31 in the folded common-source amplifier circuit.

[0017] The bias structure includes three PMOS tubes M22, M23, and M25 and two NMOS tubes M21 and M24, wherein: the drain and gate of the twenty-first NMOS tube M21 are connected to the gate of the twenty-fourth NMOS tube and the drain of the twenty-second PMOS tube, the gate of the twenty-second PMOS tube is connected to the gate and ground of the twenty-third PMOS tube M23, the drain of the twenty-third PMOS tube M23 is connected to the source of the twenty-second PMOS tube M22, and the drain of the twenty-fourth NMOS tube M24 is connected to the drain and gate of the twenty-fifth PMOS tube M25.

[0018] The folded common source amplifier circuit comprises: six NMOS tubes M29-M31, M34, M35, M39, eight PMOS tubes M26-M28, M22, M23, M36-M38, a zero adjustment resistor R, and a Miller compensation capacitor C, wherein: the drain of the twenty-sixth PMOS tube M26 is connected to the source of the twenty-seventh PMOS tube M27 and the twenty-eighth PMOS tube M28, the drain of the thirty-first NMOS tube M31 is connected to the source of the twenty-ninth PMOS tube M29 and the thirtieth PMOS tube M30, the positive input terminal VINP is connected to the gate of the twenty-eighth PMOS tube M28 and the twenty-ninth NMOS tube M29, the reverse input terminal is connected to the gate of the twenty-seventh PMOS tube M27 and the thirtieth NMOS tube M30, the drain of the twenty-seventh PMOS tube M27 is connected to the source of the thirty-second PMOS tube M31, The drain of the twenty-eighth PMOS tube M28 is connected to the drain of the thirty-seventh PMOS tube M37, the drain of the thirty-fifth NMOS tube M35, one end of the zero adjustment resistor R, and the gate of the thirty-ninth NMOS tube M39. The drain of the twenty-ninth PMOS tube M29 is connected to the gate of the thirty-second PMOS tube M32 and the drain and gate of the thirty-third PMOS tube M33. The drain of the thirtieth PMOS tube M30 is connected to the gate of the thirty-seventh PMOS tube M37 and the drain and gate of the thirty-sixth PMOS tube M36. The other end of the zero adjustment resistor R is connected to one end of the Miller compensation capacitor C. The other end of the Miller compensation capacitor C is connected to the drain of the thirty-ninth NMOS tube M39, the drain of the thirty-eighth PMOS tube M38, and the output end VOUT.

[0019] The voltage regulation method of the present embodiment based on the above circuit includes:

[0020] Step 1, when the power supply voltage is 0.9V and the output voltage is in the range of 0.3-0.7V, the voltage followers in the two potential detection circuits detect the potential of the second node, and the potential of the second node first follows the node, that is, the output potential, so the potential of the third node and the fourth node first follows the node change. At this time, the fourteenth PMOS tube M14 and the eighteenth PMOS tube M18 are turned off, the fifteenth NMOS tube M15 and the sixteenth PMOS tube M16 are turned on, and the gate potential of the fifteenth NMOS tube M15 and the sixteenth PMOS tube M16 first follows the potential change of the node, and the fifteenth NMOS tube M15 and the sixteenth PMOS tube M16 respectively extract the current of M8 and the tenth PMOS tube M10, which is equivalent to the sixteenth PMOS tube M16 and the fifteenth NMOS tube M15 extracting the upper and lower charging and discharging currents respectively. When the output voltage is lower than the center potential, due to the channel length modulation effect, the charging current is greater than the discharging current. At this time, the gate voltages of the fifteenth NMOS tube M15 and the sixteenth PMOS tube M16 follow the output potential, and the Vgs of the fifteenth NMOS tube M15 is less than the Vgs of the sixteenth PMOS tube M16, so that the current I of the fifteenth NMOS tube M15 is less than the current I of the sixteenth PMOS tube M16. At this time, the extraction degree of the charging current by the sixteenth PMOS tube M16 is greater than the extraction degree of the discharging current by the fifteenth NMOS tube M15. The difference between the current I of the sixteenth PMOS tube M16 and the current I of the fifteenth NMOS tube M15 is used to compensate the charging and discharging currents. When the output voltage is higher than the center potential, the principle is similar.

[0021] Step 2, when the output voltage is in the range of 0.1-0.2V or 0.7-0.8V, since the third node and the fourth node follow the change of the first node, that is, the output potential, at this time, the fifteenth NMOS tube M15 and the sixteenth PMOS tube M16 are turned on, and the fourteenth PMOS tube M14 or the eighteenth PMOS tube M18 is turned on. While the fifteenth NMOS tube M15 and the sixteenth PMOS tube M16 perform charge and discharge current compensation as described in step 1, the conduction of the fourteenth PMOS tube M14 or the eighteenth PMOS tube M18 enables one of the two current mirrors of the twelfth and thirteenth NMOS tubes M13 and M12 and the seventeenth and eleventh PMOS tubes M17 and M11 to work, and the current of the eighth NMOS tube M8 or the tenth PMOS tube M10 is extracted to perform current compensation. When the output voltage is between 0.1 and 0.2 V, due to the channel length modulation effect, the charging current is greater than the discharging current, and the current extraction of the fifteenth NMOS tube M15 and the sixteenth PMOS tube M16 is insufficient to compensate for the difference between the charging and discharging currents. At this time, the fourteenth PMOS tube M14 is turned off, and the eighteenth PMOS tube M18 is turned on, so that the current mirror group of M11 and the seventeenth PMOS tube M17 also extracts the current of the tenth PMOS tube M10 to further compensate for the difference between the charging and discharging currents. When the output voltage is between 0.7 and 0.8 V, the principle is similar.

[0022] like Figure 3 As shown, after specific actual experiments, under the conditions of TT_0.9V_27℃ and charge pump current Icp of 65A, the overall circuit is simulated by TRAN, the output voltage is scanned from 0.1V to 0.8V, and the upper and lower charge and discharge currents are sampled. It can be obtained that the output voltage is in the range of 0.1-0.8V, and the maximum mismatch of charge and discharge current is less than 300nA.

[0023] Compared with the prior art, the present invention adopts a dual feedback branch current compensation architecture to detect the potential change of the output voltage in real time, and then performs staged current compensation for the upper and lower charging and discharging currents through the dual feedback branches according to the degree to which the output voltage deviates from the center potential, thereby achieving a smaller current mismatch between the upper and lower charging and discharging currents within a larger output voltage range.

[0024] The above-mentioned specific implementation can be partially adjusted in different ways by those skilled in the art without departing from the principle and purpose of the present invention. The protection scope of the present invention shall be based on the claims and shall not be limited by the above-mentioned specific implementation. Each implementation scheme within its scope shall be subject to the constraints of the present invention.

Claims

1. A dual feedback branch current compensation type charge pump circuit, characterized in that: include: A core circuit, a dual feedback branch and a bias circuit are connected in sequence, wherein: an input node of the dual feedback branch is connected to the core circuit for detecting a potential change of an output voltage, a first output node of a first feedback branch in the dual feedback branch is connected to a gate of a bias circuit, and a second output node of a second feedback branch is connected to a bias circuit. According to the degree to which the output voltage deviates from a center potential, current compensation is performed in stages on upper and lower charge and discharge currents through a bias circuit.

2. The dual feedback branch current compensation type charge pump circuit according to claim 1, characterized in that: The bias circuit includes: six NMOS tubes, five PMOS tubes and two resistors, wherein: the bias current input terminal i_bias is connected to one end of the first resistor, the gate of the zeroth NMOS tube and the gate of the seventh NMOS tube, the other end of the first resistor is connected to the gate of the first NMOS tube, the gate of the second NMOS tube, the gate of the third NMOS tube and the drain of the zeroth NMOS tube, the source of the zeroth NMOS tube is connected to the drain of the first NMOS tube, the drain of the second NMOS tube is connected to the gate of the fourth PMOS tube, the gate of the ninth PMOS tube and the drain of the One end of the second resistor is connected to the gate of the fifth PMOS tube, the gate of the sixth PMOS tube and the drain of the fourth PMOS tube, the source of the fourth PMOS tube is connected to the drain of the fifth PMOS tube, the drain of the sixth PMOS tube is connected to the drain of the seventh NMOS tube and the gate of the eighth NMOS tube, the drain of the third NMOS tube is connected to the drain of the ninth PMOS tube and the gate of the tenth PMOS tube, the source of the ninth PMOS tube is connected to the drain of the tenth PMOS tube, and the source of the seventh NMOS tube is connected to the drain of the eighth NMOS tube.

3. The dual feedback branch current compensation type charge pump circuit according to claim 2, characterized in that: The core circuit includes: four transmission gates, a rail-to-rail input operational amplifier, a third rail-to-rail input operational amplifier, a twentieth NMOS tube and a nineteenth PMOS tube, wherein: the drain of the nineteenth NMOS tube is connected to the first transmission gate and one end of the second transmission gate, the other end of the first transmission gate is connected to the output end, the reverse input end and one end of the third rail-to-rail input operational amplifier, the other end of the second transmission gate is connected to the positive input end, the output end VC and one end of the fourth transmission gate of the third rail-to-rail input operational amplifier, the other ends of the third transmission gate and the fourth transmission gate are connected to the drain of the twentieth NMOS tube, the forward control end of the first transmission gate is connected to the reverse control end and the switch signal input end of the second transmission gate, the forward control end of the third transmission gate is connected to the reverse control end and the switch signal input end of the fourth transmission gate, the switch signal input end is connected to the reverse control end of the first transmission gate and the forward control end of the second transmission gate, and the switch signal input end is connected to the reverse control end of the third transmission gate and the forward control end of the fourth transmission gate.

4. The dual feedback branch current compensation type charge pump circuit according to any one of claims 1 to 3, characterized in that: The first feedback branch includes: a first rail-to-rail input operational amplifier, two PMOS tubes, and two NMOS tubes, wherein: the second output node is connected to the gate of the fourteenth PMOS tube and the drain of the sixteenth PMOS tube, the input node is connected to the gate of the sixteenth PMOS tube and the positive input terminal of the first rail-to-rail input operational amplifier, the source of the fourteenth PMOS tube is connected to the reverse input terminal and the output terminal of the first rail-to-rail input operational amplifier, the drain of the fourteenth PMOS tube is connected to the gate and drain of the thirteenth NMOS tube and the gate of the twelfth NMOS tube, and the drain of the twelfth NMOS tube is connected to the first output node; The second feedback branch includes: a second rail-to-rail input operational amplifier, two PMOS tubes, and two NMOS tubes, wherein: the first output node is connected to the gate of the eighteenth PMOS tube and the drain of the fifteenth NMOS tube, the input node is connected to the gate of the fifteenth NMOS tube and the positive input terminal of the second rail-to-rail input operational amplifier, the source of the eighteenth NMOS tube is connected to the reverse input terminal and the output terminal of the second rail-to-rail input operational amplifier, the drain of the eighteenth NMOS tube is connected to the gate and drain of the seventeenth PMOS tube and the gate of the eleventh PMOS tube, and the drain of the eleventh PMOS tube is connected to the second output node.

5. The dual feedback branch current compensation type charge pump circuit according to claim 4, characterized in that: The rail-to-rail input operational amplifier includes: a bias structure and a folded common-source amplifier circuit connected thereto, wherein: the gate and drain of the twenty-fifth PMOS tube in the bias structure are connected to the gate of the twenty-sixth PMOS tube and the gate of the thirty-eighth PMOS tube in the folded common-source amplifier circuit, and the gate of the twenty-fourth NMOS tube in the bias structure is connected to the gate of the thirty-first NMOS tube in the folded common-source amplifier circuit.

6. The dual-feedback branch current compensation type charge pump circuit according to claim 5, characterized in that: The bias structure includes three PMOS tubes and two NMOS tubes, wherein: the drain and gate of the twenty-first NMOS tube are connected to the gate of the twenty-fourth NMOS tube and the drain of the twenty-second PMOS tube, the gate of the twenty-second PMOS tube is connected to the gate and ground of the twenty-third PMOS tube, the drain of the twenty-third PMOS tube is connected to the source of the twenty-second PMOS tube, and the drain of the twenty-fourth NMOS tube is connected to the drain and gate of the twenty-fifth PMOS tube.

7. The dual-feedback branch current compensation type charge pump circuit according to claim 5, characterized in that: The folded common source amplifier circuit comprises: six NMOS tubes, eight PMOS tubes, a zero adjustment resistor and a Miller compensation capacitor, wherein: the drain of the twenty-sixth PMOS tube is connected to the source of the twenty-seventh PMOS tube and the twenty-eighth PMOS tube, the drain of the thirty-first NMOS tube is connected to the source of the twenty-ninth PMOS tube and the thirtieth PMOS tube, the positive input terminal VINP is connected to the gate of the twenty-eighth PMOS tube and the twenty-ninth NMOS tube, the reverse input terminal is connected to the gate of the twenty-seventh PMOS tube and the thirtieth NMOS tube, the drain of the twenty-seventh PMOS tube is connected to the drain of the thirty-second PMOS tube and the thirty-fourth NMOS tube The gate and drain of the twenty-eighth PMOS tube are connected, the drain of the thirty-seventh PMOS tube, the drain of the thirty-fifth NMOS tube, one end of the zero adjustment resistor, and the gate of the thirty-ninth NMOS tube, the drain of the twenty-ninth PMOS tube is connected to the gate of the thirty-second PMOS tube, the drain and the gate of the thirty-third PMOS tube, the drain of the 30th PMOS tube is connected to the gate of the thirty-seventh PMOS tube, the drain and the gate of the thirty-sixth PMOS tube, the other end of the zero adjustment resistor is connected to one end of the Miller compensation capacitor, and the other end of the Miller compensation capacitor is connected to the drain of the thirty-ninth NMOS tube, the drain of the thirty-eighth PMOS tube, and the output end.

8. A voltage regulation method based on the dual feedback branch current compensation type charge pump circuit according to any one of claims 1 to 7, characterized in that: include: Step 1, when the power supply voltage is 0.9V and the output voltage is in the range of 0.3-0.7V, the voltage followers in the two potential detection circuits detect the potential of the second node, and the potential of the second node first follows the node, that is, the output potential. Therefore, the potential of the third node and the fourth node first follows the node change. At this time, the fourteenth PMOS tube and the eighteenth PMOS tube are turned off, the fifteenth NMOS tube and the sixteenth PMOS tube are turned on, and the gate potential of the fifteenth NMOS tube and the sixteenth PMOS tube first follows the potential change of the node, and the fifteenth NMOS tube and the sixteenth PMOS tube respectively extract the current of the tenth PMOS tube, which is equivalent to the sixteenth PMOS tube and the fifteenth NMOS tube. The upper and lower charging and discharging currents are extracted respectively. When the output voltage is lower than the center potential, due to the channel length modulation effect, the charging current is greater than the discharging current. At this time, the gate voltages of the fifteenth NMOS tube and the sixteenth PMOS tube follow the output potential, and the Vgs of the fifteenth NMOS tube is less than the Vgs of the sixteenth PMOS tube, so that the current of the fifteenth NMOS tube is less than the current of the sixteenth PMOS tube. At this time, the extraction degree of the charging current by the sixteenth PMOS tube is greater than the extraction degree of the discharging current by the fifteenth NMOS tube. The difference between the current of the sixteenth PMOS tube and the current of the fifteenth NMOS tube is used to compensate the charging and discharging currents. When the output voltage is higher than the center potential, the principle is similar. Step 2, when the output voltage is in the range of 0.1-0.2V or 0.7-0.8V, since the third node and the fourth node follow the change of the first node, that is, the output potential, at this time, the fifteenth NMOS tube and the sixteenth PMOS tube are turned on, and the fourteenth PMOS tube or the eighteenth PMOS tube is turned on. While the fifteenth NMOS tube and the sixteenth PMOS tube perform charge and discharge current compensation, the conduction of the fourteenth PMOS tube or the eighteenth PMOS tube makes the twelfth and thirteenth NMOS tubes and the seventeenth and eleventh PMOS tubes and one of the two current mirrors work, and the eighth NMOS tube Or the current of the tenth PMOS tube is extracted to perform current compensation. When the output voltage is in the range of 0.1-0.2V, due to the channel length modulation effect, the charging current is greater than the discharging current. The current extraction of the fifteenth NMOS tube and the sixteenth PMOS tube is not enough to compensate for the difference between the charging and discharging currents. At this time, the fourteenth PMOS tube is turned off and the eighteenth PMOS tube is turned on, so that the current mirror group with the seventeenth PMOS tube also extracts the current of the tenth PMOS tube to further compensate for the difference between the charging and discharging currents. When the output voltage is in the range of 0.7-0.8V, the principle is similar.

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