Manufacturing method of ETOX NOR flash memory
By using high-temperature thermal oxidation process to form the first side wall structure during the manufacturing process of ETOX NOR flash memory, the bird beak structure problem caused by the rapid thermal annealing process is solved and the device performance is improved.
Patent Information
- Application Number
- CN202510107922.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2025-04-29
AI Technical Summary
During the manufacturing of ETOX NOR flash memory, the rapid thermal annealing process will cause the sharp angle positions of floating gate polysilicon and control gate polysilicon to be peroxidized to form a bird's beak structure, affecting device performance.
The first side wall structure is formed by oxidizing the sides of the storage unit by using a high-temperature thermal oxidation process to avoid peroxidizing the sharp corner positions of the control gate polysilicon layer and the floating gate polysilicon layer, thereby not forming a bird beak structure.
The first side wall structure formed by the high-temperature thermal oxidation process can effectively avoid the formation of the beak structure and improve device performance.
Smart Images
Figure CN119907242A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a method for manufacturing an ETOX NOR flash memory. Background Art
[0002] The storage unit of the ETOX NOR flash memory includes a floating gate polysilicon layer located on the active area and a control gate polysilicon layer formed on the floating gate polysilicon layer, an inter-polysilicon dielectric layer is formed between the floating gate polysilicon layer and the control gate polysilicon layer, and a sidewall structure is formed on the outer surface of the storage unit.
[0003] Related Technology In the process of manufacturing ETOX NOR flash memory, a rapid thermal annealing process is usually used to form the sidewall structure. However, the rapid thermal annealing process will cause the sharp corners of the floating gate polysilicon and the control gate polysilicon to be over-oxidized to form a bird's beak structure, which is not conducive to the performance of the device. Summary of the invention
[0004] The present application provides a method for manufacturing an ETOX NOR flash memory, which can solve the problem in related technologies that the sharp corners of the floating gate polysilicon and the control gate polysilicon are over-oxidized to form a bird's beak structure.
[0005] In order to solve the technical problem in the background technology, the present application provides a method for manufacturing an ETOX NOR flash memory, and the method for manufacturing an ETOX NOR flash memory comprises the following steps:
[0006] providing a semiconductor substrate layer;
[0007] Forming a memory cell on the semiconductor substrate layer, with adjacent memory cells spaced apart, the memory cell comprising a floating gate oxide layer, a floating gate polysilicon layer, an inter-polysilicon dielectric layer and a control gate polysilicon layer stacked in sequence from bottom to top;
[0008] Oxidizing the side surface of the memory cell by a high temperature thermal oxidation process to form a first spacer structure;
[0009] Oxidizing the side surface of the memory cell by a rapid thermal oxidation process to form a second spacer on the first spacer structure;
[0010] Performing rapid thermal annealing on the active area;
[0011] The spaces between adjacent storage cells are filled with a dielectric layer.
[0012] Optionally, a rapid thermal oxidation process is performed at a temperature of 700° C. to 900° C. in an oxidizing atmosphere for 5 seconds to 90 seconds to oxidize the side surfaces of the storage unit to form a second spacer on the first spacer structure.
[0013] Optionally, the thickness of the second side wall is to
[0014] Optionally, the step of oxidizing the side surface of the memory cell by a high temperature thermal oxidation process to form a first spacer structure includes:
[0015] A high temperature thermal oxidation process is performed at a temperature of 700° C. to 900° C. in an oxidizing gas atmosphere for 60 min to 300 min to oxidize the side surfaces of the memory cell to form a first sidewall structure.
[0016] Optionally, the thickness of the first sidewall structure is to
[0017] Optionally, the step of oxidizing the side surface of the memory cell by a high temperature thermal oxidation process to form a first spacer structure includes:
[0018] At a temperature of 700° C. to 900° C., a silicon source gas is introduced to deposit a compensation polysilicon layer on the surface of the memory cell;
[0019] A high temperature thermal oxidation process is performed at a temperature of 700° C. to 900° C. in an oxidizing atmosphere for 60 min to 300 min to form a first sidewall structure on the surface of the compensation polysilicon layer.
[0020] Optionally, the step of performing rapid thermal annealing on the active area includes:
[0021] The active region is subjected to rapid thermal annealing at a temperature of 900° C. to 1200° C. for a period of 5 seconds to 90 seconds in an atmosphere including an inert gas.
[0022] The technical solution of the present application includes at least the following advantages: in this embodiment, the first sidewall structure formed by oxidizing the side of the storage unit through a high-temperature thermal oxidation process can avoid over-oxidation of the side surface of the control gate polysilicon layer and the sharp corners of the side surface of the floating gate polysilicon layer, that is, avoid forming a bird's beak structure, thereby improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0024] Figure 1A flow chart of a method for manufacturing an ETOX NOR flash memory provided by an embodiment of the present application is shown;
[0025] Figure 2 A schematic diagram of the cross-sectional structure of the device after step S2 is completed is shown;
[0026] Figure 3 FIG. 4 shows a schematic diagram of a cross-sectional structure of the device after step S3 is completed. DETAILED DESCRIPTION
[0027] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.
[0028] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0029] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0030] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0031] Figure 1 The flowchart of the manufacturing method of ETOX NOR flash memory provided by an embodiment of the present application is shown. Figure 1 As can be seen, the manufacturing method of the ETOX NOR flash memory includes the following steps:
[0032] Step S1: providing a semiconductor base layer.
[0033] Step S2: forming a memory cell on the semiconductor substrate layer, with adjacent memory cells spaced apart, the memory cell comprising a floating gate oxide layer, a floating gate polysilicon layer, an inter-polysilicon dielectric layer and a control gate polysilicon layer stacked in sequence from bottom to top.
[0034] Figure 2 The schematic diagram of the cross-sectional structure of the device after step S2 is completed is shown. Figure 2 As can be seen in the figure, a memory cell 200 is formed on the semiconductor substrate layer 100, and adjacent memory cells 200 are spaced apart. The memory cell 200 includes a floating gate oxide layer 210, a floating gate polysilicon layer 220, an inter-polysilicon dielectric layer 230, and a control gate polysilicon layer 240 stacked sequentially from bottom to top.
[0035] The inter-polysilicon dielectric layer 230 may be an ONO structure, that is, it includes a lower oxide layer, an upper oxide layer, and a silicon nitride layer located between the upper oxide layer and the lower oxide layer.
[0036] Step S3: oxidizing the side surface of the memory cell by a high temperature thermal oxidation process to form a first spacer structure.
[0037] Figure 3 The schematic diagram of the cross-sectional structure of the device after step S3 is completed is shown. Figure 3 As can be seen in FIG. 1 , after the high temperature thermal oxidation process, a first spacer structure 310 is formed on the side of the memory cell 200. The side surface of the control gate polysilicon layer 240 and the side surface of the floating gate polysilicon layer 220 of the memory cell 200 are oxidized to form the first spacer structure 310.
[0038] The side surfaces of the control gate polysilicon layer and the floating gate polysilicon layer connected to the inter-polysilicon dielectric layer are easily over-oxidized at the corners to form a bird's beak structure. In this embodiment, the first sidewall structure formed by oxidizing the side surfaces of the memory cell by a high-temperature thermal oxidation process can avoid over-oxidation of the side surfaces of the control gate polysilicon layer and the floating gate polysilicon layer at the corners, that is, avoid forming a bird's beak structure, thereby improving device performance.
[0039] For example, the side of the storage unit can be oxidized to form the first spacer structure by a high temperature thermal oxidation process at a temperature of 700° C. to 900° C. in an oxidizing atmosphere for 60 min to 300 min. The thickness of the first spacer structure formed in this embodiment is to
[0040] Exemplarily, step S3 may also be implemented through the following steps S31 to S32:
[0041] Step S31: introducing silicon source gas at a temperature of 700° C. to 900° C., and depositing a compensation polysilicon layer on the surface of the memory cell for a treatment time of 60 min to 300 min.
[0042] Step S32: performing a high temperature thermal oxidation process at a temperature of 700° C. to 900° C. in an oxidizing atmosphere for 60 min to 300 min to form a first sidewall structure on the surface of the compensation polysilicon layer.
[0043] A compensation polysilicon layer is deposited on the surface of the storage unit by silicon source gas in advance, and then a high-temperature thermal oxidation process is performed to form a first sidewall structure to prevent over-oxidation of the side surfaces of the control gate polysilicon layer and the sharp corners of the side surfaces of the floating gate polysilicon layer.
[0044] In other embodiments, after completing step S3, the following steps may be performed before performing step S4:
[0045] The side surface of the memory cell is oxidized by a rapid thermal oxidation process to form a second spacer on the first spacer structure.
[0046] Illustratively, a rapid thermal oxidation process is performed at a temperature of 700° C. to 900° C. in an oxidizing atmosphere for 5 seconds to 90 seconds to oxidize the side surfaces of the storage unit, thereby forming a second spacer on the first spacer structure.
[0047] Although the high temperature thermal oxidation process is relatively stable and can avoid the problem of over-oxidation of the polysilicon corners to form sharp corners, the first sidewall structure formed by the high temperature thermal oxidation process is relatively thin, and the protection of the floating gate polysilicon layer and the control gate polysilicon layer is limited. Therefore, in other embodiments, a rapid thermal oxidation process can be added after the high temperature thermal oxidation process is completed to form a thicker second sidewall. And because the first sidewall structure is formed in advance by the high temperature thermal oxidation process performed first, the subsequent rapid thermal oxidation process will not cause over-oxidation at the sharp corners of the side surface of the control gate polysilicon layer and the side surface of the floating gate polysilicon layer, that is, avoid the formation of a bird's beak structure.
[0048] Step S4: performing rapid thermal annealing on the active region.
[0049] For example, the active region may be subjected to rapid thermal annealing at a temperature of 900° C. to 1200° C. in an atmosphere including an inert gas for a period of 5 seconds to 90 seconds.
[0050] Step S5: filling the spaces between adjacent storage cells with a dielectric layer.
[0051] In this embodiment, the first sidewall structure formed by oxidizing the side of the storage unit through a high-temperature thermal oxidation process can avoid over-oxidation of the sharp corners of the side surface of the control gate polysilicon layer and the side surface of the floating gate polysilicon layer, that is, avoid forming a bird's beak structure, thereby improving device performance.
[0052] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A method for manufacturing an ETOX NOR flash memory, characterized in that: The manufacturing method of the ETOX NOR flash memory comprises the following steps: providing a semiconductor substrate layer; Forming a memory cell on the semiconductor substrate layer, with adjacent memory cells spaced apart, the memory cell comprising a floating gate oxide layer, a floating gate polysilicon layer, an inter-polysilicon dielectric layer and a control gate polysilicon layer stacked in sequence from bottom to top; Oxidizing the side surface of the memory cell by a high temperature thermal oxidation process to form a first spacer structure; Oxidizing the side surface of the memory cell by a rapid thermal oxidation process to form a second spacer on the first spacer structure; Performing rapid thermal annealing on the active area; The spaces between adjacent storage cells are filled with a dielectric layer.
2. The method for manufacturing the ETOX NOR flash memory according to claim 1, wherein: A rapid thermal oxidation process is performed at a temperature of 700° C. to 900° C. in an oxidizing atmosphere for 5 seconds to 90 seconds to oxidize the side surface of the storage unit to form a second spacer on the first spacer structure.
3. The method for manufacturing the ETOX NOR flash memory according to claim 1, wherein: The thickness of the second side wall is to 4. The method for manufacturing the ETOX NOR flash memory according to claim 1, wherein: The step of oxidizing the side surface of the memory cell by a high temperature thermal oxidation process to form a first spacer structure comprises: A high temperature thermal oxidation process is performed at a temperature of 700° C. to 900° C. in an oxidizing gas atmosphere for 60 min to 300 min to oxidize the side surfaces of the memory cell to form a first sidewall structure.
5. The method for manufacturing the ETOX NOR flash memory according to claim 1, wherein: The thickness of the first sidewall structure is to 6. The method for manufacturing the ETOX NOR flash memory according to claim 1, wherein: The step of oxidizing the side surface of the memory cell by a high temperature thermal oxidation process to form a first spacer structure comprises: At a temperature of 700° C. to 900° C., a silicon source gas is introduced to deposit a compensation polysilicon layer on the surface of the memory cell; A high temperature thermal oxidation process is performed at a temperature of 700° C. to 900° C. in an oxidizing atmosphere for 60 min to 300 min to form a first sidewall structure on the surface of the compensation polysilicon layer.
7. The method for manufacturing the ETOX NOR flash memory according to claim 1, wherein: The step of performing rapid thermal annealing on the active area comprises: The active region is subjected to rapid thermal annealing at a temperature of 900° C. to 1200° C. for a period of 5 seconds to 90 seconds in an atmosphere including an inert gas.