A wide bandgap semiconductor composite high-voltage vertical power chip and its manufacturing process

Abstract

This invention discloses a wide-bandgap semiconductor composite high-voltage vertical power chip and its fabrication process. The chip includes at least one cell structure unit, which includes a substrate, a horizontally integrated high-voltage withstand layer made of a wide-bandgap thin-film material, a silicon thin film layer, a silicon CMOS logic and switch control unit connected to the silicon thin film layer, and a first multilayer dielectric layer. The horizontally integrated high-voltage withstand layer and the silicon thin film layer are vertically arranged. + The buried layer and P-Top layer are located on the upper and lower sides of the high-voltage structure region, respectively. The horizontally integrated high-voltage layer and silicon thin film layer are connected by an interface bonding dielectric layer. The silicon CMOS logic and switch control unit includes a silicon switch control unit and a silicon CMOS low-voltage logic unit. The silicon switch control unit is located in region 1 of the upper arm of the high-voltage power transistor, and the silicon CMOS low-voltage logic unit is located in region 1 of the lower arm of the high-voltage power transistor. This invention can optimize the high-voltage integrated chip architecture, achieving lower chip area and process cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, specifically to a wide bandgap semiconductor composite high-voltage vertical power chip and its fabrication process. Background Technology

[0002] High-voltage power integrated circuits based on 8-inch / 12-inch fab platform BCD processes (Bipolar, CMOS, and DMOS) are widely used in various power management and power chip fields, enabling the fabrication of bipolar, CMOS, and DMOS devices on the same chip. The development of BCD processes does not entirely follow Moore's Law, but rather diverges towards high voltage, high power, and high density. In recent years, in particular, industry demands have required higher voltage levels, reaching 500-700V or even higher, and monolithically integrated PMIC (power management IC) chips with higher power density. However, silicon itself has limited voltage withstand capability; each μm thick / length silicon epitaxial layer can only withstand about 10V. For high-voltage, especially above 700V, the voltage withstand length of the silicon epitaxial layer in the high-voltage region of BCD processes often needs to be over 70μm, making process structure development difficult and the process complex. There is still no large-scale, effective technical solution for silicon-based BCD processes above 1200V. In addition, existing high-voltage BCD power chips require a large area due to the limited voltage withstand capability of silicon materials, and the high-low voltage isolation scheme is also very complex, resulting in the high-voltage transistor DMOS or LDMOS part occupying a very large area in the chip, with complex processes and high costs.

[0003] In recent years, wide bandgap semiconductor materials such as SiC, GaN, Ga2O3, and AlN have attracted much attention due to their superior high voltage resistance, high temperature resistance, and radiation resistance compared to silicon. If wide bandgap semiconductor wafer substrates (1) and epitaxial wafers are used directly to fabricate high-voltage BCD integrated chips, one problem is that the development of wide bandgap semiconductor materials themselves is not mature, and the cost of complete wafers of many materials is high. Another problem is that devices made from wide bandgap semiconductor materials have their own problems. For example, silicon carbide MOSFET structures have many gate oxide layer defects, threshold voltage is prone to drift, and various reliability problems. Moreover, they require large special process equipment and the process is complex. GaN and Ga2O3 materials have problems with poor P-type mobility or lack of effective P-type ion implantation activation structures. AlN has the problem of small crystal size, less than 6 inches, and very high cost. However, these wide bandgap semiconductor thin film materials can be grown on the surface of different substrates (1) through high-temperature CVD, MOCVD, or MBE processes. Large-size wafer-level wide bandgap semiconductor thin film materials with thicknesses of hundreds of nanometers to tens of micrometers can be constructed at low cost and with high quality.

[0004] The industry currently lacks effective chip architectures and process methods to combine mature silicon-based CMOS chip technology with the high voltage withstand capability of wide-bandgap semiconductors, in order to construct more efficient, higher-performance, and lower-cost composite power integrated chips. In the future, with the increasing demand from industry for monolithically integrated PMIC (power management IC) chips with higher voltage levels, 1200V or even higher, and higher power densities, there is an urgent need to explore new composite high-voltage power chip construction technologies.

[0005] Existing solutions based on all-silicon CMOS and BCD process technologies often require the development of complex BCD high-voltage power cell processes and complex isolation processes between medium- and high-voltage logic regions to fabricate medium- and high-voltage power chips. This is especially true for high-voltage DMOS and LDMOS, where the voltage-bearing region not only occupies a significant amount of valuable chip area (e.g., ... Figure 1 As shown, the medium- and high-voltage power regions and high-voltage power chip regions often account for more than 50% of the total chip area. Moreover, it is necessary to fabricate expensive and complex isolation process structures such as junction isolation (JI), deep isolation (DTI), and SOI isolation, and develop supporting high-uniformity ultra-deep hole etching, ultra-deep via metal filling, and planarization processes. This poses challenges to the development of processes for each module. For example, it involves supporting stress control during thick oxide layer growth, uniformity control during ultra-deep hole etching, metallization filling control during ultra-deep vias, and control of planarization process stop points and grinding uniformity, etc., which brings about process complexity, various device characteristic issues, and yield problems.

[0006] Wide bandgap semiconductor materials such as SiC, GaN, Ga2O3, and AlN possess superior properties compared to silicon, including high voltage resistance, high temperature resistance, and radiation resistance. The technical problem this invention aims to solve is whether, through novel chip architectures, device structures, and fabrication methods, the silicon switching control units in silicon CMOS logic cell regions and power device structures can still be fabricated using traditional silicon materials, while integrating wide bandgap semiconductor drift regions as voltage-resistant units to form composite device chips. This would optimize the high-voltage integrated chip architecture, achieve better performance, lower chip area, and lower process costs, resulting in novel composite high-voltage BCD power integrated chips. Summary of the Invention

[0007] Based on the above description, the present invention provides a wide bandgap semiconductor composite high-voltage vertical power chip and its fabrication process to solve the technical problems of existing chips being based on all-silicon fabrication, requiring the development of complex BCD high-voltage power unit processes and complex isolation process solutions for medium-high voltage and low-voltage logic regions. The solution of the present invention can optimize the high-voltage integrated chip architecture, achieving better performance, lower chip area, and lower process cost.

[0008] The technical solution of the present invention to solve the above-mentioned technical problems is as follows:

[0009] On one hand, the present invention provides a wide bandgap semiconductor composite high-voltage vertical power chip, which is a high-voltage BCD chip;

[0010] The chip includes at least one cell structure unit, which includes a substrate, a horizontally integrated high-voltage layer made of a wide bandgap thin film material, a silicon thin film layer, a silicon CMOS logic and switch control unit connected to the silicon thin film layer, and a first multilayer dielectric layer. The horizontally integrated high-voltage layer and silicon thin film layer are arranged vertically to enable self-isolation of the high-voltage power transistor region and the low-voltage logic region in different physical layers.

[0011] The laterally integrated high-pressure-resistant layer includes a laterally integrated high-pressure-resistant structural region made of a wide-bandgap thin-layer material, P + Buried layer and P-Top layer, wherein P + The buried layer and the P-Top layer are located on the upper and lower sides of the horizontally integrated high-pressure-resistant structure area, and the horizontally integrated high-pressure-resistant layer and the silicon thin film layer are connected by an interface bonding dielectric layer.

[0012] The silicon thin film layer is divided into the upper arm 1 region of the high voltage power tube, the lower arm 1 region of the high voltage power tube, and other arm regions of the high voltage power tube by a first isolation trench and a second isolation trench filled with multiple dielectric layers.

[0013] The silicon CMOS logic and switch control unit includes a silicon switch control unit and a silicon CMOS low-voltage logic unit. The silicon switch control unit is located in region 1 of the upper arm of the high-voltage power transistor, and the silicon CMOS low-voltage logic unit is located in region 1 of the lower arm of the high-voltage power transistor.

[0014] The silicon CMOS logic and switch control unit is isolated by partially or completely etching a silicon thin film layer to form an surrounding isolation trench and filling it with a first multilayer dielectric layer.

[0015] Based on the above technical solution, the present invention can be further improved as follows.

[0016] Furthermore, in the aforementioned wide-bandgap semiconductor composite high-voltage vertical power chip, the silicon switch control unit includes a source, a first gate serving as a control switch, a drain, a first P-well region, and a first N-well region. + The components are: a first N+ region, a second N+ region, a third N+ region, a fourth N+ region, a P-connecting post, a first connecting metal, a second connecting metal, and a third connecting metal. The drain electrode is located in the other arm region of the high-voltage power tube.

[0017] Furthermore, in the aforementioned wide bandgap semiconductor composite high voltage vertical power chip, the laterally integrated high voltage withstand layer is connected between the silicon thin film layer and the substrate, and the side of the silicon thin film layer near the substrate is connected to the high voltage withstand structure region through an interface bonding dielectric layer. The P-Top layer is connected to the high voltage withstand structure region at the interface bonding dielectric layer, with one end located below the upper arm 1 region of the high voltage power transistor and the other end located below other arm regions of the high voltage power transistor.

[0018] Furthermore, in the aforementioned wide bandgap semiconductor composite high-voltage vertical power chip, the silicon thin film layer is connected between the laterally integrated high-voltage layer and the substrate. The silicon CMOS logic and switch control unit on the side of the silicon thin film layer away from the substrate is isolated by partially or completely etching the silicon thin film layer to form an surrounding isolation trench and filling it with a first multilayer dielectric layer. It is connected to the P+ buried layer through an interface bonding dielectric layer. The P-Top layer side of the laterally integrated high-voltage layer is connected to the second multilayer dielectric layer.

[0019] Furthermore, in the aforementioned wide bandgap semiconductor composite high-voltage vertical power chip, a first metal via is formed on the upper arm 1 region of the high-voltage power transistor near the first isolation trench. A first P well region is provided on the side of the upper arm 1 region of the high-voltage power transistor away from the first metal via, and a first N+ region is provided on the other side. A second N+ region is provided on the first P well region. Ohmic contacts are connected to both N+ regions. A first gate oxide layer is provided in the first multilayer dielectric layer at the junction with the two N+ regions. The end of the first gate oxide layer near the first N+ region is connected to the ohmic contact on the first N+ region. The side of the first gate oxide layer away from the high-resistivity substrate is connected to the first gate.

[0020] The first metal via is connected to a first connecting metal. A source electrode is connected above the tube arm 1 region on the side of the first multilayer dielectric layer away from the substrate. One end of the source electrode is ohmic contact connected to the second N+ region, and the other end is connected to the upper end of the first connecting metal. The lower end of the first connecting metal is ohmic contact connected to the end of the P-Top layer away from the second isolation trench.

[0021] A second metal through-hole is formed on the side of the first N+ region near the first metal through-hole and where it connects with the first N+ region. The lower end of the second metal through-hole is located in the horizontally integrated high-voltage structure region. A second connecting metal is connected inside the second metal through-hole. A P-connecting post is connected below the second metal through-hole on the high-voltage structure region. A third N+ region is connected on the side of the P-connecting post near the second isolation trench. The side of the third N+ region near the second isolation trench extends beyond the P-connecting post. The lower end of the second connecting metal is connected to an ohmic contact that connects both the P-connecting post and the third N+ region. The upper end is connected to an ohmic contact on the first N+ region. A third metal through-hole is formed in the other tube arm regions of the high-voltage power tube. A third connecting metal is connected inside the third metal through-hole. A fourth N+ region with an ohmic contact is connected below the third metal through-hole on the high-voltage structure region. The drain is connected to the ohmic contact in the fourth N+ region through the third connecting metal.

[0022] The walls of the first, second, and third metal vias are covered with a dielectric isolation layer with a thickness of 10nm-800nm.

[0023] Furthermore, the aforementioned wide-bandgap semiconductor composite high-voltage vertical power chip...

[0024] The silicon switch control unit includes a source, a first gate serving as a control switch, a drain, a first P-well region, and a first N-well region. + District, Second N + District, Third N + District, Fourth N + The components are: a region, a P-connecting post, a fourth connecting metal, a fifth connecting metal, a sixth connecting metal, and a seventh connecting metal. The drain electrode is located in the other arm region of the high-voltage power tube.

[0025] A fourth metal via extending to the silicon thin film layer is provided above the upper arm 1 region of the high voltage power transistor on the horizontally integrated high voltage layer. A first P well region is provided on the side of the upper arm 1 region of the high voltage power transistor away from the fourth metal via, and a first N+ region is provided on the other side. A second N+ region is provided on the first P well region. Ohmic contacts are connected to both N+ regions. A first gate oxide layer is provided in the first multilayer dielectric layer at the junction with the two N+ regions. The end of the first gate oxide layer near the first N+ region is connected to the ohmic contact on the first N+ region. The side of the first gate oxide layer away from the high-resistivity substrate is connected to the first gate.

[0026] A source electrode is connected above the second multilayer dielectric layer. One end of the source electrode is connected to the ohmic contact on the second N+ region through the fifth connecting metal, and the other end is connected to the ohmic contact on the P-Top layer away from the second isolation trench through the sixth connecting metal.

[0027] The fourth metal via is connected to a fourth connecting metal. A P-connecting post is connected to one end of the horizontally integrated high-voltage layer away from the second isolation trench. The side of the P-connecting post near the second isolation trench is connected to the third N+ region. The side of the third N+ region near the second isolation trench extends beyond the P-connecting post. The lower end of the fourth connecting metal is connected to the ohmic contact on the first N+ region, and the upper end is connected to the ohmic contact on both the P-connecting post and the third N+ region. The fourth N+ region with ohmic contact is connected above the other tube arm regions of the high-voltage power transistor on the horizontally integrated high-voltage layer. The drain is connected above the other tube arm regions of the high-voltage power transistor on the second multilayer dielectric layer. The drain is connected to the ohmic contact in the fourth N+ region through a seventh connecting metal.

[0028] The fourth metal via is covered with a dielectric isolation layer with a thickness of 10nm-800nm.

[0029] Furthermore, in the aforementioned wide bandgap semiconductor composite high-voltage vertical power chip, the substrate is a high-resistivity substrate disposed on the side of the P+ buried layer away from the high-voltage-resistant structure region of lateral integration, or the substrate includes a high-resistivity SiC single-crystal thin film layer connected to the side of the P+ buried layer away from the high-voltage-resistant structure region of lateral integration and a polycrystalline silicon carbide layer connected to the side of the high-resistivity SiC single-crystal thin film layer away from the high-voltage-resistant structure region of lateral integration, and the bottom of the isolation trench penetrates the P+ buried layer and is located within the high-resistivity SiC single-crystal thin film layer;

[0030] The high-resistivity substrate is high-resistivity SiC, sapphire, or a high-resistivity silicon wafer, and the thickness of the polycrystalline silicon carbide layer is 100-500 μm.

[0031] Furthermore, in the aforementioned wide-bandgap semiconductor composite high-voltage vertical power chip, the laterally integrated high-voltage-resistant layer is a wide-bandgap thin-film material, which is an N-type doped semiconductor material; the wide-bandgap thin-film material is made of SiC, GaN, Ga2O3, or AlN, with a thickness of 100nm-50μm, preferably 2μm; when the wide-bandgap thin-film material is made of SiC, the ohmic contact metal is a nickel metal layer or a titanium-nickel-aluminum composite metal layer; and / or,

[0032] The material of the interfacial bonding dielectric layer is SiO2 or benzocyclobutene resin, and the thickness of the interfacial bonding dielectric layer is 1 nm-10 μm; and / or

[0033] The multilayer dielectric layer is composed of SiO2 and SiN composited by CVD chemical vapor deposition, and the thickness of the silicon thin film layer is 100nm-10μm; and / or,

[0034] The silicon thin film layer is N-type doped and has a thickness of 100 nm-10 μm; and / or,

[0035] The laterally integrated high-pressure-resistant layer is formed by epitaxial or bonding methods.

[0036] Furthermore, in the aforementioned wide bandgap semiconductor composite high-voltage vertical power chip, the silicon CMOS low-voltage logic unit includes a second P well region, an N well region, a second gate, a third gate, a second gate oxide layer, and a third gate oxide layer.

[0037] The second P-well region has a fifth N+ region and a sixth N+ region on both sides, and both N+ regions are connected to ohmic contacts. A second gate oxide layer is connected to the multilayer dielectric layer at the junction with the second P-well region, and both ends of the second gate oxide layer are connected to ohmic contacts. The N-well region has a P+ buried layer on both sides, and both P+ buried layers are connected to ohmic contacts. A third gate oxide layer is connected to the multilayer dielectric layer at the junction with the N-well region, and both ends of the third gate oxide layer are connected to ohmic contacts. The side of the second gate oxide layer away from the high-resistivity substrate is connected to the second gate, and the side of the third gate oxide layer away from the high-resistivity substrate is connected to the third gate.

[0038] On the other hand, the present invention also provides a fabrication process for a wide bandgap semiconductor composite high-voltage vertical power chip, comprising the following steps:

[0039] S1. An N-type doped wide bandgap thin layer is epitaxially or bonded on the substrate as a high-voltage-resistant layer for lateral integration. A P+ buried layer is connected to the side of the wide bandgap thin layer close to the high-resistivity substrate.

[0040] S2. In a wide bandgap thin-layer material, a third N+ region, a fourth N+ region, a P-connecting pillar, and a P-Top withstand field plate region are formed by ion implantation, and then activated by annealing.

[0041] S3. In the area where the device needs to be connected to the via of the silicon thin film layer, ohmic contact metal is deposited and annealed to form ohmic contacts.

[0042] S4. Deposit an interfacial bonding dielectric layer on the side of the high-voltage-resistant layer made of wide-bandgap thin-film material away from the high-resistivity substrate using CVD, ALD or spin coating processes.

[0043] S5. A layer of N-type doped silicon thin film is bonded through a wafer-level bonding process;

[0044] S6. A silicon switch control unit and a silicon CMOS low-voltage logic unit are fabricated in a silicon thin film layer using CMOS technology.

[0045] S7. Etch metal vias and isolation trenches in the silicon thin film layer. The walls of the metal vias are covered with a dielectric isolation layer with a thickness of 10nm-800nm. The center of the metal vias is filled with connecting metal. The bottom of the connecting metal contacts the ohmic contact metal region of the wide bandgap semiconductor, which serves as an electrical connection.

[0046] Furthermore, in the above-mentioned fabrication process of a wide bandgap semiconductor composite high voltage vertical power chip, steps S5, S6, and S7 are replaced with steps S5-1 and S6-1.

[0047] S5-1. After temporarily bonding the carrier wafer and grinding the back silicon substrate to 2-10μm, the substrate is then bonded at the wafer level to a high-voltage-resistant layer made of a wide bandgap thin-film material on the side away from the high-resistivity substrate; the carrier wafer is a silicon thin-film layer that integrates silicon CMOS logic and switch control unit.

[0048] S6-1. Etch metal vias and isolation trenches in the silicon thin film layer. The walls of the metal vias are covered with a dielectric isolation layer with a thickness of 10nm-800nm. The center of the metal vias is filled with connecting metal. The bottom of the connecting metal contacts the ohmic contact metal region of the wide bandgap semiconductor, which serves as an electrical connection.

[0049] Compared with the prior art, the technical solution of the present invention has the following beneficial technical effects:

[0050] First, the architecture and fabrication process of this novel high-voltage BCD power chip combine the high voltage and high power characteristics of wide-bandgap semiconductors with the mature process platform of traditional silicon-based CMOS technology. Wide-bandgap semiconductor (WBG) materials such as SiC, GaN, Ga2O3, and AlN possess superior properties compared to silicon, including high voltage resistance, high temperature resistance, and radiation resistance. The voltage withstand capability of a wide-bandgap semiconductor epitaxial layer per μm thickness / length can reach over 100V, more than 10 times higher than that of silicon epitaxial layers per μm thickness. This solution utilizes a novel chip architecture, device construction, and fabrication method. While the silicon switch control unit components in the traditional silicon CMOS logic cell region and power device structure are still fabricated using silicon, the wide-bandgap semiconductor drift region is integrated as a voltage-resistant unit to form a composite high-voltage device chip technology. This optimizes the high-voltage integrated chip architecture, achieving a novel composite high-voltage BCD power integrated chip with better performance, lower chip area, and lower process costs.

[0051] Secondly, it avoids the construction difficulties of special processes such as high-voltage power DMOS or LDMOS die fabrication and high-voltage isolation in traditional silicon-based high-voltage BCD chip manufacturing, as well as the difficulties in further evolving to high-voltage BCD processes above 1200V. For example, existing silicon-based high-voltage BCD processes require the fabrication of expensive and complex isolation structures such as junction isolation (JI), deep isolation (DTI), and SOI isolation, and the development of supporting high-uniformity ultra-deep hole etching, ultra-deep via metal filling, and planarization processes. This poses challenges to the development of various module processes, such as the control of stress during thick oxide layer growth, the control of uniformity within ultra-deep hole etching, the control of ultra-deep via metallization filling, the control of planarization process stop points and grinding uniformity, etc., which brings about process complexity, various device characteristic issues, and yield problems. Furthermore, since the withstand voltage of silicon epitaxial layers with a thickness / length of only about 10V per μm, it is very difficult to continue evolving to high-voltage BCD processes of 1200V and above, and there is no suitable process solution for large-scale production in the industry. The architecture and fabrication process of this new high-voltage BCD power chip utilizes a combination of silicon CMOS logic and switch control units and wide-bandgap semiconductor withstand voltage units. The withstand voltage of wide-bandgap semiconductor epitaxial layers with a thickness / length of only μm per μm can reach more than 100V, which can be easily evolved to high-voltage power integrated chip technology of 1200V and above. It also has a simple and easy isolation scheme for self-isolation between the high-voltage transistor region and the low-voltage logic region. The high-voltage withstand voltage region of the high-voltage power transistor is located in the wide-bandgap semiconductor material layer, which is not on the same physical layer as the silicon-based low-voltage logic unit layer, and is naturally isolated by an interface bonding dielectric layer in between. It does not require the additional complex isolation design and complex process of traditional silicon-based BCD processes. Attached Figure Description

[0052] Figure 1 The diagram shows a typical PMIC chip based on silicon BCD process (left figure) and an actual ST chip area analysis diagram (right figure) for the background technology.

[0053] Figure 2 This is a schematic diagram of the overall structure of a wide bandgap semiconductor composite high-voltage vertical power chip according to Embodiment 1 of the present invention;

[0054] Figure 3 The diagram shows the current conduction path (indicated by the green dashed arrow) of a high-voltage power MOS transistor device of a wide bandgap semiconductor composite high-voltage vertical power chip of the present invention when a positive voltage is applied to the gate relative to the source and a positive voltage is also applied to the drain relative to the source.

[0055] Figure 4This is a schematic diagram of a high-voltage power MOSFET device in a wide-bandgap semiconductor composite high-voltage vertical power chip according to Embodiment 1 of the present invention. When the device is turned off, i.e., when the gate of the silicon switch control unit is negatively charged or 0V relative to the source, and the drain of the device is positively charged relative to the source, the P-Top layer and the N-type drift region are extended to pinch off the drift region channel, forming an effective reverse withstand voltage. At the same time, the bottom P+ layer of the wide-bandgap semiconductor thin layer is connected to the upper silicon switch control unit through the P-connection pillar and is at a low potential. It will also form a reverse PN structure with the N-type drift region, which will assist in the reverse depletion pinching off of the N-type drift region and help improve the withstand voltage capability.

[0056] Figure 5 This is a schematic diagram of the connection relationship between the substrate (including a high-resistivity SiC single-crystal thin film layer and a polycrystalline silicon carbide layer), the lateral high-voltage-resistant layer made of a wide-bandgap thin film material, and the silicon thin film layer in Embodiment 2 of the present invention.

[0057] Figure 6 This is a schematic diagram of the structure of the isolation trench, the upper tube arm 1 region of the high-voltage power tube, the lower tube arm 1 region of the high-voltage power tube, and other tube arm regions of the high-voltage power tube in Embodiment 2 of the present invention (P-Top layer is not shown).

[0058] Figure 7 This is a schematic diagram of the overall structure of a wide bandgap semiconductor composite high-voltage vertical power chip according to Embodiment 3 of the present invention;

[0059] Figure 8 This is a schematic diagram of the connection relationship between the substrate (high-resistivity SiC, sapphire, or high-resistivity silicon wafer), the lateral high-voltage layer made of a wide-bandgap thin-film material, and the silicon thin film layer in Embodiment 1 of the present invention.

[0060] Figures 9-16 This is a schematic diagram of the various steps in the fabrication process of a wide bandgap semiconductor composite high-voltage vertical power chip according to Embodiment 1 of the present invention.

[0061] Figure 17 A schematic diagram comparing the placement of CMOS low-voltage logic cells in the upper region of the high-voltage withstand layer P-Top layer of the high-voltage power transistor region (left figure) and placement in the region outside the high-voltage power transistor die (right figure);

[0062] Figure 18 This is a schematic diagram of the structure of the carrier wafer for the silicon CMOS logic and switch control unit fabricated in step S5-1 of Example 5.

[0063] The attached diagram lists the components represented by each number as follows:

[0064] 1. Substrate; 2. High-voltage layer, 201. High-voltage structural region, 202. P+ buried layer, 203. P-Top layer; 3. Silicon thin film layer, 301. First isolation trench, 302. Second isolation trench, 303. Upper arm 1 region of high-voltage power transistor, 304. Lower arm 1 region of high-voltage power transistor, 305. Other arm regions of high-voltage power transistor; 4. First multilayer dielectric layer; 5. Second multilayer dielectric layer; 6. Silicon switch control unit, 601. Source, 602. First gate, 603. Drain, 604. First P-top layer. 7. Well region, 605. First N+ region, 606. Second N+ region, 607. Third N+ region, 608. Fourth N+ region, 609. P-connection post, 610. First metal via, 6101. First connecting metal, 611. Second metal via, 6111. Second connecting metal, 612. Third metal via, 6121. Third connecting metal, 613. Fourth metal via, 6131. ​​Fourth connecting metal, 614. Fifth connecting metal, 615. Sixth connecting metal, 616. Seventh connecting metal; 7. CMOS low-voltage logic cell, 701. Second P well region, 702. N well region, 703. Second gate, 704. Third gate, 705. Second gate oxide layer, 706. Third gate oxide layer; 8. Interface bonding dielectric layer; 9. Ohmic contact. Detailed Implementation

[0065] To facilitate understanding of this application, a more complete description will be provided below. This application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0067] It should be noted that when one element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediary element. In the following embodiments, "connection" should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have the transmission of electrical signals or data between them.

[0068] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0069] Existing solutions based on all-silicon CMOS and BCD process technologies often require the development of complex BCD high-voltage power cell processes and complex isolation processes between medium- and high-voltage logic regions to fabricate integrated medium- and high-voltage power chips. In particular, the following three technical challenges exist:

[0070] 1. High-voltage DMOS or LDMOS power chips have a large area ratio; silicon material itself has limited voltage withstand capability. Each μm thick / length silicon epitaxial layer can only withstand about 10V. For high voltage, especially BCD process high voltage tubes above 700V, the silicon epitaxial layer in the high voltage region often needs to be more than 70μm long. The process structure is difficult to develop, the process is complex, and the process cost is high.

[0071] 2. The high-voltage power transistor region, the CMOS logic chip region, and the low-voltage transistor region require complex isolation designs and various expensive and complex isolation process technologies;

[0072] 3. The development of high-power PMIC chips and BCD technology does not completely follow Moore's Law, but rather diverges in three directions: high voltage, high power, and high density. In particular, in recent years, the industry has demanded monolithically integrated PMIC (power management IC) chips with higher voltage levels and higher power densities. However, silicon material itself has limited voltage withstand capability; each μm thick / length silicon epitaxial layer can only withstand about 10V. There is still no large-scale and effective technical solution for silicon-based BCD technology with voltages higher than 1200V.

[0073] Wide bandgap semiconductor (WBG) materials such as SiC, GaN, Ga2O3, and AlN possess superior properties compared to silicon, including high voltage resistance, high temperature resistance, and radiation resistance. The voltage withstand capability of a wide bandgap semiconductor epitaxial layer per μm thickness / length can reach over 100V, more than 10 times higher than that of silicon epitaxial layers per μm thickness. This solution utilizes a novel chip architecture, device construction, and fabrication method. While the silicon switch control unit components in the silicon CMOS low-voltage logic unit and power device structure are still fabricated using traditional silicon materials, the wide bandgap semiconductor drift region is integrated as a voltage-resistant unit to form a composite high-voltage device chip. This optimizes the high-voltage integrated chip architecture, achieving better performance, lower chip area, and lower process costs, thus producing a novel composite high-voltage BCD power integrated chip.

[0074] Example 1

[0075] The chip schematic diagram of this solution is as follows: Figure 2 As shown, a novel high-voltage BCD chip technology is proposed, which employs silicon CMOS logic and switch control unit and a horizontally integrated wide bandgap WBG thin-film material with a vertically arranged high-voltage resistant area. The specific scheme is as follows.

[0076] A wide-bandgap semiconductor composite high-voltage vertical power chip, which is a high-voltage BCD chip;

[0077] The chip includes at least one cell structure unit, which includes a substrate 1, a horizontally integrated high-voltage layer 2 made of a wide bandgap thin film material, a silicon thin film layer 3, a silicon CMOS logic and switch control unit connected to the silicon thin film layer 3, and a first multilayer dielectric layer 4. The horizontally integrated high-voltage layer 2 and silicon thin film layer 3 are arranged vertically to enable the high-voltage power transistor region and the low-voltage logic region to be in different physical layers to achieve self-isolation.

[0078] The laterally integrated high-pressure-resistant layer 2 includes a laterally integrated high-pressure-resistant structural region 201, a P+ buried layer 202, and a P-Top layer 203 made of a wide bandgap thin-layer material. + The buried layer 202 and the P-Top layer 203 are located on the upper and lower sides of the horizontally integrated high-pressure-resistant structural region 201, and the horizontally integrated high-pressure-resistant layer 2 and the silicon thin film layer 3 are connected by an interface bonding dielectric layer 8.

[0079] The silicon thin film layer 3 is divided into the upper arm 1 region 303, the lower arm 1 region 304, and other arm regions 305 of the high-voltage power tube by the first isolation trench 301 and the second isolation trench 302 filled with multiple dielectric layers.

[0080] The silicon CMOS logic and switch control unit includes a silicon switch control unit 6 and a silicon CMOS low-voltage logic unit 7. The silicon switch control unit 6 is located in region 303 of the upper arm of the high-voltage power transistor, and the silicon CMOS low-voltage logic unit 7 is located in region 304 of the lower arm of the high-voltage power transistor.

[0081] The silicon CMOS logic and switch control unit is isolated by etching part or all of the silicon thin film layer 3 to form an surrounding isolation trench and filling it with the first multilayer dielectric layer 4.

[0082] Furthermore, the horizontally integrated high-voltage layer 2 is connected between the silicon thin film layer 3 and the substrate 1, and the side of the silicon thin film layer 3 closest to the substrate 1 is connected to the high-voltage structure region 201 through the interface bonding dielectric layer 8. The P-Top layer 203 is connected to the high-voltage structure region 201 at the interface bonding dielectric layer 8, with one end located below the upper arm 1 region 303 of the high-voltage power transistor and the other end located below the other arm regions 305 of the high-voltage power transistor.

[0083] Furthermore, a first metal via 610 is formed on the upper arm 1 region 303 of the high-voltage power transistor near the first isolation trench 301. A first P well region 604 is provided on the side of the upper arm 1 region 303 of the high-voltage power transistor away from the first metal via 610, and a first N+ region 605 is provided on the other side. A second N+ region 606 is provided on the first P well region 604. Ohmic contacts 9 are connected to both N+ regions. A first gate oxide layer is provided in the first multilayer dielectric layer 4 at the junction with the two N+ regions. One end of the first gate oxide layer near the first N+ region 605 is connected to the ohmic contact 9 on the first N+ region 605. The side of the first gate oxide layer away from the high-resistivity substrate is connected to the first gate 602.

[0084] The first metal via 610 is connected to a first connecting metal 6101. A source electrode 601 is connected above the tube arm 1 region 303 on the side of the first multilayer dielectric layer 4 away from the substrate. One end of the source electrode 601 is connected to the ohmic contact 9 on the second N+ region 606, and the other end is connected to the upper end of the first connecting metal 6101. The lower end of the first connecting metal 6101 is connected to the ohmic contact 9 on the side of the P-Top layer 203 away from the second isolation trench 302.

[0085] A second metal through-hole 611 is formed on the side of the first N+ region 605 near the first metal through-hole 610 and at the junction with the first N+ region 605. The lower end of the second metal through-hole 611 is located in the horizontally integrated high-pressure resistant structural region 201. A second connecting metal 6111 is connected inside the second metal through-hole 611. A P-connecting post 609 is connected below the second metal through-hole 611 on the high-pressure resistant structural region 201. The side of the P-connecting post 609 near the second isolation trench 302 is connected to the third N+ region 607. The side of the third N+ region 607 near the second isolation trench 302 extends beyond the P-connecting post 609. The lower end of the second connecting metal 6111 is connected to the ohmic contact 9 that simultaneously connects the P connecting post 609 and the third N+ region 607, and the upper end is connected to the ohmic contact 9 on the first N+ region 605. The other tube arm region 305 of the high-voltage power tube has a third metal through hole 612. The third metal through hole 612 is connected to the third connecting metal 612. The third N+ region 608 with ohmic contact 9 is connected below the third metal through hole 612 on the high-voltage structure region 201. The drain electrode 603 is connected to the ohmic contact 9 in the fourth N+ region 608 through the third connecting metal 6121.

[0086] The walls of the first metal through-hole 610, the second metal through-hole 611, and the third metal through-hole 612 are covered with a dielectric isolation layer with a thickness of tens of nanometers to hundreds of nanometers, such as silicon dioxide, and the size can be 10nm, 50nm, 100nm, 500nm, 800nm, etc.

[0087] Furthermore, the silicon switch control unit 6 includes a source 601, a first gate 602 serving as a control switch, a drain 603, a first P-well region 604, a first N+ region 605, a second N+ region 606, a third N+ region 607, a fourth N+ region 608, a P-connection post 609, a first connection metal 6101, a second connection metal 6111, and a third connection metal 6121. The drain 603 is located in the other arm region 305 of the high-voltage power transistor. The first gate 602 is the control gate for the composite power MOSFET switch.

[0088] Furthermore, the substrate 1 is a high-resistivity substrate disposed on the side of the P+ buried layer 202 away from the high-voltage structure region 201 of the laterally integrated structure, and the high-resistivity substrate is high-resistivity SiC, sapphire, or a high-resistivity silicon wafer.

[0089] Furthermore, in the aforementioned wide bandgap semiconductor composite high voltage vertical power chip, the silicon CMOS low voltage logic unit 7 includes a second P well region 701, an N well region 702, a second gate 703, a third gate 704, a second gate oxide layer 705, and a third gate oxide layer 706.

[0090] The second P well region 701 has a fifth N+ region and a sixth N+ region on both sides, and ohmic contacts are connected to both N+ regions. A second gate oxide layer 705 is connected to the multilayer dielectric layer at the connection point with the second P well region 701, and both ends of the second gate oxide layer 705 are connected to ohmic contacts. The N well region 702 has a P+ buried layer on both sides, and ohmic contacts are connected to both P+ buried layers. A third gate oxide layer 706 is connected to the multilayer dielectric layer at the connection point with the N well region 702, and both ends of the third gate oxide layer 706 are connected to ohmic contacts. The side of the second gate oxide layer 705 away from the high-resistivity substrate is connected to the second gate 703, and the side of the third gate oxide layer 706 away from the high-resistivity substrate is connected to the third gate 704.

[0091] The working principle of this chip's high-voltage power MOSFET device is as follows:

[0092] (a) such as Figure 3 As shown, when the device is turned on, that is, when the silicon switch control unit 6 controls the silicon CMOS logic and the switch control unit to apply a positive voltage to the gate relative to the source 601, and the device drain 603 also applies a positive voltage relative to the source 601, the current conduction path of the high-voltage power MOS transistor device of the composite structure chip when it is turned on is indicated by the green dashed arrow.

[0093] (b) such as Figure 4 As shown, when the device is turned off, i.e., the silicon switch control unit 6 controls the silicon CMOS logic and switch control unit to apply a negative voltage or 0V relative to the source 601, while the device drain 603 is at a positive high voltage relative to the source 601, the P-Top layer and the N-drift region reverse bias depletion region expand to pinch off the drift region channel, forming an effective reverse breakdown voltage; at the same time, the bottom P-Top layer of the wide bandgap semiconductor thin film material... + Because the buried layer 202 is connected to the upper silicon switch control unit 6 area through the P-connection post 609, the potential is at a low potential. It will also form a reverse PN structure with the N-type drift region, which will help to reverse deplete the N drift region and help improve the withstand voltage.

[0094] The above description is a cell structure unit of a novel wide-bandgap semiconductor composite high-voltage vertical power chip. In reality, a power chip can be formed by countless such cell structures connected in parallel.

[0095] Example 2

[0096] This embodiment is basically the same as Embodiment 1, except that, as Figure 5As shown, the substrate 1 includes a high-resistivity SiC single-crystal thin film layer connected to the side of the P+ buried layer 202 away from the high-voltage-resistant structural region 201 of the laterally integrated layer, and a polycrystalline silicon carbide layer connected to the side of the high-resistivity SiC single-crystal thin film layer away from the high-voltage-resistant structural region 201 of the laterally integrated layer. The bottom of the isolation trench penetrates the P+ buried layer 202 and is located within the high-resistivity SiC single-crystal thin film layer. The thickness of the polycrystalline silicon carbide layer is 100-500 μm.

[0097] The advantage of this alternative is that polycrystalline silicon carbide substrates have low wafer substrate costs and excellent heat dissipation characteristics, which can further optimize chip costs and heat dissipation capabilities.

[0098] like Figure 6 As shown, in the subsequent integration of multiple high-voltage, high-power dies, the high-resistivity SiC single-crystal thin film layer can provide a simple trench isolation technology for the upper and lower high-voltage tube sides. This only requires etching trenches down to the P-type surface of the high-resistivity SiC single-crystal thin film layer. + By etching away the buried layer 202, high-voltage isolation between different circuit structures of the high-voltage die can be achieved.

[0099] The manufacturing process for subsequent high-voltage integrated BCD power chips is exactly the same.

[0100] Example 3

[0101] This novel high-voltage BCD composite power chip can also employ a wide-bandgap withstand voltage layer on top and a silicon CMOS layer on the bottom, as shown in the chip structure below. Figure 7 As shown.

[0102] A wide-bandgap semiconductor composite high-voltage vertical power chip, which is a high-voltage BCD chip;

[0103] The chip includes at least one cell structure unit, which includes a substrate 1, a horizontally integrated high-voltage layer 2 made of a wide bandgap thin film material, a silicon thin film layer 3, a silicon CMOS logic and switch control unit connected to the silicon thin film layer 3, and a first multilayer dielectric layer 4. The horizontally integrated high-voltage layer 2 and silicon thin film layer 3 are arranged vertically to enable the high-voltage power transistor region and the low-voltage logic region to be in different physical layers to achieve self-isolation.

[0104] The laterally integrated high-pressure-resistant layer 2 includes a laterally integrated high-pressure-resistant structural region 201 and P made of a wide-bandgap thin-layer material. + Burial layer 202 and P-Top layer 203, wherein P + The buried layer 202 and the P-Top layer 203 are located on the upper and lower sides of the horizontally integrated high-pressure-resistant structural region 201, and the horizontally integrated high-pressure-resistant layer 2 and the silicon thin film layer 3 are connected by an interface bonding dielectric layer 8.

[0105] The silicon thin film layer 3 is divided into the upper arm 1 region 303, the lower arm 1 region 304, and other arm regions 305 of the high-voltage power tube by the first isolation trench 301 and the second isolation trench 302 filled with multiple dielectric layers.

[0106] The silicon CMOS logic and switch control unit includes a silicon switch control unit 6 and a silicon CMOS low-voltage logic unit 7. The silicon switch control unit 6 is located in region 303 of the upper arm of the high-voltage power transistor, and the silicon CMOS low-voltage logic unit 7 is located in region 304 of the lower arm of the high-voltage power transistor.

[0107] The silicon CMOS logic and switch control unit is isolated by etching part or all of the silicon thin film layer 3 to form an surrounding isolation trench and filling it with the first multilayer dielectric layer 4.

[0108] Furthermore, the silicon thin film layer 3 is connected between the laterally integrated high-voltage layer 2 and the substrate 1, and the silicon CMOS logic and switch control unit on the side of the silicon thin film layer 3 away from the substrate 1 is isolated by partially or completely etching the silicon thin film layer 3 to form an isolation trench and filling it with the first multilayer dielectric layer 4, and is connected to the P+ buried layer 202 through the interface bonding dielectric layer 8. The P-Top layer 203 side of the laterally integrated high-voltage layer 2 is connected to the second multilayer dielectric layer 5.

[0109] Furthermore, the silicon switch control unit 6 includes a source 601, a first gate 602 serving as a control switch, a drain 603, a first P-well region 604, and a first N-well region. + District 605, Second N + District 606, Third N + District 607, Fourth N + Area 608, P-connecting post 609, fourth connecting metal 6131, fifth connecting metal 614, sixth connecting metal 615, and seventh connecting metal 616, the drain 603 is located in the other tube arm area 305 of the high-voltage power tube.

[0110] Furthermore, a fourth metal via 613 extending to the silicon thin film layer 3 is formed above the upper arm 1 region 303 of the high-voltage power transistor on the laterally integrated high-voltage layer 2. A first P well region 604 is formed on the side of the upper arm 1 region 303 of the high-voltage power transistor away from the fourth metal via 613, and a first N well region 604 is formed on the other side. + Zone 605, the first P well zone 604 has a second N + Section 606, two N's + Each region is connected to an ohmic contact 9, and the first multilayer dielectric layer 4 is connected to two N-type contacts. + A first gate oxide layer is provided at the junction of the regions, and the first gate oxide layer is close to the first N. +One end of zone 605 is connected to the first N + The ohmic contact 9 on region 605 is connected, and the side of the first gate oxide layer away from the high-resistivity substrate is connected to the first gate 602;

[0111] A source electrode 601 is connected above the second multilayer dielectric layer 5. One end of the source electrode 601 is connected to the second N through a fifth connecting metal 614. + The ohmic contact 9 on zone 606 is connected, and the other end is connected to the ohmic contact 9 on the P-Top layer 203 away from the second isolation trench 302 through the sixth connecting metal 615;

[0112] The fourth metal through-hole 613 is connected to a fourth connecting metal 6131. ​​A P-connecting post 609 is internally connected to one end of the laterally integrated high-pressure-resistant layer 2 away from the second isolation trench 302. The side of the P-connecting post 609 closest to the second isolation trench 302 is connected to a third N-connecting post. + District 607, Third N + The side of zone 607 near the second isolation trench 302 extends beyond the P-connecting post 609, and the lower end of the fourth connecting metal 6131 is connected to the first N-connecting post. + The ohmic contact 9 on section 605 is connected, and its upper end is simultaneously connected to the P connecting post 609 and the third N. + The ohmic contact 9 of zone 607 is connected above the other tube arm zone 305 of the high-voltage power tube on the laterally integrated high-voltage layer 2, and is connected to the fourth N tube with ohmic contact 9. + In region 608, the drain 603 is connected above the other tube arm region 305 of the high-voltage power tube on the second multilayer dielectric layer 5. The drain 603 is connected to the fourth N via the seventh connecting metal 616. + The ohmic contact 9 connection is made within zone 608;

[0113] The fourth metal through-hole 613 is covered with a dielectric isolation layer with a thickness of tens to hundreds of nanometers.

[0114] Furthermore, the substrate 1 is disposed on P + The buried layer 202 is located on a high-resistivity substrate on the side away from the laterally integrated high-voltage structure region 201. The high-resistivity substrate is high-resistivity SiC, sapphire, or a high-resistivity silicon wafer.

[0115] Compared to the main scheme of Embodiment 1, the silicon CMOS logic and switch control unit in this embodiment has more thorough isolation between the high and low voltage regions in the area close to substrate 1, and is less affected by high voltage large signal interference from the top high voltage section. However, it requires more via connections and metal layer processes, which increases the process cost.

[0116] Furthermore, in the aforementioned wide bandgap semiconductor composite high voltage vertical power chip, the silicon CMOS low voltage logic unit 7 includes a second P well region 701, an N well region 702, a second gate 703, a third gate 704, a second gate oxide layer 705, and a third gate oxide layer 706.

[0117] The second P well region 701 has a fifth N+ region and a sixth N+ region on both sides, and ohmic contacts are connected to both N+ regions. A second gate oxide layer 705 is connected to the multilayer dielectric layer at the connection point with the second P well region 701, and both ends of the second gate oxide layer 705 are connected to ohmic contacts. The N well region 702 has a P+ buried layer on both sides, and ohmic contacts are connected to both P+ buried layers. A third gate oxide layer 706 is connected to the multilayer dielectric layer at the connection point with the N well region 702, and both ends of the third gate oxide layer 706 are connected to ohmic contacts. The side of the second gate oxide layer 705 away from the high-resistivity substrate is connected to the second gate 703, and the side of the third gate oxide layer 706 away from the high-resistivity substrate is connected to the third gate 704.

[0118] In the above embodiments, the laterally integrated high-voltage layer 2 is a wide-bandgap thin-film material, which is an N-type doped semiconductor material; the wide-bandgap thin-film material is made of SiC, GaN, Ga2O3 or AlN, with a thickness of 100nm-50μm, preferably 2μm. When the wide-bandgap thin-film material is made of SiC, the ohmic contact 9 metal is a nickel metal layer (Ni) or a titanium-nickel-aluminum composite metal layer (Ti, Ni, Al);

[0119] The material of the interface bonding medium layer 8 is SiO2 or benzocyclobutene resin, and the thickness of the interface bonding medium layer 8 is 1nm-10μm, preferably 300nm.

[0120] The multilayer dielectric layer is composed of SiO2 and SiN through CVD chemical vapor deposition, and the thickness of the silicon thin film layer 3 is 100nm-10μm, preferably 600nm.

[0121] The silicon thin film layer 3 is N-type doped; the laterally integrated high-voltage layer 2 is formed by epitaxy or bonding.

[0122] Example 4: Fabrication process of a wide bandgap semiconductor composite high-voltage vertical power chip according to Example 1

[0123] The novel composite BCD power chip in this solution can be fabricated using the following process technologies:

[0124] 1. The silicon-wide bandgap thin-film composite wafer technology used in the chip

[0125] This BCD power chip is fabricated using a composite wafer stacked with silicon and wide-bandgap semiconductor thin film materials. The silicon thin film layer 3 (typically 100nm-10μm thick) is bonded to a wide-bandgap semiconductor thin film material such as SiC, GaN, Ga2O3, or AlN (typically 100nm-50μm thick) on a high-resistivity substrate via a silicon dioxide interface bonding dielectric layer or other dielectric layer materials such as BCB, and integrated through wafer-level bonding to form the composite wafer. Typical composite wafer parameters are as follows: Figure 8 As shown:

[0126] 2. A fabrication process for a wide-bandgap semiconductor composite high-voltage vertical power chip:

[0127] S1, such as Figure 9 As shown, high-resistivity SiC, sapphire, high-resistivity silicon wafers, or other high-resistivity substrates are purchased, and then a wide bandgap thin layer material is epitaxially or bonded as a high-voltage-resistance structural region. This is typically an N-type doped layer with a thickness of 100nm-50μm, preferably 2μm. The high-voltage-resistance structural region fabricated from this wide bandgap thin material has a thin P layer on the side closest to the high-resistivity substrate. + Buried layer 202, 10nm-500nm, preferably 100nm; the P + The buried layer 202 can be obtained by peeling off after epitaxy or P-type ion implantation and then bonding it.

[0128] S2, such as Figure 10 As shown, a third N-type structure is formed by ion implantation in a high-pressure-resistant structural region made of a wide-bandgap thin-layer material. + District, Fourth N + Zone 608, P connecting column 609 and P-Top pressure-resistant field plate area, and annealed and activated;

[0129] S3, such as Figure 11 As shown, in the area that needs to be connected to the via of the device region of the silicon thin film layer 3 above, a suitable ohmic contact 9 metal is deposited and annealed to form the ohmic contact 9; for example, if the wide bandgap material is SiC, the ohmic contact 9 metal can be a nickel metal layer (Ni) or a titanium-nickel-aluminum composite metal layer (Ti, Ni, Al).

[0130] S4, such as Figure 12As shown, an interfacial bonding dielectric layer is deposited on the surface of the laterally integrated high-pressure-resistant layer 2, which has already undergone ion implantation and ohmic contact 9, using CVD, ALD, or spin coating processes. The dielectric layer material can be silicon dioxide or BCB, etc. BCB (Benzocyclobutene) is an active resin. Under specific heat treatment conditions, BCB can form a thermosetting polymer. This material has low dielectric constant, low dielectric loss, low moisture absorption, high thermal stability, and good chemical stability. The interfacial bonding dielectric layer material is generally 1nm-10μm, and optimized, the interfacial bonding dielectric layer 8 is 300nm SiO2.

[0131] S5, such as Figure 12 As shown, a silicon thin film layer 3 with a thickness of 100nm-10μm is then bonded through a wafer-level bonding process. It is generally an N-type doped layer, preferably 600nm.

[0132] S6, such as Figure 13 As shown, the silicon switch control unit 6 of the high-voltage power chip and the CMOS low-voltage logic unit are then fabricated in the silicon thin film layer 3 using CMOS technology.

[0133] Preferred, such as Figure 14 As shown, the silicon CMOS low-voltage logic cell 7 can be positioned on the upper region of the high-voltage structure region P-Top layer 203, which is made of a wide bandgap thin layer material in the area of ​​the high-voltage power transistor, to save the overall chip area; a schematic diagram of the process cross-section when the silicon CMOS low-voltage logic cell 7 is positioned on the upper region of the wide bandgap material P-Top layer 203 in the high-voltage power transistor region is shown below. Figure 15 As shown:

[0134] Alternatively, the silicon CMOS low-voltage logic cell 7 can also be located in an area outside the high-voltage power die.

[0135] S7, such as Figure 15 As shown, metal vias and isolation trenches are etched in the silicon thin film layer 3, and metal vias (Via) are filled with metal in the region where electrical connections are formed between the silicon CMOS logic and switch control unit and the high-voltage layer 2 for lateral integration of the lower wide-bandgap semiconductor. Preferably, the metal vias (Via) are filled with metals such as titanium (Ti), titanium nitride (TiN), and tungsten (W), or aluminum or copper. These are all processes commonly used in CMOS processes and will not be described in detail here.

[0136] The via is constructed by etching a via that penetrates the silicon thin film layer 3 and the bonding interface dielectric layer. The bottom of the via contacts the ohmic contact 9 metal region on the surface of the wide bandgap semiconductor material. The via wall is covered with a dielectric isolation layer with a thickness of tens to hundreds of nanometers. The center of the via is filled with metal Via material, which contacts the ohmic contact 9 metal region of the wide bandgap semiconductor, providing an electrical connection. A cross-sectional diagram of the completed chip fabrication in the high-voltage power transistor region is shown below. Figure 15 As shown: A schematic diagram of the process cross-section when the CMOS low-voltage logic cells are located in the upper region of the P-Top layer 203 of the high-voltage power transistor region. Figure 16 As shown.

[0137] A schematic diagram comparing the optimized layout of two types of CMOS low-voltage logic cell chip regions, as shown below. Figure 17 As shown.

[0138] Example 5: Fabrication process of a wide bandgap semiconductor composite high-voltage vertical power chip according to Example 2

[0139] This embodiment is basically the same as embodiment 4, except that process steps S5-S7 can also be implemented using another alternative process.

[0140] That is, after the fabrication of the wide bandgap semiconductor voltage-resistant structure region and the deposition of the interface bonding dielectric layer 8 in step S4 of Example 4 are completed, as follows: Figure 18 As shown, the top bonded silicon thin film layer 3 can be a wafer made from another silicon epitaxial wafer and fabricated using CMOS technology to produce silicon CMOS logic and switch control units. Then, a temporary bonding is performed on the carrier wafer with the silicon CMOS logic and switch control units fabricated, and the back side is ground to thin away the silicon substrate portion, typically to 2-10 μm. After this, it is then wafer-level bonded to the surface of the composite wafer after the wide bandgap semiconductor voltage withstand structure region is fabricated and the interface bonding dielectric layer 8 is deposited.

[0141] S6-1. Then, similar to step S7 above, metal vias and isolation trenches are etched in the silicon thin film layer 3. Metal vias (Via) are filled with metal in the areas where electrical connections are formed between the silicon CMOS logic and switch control unit and the lower wide-bandgap semiconductor lateral integration high-voltage layer 2. Preferably, the via connection metal filler uses metals such as titanium (Ti), titanium nitride (TiN), or tungsten (W), but aluminum or copper can also be used. These are commonly used processes in CMOS manufacturing and will not be detailed further. At this point, the process is complete. The finished chip... Figure 16 As shown.

[0142] The key technical points of this invention are as follows:

[0143] 1. The chip is fabricated using a composite wafer stacked with a high-resistivity substrate and a wide-bandgap semiconductor material; a silicon thin film layer 3 (typically 100nm-10μm thick) is bonded to a wide-bandgap semiconductor material such as SiC, GaN, Ga2O3, AlN (typically 100nm-50μm thick) on a high-resistivity substrate through a silicon dioxide dielectric or other dielectric layer material such as BCB, and the composite wafer is formed by wafer-level bonding.

[0144] 2. The silicon switch control unit 6 and silicon CMOS low-voltage logic unit 7 of the chip are fabricated in the silicon thin film layer; the low-voltage logic area can be isolated by etching part or all of the silicon thin film layer 3 to form an surrounding isolation trench and filling it with SiO2 / SiN or other media, which is a simple and convenient process.

[0145] 3. The high-voltage power DMOS or LDMOS transistor section of the chip adopts a composite structure. The silicon switch control unit 6 of the power transistor is completed in the silicon thin film layer. The MOS switch control region is constructed using conventional silicon-based CMOS technology, and then connected to the high-voltage region of the wide bandgap semiconductor material under the bonding interface dielectric layer through metal vias. The typical structure of the high-voltage region is constructed by combining the lateral P-Top layer 203 and the P+ buried layer of the wide bandgap semiconductor region, which can effectively provide lateral voltage withstand turn-off in reverse and good forward conduction characteristics. The P-Top layer 203 at the top of the wide bandgap semiconductor thin film layer is connected to the source 601 of the upper silicon switch control unit through metal vias. The source metal field plate is connected to construct a lateral equipotential P-type field plate to achieve more reliable lateral withstand voltage capability; the metal via is constructed by etching a via that penetrates the silicon thin film layer 3 and the bonding interface dielectric layer. The bottom of the via contacts the ohmic contact 9 metal region on the surface of the wide bandgap semiconductor material. The wall of the metal via is covered with a dielectric isolation layer with a thickness of tens of nanometers to hundreds of nanometers. The center of the metal via is filled with metal Via material, which contacts the ohmic contact 9 metal region of the wide bandgap semiconductor and plays an electrical connection role.

[0146] 4. Optionally, the silicon CMOS logic and switch control unit of the chip can be placed above the P-Top layer of the high-voltage power DMOS or LDMOS in the chip top view layout to save chip layout area; or it can be placed separately in an area other than the high-voltage power transistor.

[0147] 5. This solution features a simple and easy isolation scheme that self-isolates the high-voltage power transistor region and the low-voltage logic region. The high-voltage withstand region of the high-voltage power transistor is located in a wide-bandgap semiconductor thin film material, which is not on the same physical layer as the silicon CMOS logic and switch control unit, and is naturally isolated by an interface bonding dielectric layer 8 in between; it does not require the additional fabrication of various complex isolation designs and complex processes in the traditional silicon-based BCD process.

[0148] 6. This solution can also be fabricated using a composite wafer of a high-resistivity SiC single-crystal thin film layer and a polycrystalline silicon carbide layer. The advantage of this alternative is that the polycrystalline silicon carbide substrate has low wafer substrate cost and excellent heat dissipation characteristics, which can further optimize chip cost and heat dissipation capabilities. Simultaneously, in subsequent integration of multiple high-voltage, high-power dies, the high-resistivity SiC single-crystal thin film layer can provide a simple trench isolation technique for the upper arm 1 region 303, the lower arm 1 region 304, and other arm regions 305 of the high-voltage power transistor. Only the isolation trenches need to be etched down to the P-type region on the upper surface of the high-resistivity SiC single-crystal thin film layer. + By etching away the buried layer 202, high-voltage isolation between different circuit structures of the high-voltage die can be achieved.

[0149] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A wide-bandgap semiconductor composite high-voltage vertical power chip, characterized in that, It is a high-voltage BCD chip; The chip includes at least one cell structure unit, which includes a substrate (1), a horizontally integrated high-voltage layer (2) made of a wide bandgap thin film material, a silicon thin film layer (3), a silicon CMOS logic and switch control unit connected to the silicon thin film layer (3), and a first multilayer dielectric layer (4). The horizontally integrated high-voltage layer (2) and the silicon thin film layer (3) are arranged vertically. The laterally integrated high-pressure-resistant layer (2) includes a laterally integrated high-pressure-resistant structural region (201) made of a wide-bandgap thin-layer material, P + Burial layer (202) and P-Top layer (203), wherein the P + The buried layer (202) and the P-Top layer (203) are located on the upper and lower sides of the horizontally integrated high-pressure-resistant structure area (201), respectively. The horizontally integrated high-pressure-resistant layer (2) and the silicon thin film layer (3) are connected by an interface bonding dielectric layer (8). The silicon thin film layer (3) is divided into the upper arm 1 region (303), the lower arm 1 region (304), and the other arm regions (305) of the high voltage power tube by a first isolation trench (301) and a second isolation trench (302) filled with multiple dielectric layers. The silicon CMOS logic and switch control unit includes a silicon switch control unit (6) and a silicon CMOS low-voltage logic unit (7). The silicon switch control unit (6) is located in region 1 (303) of the upper arm of the high-voltage power transistor, and the silicon CMOS low-voltage logic unit (7) is located in region 1 (304) of the lower arm of the high-voltage power transistor. The silicon CMOS logic and switch control unit is isolated by partially or completely etching the silicon thin film layer (3) to form an surrounding isolation trench and filling it with a first multilayer dielectric layer (4).

2. The wide bandgap semiconductor composite high-voltage vertical power chip according to claim 1, characterized in that, The silicon switch control unit (6) includes a source (601), a first gate (602) used as a control switch, a drain (603), a first Pwell region (604), and a first N-type gate. + District (605), Second N + District (606), Third N + District (607), Fourth N + The tube has a region (608), a P-connector post (609), a first connecting metal (6101), a second connecting metal (6111), and a third connecting metal (6121), with the drain (603) located in the other arm region (305) of the high-voltage power tube.

3. The wide bandgap semiconductor composite high-voltage vertical power chip according to claim 2, characterized in that, The horizontally integrated high-voltage layer (2) is connected between the silicon thin film layer (3) and the substrate (1), and the side of the silicon thin film layer (3) close to the substrate (1) is connected to the high-voltage structure region (201) through the interface bonding dielectric layer (8). The P-Top layer (203) is connected to the high-voltage structure region (201) at the interface bonding dielectric layer (8), with one end located below the upper arm 1 region (303) of the high-voltage power transistor and the other end located below the other arm regions (305) of the high-voltage power transistor.

4. The wide bandgap semiconductor composite high-voltage vertical power chip according to claim 1, characterized in that, The silicon thin film layer (3) is connected between the horizontally integrated high voltage-resistant layer (2) and the substrate (1). The silicon CMOS logic and switch control unit on the side of the silicon thin film layer (3) away from the substrate (1) is isolated by partially or completely etching the silicon thin film layer (3) to form an isolation trench and filling it with a first multilayer dielectric layer (4). It is connected to the P+ buried layer (202) through the interface bonding dielectric layer (8). The P-Top layer (203) side of the horizontally integrated high voltage-resistant layer (2) is connected to the second multilayer dielectric layer (5).

5. A wide bandgap semiconductor composite high-voltage vertical power chip according to claim 3, characterized in that, A first metal through hole (610) is formed on the upper arm 1 region (303) of the high-voltage power tube near the first isolation trench (301). A first P well region (604) is provided on the side of the upper arm 1 region (303) away from the first metal through hole (610), and a first N well region (604) is provided on the other side. + A second N is provided on the first P well area (604) in area (605). + Zone (606), two N + All regions are connected to ohmic contacts (9), and the first multilayer dielectric layer (4) is connected to two N-type contacts. + A first gate oxide layer is provided at the junction of the regions, and the first gate oxide layer is close to the first N. + One end of region (605) is connected to the first N + The ohmic contact (9) on region (605) is connected, and the first gate (602) is connected to the side of the first gate oxide layer away from the high-resistivity substrate. The first metal via (610) is connected to a first connecting metal (6101). A source electrode (601) is connected above the upper arm 1 region (303) of the high-voltage power transistor on the side of the first multilayer dielectric layer (4) away from the substrate. One end of the source electrode (601) is connected to the second N + The ohmic contact (9) on the area (606) is connected, and the other end is connected to the upper end of the first connecting metal (6101). The lower end of the first connecting metal (6101) is connected to the ohmic contact (9) at the end of the P-Top layer (203) away from the second isolation trench (302). First N + The area (605) is located on the side near the first metal through-hole (610) and is adjacent to the first N. + A second metal through-hole (611) is provided at the junction of the zones (605). The lower end of the second metal through-hole (611) is located in the horizontally integrated high-pressure resistant structural zone (201). A second connecting metal (6111) is connected inside the second metal through-hole (611). A P-connecting post (609) is connected below the second metal through-hole (611) on the high-pressure resistant structural zone (201). The side of the P-connecting post (609) near the second isolation trench (302) is connected to a third N-connecting post. + District (607), Third N + The area (607) extends beyond the P-connecting post (609) on the side near the second isolation trench (302), and the lower end of the second connecting metal (6111) is simultaneously connected to the P-connecting post (609) and the third N-connecting post. + The ohmic contact (9) of zone (607) is connected, and the upper end is connected to the first N. + The high-voltage power tube is connected by an ohmic contact (9) on the region (605). A third metal through-hole (612) is provided in the other tube arm region (305). A third connecting metal (6121) is connected inside the third metal through-hole (612). A fourth N+ region (608) with an ohmic contact (9) is connected below the third metal through-hole (612) on the high-voltage structure region (201). The drain (603) is connected to the fourth N+ region (608) through the third connecting metal (6121). + The ohmic contact (9) within zone (608) is connected; The walls of the first metal through-hole (610), the second metal through-hole (611), and the third metal through-hole (612) are covered with a dielectric isolation layer with a thickness of 10nm-800nm.

6. The wide bandgap semiconductor composite high-voltage vertical power chip according to claim 4, characterized in that, The silicon switch control unit (6) includes a source (601), a first gate (602) used as a control switch, a drain (603), a first P-well region (604), and a first N-well region. + District (605), Second N + District (606), Third N + District (607), Fourth N + Region (608), P-connecting post (609), fourth connecting metal (6131), fifth connecting metal (614), sixth connecting metal (615), seventh connecting metal (616), the drain (603) is located in the other tube arm region (305) of the high-voltage power tube; A fourth metal via (613) extending to the silicon thin film layer (3) is provided above the upper arm 1 region (303) of the high voltage power transistor on the horizontally integrated high voltage-resistant layer (2). A first P well region (604) is provided on the side of the upper arm 1 region (303) of the high voltage power transistor away from the fourth metal via (613), and a first N well region (604) is provided on the other side. + A second N is provided on the first P well area (604) in area (605). + Zone (606), two N + All regions are connected to ohmic contacts (9), and the first multilayer dielectric layer (4) is connected to two N-type contacts. + A first gate oxide layer is provided at the junction of the regions, and the first gate oxide layer is close to the first N. + One end of region (605) is connected to the first N + The ohmic contact (9) on region (605) is connected, and the first gate (602) is connected to the side of the first gate oxide layer away from the high-resistivity substrate. A source electrode (601) is connected above the second multilayer dielectric layer (5), and one end of the source electrode (601) is connected to the second N through a fifth connecting metal (614). + The ohmic contact (9) on the zone (606) is connected, and the other end is connected to the ohmic contact (9) on the end of the P-Top layer (203) away from the second isolation trench (302) through the sixth connecting metal (615); The fourth metal through-hole (613) is connected to a fourth connecting metal (6131). A P-connecting post (609) is connected to one end of the laterally integrated high-pressure-resistant layer (2) away from the second isolation trench (302). The side of the P-connecting post (609) closest to the second isolation trench (302) is connected to a third N-connecting post. + District (607), Third N + The area (607) extends beyond the P-connecting post (609) on the side near the second isolation trench (302), and the lower end of the fourth connecting metal (6131) is connected to the first N-connecting post. + The ohmic contact (9) on the zone (605) is connected, and the upper end is simultaneously connected to the P connecting post (609) and the third N. + The ohmic contact (9) of the zone (607) is connected above the other tube arm zone (305) of the high voltage power tube on the laterally integrated high voltage layer (2), and the fourth N with ohmic contact (9) is connected. + In region (608), the drain (603) is connected above the other tube arm region (305) of the high-voltage power tube on the second multilayer dielectric layer (5). The drain (603) is connected to the fourth N-type tube arm region (305) via the seventh connecting metal (616). + The ohmic contact (9) within zone (608) is connected; The fourth metal via (613) is covered with a dielectric isolation layer with a thickness of 10nm-800nm.

7. The wide bandgap semiconductor composite high-voltage vertical power chip according to claim 1, characterized in that, The substrate (1) is disposed on P + The buried layer (202) is a high-resistivity substrate on the side away from the laterally integrated high-voltage structure region (201); or the substrate (1) includes a connection to P + The buried layer (202) consists of a high-resistivity SiC single-crystal thin film layer on the side away from the laterally integrated high-voltage-resistant structural region (201) and a polycrystalline silicon carbide layer connected to the high-resistivity SiC single-crystal thin film layer on the side away from the laterally integrated high-voltage-resistant structural region (201). The bottom of the isolation trench penetrates P. + The buried layer (202) is located within the high-resistivity SiC single-crystal thin film layer; The high-resistivity substrate is high-resistivity SiC, sapphire, or a high-resistivity silicon wafer, and the thickness of the polycrystalline silicon carbide layer is 100-500 μm.

8. The wide bandgap semiconductor composite high-voltage vertical power chip according to claim 1, characterized in that, The laterally integrated high-voltage layer (2) is a wide-bandgap thin-film material, which is an N-type doped semiconductor material; the wide-bandgap thin-film material is made of SiC, GaN, Ga2O3 or AlN, with a thickness of 100nm-50μm; and / or, The material of the interfacial bonding dielectric layer (8) is SiO2 or benzocyclobutene resin, and the thickness of the interfacial bonding dielectric layer (8) is 1 nm-10 μm; and / or, The multilayer dielectric layer is composed of SiO2 and SiN composited by CVD chemical vapor deposition, and the thickness of the silicon thin film layer (3) is 100nm-10μm; and / or, The silicon thin film layer (3) is N-type doped and has a thickness of 100 nm-10 μm; and / or, The horizontally integrated high-pressure-resistant layer (2) is formed by epitaxy or bonding.

9. The fabrication process of a wide bandgap semiconductor composite high-voltage vertical power chip according to claim 5, characterized in that, Includes the following steps: S1. An N-type doped wide bandgap thin film is epitaxially or bonded on the substrate (1) as a high-voltage-resistant layer (2) for lateral integration. A P-type doped wide bandgap thin film is attached to the side of the wide bandgap thin film close to the high-resistivity substrate. + Burial layer (202); S2. Forming a third N-type material through ion implantation in a wide bandgap thin-layer material. + District (607), Fourth N + Zone (608), P connecting column (609) and P-Top pressure field plate area, and annealed and activated; S3. In the area where the device vias of the silicon thin film layer (3) need to be connected, ohmic contact (9) metal deposition is performed and annealing is performed to form ohmic contact (9). S4. Deposit an interfacial bonding dielectric layer on the side of the high-voltage-resistant layer made of wide-bandgap thin-film material away from the high-resistivity substrate using CVD, ALD or spin coating processes. S5. A layer of N-type doped silicon thin film is bonded by wafer-level bonding process (3). S6. A silicon switch control unit (6) and a silicon CMOS low-voltage logic unit (7) are fabricated in the silicon thin film layer (3) using CMOS technology. S7. Etch metal vias and isolation trenches in the silicon thin film layer (3). A dielectric isolation layer with a thickness of 10nm-800nm ​​is covered on the wall of the metal via. The center of the metal via is filled with connecting metal. The bottom of the connecting metal contacts the ohmic contact (9) metal region of the wide bandgap semiconductor to play an electrical connection role.

10. The fabrication process of a wide bandgap semiconductor composite high-voltage vertical power chip according to claim 9, characterized in that, Replace steps S5, S6, and S7 with steps S5-1 and S6-1; S5-1. After temporarily bonding the carrier wafer and grinding the back silicon substrate to 2-10μm, the substrate is then bonded at the wafer level to a high-voltage-resistant layer made of a wide bandgap thin-film material on the side away from the high-resistivity substrate; the carrier wafer is a silicon thin-film layer that integrates silicon CMOS logic and switch control unit. S6-1. Etch metal vias and isolation trenches in the silicon thin film layer. The walls of the metal vias are covered with a dielectric isolation layer with a thickness of 10nm-800nm. The center of the metal vias is filled with connecting metal. The bottom of the connecting metal contacts the ohmic contact (9) metal region of the wide bandgap semiconductor to play an electrical connection role.

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