Transistor device with dual-side contacts

Abstract

Devices including transistors and methods of manufacturing the same are disclosed. The transistor may include a source / drain (120) substantially enclosed in a source silicide layer / drain silicide layer (124), where an integrated source via portion / integrated drain via portion (122) of the source silicide layer / drain silicide layer (124) is directly coupled to a second source contact / second drain contact (104) on the top surface of the device, and wherein the first source / drain via (134) couples the source / drain silicide layer (124) to the first source / drain contact (144) on the backside surface of the device. The transistor may also include a gate disposed between the source and the drain.

Description

Technical Field

[0001] Various aspects of the present disclosure generally relate to three-dimensional integrated circuit (3DIC) devices, including transistor devices with dual-sided contacts or dual-sided contacts, and also including dual-sided (e.g., front-side and / or back-side) contacts in fin field effect transistor (FinFET) and all-around gate (GAA) devices. Background Art

[0002] Integrated circuit technology has made great progress in advancing computing power through miniaturized components such as semiconductor transistors. The development of semiconductors has evolved from bulk substrate and planar CMOS, FinFET, nanowire or nanoribbon, FinFET 3D stacking to nanowire or nanoribbon 3D stacking. 3DIC is one of the main trends in very large scale integration (VLSI) devices that continues the Moore (More Moore) era. Through silicon vias are important process modules that allow 3D stacking. An industrial trend is to stack active chips (e.g., system on chip (SOC) / high bandwidth memory (HBM)) vertically using through silicon vias (TSV) or buried power rails (BPR). However, conventional contact configurations limit the ability to connect high density in a stacked configuration.

[0003] Therefore, there is a need for systems, apparatus, and methods that overcome the deficiencies of conventional designs, including those provided herein below in the disclosure for FinFET and gate-all-around (GAA) devices. Summary of the invention

[0004] A simplified summary of the invention related to one or more aspects disclosed herein is presented below. Therefore, the following summary of the invention should not be regarded as a general overview related to all considered aspects, nor should the following summary of the invention be regarded as identifying key or important elements related to all considered aspects or as describing the scope associated with any particular aspect. Therefore, the sole purpose of the following summary of the invention is to present certain concepts related to one or more aspects related to the mechanisms disclosed herein in a brief form before the specific embodiments presented below.

[0005] One or more aspects include a device comprising a transistor, the transistor comprising: a drain, the drain being substantially enclosed in a drain silicide layer, wherein an integrated drain via portion of the drain silicide layer is coupled to a second drain contact, and wherein a first drain via couples the drain silicide layer to the first drain contact; a source, the source being substantially enclosed in a source silicide layer, wherein an integrated source via portion of the source silicide layer is coupled to a second source contact, and wherein a first source via couples the source silicide layer to a first source contact; and a gate, the gate being disposed between the source and the drain.

[0006] One or more aspects include a method for manufacturing a device including a transistor, comprising: forming a drain substantially enclosed in a drain silicide layer, wherein an integrated drain via portion of the drain silicide layer is coupled to a second drain contact, and wherein a first drain via couples the drain silicide layer to the first drain contact; forming a source substantially enclosed in a source silicide layer, wherein an integrated source via portion of the source silicide layer is coupled to a second source contact, and wherein a first source via couples the source silicide layer to a first source contact; and forming a gate disposed between the source and the drain.

[0007] Other objects and advantages associated with the various aspects disclosed herein will be apparent to those skilled in the art based on the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are presented to aid in describing various aspects of the present disclosure and are provided for purposes of illustration only and not limitation of the various aspects.

[0009] Figure 1A A partial top view of an apparatus according to one or more aspects of the present disclosure is shown.

[0010] Figure 1B According to one or more aspects of the present disclosure, Figure 1A Partial cross-sectional view of the device.

[0011] Figure 1C According to one or more aspects of the present disclosure, Figure 1A Partial cross-sectional view of the device.

[0012] Figure 1D According to one or more aspects of the present disclosure, Figure 1A Partial cross-sectional view of the device.

[0013] Figure 2A A partial top view of an apparatus according to one or more aspects of the present disclosure is shown.

[0014] Figure 2B According to one or more aspects of the present disclosure, Figure 2A Partial cross-sectional view of the device.

[0015] Figure 2C According to one or more aspects of the present disclosure, Figure 2A Partial cross-sectional view of the device.

[0016] Figure 2D According to one or more aspects of the present disclosure, Figure 2A Partial cross-sectional view of the device.

[0017] Figure 3 A partial cross-sectional view of an apparatus according to one or more aspects of the present disclosure is shown.

[0018] Figure 4A-4H An example of stages in fabricating an integrated circuit structure according to one or more aspects of the present disclosure is shown.

[0019] Figure 5 Components of an integrated device according to one or more aspects of the present disclosure are shown.

[0020] Figure 6 A flow chart of a method for manufacturing a device according to one or more aspects of the present disclosure is shown.

[0021] Figure 7 An exemplary mobile device in accordance with one or more aspects of the present disclosure is shown.

[0022] Figure 8 Various electronic devices are shown that may be integrated with any of the devices disclosed according to one or more aspects of the present disclosure.

[0023] As a matter of convention, the features depicted in the drawings may not be drawn to scale. Therefore, the dimensions of the depicted features may be arbitrarily expanded or reduced for clarity. As a matter of convention, some of the drawings are simplified for clarity. Therefore, the drawings may not depict all components of a particular device or method. In addition, throughout the specification and drawings, the same reference numerals represent the same features. DETAILED DESCRIPTION

[0024] Various aspects of the present disclosure are provided in the following description and related drawings for various examples provided for illustrative purposes. Alternative aspects may be designed without departing from the scope of the present disclosure. In addition, well-known elements of the present disclosure will not be described in detail or will be omitted so as not to obscure the relevant details of the present disclosure.

[0025] The words "exemplary" and / or "example" are used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" and / or "example" is not necessarily to be construed as preferred or advantageous over other aspects. Likewise, the term "aspects of the disclosure" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation.

[0026] Those skilled in the art will appreciate that any of a variety of different techniques and technologies may be used to represent the information and signals described below. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the following description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof, which depends in part on the specific application, in part on the desired design, in part on the corresponding technology, and so on.

[0027] In some of the described example implementations, instances are identified where portions of various component structures and operations may be taken from known conventional techniques and then arranged according to one or more exemplary aspects. In these instances, internal details of portions of known conventional component structures and / or operations may be omitted to help avoid potential confusion of the concepts illustrated in the illustrative aspects disclosed herein.

[0028] The terms used herein are for the purpose of describing particular aspects and are not intended to be limiting. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises", "comprising", "includes", and / or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, without excluding the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0029] Figure 1A A partial top view of a device 100 according to one or more aspects of the present disclosure is shown. The top view is a top view of a wafer flipped backside. In some aspects, the device can be or include one or more three-dimensional integrated circuit (3DIC) devices. The top view shows a plurality of transistors in a cell configuration, with cross-sectional lines AA', BB', and CC', which will be described in detail in the following description.

[0030] Figure 1B According to one or more aspects of the present disclosure, Figure 1A 1. A partial cross-sectional view of a device 100. Specifically, along a path including a plurality of gate structures 150 Figure 1AThe BB' line of FIG. 1 shows the cross-sectional view. The gate polysilicon 156 can be heavily doped polysilicon (Poly) and includes a plurality of channels 152, which are lightly doped silicon (Si) in some aspects and are surrounded by a gate oxide 154, which is silicon dioxide (SiO2) in some aspects. A gate contact layer 158, which is a silicide in some aspects, is disposed on the gate polysilicon 156. A front side dielectric 162 is disposed on the plurality of gate structures 150, and a back side dielectric 164 is disposed on the opposite side of the plurality of gate structures 150.

[0031] Figure 1C According to one or more aspects of the present disclosure, Figure 1A A partial cross-sectional view of the device 100. Specifically, along Figure 1AThe cross-sectional view is shown by line AA' of . The device 100 includes a transistor 101 having a drain 110 substantially enclosed in a drain silicide layer 114 (e.g., in some aspects, only a portion of a source-adjacent channel 152 is exposed). An integrated drain via portion 112 of the drain silicide layer 114 is coupled to a second drain contact 102 (which is part of a backside metallization structure discussed in further detail below). A first drain via 132 couples the drain silicide layer 114 to a first drain contact 142 (which is part of a frontside metallization structure discussed in further detail below). The source 120 is substantially enclosed in a source silicide layer 124. An integrated source via portion 122 of the source silicide layer 124 is coupled to a second source contact 104 (which is part of a backside metallization structure discussed in further detail below). The first source via 134 couples the source silicide layer 124 to the first source contact 144 (which is part of the front side metallization structure discussed in further detail below). The gate structure 150 is disposed between the source 120 and the drain 110. The front side dielectric 162 is disposed on the front side of the transistor 101 and the back side dielectric 164 is disposed on the opposite side of the transistor 101. In some aspects, the thickness of the integrated drain via portion (112) and the integrated source via portion (122) (indicated by the dotted lines) are each on the order of 5nm to 40nm. In some aspects, the integrated source via portion 122 is in direct contact with the second source contact 104, and the integrated drain via portion 112 is in direct contact with the second drain contact 102. In some aspects, the drain silicide layer 114 and the source silicide layer 124 each have a substantially uniform thickness. In some aspects, drain silicide layer 114 and source silicide layer 124 have substantially the same thickness. In some aspects, integrated drain via portion 112 is embedded in drain silicide 114 and drain 110 (e.g., integrated drain via portion 112 is formed as part of the drain layer). In some aspects, integrated drain via portion 112 is an extension of drain silicide 114 and drain 110 (e.g., integrated drain via portion 112 is formed as an additional portion of the drain layer).

[0032] Figure 1D According to one or more aspects of the present disclosure, Figure 1A A partial cross-sectional view of the device 100. Specifically, along Figure 1AThe CC' line of FIG. 1 shows a cross-sectional view. The device 100 includes a transistor 101 having a drain 110, wherein a source 120 is substantially enclosed in a source silicide layer 124. An integrated source via portion 122 of the source silicide layer 124 is coupled to a second source contact 104 (which is part of a backside metallization structure discussed in further detail below). A first source via 134 couples the source silicide layer 124 to a first source contact 144 (which is part of a frontside metallization structure discussed in further detail below). In some aspects, the integrated source via portion 122 is embedded in the source silicide 124 and the source 120 (e.g., the integrated source via portion 122 is formed as part of the source layer). In some aspects, the integrated source via portion 122 is an extension of the source silicide 124 and the source 120 (e.g., the integrated source via portion 122 is formed as an additional portion of the source layer). Front side dielectric 162 is disposed on the front side of transistor 101 and back side dielectric 164 is disposed on the opposite side of transistor 101, however, in some portions, front side dielectric 162 and back side dielectric 164 may form a substantially homogenous dielectric portion surrounding transistor 101 and other transistors of device 100. A portion of another transistor 171 is shown and has similar features as transistor 101, so details will not be provided.

[0033] In some aspects, the drain 110 and the source 120 can be formed of one of silicon or carbon-doped silicon (e.g., for nFET) or silicon germanium (SiGE) (e.g., for pFET). In some aspects, the second source contact 104, the second drain contact 102, the first drain contact 142, and the first source contact 144 are formed of one or more of tungsten (W), copper (Cu), palladium (Pd), nickel (Ni), gold (Au), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), bismuth (Bi), antimony (Sb), molybdenum (Mo), and ruthenium (Ru), or any highly conductive material. In some aspects, the first drain via 132 and the first source via 134 are formed of tungsten (W) or any highly conductive material.

[0034] It will be appreciated that in various aspects disclosed, the transistors (e.g., 101, 171) of the device 100 can be electrically connected to the source and drain on a first side (front side) and / or a second side (back side). In addition, it will be appreciated that, although it is possible to be electrically connected on both sides, in some aspects, the source and / or drain can be connected only on one side. For example, the source and drain of transistor 101 can be connected on the front side, and the drain and source of transistor 171 can be connected only on the back side. In addition, it will be appreciated that the ability to have front side contacts and / or back side contacts to form front side connections and / or back side connections allows for improved standard cell configurations, which are discussed in subsequent portions of the present disclosure.

[0035] Figure 2A A partial top view of a device 200 according to one or more aspects of the present disclosure is shown. The top view is a view of the wafer backside flipped. In some aspects, the device can be or include one or more three-dimensional integrated circuit (3DIC) devices, including all-around gate (GAA) devices. The top view shows multiple transistors in a cell configuration, with cross-sectional lines AA', BB', and CC', which will be described in detail in the following description.

[0036] Figure 2B According to one or more aspects of the present disclosure, Figure 2A 200. Specifically, along the path including the plurality of gate structures 250 Figure 2A The BB' line shows the cross-sectional view. The gate polysilicon 256 can be heavily doped polysilicon (Poly) and includes a plurality of gate stack portions 252, which are lightly doped silicon in some aspects and are surrounded by a gate oxide 254, which is silicon dioxide (SiO2) in some aspects. A gate contact layer 258, which is a silicide in some aspects, is disposed on the gate polysilicon 256. A front side dielectric 262 is disposed on the plurality of gate structures 250, and a back side dielectric 264 is disposed on the opposite side of the plurality of gate structures 250.

[0037] Figure 2C According to one or more aspects of the present disclosure, Figure 2A A partial cross-sectional view of the device 200. Specifically, along Figure 2AThe cross-sectional view is shown along the AA' line of FIG. 2. The device 200 includes a transistor 201 having a drain 210 substantially enclosed in a drain silicide layer 214. An integrated drain via portion 212 of the drain silicide layer 214 is coupled to a second drain contact 202 (which is part of a backside metallization structure discussed in further detail below). A first drain via 232 couples the drain silicide layer 214 to a first drain contact 242 (which is part of a frontside metallization structure discussed in further detail below). The source 220 is substantially enclosed in a source silicide layer 224. An integrated source via portion 222 of the source silicide layer 224 is coupled to a second source contact 204 (which is part of a backside metallization structure discussed in further detail below). A first source via 234 couples the source silicide layer 224 to a first source contact 244 (which is part of a frontside metallization structure discussed in further detail below). The gate structure 250 is disposed between the source 220 and the drain 210. The front side dielectric 262 is disposed on the front side of the transistor 201, and the back side dielectric 264 is disposed on the opposite side of the transistor 201. In some aspects, the integrated source via portion 222 is in direct contact with the second source contact 204, and the integrated drain via portion 212 is in direct contact with the second drain contact 202. In some aspects, the drain silicide layer 214 and the source silicide layer 224 each have a substantially uniform thickness. In some aspects, the drain silicide layer 214 and the source silicide layer 224 have substantially the same thickness. In some aspects, the integrated drain via portion 212 is embedded in the drain silicide 214 and the drain 210. In some aspects, the integrated drain via portion 212 is an extension of the drain silicide 214 and the drain 210.

[0038] Figure 2D According to one or more aspects of the present disclosure, Figure 2A A partial cross-sectional view of the device 200. Specifically, along Figure 2AThe cross-sectional view is shown by the CC' line of FIG. 2. The device 200 includes a transistor 201 in which a source 220 is substantially enclosed in a source silicide layer 224. An integrated source via portion 222 of the source silicide layer 224 is coupled to a second source contact 204 (which is part of a backside metallization structure discussed in further detail below). A first source via 234 couples the source silicide layer 224 to a first source contact 244 (which is part of a frontside metallization structure discussed in further detail below). In some aspects, the integrated source via portion 222 is embedded in the source silicide 224 and the source 220. In some aspects, the integrated source via portion 222 is an extension of the source silicide 224 and the source 220. A front side dielectric 262 is disposed on the front side of the transistor 201, and a back side dielectric 264 is disposed on the opposite side of the transistor 201. The front side dielectric 262 is disposed on the front side of the transistor 201 and the back side dielectric 264 is disposed on the opposite side of the transistor 201, however, in some portions, the front side dielectric 262 and the back side dielectric 264 can form a substantially homogeneous dielectric portion surrounding the transistor 201 and other transistors of the device 200.

[0039] In some aspects, the drain 210 and the source 220 can be formed of one of carbon-doped silicon (e.g., for nFET) or silicon germanium (SiGE) (e.g., for pFET). In some aspects, the second source contact 204, the second drain contact 202, the first drain contact 242, and the first source contact 244 are formed of one or more of tungsten (W), copper (Cu), palladium (Pd), nickel (Ni), gold (Au), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), bismuth (Bi), antimony (Sb), molybdenum (Mo), and ruthenium (Ru), or any highly conductive material. In some aspects, the first drain via 232 and the first source via 234 are formed of tungsten (W) or any highly conductive material.

[0040] It will be appreciated that in various aspects disclosed, the transistors (e.g., 201, 271) of the device 200 can be electrically connected to the source and drain on a first side (front side) and / or a second side (back side). In addition, it should be appreciated that, although capable of being electrically connected on both sides, in some aspects, the source and / or drain can be connected only on one side. For example, the source and drain of transistor 201 can be connected on the front side, and the drain and source of transistor 271 can be connected only on the back side.

[0041] Figure 3A partial cross-sectional view of a device 300 according to one or more aspects of the present disclosure is shown. The device 300 includes a transistor 301, similar to the transistors described above (e.g., 101, 201). Therefore, details of all transistor 301 structures will not be specifically labeled or provided. As discussed with respect to existing transistors, the transistor 301 has a drain 310 substantially enclosed in a drain silicide layer 314, and a source 320 substantially enclosed in a source silicide layer 324. An integrated drain via portion 312 of the drain silicide layer 314 is coupled to a second drain contact 302 that is part of a backside metallization 370 structure (specifically, a metal layer 370-0 (BM0)). An integrated source via portion 322 of the source silicide layer 324 is coupled to a second source contact 304, which is also part of a backside metallization 370 structure (specifically, a metal layer 370-0 (BM0)). The first drain via 332 couples the drain silicide layer 314 to a first drain contact 342 that is part of the front side metallization structure 360, specifically the metal layer 360-0 (M0). The first source via 334 couples the source silicide layer 324 to a first source contact 344 that is also part of the front side metallization structure 360, specifically the metal layer 360-0 (M0). The front side metal layers 360-0, 360-1, 360-2, 360-n are formed in a front side dielectric 362. The front side dielectric 362 provides insulation for the front side metallization structure 360. The back side metal layers 370-0, 370-1, 370-2, 370-m are formed in the front side dielectric 372. The back side dielectric 372 provides insulation for the back side metallization structure 370.

[0042] It will be appreciated that in the various disclosed aspects, the front side metallization structure 360 ​​and the back side metallization structure 370 can be coupled to different front side contact structures and back side contact structures as disclosed herein (e.g., directly to silicide, silicide to vias, etc.). For example, vias can be used to couple to one or both of the front side metallization structure 360 ​​or the back side metallization structure 370.

[0043] It will be appreciated that the reduction in IC thickness can be achieved by directly coupling the integrated drain via portion 312 to the second drain contact 302 and the integrated source via portion 322 to the second source contact 304 (both of which are part of the backside metallization 370 structure). In addition, the connectivity and 3DIC performance of local devices can be improved. For example, multiple ICs can be stacked to provide increased functionality and a smaller form factor. In some aspects, the integrated drain via portion 312 and / or the integrated source via portion 322 can be directly coupled to a buried power rail (BPR). In this configuration, the limitations of conventional micro-silicon through-via (mTSV) coupling are eliminated. In addition, the integrated drain via portion 312 and the integrated source via portion 322 allow backside interconnection and can be directly used to connect power rails similar to BPR. However, unlike BPR, the integrated drain via portion 312 / integrated source via portion 322 does not require any additional area outside the active device, which provides more flexibility for connection and is not limited to power or ground grids.

[0044] Figures 4A-4H An example of stages in fabricating an integrated circuit structure according to one or more aspects of the present disclosure is shown. In this case, these stages can be applied to the fabrication of an apparatus 400 similar to the apparatus 100, 200, and 300 described above.

[0045] Figure 4A A portion of the manufacturing process of the device 400 according to one or more aspects of the present disclosure is shown. In the illustration, a plan view and three cross-sectional views are provided. The cross-sectional views are along the AA' line, the BB' line and the CC' line of the plan view, and the plan view is a top view. At this stage of the manufacturing process, a channel 452 and a gate spacer 451 are formed. Specifically, the cross-sectional view is shown along the BB' line and includes a plurality of gate structures 450. The gate polysilicon 256 can be heavily doped polysilicon (Poly) and includes a plurality of channels 452, which are lightly doped silicon in some aspects and are surrounded by a gate oxide 454, which is silicon dioxide (SiO2) in some aspects. A buried oxide layer 459, which is SiO2 in some aspects, is disposed on a substrate 461, which is lightly doped silicon in some aspects. The cross-sectional view shown along the AA' line and the cross-sectional view shown along the CC' line (along the source / drain (S / D) region) each include similar elements observed from the perspective shown.

[0046] Figure 4BA portion of a manufacturing process of a device 400 according to one or more aspects of the present disclosure is shown. In the illustration, a plan view and three cross-sectional views are provided. The cross-sectional views are along the AA' line, the BB' line, and the CC' line of the plan view, and the plan view is a top view. At this stage of the manufacturing process, a source / drain is formed. The source 420 / drain 410 (S / D) can be formed by the commonly used epitaxial (epi) technology. Epitaxy involves growing crystalline material (e.g., using carbon-doped silicon or SiGe) on the surface of the channel 452 to reduce parasitic series resistance. The cross-sectional view shown along the AA' line includes the source 420 and the drain 410 and the gate structure 450, and the gate structure 450 includes the channel 452, the gate polysilicon 456, and the channel 452. The buried oxide layer 459 between the substrate 461, the cross-sectional view shown along the CC' line (along the source / drain region, each of which will have a similar structure), each source 420 (and drain) has a generally diamond shape in some aspects in this perspective view. The cross-sectional view shown along the BB' line (channel portion) includes multiple gate structures 450, which include gate polysilicon 456, which includes multiple channels 452, gate oxide 454, and gate oxide 454 is SiO2 in some aspects. The cross-sectional view shown along the BB' line is similar to Figure 4A The components are unchanged, and thus detailed descriptions of all the elements will not be presented.

[0047] Figure 4CA portion of the manufacturing process of a device 400 according to one or more aspects of the present disclosure is shown. In the illustration, a plan view and three cross-sectional views are provided. The cross-sectional views are along the AA' line, the BB' line and the CC' line of the plan view, and the plan view is a top view. At this stage of the manufacturing process, the silicide is disposed above the source / drain portion. The cross-sectional view shown along the AA' line includes a source 420 substantially surrounded by a source silicide layer 424 and a drain 410 substantially surrounded by a drain silicide layer 414. The gate structure 450 also has a portion of the gate polysilicon 456 that is removed and replaced by a gate contact layer 458 opposite to the channel 452. A buried oxide layer 459 is disposed between the silicide layers 414, 424 and the substrate 461. The cross-sectional view shown along the CC' line (along the source region) includes a plurality of source structures, each source 420 having a diamond shape in some aspects in this perspective view and surrounded by a source silicide layer 424. The silicide layers 414 and 424 may also have a diamond shape, such as in some aspects, the silicide layers 414 and 424 have a uniform thickness and may also have the same thickness. The cross-sectional view shown along the BB' line (channel portion) includes a plurality of gate structures 450, which include gate polysilicon 456, which includes a plurality of channels 452 and a gate oxide 454. In addition to the silicide forming the gate contact layer 458, the cross-sectional view shown along the BB' line is similar to Figure 4A The components are unchanged, and thus detailed descriptions of all the elements will not be presented.

[0048] Figure 4DA portion of a manufacturing process for a device 400 according to one or more aspects of the present disclosure is shown. In the illustration, a plan view and three cross-sectional views are provided. The cross-sectional views are along the AA' line, the BB' line, and the CC' line of the plan view, and the plan view is a flipped top view. At this stage of the manufacturing process, one or more front-side metal layers may be formed, including a first drain contact 442, a first drain via 432, a first source via 434, and a first source contact 444. This may be achieved through standard CMOS front-end-of-line (FEOL), middle-of-line (MOL), and back-end-of-line (BEOL) processes. In addition, after BEOL processing, the wafer is flipped, so the top view is from a flipped perspective. The cross-sectional view shown along the AA' line includes a source 420 substantially surrounded by a source silicide layer 424, which is coupled to a first source via 434 and a first source contact 444. The drain 410 is substantially surrounded by a drain silicide layer 414, which is coupled to the first drain via 432 and the first drain contact 442. A front side dielectric 462 is disposed on the front side of the transistor 401. The cross-sectional view shown along the CC' line (along the source region) includes a plurality of source structures, each source 420 having a diamond shape in some aspects of the perspective view, and surrounded by a source silicide layer 424 coupled to the first source via 434 and the first source contact 444. The cross-sectional view shown along the BB' line (channel portion) includes a plurality of gate structures 450, which include gate polysilicon 456, and each gate structure includes a channel 452, a gate oxide 454. A gate contact layer 458 is disposed between the gate polysilicon 456 and the front side dielectric 462. Since the wafer has been flipped, the substrate 461 and the buried oxide layer 459 are now shown on the top.

[0049] Figure 4E A portion of a manufacturing process of a device 400 according to one or more aspects of the present disclosure is shown. In the illustration, a plan view and three cross-sectional views are provided. The cross-sectional views are along the AA' line, the BB' line, and the CC' line of the plan view, and the plan view is a flipped top view. At this stage of the manufacturing process, the substrate and the buried oxide layer are removed, which exposes the bottom side of the source 420, the source silicide layer 424, the drain 410, and the drain silicide layer 414 for further processing. Since no other changes are made at this stage, further details of the cross-sectional views along the AA' line, the BB' line, and the CC' line will not be provided.

[0050] Figure 4FA portion of the manufacturing process of the device 400 according to one or more aspects of the present disclosure is shown. In the illustration, a plan view and three cross-sectional views are provided. The cross-sectional views are along the AA' line, BB' line and CC' line of the plan view, and the plan view is a flipped top view. At this stage of the manufacturing process, selective etching is used to remove silicon from a portion of the channel 452 and the polysilicon (gate polysilicon 456), but the silicide is retained. This forms a groove 475 between the source 420, the source silicide layer 424, the drain 410 and the drain silicide layer 414 in the channel region. Since no other changes are made at this stage, further details of the cross-sectional views along the AA' line, the BB' line and the CC' line will not be provided.

[0051] Figure 4G A portion of a manufacturing process for a device 400 according to one or more aspects of the present disclosure is shown. In the illustration, a plan view and three cross-sectional views are provided. The cross-sectional views are along the AA' line, the BB' line, and the CC' line of the plan view, and the plan view is a flipped top view. At this stage of the manufacturing process, a backside dielectric layer is deposited, and chemical mechanical polishing (CMP) is performed to expose the source 420 enclosed in the source silicide layer 424 and the drain 410 enclosed in the drain silicide layer 414. In addition, CMP provides a smooth planar surface on the backside dielectric 464, the source silicide layer 424, and the drain silicide layer 414. In particular, CMP provides a smooth contact surface for the integrated source via portion 422 of the source silicide layer 424 and the integrated drain via portion 412 of the drain silicide layer 414 for further processing. It will be appreciated that in some aspects, the integrated drain via portion 412 can be embedded, e.g., formed as part of the drain silicide layer 414, or in other aspects, the integrated drain via portion 412 can be extended, e.g., formed as an additional portion / layer of the drain silicide layer 414. Likewise, it will be appreciated that in some aspects, the integrated source via portion 422 can be embedded, e.g., formed as part of the source silicide layer 424, or in other aspects, the integrated source via portion 422 can be extended, e.g., formed as an additional portion / layer of the source silicide layer 424. Further details of the cross-sectional views along lines AA', BB', and CC' will not be provided as no other changes are made at this stage.

[0052] Figure 4HA portion of a manufacturing process for a device 400 according to one or more aspects of the present disclosure is shown. In the illustration, a plan view and three cross-sectional views are provided. The cross-sectional views are along lines AA', BB', and CC' of the plan view, which is a flipped top view. At this stage of the manufacturing process, BEOL processing is performed on the back side of the device 400. The BEOL processing is used to form a second drain contact 402 directly on an integrated drain via portion 412 of the drain silicide layer 414, and to form a second source contact 404 directly on an integrated source via portion 422 of the source silicide layer 424. The integrated via portions 412 and 422 allow for improved resistance to overlap or coverage between the integrated via portions 412 and 422 and metal wiring (e.g., contacts 102 and 104). As part of the BEOL processing on the back side, a backside dielectric 464 is disposed over the contacts and additional metal layers on the back side (note that the additional metal layers are not shown). As no other changes were made at this stage, further details of the cross-sectional views along lines AA', BB' and CC' will not be provided, however the various elements are numbered consistently with previously described elements.

[0053] Figure 5Components of an integrated device 500 according to one or more aspects of the present disclosure are shown. Regardless of the various configurations of the device including the transistor with the above-described double-sided contacts, it will be appreciated that any of these configurations (e.g., 100, 200, 300, 400) can be configured as a die 510, a die 511, and / or a die 512, which can be encapsulated in an encapsulation material 515 to form a three-dimensional integrated circuit (3DIC) device 501. It will be appreciated that the various aspects are not limited to this configuration, and more or fewer dies can be provided with or without encapsulation. The packaging substrate 520 can be configured to couple the die 510 to a printed circuit board 590 (PCB 590). PCB 590 is also coupled to a power source 580 (e.g., a power management integrated circuit (PMIC) that allows package substrate 520 and die 510 to be electrically coupled to PMIC 580. Specifically, one or more power (VDD) lines 591 and one or more ground (GND) lines 592 may be coupled to PMIC 580 to distribute power to PCB 590, package substrate 520 via VDD BGA pins 525 and GND BGA pins 527, and to distribute power to die 510 coupled to top metal layer / M1 layer 526 of package substrate 520. As is known in the art, package substrate 520 has a bottom metal layer 522 and may have one or more internal metal layers 524. It will be appreciated that the various aspects disclosed are not limited to any particular number of metal layers in package substrate 520. VDD line 591 and GND line 592 may each be formed by a trace, shape, or pattern in one or more metal layers of PCB 590 (e.g., layers 1-6) that are connected to the PCB 590 by one or more vias. 590. As is known to those skilled in the art, PCB 590 may have one or more PCB capacitors (PCB caps) 595 that may be used to regulate power signals. Additional connections and devices may be coupled to PCB 590 and / or pass through PCB 590 to package substrate 520 via one or more additional BGA pins (not shown) on package substrate 520. It will be appreciated that the configurations and descriptions shown are intended only to help explain the various aspects disclosed herein. For example, PCB 590 may have more or fewer metal layers and insulating layers, there may be multiple lines providing power to various components, etc. Therefore, the above-described illustrative examples and associated drawings should not be construed as limiting the various aspects disclosed and claimed herein.

[0054] In order to fully illustrate the various aspects of the design of the present disclosure, manufacturing methods are discussed herein with respect to the various aspects disclosed. Other manufacturing methods are possible, and the manufacturing methods discussed are presented only to assist in understanding the concepts disclosed herein. It will be appreciated that any of the manufacturing processes discussed are provided only as a general illustration of some of the aspects of the present disclosure and are not intended to limit the present disclosure or the appended claims. In addition, many details of the manufacturing processes known to those skilled in the art may have been omitted or combined in the overview process section to facilitate understanding of the various aspects disclosed without the need for detailed description of each detail and / or all possible process variations.

[0055] From the foregoing it will be appreciated that there are various methods for making the devices disclosed herein. Figure 6 A flow chart of a method 600 for fabricating a device (e.g., 100, 200, 300, 400, 500) is shown. The method may include forming a drain substantially enclosed in a drain silicide layer at block 602, wherein an integrated drain via portion of the drain silicide layer is coupled to a second drain contact, and wherein a first drain via couples the drain silicide layer to the first drain contact. The method also includes forming a source substantially enclosed in a source silicide layer at block 604, wherein an integrated source via portion of the source silicide layer is coupled to a second source contact, and wherein the first source via couples the source silicide layer to the first source contact. The method also includes forming a gate disposed between the source and the drain at block 606. It will be appreciated that the fabrication methods described above are provided at a high level to highlight the fabrication of the general novel aspects of the various aspects disclosed, and are not intended to provide a detailed fabrication process, which may vary according to various designs known in the art.

[0056] Therefore, it will be appreciated from the foregoing disclosure that additional processes for making various aspects disclosed herein will be apparent to those skilled in the art, and detailed process descriptions related to the processes discussed above will not be provided or shown in the included figures. It will be appreciated that the sequence of fabrication processes need not be in any order, and that later processes may be discussed earlier for convenience and to provide an example of the scope of the various aspects disclosed.

[0057] The aforementioned disclosed devices and functions may be designed and stored in computer files (e.g., register transfer level (RTL), geometry data flow (GDS) Gerber, etc.) stored on a computer readable medium. Some or all of such files may be provided to a fabrication operator who fabricates the device based on such files. The resulting products may include various components, including semiconductor wafers, which are then cut into semiconductor dies and packaged into semiconductor packages, integrated devices, packages on packages, system-on-chip devices, etc., which may then be used in the various devices described herein.

[0058] It will be appreciated that the various aspects disclosed herein may be described as functional equivalents to structures, materials, and / or devices described and / or identified by those skilled in the art. For example, in one aspect, an apparatus may include units for performing the various functions discussed above. It will be appreciated that the foregoing aspects are provided by way of example only, and the various aspects claimed are not limited to the specific references and / or illustrations cited as examples.

[0059] Figure 7 An exemplary mobile device according to some examples of the present disclosure is shown. Figure 7 , depicts a block diagram of a mobile device configured according to exemplary aspects and generally designated as a mobile device 700. In some aspects, the mobile device 700 can be configured as a wireless communication device. As shown, the mobile device 700 includes a processor 701. The processor 701 can be communicatively coupled to a memory 732 via a link, which can be a die-to-die link or a chip-to-chip link. The mobile device 700 also includes a display 728 and a display controller 726, wherein the display controller 726 is coupled to the processor 701 and the display 728.

[0060] In some respects, Figure 7 It may include: a coder / decoder (CODEC) 734 (e.g., an audio and / or voice CODEC) coupled to the processor 701; a speaker 736 and a microphone 738 coupled to the CODEC 734; and a wireless circuit 740 coupled to a wireless antenna 742 and the processor 701.

[0061] In one or more aspects, the processor 701, memory 732, wireless circuit 740 and / or other components of the mobile device 700 can be implemented using one or more of three-dimensional integrated circuit (3DIC) devices, which include transistor devices with double-sided contacts and further include double-sided contacts in FinFET and all-around gate (GAA) devices, as disclosed herein.

[0062] In certain aspects, with one or more of the above blocks present, the processor 701, display controller 726, memory 732, CODEC 734, and wireless circuit 740 may be included in a system-level package or system-on-chip device 722, which may be implemented in whole or in part using various aspects disclosed herein. Input device 730 (e.g., a physical or virtual keyboard), power supply 744 (e.g., a battery), display 728, input device 730, speaker 736, microphone 738, wireless antenna 742, and power supply 744 may be external to the system-on-chip device 722 and may be coupled to components in the system-on-chip device 722, such as an interface or controller.

[0063] It should be noted that although Figure 7 Mobile device 700 is depicted, but processor 701 and memory 732 may also be integrated into a set-top box, music player, video player, entertainment unit, navigation device, personal digital assistant (PDA), fixed location data unit, computer, laptop computer, tablet computer, communication device, mobile phone, or other similar device.

[0064] Figure 8 Various electronic devices that can be integrated with any of the aforementioned devices / three-dimensional integrated circuit (3DIC) devices according to various examples of the present disclosure are shown. For example, a mobile phone device 802, a laptop device 804, and a fixed location terminal device 806 can each be generally regarded as a user equipment (UE) and can include a semiconductor device 800 as described herein. The semiconductor device 800 can be, for example, any of the integrated circuits, bare chips, integrated devices, integrated device packages, integrated circuit devices, device packages, integrated circuit (IC) packages, single bare chips / multi-bare chips / molded multi-chip devices, etc. described herein. Figure 8 The devices 802, 804, 806 shown in the figure are merely exemplary. Other electronic devices may also feature the semiconductor device 800, including but not limited to a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), devices enabled with a global positioning system (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smart phones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, or any other devices that store or retrieve data or computer instructions, or any combination thereof.

[0065] It will be appreciated that the various aspects disclosed herein may be described as functional equivalents to structures, materials, and / or devices described and / or identified by those skilled in the art. For example, in one aspect, an apparatus may include units for performing the various functions discussed above. It will be appreciated that the foregoing aspects are provided by way of example only, and the various aspects claimed are not limited to the specific references and / or illustrations cited as examples.

[0066] Figure 1A-8 One or more of the components, processes, features, and / or functions shown in the drawings may be rearranged and / or combined into a single component, process, feature, or function, or incorporated into several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figure 1A-8 and the corresponding descriptions in the present disclosure are not limited to bare die and / or IC. In some implementations, Figure 1A-8 The corresponding descriptions may be used to manufacture, create, provide, and / or produce an integrated device. In some implementations, the device may include a bare die, an integrated device, a bare die package, an integrated circuit (IC), a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a system-in-package (SiP), a system-on-chip (SoC), a package-on-package (PoP) device, etc.

[0067] As used herein, the terms "user equipment" (or "UE"), "user device", "user terminal", "client device", "communication device", "wireless device", "wireless communication device", "handheld device", "mobile device", "mobile terminal", "mobile station", "handset", "access terminal", "subscriber device", "subscriber terminal", "subscriber station", "terminal" and variations thereof may interchangeably refer to any suitable mobile or fixed device that can receive wireless communications and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smart phones, personal digital assistants, fixed location terminals, tablet computers, computers, wearable devices, laptop computers, servers, automotive devices in motor vehicles, and / or other types of portable electronic devices that are typically carried by a person and / or have communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include devices that communicate with another device that can receive wireless communications and / or navigation signals (such as via a short-range wireless, infrared, wired connection or other connection), regardless of whether satellite signal reception, assistance data reception and / or location-related processing occurs at the device or at another device. A UE may be implemented by any of a variety of types of devices including, but not limited to, a printed circuit (PC) card, a compact flash device, an external or internal modem, a wireless or wired phone, a smart phone, a tablet computer, a consumer tracking device, an asset tag, etc.

[0068] Wireless communications between electronic devices can be based on different technologies, such as code division multiple access (CDMA), W-CDMA, time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal frequency division multiplexing (OFDM), global system for mobile communications (GSM), 3GPP long term evolution (LTE), 5G new radio, (BT), Low Energy (BLE), IEEE 802.11 and IEEE 802.15.4 (Zigbee / Thread) or other protocols that may be used in a wireless communication network or a data communication network. Low Energy (also known as LE, BLE, and Smart).

[0069] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" should not be construed as preferred over other examples. Likewise, the term "example" does not mean that all examples include the discussed features, advantages, or modes of operation. Furthermore, particular features and / or structures may be combined with one or more other features and / or structures. Furthermore, at least a portion of the apparatus described herein may be configured to perform at least a portion of the methods described herein.

[0070] It should be noted that the terms “connected,” “coupled,” or any variations thereof mean any connection or coupling, direct or indirect, between elements, and may encompass the presence of intermediate elements between two elements that are “connected” or “coupled” together via intermediate elements, unless the connection is explicitly disclosed as being directly connected.

[0071] Any reference to an element using names such as "first", "second" or the like herein does not limit the quantity and / or order of those elements. Instead, these names are used as a convenient method of distinguishing between two or more elements and / or instances of elements. In addition, unless otherwise stated, an element set may include one or more elements.

[0072] Those skilled in the art will appreciate that any of a variety of different techniques and technologies may be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0073] Nothing stated or shown in the present application is intended to contribute any component, act, feature, benefit, advantage, or equivalent to the public regardless of whether the component, act, feature, benefit, advantage, or equivalent is recited in the claims.

[0074] In addition, those skilled in the art will appreciate that the various illustrative logic blocks, modules, circuits and algorithmic steps described in conjunction with the examples disclosed herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, frames, modules, circuits and actions have been generally described in terms of their functionality. Whether this function is implemented as hardware or software depends on specific applications and the design constraints imposed on the entire system. Those skilled in the art can implement the described functions in different ways for each specific application, but such implementation decisions should not be interpreted as causing deviations from the scope of the present disclosure.

[0075] Although some aspects have been described in conjunction with the device, these aspects also constitute the description of the corresponding method, and therefore the block or assembly of the device should also be understood as the corresponding method action or the feature of the method action. Similarly, the aspects described in conjunction with or as the method action also constitute the description of the corresponding block or details or features of the corresponding device. Some or all of the method actions can be performed by hardware devices (or using hardware devices) (such as, for example, microprocessors, programmable computers or electronic circuits). In some examples, some or more of the most important method actions can be performed by such devices.

[0076] In the detailed description above, it can be seen that different features are grouped together in the examples. This disclosure should not be understood as wanting the example clauses to have more features than the features explicitly mentioned in each clause. Instead, various aspects of the present disclosure may include less than all the features of the disclosed single example clauses. Therefore, the following clauses should be deemed to be included in the specification accordingly, wherein each clause itself can be used as a separate example. Although each dependent clause can be cited in a clause in a specific combination with one of the other clauses, the aspects of the dependent clause are not limited to the specific combination. It will be appreciated that other example clauses may also include a combination of the subject matter of the dependent clause aspect with any other dependent clause or independent clause, or a combination of any feature with other dependent and independent clauses. The various aspects disclosed herein explicitly include these combinations, unless it is explicitly expressed or can be easily inferred that a specific combination is not expected (e.g., contradictory aspects, such as defining an element as an electrical insulator and an electrical conductor). In addition, it is also desired that various aspects of the clause can be included in any other independent clause, even if the clause is not directly subordinate to the independent clause.

[0077] Implementation examples are described in the following numbered clauses.

[0078] Item 1. A device comprising a transistor, the transistor comprising: a drain, which is substantially enclosed in a drain silicide layer, wherein an integrated drain via portion of the drain silicide layer is coupled to a second drain contact, and wherein a first drain via couples the drain silicide layer to the first drain contact; a source, which is substantially enclosed in a source silicide layer, wherein an integrated source via portion of the source silicide layer is coupled to a second source contact, and wherein a first source via couples the source silicide layer to a first source contact; and a gate, which is disposed between the source and the drain.

[0079] Clause 2. The device of clause 1, wherein the integrated source via portion is in direct contact with the second source contact, and the integrated drain via portion is in direct contact with the second drain contact.

[0080] Clause 3. The device of any of Clauses 1 to 2, wherein the drain silicide layer and the source silicide layer each have a substantially uniform thickness.

[0081] Item 4. The device of Item 3, wherein the drain silicide layer and the source silicide layer have substantially the same thickness.

[0082] Clause 5. The device of any one of clauses 1 to 4, wherein the integrated drain via portion and the integrated source via portion have a thickness of about 5 nm to 40 nm.

[0083] Item 6. The device according to any one of items 1 to 5, further comprising: a front side metallization structure having a plurality of front side metal layers, wherein the first drain contact and the first source contact are formed by one front side metal layer of the plurality of front side metal layers.

[0084] Item 7. The apparatus of Item 6, further comprising: a backside metallization structure having a plurality of backside metal layers, wherein the second drain contact and the second source contact are formed by one backside metal layer of the plurality of backside metal layers.

[0085] Item 8. A device according to Item 7, wherein the integrated source via portion is in direct contact with the second source contact formed by the first portion of the first backside metal layer, and the integrated drain via portion is in direct contact with the second drain contact formed by the second portion of the first backside metal layer.

[0086] Clause 9. The apparatus of any of clauses 1 to 8, wherein the transistor is a FinFET or a gate-all-around (GAA) device.

[0087] Clause 10. An apparatus as described in any one of clauses 1 to 9, wherein the apparatus comprises at least one of the following: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, an access point, a base station, or a device in a motor vehicle.

[0088] Item 11. A method for making a device including a transistor, the method comprising: forming a drain substantially enclosed in a drain silicide layer, wherein an integrated drain via portion of the drain silicide layer is coupled to a second drain contact, and wherein a first drain via couples the drain silicide layer to the first drain contact; forming a source substantially enclosed in a source silicide layer, wherein an integrated source via portion of the source silicide layer is coupled to a second source contact, and wherein a first source via couples the source silicide layer to a first source contact; and forming a gate disposed between the source and the drain.

[0089] Clause 12. The method of clause 11, wherein the integrated source via portion is in direct contact with the second source contact, and the integrated drain via portion is in direct contact with the second drain contact.

[0090] Clause 13. The method of any one of Clauses 11 to 12, wherein the drain silicide layer and the source silicide layer each have a substantially uniform thickness.

[0091] Item 14. The method of Item 13, wherein the drain silicide layer and the source silicide layer have substantially the same thickness.

[0092] Clause 15. The method of any one of clauses 11 to 14, wherein the thickness of the integrated drain via portion and the integrated source via portion is about 5 nm to 40 nm.

[0093] Clause 16. The method of any one of Clauses 11 to 15, wherein the integrated drain via is partially embedded in the drain silicide layer.

[0094] Clause 17. The method of any one of Clauses 11 to 15, wherein the integrated drain via portion is an extension of the drain silicide layer.

[0095] Clause 18. The method of any one of clauses 11 to 17, wherein the integrated source via portion is embedded in the source silicide layer.

[0096] Clause 19. The method of any one of clauses 11 to 17, wherein the integrated source via portion is an extension of the source silicide layer.

[0097] Clause 20. The method according to any one of clauses 11 to 19, further comprising: forming a front side metallization structure having a plurality of front side metal layers, wherein the first drain contact and the first source contact are formed by one front side metal layer of the plurality of front side metal layers.

[0098] Item 21. The method of Item 20, further comprising: forming a backside metallization structure having a plurality of backside metal layers, wherein the second drain contact and the second source contact are formed by one backside metal layer of the plurality of backside metal layers.

[0099] Item 22. A method according to Item 21, wherein the integrated source via portion is in direct contact with the second source contact formed by a first portion of a first backside metal layer, and the integrated drain via portion is in direct contact with the second drain contact formed by a second portion of the first backside metal layer.

[0100] Clause 23. The method of any one of clauses 11 to 22, wherein the transistor is a FinFET or a gate-all-around (GAA) device.

[0101] Clause 24. A method according to any one of clauses 11 to 23, wherein the device comprises at least one of the following: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, an access point, a base station, or a device in a motor vehicle.

[0102] It should also be noted that the methods, systems and apparatus disclosed in the specification or in the claims can be implemented by a device including units for performing the corresponding actions and / or functions of the disclosed methods.

[0103] In addition, in some examples, a single action can be subdivided into multiple sub-actions or include multiple sub-actions. Such sub-actions can be included in the disclosure of the single action and are part of the disclosure of the single action.

[0104] Although the foregoing disclosure shows the illustrative aspects of the present disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of the present disclosure as defined by the appended claims. In addition, the functions, steps and / or actions of the method claims according to the aspects of the disclosure described herein do not need to be performed in any particular order. In addition, although the elements of the present disclosure may be described or claimed in the singular, the plural form is conceivable unless explicitly stated to be limited to the singular.

Claims

1. A device comprising a transistor, comprising: a drain substantially enclosed in a drain silicide layer, wherein an integrated drain via portion of the drain silicide layer is coupled to a second drain contact, and wherein a first drain via couples the drain silicide layer to the first drain contact; a source substantially enclosed in a source silicide layer, wherein an integrated source via portion of the source silicide layer is coupled to a second source contact, and wherein a first source via couples the source silicide layer to the first source contact; as well as A gate is disposed between the source and the drain. 2 . The device of claim 1 , wherein the integrated source via portion is in direct contact with the second source contact, and the integrated drain via portion is in direct contact with the second drain contact.

3. The device according to claim 1, wherein: The drain silicide layer and the source silicide layer each have a substantially uniform thickness.

4. The device according to claim 3, wherein: The drain silicide layer and the source silicide layer have substantially the same thickness. 5 . The device of claim 1 , wherein the integrated drain via portion and the integrated source via portion have a thickness of about 5 nm to 40 nm.

6. The apparatus according to claim 1, further comprising: A front side metallization structure having a plurality of front side metal layers, wherein the first drain contact and the first source contact are formed by one front side metal layer of the plurality of front side metal layers.

7. The apparatus according to claim 6, further comprising: A backside metallization structure having a plurality of backside metal layers, wherein the second drain contact and the second source contact are formed by one backside metal layer of the plurality of backside metal layers.

8. The device of claim 7, wherein the integrated source via portion is in direct contact with the second source contact formed by a first portion of a first backside metal layer, and the integrated drain via portion is in direct contact with the second drain contact formed by a second portion of the first backside metal layer.

9. The device according to claim 1, wherein: The transistor is a FinFET or a gate-all-around (GAA) device.

10. The apparatus of claim 1, wherein the apparatus comprises at least one of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, an access point, a base station, or a device in a motor vehicle.

11. A method for making a device comprising a transistor, the method comprising: forming a drain substantially enclosed in a drain silicide layer, wherein an integrated drain via portion of the drain silicide layer is coupled to a second drain contact, and wherein a first drain via couples the drain silicide layer to the first drain contact; forming a source substantially enclosed in a source silicide layer, wherein an integrated source via portion of the source silicide layer is coupled to a second source contact, and wherein a first source via couples the source silicide layer to the first source contact; as well as A gate electrode is formed to be disposed between the source electrode and the drain electrode. 12 . The method of claim 11 , wherein the integrated source via portion is in direct contact with the second source contact, and the integrated drain via portion is in direct contact with the second drain contact. 13 . The method of claim 11 , wherein the drain silicide layer and the source silicide layer each have a substantially uniform thickness.

14. The method according to claim 13, wherein: The drain silicide layer and the source silicide layer have substantially the same thickness. 15 . The method of claim 11 , wherein the integrated drain via portion and the integrated source via portion have a thickness of about 5 nm to 40 nm.

16. The method of claim 11, wherein the integrated drain via is partially embedded in the drain silicide layer.

17. The method of claim 11, wherein the integrated drain via portion is an extension of the drain silicide layer.

18. The method of claim 11, wherein the integrated source via portion is embedded in the source silicide layer.

19. The method of claim 11, wherein the integrated source via portion is an extension of the source silicide layer.

20. The method according to claim 11, further comprising: A front side metallization structure having a plurality of front side metal layers is formed, wherein the first drain contact and the first source contact are formed by one front side metal layer of the plurality of front side metal layers.

21. The method according to claim 20, further comprising: A backside metallization structure having a plurality of backside metal layers is formed, wherein the second drain contact and the second source contact are formed from one backside metal layer of the plurality of backside metal layers.

22. The method of claim 21, wherein the integrated source via portion is in direct contact with the second source contact formed by a first portion of a first backside metal layer, and the integrated drain via portion is in direct contact with the second drain contact formed by a second portion of the first backside metal layer.

23. The method according to claim 11, wherein: The transistor is a FinFET or a gate-all-around (GAA) device.

24. The method of claim 11, wherein the device comprises at least one of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, an access point, a base station, or a device in a motor vehicle.

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